CY7C1019DV33 1-Mbit (128K x 8) Static RAM Functional Description[1] Features • Pin- and function-compatible with CY7C1019CV33 • High speed — tAA = 10 ns • Low Active Power — ICC = 60 mA @ 10 ns • Low CMOS Standby Power • • • • • • — ISB2 = 3 mA 2.0V Data retention Automatic power-down when deselected CMOS for optimum speed/power Center power/ground pinout Easy memory expansion with CE and OE options Available in Pb-free 32-pin 400-Mil wide Molded SOJ, 32-pin TSOP II and 48-ball VFBGA packages The CY7C1019DV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1019DV33 is available in Pb-free 32-pin 400-Mil wide Molded SOJ, 32-pin TSOP II and 48-ball VFBGA packages. Logic Block Diagram I/O0 INPUTBUFFER I/O1 128K × 8 ARRAY I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O3 I/O4 I/O5 CE WE COLUMN DECODER I/O6 POWER DOWN I/O7 A9 A10 A11 A12 A13 A14 A15 A16 OE Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com Cypress Semiconductor Corporation Document #: 38-05481 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 14, 2010 [+] Feedback CY7C1019DV33 Selection Guide –10 (Industrial) Unit Maximum Access Time 10 ns Maximum Operating Current 60 mA Maximum Standby Current 3 mA Pin Configurations[2] 48-ball VFBGA (Top View) SOJ/TSOPII Top View 2 3 4 5 6 NC OE A2 A6 A7 NC A I/O0 NC A1 A5 CE I/O7 B I/O1 NC A0 A4 NC I/O6 C VSS NC NC A3 NC VCC D VCC NC NC NC NC VSS E I/O2 NC A14 A11 I/O4 I/O5 F I/O3 NC A15 A12 WE A8 G NC A10 A16 A13 A9 NC H 1 A0 A1 A2 A3 CE I/O0 I/O1 VCC V SS I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 Note 2. NC pins are not connected on the die. Document #: 38-05481 Rev. *E Page 2 of 13 [+] Feedback CY7C1019DV33 DC Input Voltage[3] ................................ –0.3V to VCC + 0.3V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65C to +150C Ambient Temperature with Power Applied............................................. –55C to +125C Supply Voltage on VCC to Relative GND[3] ... –0.3V to + 4.6V DC Voltage Applied to Outputs in High-Z State[3] ....................................–0.3V to VCC + 0.3V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Range Ambient Temperature VCC Speed Industrial –40C to +85C 3.3V 0.3V 10 ns Electrical Characteristics Over the Operating Range Parameter Description –10 (Industrial) Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Min. Max. 2.4 Voltage[3] VIL Input LOW IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current GND < VI < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Unit V 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V –1 +1 A –1 +1 A 100MHz 60 mA 83MHz 55 mA 66MHz 45 mA 40MHz 30 mA ISB1 Automatic CE Power-down Current—TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 10 mA ISB2 Automatic CE Power-down Current—CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f = 0 3 mA Note 3. VIL (min.) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns. Document #: 38-05481 Rev. *E Page 3 of 13 [+] Feedback CY7C1019DV33 Capacitance[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. TA = 25 C, f = 1 MHz, VCC = 3.3V Unit 8 pF 8 pF Thermal Resistance[4] Parameter Description JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) Test Conditions SOJ Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board TSOP II VFBGA Unit 56.29 62.22 36 C/W 38.14 21.43 9 C/W AC Test Loads and Waveforms[5] ALL INPUT PULSES 3.0V Z = 50 90% OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT GND 30 pF* 90% 10% 10% 1.5V Rise Time: 1 V/ns (a) (b) Fall Time: 1 V/ns High-Z characteristics: R1 317 3.3V OUTPUT R2 351 5 pF (c) Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05481 Rev. *E Page 4 of 13 [+] Feedback CY7C1019DV33 Switching Characteristics Over the Operating Range [6] Parameter Description –10 (Industrial) Min. Max. Unit Read Cycle tpower[7] VCC(typical) to the first access 100 s tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 ns tDOE OE LOW to Data Valid 5 ns tLZOE OE LOW to Low Z tHZOE tLZCE OE HIGH to High CE LOW to Low 10 3 ns 0 Z[8, 9] Z[9] tHZCE CE HIGH to High tPU[10] tPD[10] CE LOW to Power-Up ns 5 3 Z[8, 9] ns ns 5 ns 10 ns 0 CE HIGH to Power-Down ns ns Write Cycle[11, 12] tWC Write Cycle Time 10 ns tSCE CE LOW to Write End 8 ns tAW Address Set-Up to Write End 8 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 7 ns tSD Data Set-Up to Write End 5 ns tHD Data Hold from Write End 0 ns 3 ns tLZWE tHZWE [9] WE HIGH to Low Z WE LOW to High Z[8, 9] 5 ns Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. This parameter is guaranteed by design and is not tested. 11. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05481 Rev. *E Page 5 of 13 [+] Feedback CY7C1019DV33 Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR [4] Chip Deselect to Data Retention Time tR[13] Operation Recovery Time Min. Max. 2.0 Unit V 3 VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V 3.0V tR tCDR CE Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[14, 15] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[15, 16] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tHZCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% ICC 50% ISB Notes 13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document #: 38-05481 Rev. *E Page 6 of 13 [+] Feedback CY7C1019DV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[17, 18] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[17, 18] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 19 tHZOE Notes 17. Data I/O is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 19. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05481 Rev. *E Page 7 of 13 [+] Feedback CY7C1019DV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[12, 18] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 19 tHD DATA VALID tLZWE tHZWE Truth Table CE OE WE I/O0–I/O7 H X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Document #: 38-05481 Rev. *E Mode Power Page 8 of 13 [+] Feedback CY7C1019DV33 Ordering Information Speed (ns) 10 Ordering Code Package Diagram Package Type CY7C1019DV33-10VXI 51-85033 32-pin (400-Mil) Molded SOJ (Pb-free) CY7C1019DV33-10ZSXI 51-85095 32-pin TSOP Type II (Pb-free) CY7C1019DV33-10BVXI 51-85150 48-ball VFBGA (Pb-free) Operating Range Industrial Ordering Code Definitions CY 7 C 1 01 9 D V33 - 10 XXX I Temperature Range: I = Industrial Package Type: XXX = VX or ZSX or BVX VX = 32-pin Molded SOJ (Pb-free) ZSX = 32-pin TSOP Type II (Pb-free) BVX = 48-ball VFBGA (Pb-free) Speed: 10 ns V33 = Voltage range (3 V to 3.6 V) D = C9, 90 nm Technology 9 = Data width × 8-bits 01 = 1-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05481 Rev. *E Page 9 of 13 [+] Feedback CY7C1019DV33 Package Diagrams Figure 1. 32-pin (400-Mil) Molded SOJ (51-85033) 51-85033 *C Figure 2. 32-pin Thin Small Outline Package Type II (51-85095) 51-85095 *A Document #: 38-05481 Rev. *E Page 10 of 13 [+] Feedback CY7C1019DV33 Package Diagrams (continued) Figure 3. 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) 51-85150 *F All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05481 Rev. *E Page 11 of 13 [+] Feedback CY7C1019DV33 Document History Page Document Title: CY7C1019DV33, 1-Mbit (128K x 8) Static RAM Document Number: 38-05481 REV. ECN NO. Issue Date Orig. of Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 233750 See ECN RKF DC parameters modified as per EROS (Spec # 01-02165 Rev *A) Pb-free Offering in Ordering Information *B 262950 See ECN RKF Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information *C 307598 See ECN RKF Reduced Speed bins to -8 and -10 ns *D 520652 See ECN VKN Converted from Preliminary to Final Removed Commercial Operating range Removed 8 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Added 48-ball VFBGA package Updated Thermal Resistance table Updated Ordering Information table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3 *E 3110052 12/14/2010 AJU Added Ordering Code Definitions. Updated Package Diagrams. Document #: 38-05481 Rev. *E Description of Change Page 12 of 13 [+] Feedback CY7C1019DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive PSoC Solutions cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF Document #: 38-05481 Rev. *E cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless Page 13 of 13 © Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback