CYPRESS CY62148DV30LL

CY62148DV30
4-Mbit (512K x 8) MoBL® Static RAM
Functional Description[1]
Features
• Temperature Ranges
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
• Very high speed: 55 ns
— Wide voltage range: 2.20V – 3.60V
• Pin-compatible with CY62148CV25, CY62148CV30 and
CY62148CV33
• Ultra low active power
The CY62148DV30 is a high-performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption when deselected
(CE HIGH).The eight input and output pins (IO0 through IO7)
are placed in a high-impedance state when:
— Typical active current: 1.5 mA @ f = 1 MHz
• Deselected (CE HIGH)
— Typical active current: 8 mA @ f = fmax(55-ns speed)
• Outputs are disabled (OE HIGH)
• Ultra low standby power
• When the write operation is active(CE LOW and WE LOW)
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 36-ball VFBGA,
Pb-free 32-pin TSOPII and 32-pin SOIC packages
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the eight IO pins (IO0
through IO7) is then written into the location specified on the
address pins (A0 through A18).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the IO pins.
Logic Block Diagram
IO 0
Data in Drivers
IO 1
512K x 8
ARRAY
IO 2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
IO 3
IO 4
IO 5
COLUMN
DECODER
CE
IO 6
POWER
DOWN
IO 7
A13
A14
A15
A16
A17
A18
WE
OE
Note:
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05341 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 25, 2007
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CY62148DV30
Pin Configuration[2, 3]
A0
IO 4
36-ball VFBGA Pinout
32-pin SOIC / TSOP II Pinout
Top View
Top View
NC
A1
A2
IO 5
A3
WE
A4
DNU
A5
A6
A8
A7
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
IO 0
IO 1
IO 2
VSS
A
IO 0
B
IO 1
C
VSS
Vcc
D
VCC
Vss
E
IO 2
F
IO 6
A18
A17
IO 7
OE
CE
A16
A15
IO 3
G
A9
A10
A11
A12
A13
A14
H
4
32
31
30
29
5
6
28
27
7
8
9
10
11
12
26
25
1
2
3
VCC
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
IO 7
IO 6
IO 5
IO 4
IO 3
24
23
22
21
20
19
18
17
13
14
15
16
Product Portfolio
Power Dissipation
Operating ICC (mA)
VCC Range (V)
f = 1 MHz
Max
Speed
(ns)
Typ[4]
3.6
55
CY62148DV30LL Industrial
Max
Typ[4]
Max
1.5
3
8
15
2
12
55
1.5
3
8
10
2
8
CY62148DV30LL Industrial
70
1.5
3
8
10
2
8
CY62148DV30LL Automotive-A
70
1.5
3
8
10
2
8
CY62148DV30L
Industrial
2.2
3.0
Standby ISB2 (µA)
Max
Range
Min
f = fmax
Typ[4]
Product
Typ[4]
Notes:
2. NC pins are not connected on the die.
3. DNU pins have to be left floating or tied to Vss to ensure proper application.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Document #: 38-05341 Rev. *D
Page 2 of 10
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CY62148DV30
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Exceeding maximum ratings may impair the useful life of the
device. For user guidelines, not tested.)
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................... 55°C to +125°C
Supply Voltage to Ground
Potential ......................................... –0.3V to VCC(max) + 0.3V
DC Voltage Applied to Outputs
in High-Z State[5, 6] ......................... –0.3V to VCC(max) + 0.3V
DC Input Voltage[5, 6] ..................... –0.3V to VCC(max) + 0.3V
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Product
CY62148DV30L
Range
Ambient
Temperature
Industrial
–40°C to +85°C
VCC[7]
2.2V to
3.6V
CY62148DV30LL
CY62148DV30LL Automotive-A –40°C to +85°C
Electrical Characteristics Over the Operating Range
55 ns
Parameter
VOH
Description
Test Conditions
Min
Typ[4]
70 ns
Max
Min Typ[4] Max
Unit
Output HIGH
Voltage
IOH = –0.1 mA
VCC = 2.20V
2.0
2.0
V
IOH = –1.0 mA
VCC = 2.70V
2.4
2.4
V
VOL
Output LOW
Voltage
IOL = 0.1 mA
VCC = 2.20V
IOL = 2.1 mA
VCC = 2.70V
VIH
Input HIGH
Voltage
VCC = 2.2V to 2.7V
1.8
VCC +
0.3V
1.8
VCC= 2.7V to 3.6V
2.2
VCC +
0.3V
2.2
VCC +
0.3V
V
V
0.4
0.4
0.4
V
0.4
V
VCC +
0.3V
V
VIL
Input LOW
Voltage
VCC = 2.2V to 2.7V
–0.3
0.6
–0.3
0.6
VCC= 2.7V to 3.6V
–0.3
0.8
–0.3
0.8
V
IIX
Input Leakage
Current
GND < VI < VCC
–1
+1
–1
+1
µA
IOZ
Output Leakage GND < VO < VCC, Output Disabled
Current
–1
+1
–1
+1
µA
ICC
VCC Operating
Supply Current
f = fmax = 1/tRC VCC = VCC(max)
IOUT = 0 mA
CMOS levels
f = 1 MHz
Ind’l
L
8
15
Ind’l
LL
8
10
Auto-A LL
Ind’l
L
1.5
3
Ind’l
LL
1.5
3
Auto-A LL
ISB1
ISB2
Automatic CE
Power-down
Current —
CMOS Inputs
CE > VCC−0.2V,
VIN>VCC–0.2V, VIN<0.2V)
f = fmax (Address and Data Only),
f = 0 (OE, and WE), VCC=3.60V
Automatic CE
Power-down
Current —
CMOS Inputs
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
Ind’l
L
2
12
Ind’l
LL
2
8
Auto-A LL
Ind’l
L
2
12
Ind’l
LL
2
8
Auto-A LL
mA
8
10
mA
8
10
mA
mA
1.5
3
mA
1.5
3
mA
µA
2
8
2
8
µA
2
8
2
8
Notes:
5. VIL(min) = –2.0V for pulse durations less than 20 ns.
6. VIH(max) = VCC+0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
Document #: 38-05341 Rev. *D
Page 3 of 10
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CY62148DV30
Capacitance (for all packages)[8]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
Unit
10
pF
10
pF
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
Thermal Resistance
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 x 4.5
inch, four-layer printed circuit
board
VFBGA
TSOP II
SOIC
Unit
72
75.13
55
°C/W
8.86
8.95
22
°C/W
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC
OUTPUT
50 pF
GND
R2
90%
10%
90%
10%
Fall time: 1 V/ns
Rise Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5V (2.2V – 2.7V)
3.0V (2.7V – 3.6V)
Unit
R1
16667
1103
Ω
R2
15385
1554
Ω
RTH
8000
645
Ω
VTH
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[8]
tR[9]
Min Typ[4] Max
Conditions
1.5
VCC = 1.5V, CE > VCC − 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V
Ind’l
L
Ind’l/Auto-A LL
Chip Deselect to Data Retention Time
Operation Recovery Time
Unit
V
9
µA
6
µA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
1.5V
VDR > 1.5 V
tCDR
1.5V
tR
CE
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
Document #: 38-05341 Rev. *D
Page 4 of 10
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CY62148DV30
Switching Characteristics (Over the Operating Range)[10]
55 ns
Parameter
Description
Min
70 ns
Max
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z[11]
tHZOE
OE HIGH to High
tLZCE
CE LOW to Low
55
CE HIGH to High
CE LOW to Power-up
Write
10
25
5
10
ns
35
ns
ns
25
20
CE HIGH to Power-up
70
10
0
ns
ns
25
0
55
ns
ns
5
20
Z[11, 12]
ns
70
55
Z[11]
tPU
tPD
10
Z[11,12]
tHZCE
70
55
ns
ns
70
ns
Cycle[13]
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
40
45
ns
tAW
Address Set-up to Write End
40
45
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
45
ns
tSD
Data Set-up to Write End
25
30
ns
tHD
Data Hold from Write End
0
0
ns
Z[11, 12]
tHZWE
WE LOW to High
tLZWE
WE HIGH to Low Z[11]
20
10
25
10
ns
ns
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
tRC
ADDRESS
tOHA
DATA OUT
PREVIOUS DATA VALID
tAA
DATA VALID
Notes:
10. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2,
input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
12. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state.
13. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
14. Device is continuously selected. OE, CE = VIL.
15. WE is HIGH for read cycle.
Document #: 38-05341 Rev. *D
Page 5 of 10
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CY62148DV30
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tHZCE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ICC
ISB
Write Cycle No. 1 (WE Controlled)[17, 18]
tWC
ADDRESS
tSCE
CE
tAW
tSA
WE
tHA
tPWE
OE
tSD
DATA IO
NOTE 19
tHD
DATAIN VALID
tHZOE
Notes:
16. Address valid prior to or coincident with CE transition LOW.
17. Data IO is high impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state.
19. During this period, the IOs are in output state and input signals should not be applied.
Document #: 38-05341 Rev. *D
Page 6 of 10
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CY62148DV30
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[17, 18]
tWC
ADDRESS
tSCE
CE
tHA
tSA
tAW
tPWE
WE
OE
tSD
DATA IO
tHD
DATAIN VALID
Write Cycle No. 3 (WE Controlled, OE LOW)[18]
tWC
ADDRESS
tSCE
CE
tAW
tSA
WE
tHA
tPWE
tSD
NOTE 19
DATA IO
tHD
DATAIN VALID
tLZWE
tHZWE
Truth Table
CE
WE
OE
Inputs/Outputs
H
X
X
High Z
Deselect/Power-down
Standby (ISB)
L
H
L
Data Out (IO0-IO7)
Read
Active (ICC)
L
H
H
High Z
Output Disabled
Active (Icc)
L
L
X
Data in (IO0-IO7)
Write
Active (Icc)
Document #: 38-05341 Rev. *D
Mode
Power
Page 7 of 10
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CY62148DV30
Ordering Information
Speed
(ns)
55
Package
Diagram
Ordering Code
CY62148DV30LL-55BVI
Operating
Range
Package Type
51-85149 36-ball VFBGA (6 × 8 × 1 mm)
CY62148DV30LL-55BVXI
Industrial
36-ball VFBGA (6 × 8 × 1 mm) (Pb-free)
CY62148DV30L-55ZSXI
51-85095 32-pin TSOP II (Pb-free)
CY62148DV30LL-55ZSXI
70
CY62148DV30LL-55SXI
51-85081 32-pin SOIC (Pb-free)
CY62148DV30LL-70ZSXI
51-85095 32-pin TSOP II (Pb-free)
Industrial
CY62148DV30LL-70ZSXA
51-85095 32-pin TSOP II (Pb-free)
Automotive-A
Contact your local Cypress sales representative for availability of these parts
Package Diagrams
Figure 1. 36-ball VFBGA (6 x 8 x 1 mm), 51-85149
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(36X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
6.00±0.10
0.15(4X)
0.10 C
0.21±0.05
0.25 C
0.55 MAX.
B
Document #: 38-05341 Rev. *D
1.00 MAX
0.26 MAX.
SEATING PLANE
C
51-85149-*C
Page 8 of 10
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CY62148DV30
Package Diagrams (continued)
Figure 2. 32-pin TSOP II, 51-85095
51-85095-**
Figure 3. 32-pin (450 MIL) Molded SOIC, 51-85081
16
1
0.546[13.868]
0.566[14.376]
0.440[11.176]
0.450[11.430]
17
32
0.793[20.142]
0.817[20.751]
0.006[0.152]
0.012[0.304]
0.101[2.565]
0.111[2.819]
0.118[2.997]
MAX.
0.004[0.102]
0.050[1.270]
BSC.
0.004[0.102]
MIN.
0.014[0.355]
0.020[0.508]
SEATING PLANE
0.047[1.193]
0.063[1.600]
0.023[0.584]
0.039[0.990]
51-85081-*B
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05341 Rev. *D
Page 9 of 10
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62148DV30
Document History Page
Document Title:CY62148DV30, 4-Mbit (512K x 8) MoBL® Static RAM
Document Number: 38-05341
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
127480
06/17/03
HRT
Created new data sheet
*A
131041
01/23/04
CBD
Changed from Advance to Preliminary
*B
222180
See ECN
AJU
Changed from Preliminary to Final
Added 70 ns speed bin
Modified footnote #6 and #12
Removed MAX value for VDR on “Data Retention Characteristics” table
Modified input and output capacitance values
Added Pb-free ordering information
Removed 32-pin STSOP package
*C
498575
See ECN
NXR
Added Automotive-A Operating Range
Removed SOIC package from Product Offering
Updated Ordering Information Table
*D
729917
See ECN
VKN
Added SOIC package and its related information
Updated Ordering Information Table
Document #: 38-05341 Rev. *D
Page 10 of 10
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