CY7C1049D 4-Mbit (512K x 8) Static RAM Functional Description[1] Features • Pin- and function-compatible with CY7C1049B • High speed — tAA = 10 ns • Low active power — ICC = 90 mA @ 10 ns • Low CMOS Standby power — ISB2 = 10 mA • 2.0V Data Retention The CY7C1049D is a high-performance CMOS static RAM organized as 512K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features • Available in lead-free 36-Lead (400-Mil) Molded SOJ package The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049D is available in a standard 400-mil-wide 36-pin SOJ package with center power and ground (revolutionary) pinout. Logic Block Diagram Pin Configuration SOJ Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 I/O0 INPUT BUFFER I/O1 ROW DECODER I/O2 512K x 8 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O3 I/O4 I/O5 COLUMN DECODER CE 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC I/O6 POWER DOWN I/O7 A 11 A 12 A 13 A14 A15 A16 A17 A18 WE OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Selection Guide -10 Unit Maximum Access Time 10 ns Maximum Operating Current 90 mA Maximum CMOS Standby Current 10 mA Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05474 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 3, 2006 [+] Feedback CY7C1049D DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-Up Current ..................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VCC to Relative GND[2] .... –0.5V to +6.0V DC Voltage Applied to Outputs in High Z State[2] ....................................–0.5V to VCC + 0.5V Range Industrial Ambient Temperature VCC –40°C to +85°C 4.5V–5.5V Electrical Characteristics Over the Operating Range -10 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Min. Max. 2.4 Unit V VOL Output LOW Voltage 0.4 V VIH[2] Input HIGH Voltage 2.0 VCC + 0.5 V VIL[2] Input LOW Voltage[2] –0.5 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 µA IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 µA ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC 100 MHz 90 mA 83 MHz 80 mA 66 MHz 70 mA 40 MHz 60 mA ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX 20 mA ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 10 mA Capacitance[3] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions Max. Unit TA = 25°C, f = 1 MHz, VCC = 5.0V 8 pF 8 pF Test Conditions SOJ Package Unit Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 57.91 °C/W 36.73 °C/W Thermal Resistance[3] Parameter Description ΘJA Thermal Resistance (Junction to Ambient)[3] ΘJC Thermal Resistance (Junction to Case)[3] Notes: 2. Minimum voltage is –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05474 Rev. *C Page 2 of 8 [+] Feedback CY7C1049D AC Test Loads and Waveforms[4] 10-ns device Z = 50Ω ALL INPUT PULSES OUTPUT 3.0V 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 90% 30 pF* GND 1.5V 90% 10% 10% ≤ 3 ns ≤ 3 ns (a) (b) HIGH-Z CHARACTERISTICS R1 481Ω 5V OUTPUT THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Equivalent to: R2 255Ω 5 pF INCLUDING JIG AND SCOPE (c) Switching Characteristics[5] Over the Operating Range -10 Parameter Description Min. Max. Unit Read Cycle tpower VCC(typical) to the First Access[6] 100 µs tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z[8] tHZOE OE HIGH to High Z[7, 8] tLZCE CE LOW to Low Z[8] 10 3 tHZCE CE HIGH to High tPU CE LOW to Power-Up tPD CE HIGH to Power-Down ns 10 5 0 ns ns ns 5 3 Z[7, 8] ns ns ns 5 0 ns ns 10 ns Write Cycle[9, 10] tWC Write Cycle Time 10 ns tSCE CE LOW to Write End 7 ns tAW Address Set-Up to Write End 7 ns tHA Address Hold from Write End 0 ns Notes: 4. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c) 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05474 Rev. *C Page 3 of 8 [+] Feedback CY7C1049D Switching Characteristics[5] Over the Operating Range (continued) -10 Parameter Description Min. Max. Unit tSA Address Set-Up to Write Start tPWE WE Pulse Width 7 ns tSD Data Set-Up to Write End 6 ns tHD Data Hold from Write End 0 ns tLZWE WE HIGH to Low Z[8] 3 ns tHZWE 0 ns [7, 8] WE LOW to High Z 5 ns Data Retention Characteristics Over the Operating Range Parameter Conditions[12] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time tR [11] Min. Max 2.0 Operation Recovery Time V 10 VCC = VDR = 2.0V, CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V Unit mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 4.5V VCC VDR > 2V tCDR 4.5V tR CE Switching Waveforms Read Cycle No. 1[13, 14] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs 12. No input may exceed VCC + 0.5V. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. Document #: 38-05474 Rev. *C Page 4 of 8 [+] Feedback CY7C1049D Switching Waveforms(continued) Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Write Cycle No. 1 (CE Controlled)[16, 17] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Notes: 15. Address valid prior to or coincident with CE transition LOW. 16. Data I/O is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05474 Rev. *C Page 5 of 8 [+] Feedback CY7C1049D Switching Waveforms(continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 18 tHZOE Write Cycle No. 3 (WE Controlled, OE LOW)[17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD NOTE 18 DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE H OE X WE X I/O0–I/O7 Mode High-Z Power-down Power Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High-Z Selected, Outputs Disabled Active (ICC) Notes: 18. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05474 Rev. *C Page 6 of 8 [+] Feedback CY7C1049D Ordering Information Speed (ns) 10 Ordering Code CY7C1049D-10VXI Package Diagram 51-85090 Operating Range Package Type 36-Lead (400-Mil) Molded SOJ (Pb-Free) Industrial Please contact your local Cypress sales representative for availability of these parts. Package Diagram 36-Lead (400-Mil) Molded SOJ (51-85090) 51-85090-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05474 Rev. *C Page 7 of 8 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1049D Document History Page Document Title: CY7C1049D 4-Mbit (512K x 8) Static RAM Document Number: 38-05474 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance Datasheet for C9 IPP *A 233729 See ECN RKF 1.AC, DC parameters are modified as per EROS(Spec # 01-2165) 2.Pb-free offering in the ‘ordering information’ *B 351096 See ECN PCI Changed from Advance to Preliminary Removed 17, 20 ns Speed bin Added footnote # 4 Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 67 and 54 mA to 75 and 70 mA for 12 and 15 ns speed bins respectively ICC (Ind’l): Changed from 80, 67 and 54 mA to 90, 85 and 80 mA for 10, 12 and 15 ns speed bins respectively Added VIH(max) spec in Note# 2 Modified Note# 10 on tR Changed tSCE from 8 to 7 ns for 10 ns speed bin Changed reference voltage level for measurement of Hi-Z parameters from ±500 mV to ±200 mV Added Truth Table on page# 6 Removed L-Version Added 10 ns parts in the Ordering Information Table Added Lead-Free Product Information Shaded Ordering Information Table *C 446328 See ECN NXR Converted from Preliminary to Final Removed -12 and -15 speed bins Removed Commercial Operating Range product information Changed Maximum Rating for supply voltage from 7V to 6V Updated Thermal Resistance table Changed tHZWE from 6 ns to 5 ns Updated footnote #7 on High-Z parameter measurement Replaced Package Name column with Package Diagram in the Ordering Information table Document #: 38-05474 Rev. *C Page 8 of 8 [+] Feedback