EVALUATION KIT AVAILABLE MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs General Description The MAX5138/MAX5139 are a family of single-channel pin-compatible and software-compatible 16-bit and 12bit DACs. The MAX5138/MAX5139 are low-power, 16bit/12-bit, buffered voltage-output, high-linearity DACs. They use a precision internal reference or a precision external reference for rail-to-rail operation. The MAX5138/MAX5139 accept a wide +2.7V to +5.25V supply-voltage range to accommodate most low-power and low-voltage applications. These devices accept a 3-wire SPI-/QSPI TM -/MICROWIRE ® -/DSP-compatible serial interface to save board space and reduce the complexity of optically isolated and transformer-isolated applications. The digital interface’s double-buffered hardware and software LDAC provide simultaneous output update. The serial interface features a READY output for easy daisy-chaining of several MAX5138/MAX5139 devices and/or other compatible devices. The MAX5138/MAX5139 include a hardware input to reset the DAC outputs to zero or midscale upon power-up or reset, providing additional safety for applications that drive valves or other transducers that need to be off during power-up. The high linearity of the DACs makes these devices ideal for precision control and instrumentation applications. The MAX5138/MAX5139 are available in an ultra-small (3mm x 3mm), 16-pin TQFN package and are specified over the -40°C to +105°C extended industrial temperature range. Applications Automatic Test Equipment Features ♦ 16-/12-Bit Resolution in a 3mm x 3mm, 16-Pin TQFN Package ♦ Hardware-Selectable on Power-Up or Reset-toZero/Midscale DAC Output ♦ Double-Buffered Input Registers ♦ LDAC Asynchronously Updates DAC Output ♦ READY Facilitates Daisy Chaining ♦ High-Performance 10ppm/°C Internal Reference ♦ Guaranteed Monotonic Over All Operating Conditions ♦ Wide +2.7V to +5.25V Supply Range ♦ Rail-to-Rail Buffered Output Operation ♦ Low Gain Error (Less Than ±0.5% FS) and Offset (Less Than ±10mV) ♦ 30MHz 3-Wire SPI-/QSPI-/MICROWIRE-/ DSP-Compatible Serial Interface ♦ CMOS-Compatible Inputs with Hysteresis ♦ Low Power Consumption (ISHDN = 2µA max) Ordering Information PART MAX5138BGTE+ 16 TQFN-EP* 16 MAX5139GTE+ 16 TQFN-EP* 12 Note: All devices are specified over the -40°C to +105°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Pin Configuration Automatic Tuning N.C. AVDD 13 MAX5138 MAX5139 REFI 14 REFO 15 AGND 16 Functional Diagram and Typical Operating Circuit appear at end of data sheet. 9 *EP + 1 2 3 4 N.C. Programmable Voltage and Current Sources 10 LDAC Process Control and Servo Loops 11 M/Z Power-Amplifier Control 12 N.C. Portable Instrumentation READY Gain and Offset Adjustment DVDD TOP VIEW OUT Communication Systems Data Acquisition RESOLUTION (BITS) PIN-PACKAGE 8 AGND 7 DIN 6 CS 5 SCLK QSPI is a trademark of Motorola Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. *CONNECT EP TO AGND OR LEAVE UNCONNECTED For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. 19-4428; Rev 2; 10/12 MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS AVDD to AGND ........................................................-0.3V to +6V DVDD to AGND ........................................................-0.3V to +6V OUT to AGND...............................................-0.3V to the lower of (AVDD + 0.3V) and +6V REFI, REFO, M/Z to AGND ...........................-0.3V to the lower of (AVDD + 0.3V) and +6V SCLK, DIN, CS to AGND ..............................-0.3V to the lower of (DVDD + 0.3V) and +6V LDAC, READY to AGND...............................-0.3V to the lower of (DVDD + 0.3V) and +6V Continuous Power Dissipation (TA = +70°C) 16-Pin TQFN (derate at 14.7mW/°C above +70°C) ..1176.5mW Maximum Current into Any Input or Output with the Exception of M/Z Pin .......................................±50mA Maximum Current into M/Z Pin ...........................................±5mA Operating Temperature Range .........................-40°C to +105°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD ≥ VDVDD, VAGND = 0V, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY (Notes 1, 2) Resolution N MAX5138 16 MAX5139 12 (Note 3) -9 MAX5138 Integral Nonlinearity INL VREFI = 5V, VAVDD = 5.25V MAX5139 Integral Nonlinearity INL VREFI = 5V, VAVDD = 5.25V Differential Nonlinearity DNL Guaranteed monotonic -1.0 (Note 4) -10 Offset Error OE ±2 TA = +25°C +11 ±6 -1 Offset-Error Drift Gain Error Bits ±0.25 ±1 +1 LSB +1.0 LSB +10 ±4 GE (Note 4) -0.5 Gain Temperature Coefficient ±0.2 LSB mV μV/°C +0.5 % of FS ppm FS/°C ±2 REFERENCE INPUT VAVDD = 3V to 5.25V Reference-Input Voltage Range VREFI VAVDD = 2.7V to 3V 2 VAVDD 2 VAVDD - 0.2 Reference Input Impedance 113 V k INTERNAL REFERENCE Reference Voltage VREFO Reference Temperature Coefficient (Note 5) Reference Output Impedance Line Regulation Maximum Capacitive Load 2 TA = +25°C CR 2.437 2.440 2.443 V 10 25 ppm/°C 1 100 ppm/V 0.1 nF Maxim Integrated MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD ≥ VDVDD, VAGND = 0V, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VAVDD - 0.02 V DAC OUTPUT VOLTAGE (Note 2) Output Voltage Range No load 0.02 DC Output Impedance Maximum Capacitive Load (Note 5) CL Resistive Load RL Short-Circuit Current ISC Power-Up Time Series resistance = 0 Series resistance = 500 0.1 0.2 nF 15 μF 2 VAVDD = 5.25V VAVDD = 2.7V k ±35 -40 From power-down mode ±20 +40 25 mA μs DIGITAL INPUTS (SCLK, DIN, CS, LDAC) (Note 6) Input High Voltage VIH Input Low Voltage VIL Input Leakage Current IIN Input Capacitance CIN 0.7 x VDVDD VIN = 0V or VDVDD -1 V ±0.1 0.3 x VDVDD V +1 μA 10 pF DIGITAL OUTPUTS (READY) VDVDD - 0.5 V Output High Voltage VOH ISOURCE = 3mA Output Low Voltage VOL ISINK = 2mA SR Positive and negative 1.25 V/μs tS 1/4 scale to 3/4 scale VREFI = VAVDD = 5V settle to ±2 LSB (Note 5) 5 μs Code 0, all digital inputs from 0V to VDVDD 0.5 nV•s 25 nV•s 0.4 V DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time Digital Feedthrough Major Code Transition Analog Glitch Impulse Output Noise 10kHz 120 nV/Hz Integrated Output Noise 1Hz to 10kHz 18 μV Maxim Integrated 3 MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD ≥ VDVDD, VAGND = 0V, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS (Note 7) Analog Supply Voltage Range AVDD 2.7 5.25 V Digital Supply Voltage Range DVDD 2.7 VAVDD V 1 1.6 mA μA IAVDD Supply Current IDVDD IAVPD Power-Down Supply Current No load, all digital inputs at 0V or VDVDD No load, all digital inputs at 0V or VDVDD IDVPD 1 10 0.2 2 0.1 2 μA TIMING CHARACTERISTICS (Note 8) (Figure 1) Serial-Clock Frequency fSCLK 0 SCLK Pulse-Width High tCH 13 30 MHz SCLK Pulse-Width Low tCL 13 ns CS Fall-to-SCLK Fall Setup Time tCSS 8 ns SCLK Fall-to CS-Rise Hold Time tCSH 5 ns DIN-to-SCLK Fall Setup Time tDS 10 ns DIN-to-SCLK Fall Hold Time tDH 2 ns ns SCLK Fall to READY Transition tSRL CS Pulse-Width High tCSW 33 ns tLDACPWL 33 ns LDAC Pulse Width (Note 9) 30 ns Static accuracy tested without load. Linearity is tested within 20mV of AGND and AVDD, allowing for gain and offset error. Codes above 2047 are guaranteed to be within ±9 LSB. Gain and offset tested within 100mV of AGND and AVDD. Guaranteed by design. Device draws current in excess of the specified supply current when a digital input is driven with a voltage of VVI < VDVDD 0.6V or VVI > 0.5V. At VVI = 2.2V with VDVDD = 5.25V, this current can be as high as 2mA. The SPI inputs are CMOS-input-level compatible. The 30MHz clock frequency cannot be guaranteed for a minimum signal swing. Note 7: Excess current from AVDD is 10mA when powered without DVDD. Excess current from DVDD is 1mA when powered without AVDD. Note 8: All timing specifications are with respect to the digital input and output thresholds. Note 9: Maximum daisy-chain clock frequency is limited to 25MHz. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: tCSW COMMAND EXECUTED ON 24th FALLING EDGE OF SCLK CS tCL tCSS tCH tCSH SCLK tDS DIN X C7 C6 C5 D3 tDH D2 D1 D0 X tSRL READY X = DON'T CARE. Figure 1. Serial-Interface Timing Diagram 4 Maxim Integrated MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. ANALOG SUPPLY VOLTAGE 6 7 5 5 -6 3 INL (LSB) INL (LSB) 1 -1 -3 -5 -5 -7 -7 -9 -9 16,384 32,768 49,152 -9 2.7 65,536 3.2 3.7 4.2 4.7 5.2 -40 20 40 60 80 TEMPERATURE (°C) DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE DIFFERENTIAL NONLINEARITY vs. ANALOG SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs. TEMPERATURE 0.6 0.8 0.6 1.0 0.8 0.6 0.4 0.2 0.2 0.2 -0.2 DNL (LSB) 0.4 DNL (LSB) 0.4 0 0 -0.2 0 -0.2 -0.4 -0.4 -0.4 -0.6 -0.6 -0.6 -0.8 -0.8 -0.8 -1.0 -1.0 16,384 32,768 49,52 -1.0 2.7 65,536 100 MAX5138 toc06 1.0 MAX5138 toc04 0.8 3.2 3.7 4.2 4.7 5.2 -40 -20 0 20 40 60 80 100 DIGITAL INPUT CODE (LSB) SUPPLY VOLTAGE (V) TEMPERATURE (°C) OFFSET ERROR vs. ANALOG SUPPLY VOLTAGE 12-BIT DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE 12-BIT INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE 6 0.08 0.06 0.04 2 0.02 DNL (LSB) 4 0 -2 0 -0.04 -6 -0.06 -8 -0.08 -10 3.7 4.2 SUPPLY VOLTAGE (V) Maxim Integrated 4.7 5.2 0.25 0 -0.25 -0.50 -0.75 -1.00 -0.10 3.2 0.75 0.50 -0.02 -4 1.00 INL (LSB) 8 MAX5138 toc09 0.10 MAX5138 toc07 10 2.7 0 SUPPLY VOLTAGE (V) 1.0 0 -20 DIGITAL INPUT CODE (LSB) MAX5138 toc05 0 1 -1 -3 MAX5138 toc08 INL (LSB) 0 -3 DNL (LSB) 7 3 3 OFFSET ERROR (mV) 9 MAX5138 toc02 9 MAX5138 toc01 9 INTEGRAL NONLINEARITY vs. TEMPERATURE MAX5138 toc03 MAX5138 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE 0 1024 2048 3072 DIGITAL INPUT CODE (LSB) 4096 0 1024 2048 3072 4096 DIGITAL INPUT CODE (LSB) 5 MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) -0.2 -0.4 -0.6 0.032 0.1 0 -0.1 -0.2 VAVDD = 5.25V VREF = 5V 0.028 0.024 0.020 0.016 -0.3 VAVDD = 2.7V VREF = 2.5V -0.8 -0.5 0 20 40 60 80 3.2 3.7 4.2 4.7 5.2 -40 0 20 40 60 100 TEMPERATURE (°C) ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE ANALOG SUPPLY CURRENT vs. TEMPERATURE ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE (POWER-DOWN MODE) 0.92 0.90 VOUT = 0 0.88 0.86 0.84 0.8 0.7 IAVDD 0.6 0.5 0.4 0.3 0.2 IDVDD 0.8 0 3.2 3.7 4.2 4.7 5.2 0.7 0.6 TA = -40°C 0.5 0.4 TA = +105°C 0.3 TA = +25°C 0.2 0.1 0.1 0.80 MAX5138 toc15 MAX5138 toc14 0.9 ANALOG SUPPLY CURRENT (μA) VOUT = VREFO 0.94 1.0 0.82 0 -40 -20 0 20 40 60 80 ANALOG SUPPLY VOLTAGE (V) TEMPERATURE (°C) EXITING/ENTERING POWER-DOWN MODE MAJOR CODE TRANSITION 100 2.7 3.2 3.7 4.2 5.2 SETTLING TIME UP MAX5138 toc18 500mV/div 20mV/div VOUT 4.7 SUPPLY VOLTAGE (V) MAX5138 toc17 MAX5138 toc16 500mV/div 4μs/div 6 80 SUPPLY VOLTAGE (V) 0.96 2.7 -20 TEMPERATURE (°C) VDVDD = 2.7V 0.98 0.008 2.7 100 ANALOG SUPPLY CURRENT (mA) 1.00 -20 MAX5138 toc13 -40 VAVDD = 2.7V VREF = 2.5V 0.012 -0.4 -1.0 ANALOG SUPPLY CURRENT (mA) 0.2 MAX5138 toc12 0.3 GAIN ERROR (%FS) VAVDD = 5.25V VREF = 5V 0 0.4 GAIN ERROR (%FS) 0.4 0.036 MAX5138 toc11 0.6 OFFSET ERROR (mV) 0.5 MAX5138 toc10 0.8 0.2 GAIN ERROR vs. TEMPERATURE GAIN ERROR vs. ANALOG SUPPLY VOLTAGE OFFSET ERROR vs. TEMPERATURE 1μs/div 400ns/div Maxim Integrated MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) SETTLING TIME DOWN DIGITAL FEEDTHROUGH MAX5138 toc19 MAX5138 toc20 SCLK 5V/div 500mV/div 50mV/div VOUT 400ns/div 40ns/div REFERENCE VOLTAGE vs. SUPPLY VOLTAGE TA = +25°C 2.4380 2.4380 2.4375 0.30 0.25 0.20 VREFO (V) 2.4375 2.4370 2.4365 TA = +105°C 0.10 2.4355 0.05 2.4350 2.4355 TA = -40°C 2.4350 2.4345 3.2 3.7 4.2 4.7 5.2 2.7 3.2 3.7 4.2 4.7 5.2 2.4345 -40 -20 0 20 40 60 DIGITAL SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) TEMPERATURE (°C) DIGITAL SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE FULL-SCALE OUTPUT vs. TEMPERATURE OUTPUT VOLTAGE vs. SUPPLY CURRENT UP 2.50 OUTPUT VOLTAGE (V) 2000 1500 DOWN 1000 2.51 2.49 EXTERNAL REF = 2.5V 2.48 2.47 2.46 2.45 INTERNAL REF 500 80 100 2.45 VAVDD = 5V 2.44 OUTPUT VOLTAGE (V) VAVDD = VDVDD = 5.25V MAX5138 toc24 2500 MAX5138 toc25 2.7 2.4365 2.4360 2.4360 0.15 2.4370 MAX5138 toc26 0.35 0 DIGITAL SUPPLY CURRENT (μA) 2.4385 VREFO (V) DIGITAL SUPPLY CURRENT (μA) 0.40 2.4385 MAX5138 toc22 VAVDD = 5.25V fSCLK = 1MHz 0.45 2.4390 MAX5138 toc21 0.50 REFERENCE VOLTAGE vs. TEMPERATURE MAX5138 toc23 DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE VAVDD = 3.3V 2.43 2.42 2.41 2.44 2.40 2.43 0 0 1 2 3 4 DIGITAL INPUT VOLTAGE (V) Maxim Integrated 5 6 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 0 10 20 30 OUTPUT CURRENT (mA) 7 MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) FULL-SCALE REFERENCE FEEDTHROUGH ZERO-SCALE REFERENCE FEEDTHROUGH MAX5138 toc27 MAX5138 toc28 VOUT 500mV/div VREF 500mV/div VREF 500mV/div 0 VOUT VOUT 20mV/div 0 VREF 20μs/div 20μs/div REFERENCE INPUT RESPONSE vs. FREQUENCY MAX5138 toc31 MAX5138 toc30 MAX5138 toc29 0 -5 ATTENUATION (dB) POWER-UP GLITCH, ZERO-SCALE, INTERNAL REFERENCE POWER-UP GLITCH, ZERO-SCALE, EXTERNAL REFERENCE 2V/div 2V/div -10 VAVDD VAVDD -15 -20 -25 -30 1V/div VOUT VOUT 1V/div -35 1 10 100 10,000 1000 4μs/div 4μs/div POWER-UP GLITCH, MIDSCALE, INTERNAL REFERENCE DC NOISE SPECTRUM, FFT PLOT BUFFERED OUTPUT INPUT FREQUENCY (kHz) POWER-UP GLITCH, MIDSCALE, EXTERNAL REFERENCE MAX5138 toc32 MAX5138 toc34 MAX5138 toc33 -40dBm 2V/div 2V/div RESOLUTION BANDWIDTH = 1Hz 50Ω LOAD VAVDD VAVDD 10dB/div 1V/div VOUT 1V/div VOUT 25kHz/div 4μs/div 8 4μs/div 2.5kHz/div Maxim Integrated MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs Pin Description PIN NAME FUNCTION 1, 4, 9 N.C. No Connection. Not internally connected. 2 M/Z Power-Up Reset Select. Connect M/Z low to AGND to power up the DAC output. Connect M/Z high to power up the DAC output to midscale. 3 LDAC Load DAC. Active-low hardware load DAC input. 5 SCLK Serial-Clock Input 6 CS Active-Low Chip-Select Input 7 DIN Data In 8 AGND Analog Ground. Internally connected to AGND. Connect AGND to AGND externally. 10 READY Data Output 11 DVDD Digital Power Supply. Bypass DVDD with a 0.1μF capacitor to AGND. 12 OUT 13 AVDD 14 REFI Reference Voltage Input. Bypass REFI with a 0.1μF capacitor to AGND. 15 REFO Reference Voltage Output 16 AGND — EP Buffered DAC Output Analog Power Supply. Bypass AVDD with a 0.1μF capacitor to AGND. DAC Ground. Internally connected to AGND. Connect AGND to AGND externally. Exposed Pad. Not internally connected. Connect EP to AGND or leave unconnected. Not intended as an electrical connection point. Detailed Description The MAX5138/MAX5139 are a family of single-channel, pin-compatible and software-compatible, 16-bit and 12bit DACs. The parts are low-power, buffered voltageoutput, high-linearity DACs. The MAX5138/MAX5139 minimize the digital noise feedthrough from input to output by powering down the SCLK and DIN input buffers after completion of each 24-bit serial input. On powerup, the MAX5138/MAX5139 reset the DAC output to zero or midscale, depending on the state of the M/Z input, providing additional safety for applications that drive valves or other transducers that need to be off on powerup. The MAX5138/MAX5139 contain a segmented resistor string-type DAC, a serial-in parallel-out shift register, a DAC register, power-on reset (POR) circuit, and control logic. On the falling edge of the clock (SCLK) pulse, the serial input (DIN) data is shifted into the device, MSB first. During power-down, an internal 80kΩ resistor pulls DAC outputs to AGND. Output Amplifier (OUT) The MAX5138/MAX5139 include an internal buffer for the DAC output. The internal buffer provides improved load regulation and transition glitch suppression for the DAC output. The output buffer slews at 1.25V/µs and drives up Maxim Integrated to 2kΩ in parallel with 200pF. The analog supply voltage (AVDD) determines the maximum output voltage range of the device as AVDD powers the output buffer. DAC Reference Internal Reference The MAX5138/MAX5139 feature an internal reference with a nominal +2.44V output. Connect REFO to REFI when using the internal reference. Bypass REFO to AGND with a 47pF (maximum 100pF) capacitor. Alternatively, if heavier decoupling is required, add a 1kΩ resistor in series with a 1µF capacitor in parallel with the existing 100pF capacitor. REFO can deliver up to 100µA of current with no degradation in performance. Configure other reference voltages by applying a resistive potential divider with a total resistance greater than 33kΩ from REFO to AGND. External Reference The external reference input features a typical input impedance of 113kΩ and accepts an input voltage from +2V to AVDD. Connect an external voltage supply between REFI and AGND to apply an external reference. Leave REFO unconnected. Visit www.maximintegrated.com/products/references for a list of available external voltage-reference devices. 9 MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs AVDD as Reference Connect AVDD to REFI to use AVDD as the reference voltage. Leave REFO unconnected. data bits (MSB first), as shown in Table 1. The serial input register transfers its contents to the input registers after loading 24 bits of data. To initiate a new data transfer, drive CS high and keep CS high for a minimum of 33ns before the next write sequence. The SCLK can be either high or low between CS write pulses. Figure 1 shows the timing diagram for the complete 3-wire serialinterface transmission. The MAX5138/MAX5139 digital input is double buffered. Depending on the command issued through the serial interface, the input register can be loaded without affecting the DAC register using the write command. To update the DAC register, either pulse the LDAC input low, or use the software LDAC command. Use the writethrough commands (see Table 1) to update the DAC output immediately after the data is received. Only use the writethrough command to update the DAC output immediately. Serial Interface The MAX5138/MAX5139 3-wire serial interface is compatible with MICROWIRE, SPI, QSPI, and DSPs (Figures 2, 3). The interface provides three inputs, SCLK, CS, and DIN and one output, READY. Use READY to verify communication or to daisy-chain multiple devices (see the READY section). READY is capable of driving a 20pF load with a 30ns (max) delay from the falling edge of SCLK. The chip-select input (CS) frames the serial data loading at DIN. Following a chip-select input’s high-to-low transition, the data is shifted synchronously and latched into the input register on each falling edge of the serial-clock input (SCLK). Each serial word is 24 bits. The first 8 bits are the control word followed by 16 Table 1. Operating Mode Truth Table 24-BIT WORD CONTROL BITS DATA BITS MSB LSB C7 C6 C5 C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 X X X X X X X X D7 D6–D0 X X DESC NOP No operation. Set DAC = 1 to move contents of input to DAC register. Setting DAC = 0 results in no operation. 0 0 0 0 0 0 0 1 X X X X X X X DAC X X LDAC 0 0 0 0 0 0 1 0 X X X X X X X X X CLR 0 0 0 0 0 0 1 1 X X X X X X 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 X X X X DAC READY_EN LIN 0 X DAC D15 D14 D13 D12 D11 D10 D9 D8 0 0 1 1 X X X DAC D15 D14 D13 D12 D11 D10 D9 D8 0 0 1 0 0 0 0 0 X X X X X X X X 0 D7 FUNCTION Software clear. X Set DAC = 1 to power down DAC. Set Power READY_EN = 1 to Control enable READY. Setting DAC = 0 results in no operation. 0 Linearity Optimize DAC linearity. D6 D7 D6 X X Write Write to selected input registers (DAC output not affected). Setting DAC = 0 results in no operation. Write to selected input and DAC register, Write- DAC output updated through (writethrough). Setting DAC = 0 results in no operation. NOP No operation. *For the MAX5139, D3–D0 are X = don’t-care bits. 10 Maxim Integrated MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs The MAX5138’s DAC code is unipolar binary with VOUT = (code/65536) x VREF. See Table 1 for the serial interface commands. The MAX5139’s DAC code is unipolar with V OUT = (code/4096) x VREF. See Table 1 for the serial interface commands. D15–D0 are the data bits that are written to the internal register. 3) After clocking in the last data bit, drive CS high. CS must remain high for 33ns before the next transmission is started. Figure 1 shows a write operation for the transmission of 24 bits. If CS is driven high at any point prior to receiving 24 bits, the transmission is discarded. Connect the MAX5138/MAX5139 DVDD supply to the supply of the host DSP or microprocessor. The AVDD supply may be set to any voltage within the 2.7V to 5.25V operating range, but must be greater than or equal to the DVDD supply. READY Connect READY to a microcontroller (µC) input to monitor the serial interface for valid communications. The READY pulse appears 24 clock cycles after the negative edge of CS (Figure 4). Since the MAX5138/ MAX5139 look at the first 24 bits of the transmission following the falling edge of CS, it is possible to daisy chain devices with different command word lengths. READY goes high 16ns after CS is driven high. Writing to the MAX5138/MAX5139 Write to the MAX5138/MAX5139 using the following sequence: 1) Drive CS low, enabling the shift register. 2) Clock 24 bits of data into DIN (C7 first and D0 last), observing the specified setup and hold times. Bits +5V MAX5138 MAX5139 SCLK SK DIN SO MICROWIRE PORT READY* SI* CS I/O MISO* READY* MAX5138 MAX5139 MOSI DIN SPI/QSPI PORT SCK SCLK *THE READY-TO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE *MAX5138/MAX5139 BUT MAY BE USED FOR TRANSMISSION VERIFICATION. SS I/O CS *THE READY-TO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5138/MAX5139 BUT MAY BE USED FOR TRANSMISSION VERIFICATION. Figure 3. Connections for SPI/QSPI Figure 2. Connections for MICROWIRE CS DIN SLAVE 1 DATA SLAVE 2 DATA SLAVE 3 DATA SCLK 1 2 3 4 20 21 22 23 24 1 2 3 4 5 21 22 23 24 1 2 3 4 5 21 22 23 24 READY 1 READY 2 READY 3 Figure 4. READY Timing Maxim Integrated 11 MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs Daisy chain multiple MAX5138/MAX5139 devices by connecting the first device conventionally, then connect its READY output to the CS of the following device. Repeat for any other devices in the chain, and drive the SCLK and DIN lines in parallel (Figure 5). When sending commands to daisy-chained MAX5138/MAX5139s, the devices are accessed serially starting with the first device in the chain. The first 24 data bits are read by the first device, the second 24 data bits are read by the second device and so on (Figure 4). Figure 6 shows the configuration when CS is not driven by the µC. These devices can be daisy chained with other compatible devices, such as the MAX5510 and the MAX5511. To perform a daisy-chain write operation, drive CS low and output the data serially to DIN. The propagation of the READY signal then controls how the data is read by each device. As the data propagates through the daisy chain, each individual command in the chain is executed on the 24th falling clock edge following the falling edge of the respective CS input. To update just one device in a daisy chain, send the no-op command to the other devices in the chain. If READY is not required, write command 0x03 (power control) and set READY_EN = 0 (see Table 1) to disable the READY output. Clear Command The MAX5138/MAX5139 feature a software clear command (0x02). The software clear command acts as a software POR, erasing the contents of all registers. The output returns to the state determined by the M/Z input. Power-Down Mode The MAX5138/MAX5139 feature a software-controlled power-down mode. The internal reference and biasing circuits power down to conserve power when powered down. In power-down, the output disconnects from the buffer and is grounded with an internal 80kΩ resistor. The DAC register holds the retained code so that the output is restored when powered up. The serial interface remains active in power-down mode. Load DAC (LDAC) Input The MAX5138/MAX5139 feature an active-low LDAC logic input that updates the output. Keep LDAC high during normal operation (when the device is controlled only through the serial interface). Drive LDAC low to update the DAC output with data from the input register. Figure 7 shows the LDAC timing with respect to OUT. Holding LDAC low causes the input register to become transparent and data written to the DAC register to immediately update the DAC output. A software command can also activate the LDAC operation. To activate LDAC by software, set control word 0x01 to load the DAC, and all other data bits to don’t care. See Table 1 for the data format. This operation updates the DAC output if it is flagged with a 1. If the DAC output is flagged with a 0 it remains unchanged. μC MOSI SCK SLAVE 1 DIN DIN SCLK I/O CS SLAVE 2 DIN SCLK READY CS SLAVE 3 SCLK READY CS READY Figure 5. Daisy-Chain Configuration 12 Maxim Integrated MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs TO OTHER CHIPS/CHAINS CSm μC SLAVE 1 CS1 CS SCLK DWRITE DREAD INT CS SCLK MAX5138 DIN MAX5139 READY SLAVE 2 CS SCLK MAX5138 MAX5139 DIN READY SLAVE N CS SCLK MAX5138 DIN MAX5139 DOUT ERROR READY Figure 6. Daisy Chain (CS Not Used) tLDACPWL LDAC tS ±2 LSB OUT Figure 7. Output Timing Maxim Integrated 13 MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs Applications Information Power-On Reset (POR) On power-up, the input register is set to zero, and the DAC output powers up to zero or midscale, depending on the configuration of M/Z. Connect M/Z to AGND to power the output to AGND. Connect M/Z to AVDD to power the output to midscale. To guarantee DAC linearity, wait until the supplies have settled. Set the LIN bit in the DAC linearity register; wait 10ms, and clear the LIN bit. Unipolar Output The MAX5138/MAX5139 unipolar output voltage range is 0 to VREFI. The output buffer drives a 2kΩ load in parallel with 200pF. Bipolar Output Use the MAX5138/MAX5139 in bipolar applications with additional external components (see the Typical Operating Circuit). Power Supplies and Bypassing Considerations For best performance, use a separate supply for the MAX5138/MAX5139. Bypass both DVDD and AVDD with high-quality ceramic capacitors to a low-impedance ground as close as possible to the device. Minimize lead lengths to reduce lead inductance. Connect both MAX5138/MAX5139 AGND inputs to the analog ground plane. Table 2. MAX5138 Input Code vs. Output Voltage DAC LATCH CONTENTS MSB 14 ANALOG OUTPUT, VOUT LSB 1111 1111 1111 1111 VREF x (65,535/65,536) 1000 0000 0000 0000 VREF x (32,768/65,536) = 1/2 VREF 0000 0000 0000 0001 VREF x (1/65,536) 0000 0000 0000 0000 0 Layout Considerations Digital and AC transient signals on AGND inputs can create noise at the outputs. Connect both AGND inputs to form the star ground for the DAC system. Refer remote DAC loads to this system ground for the best possible performance. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to the MAX5138/MAX5139 AGND. Do not use wire-wrapped boards and sockets. Use shielding to improve noise immunity. Do not run analog and digital signals parallel to one another (especially clock signals) and avoid routing digital lines underneath the MAX5138/MAX5139 package. Definitions Integral Nonlinearity (INL) INL is the deviation of the measured transfer function from a best fit straight line drawn between two codes. This best fit line for the MAX5138 is a line drawn between codes 3072 and 64,512 of the transfer function and the best fit line for the MAX5139 is a line drawn between codes 192 and 4032 of the transfer function, once offset and gain errors have been nullified. Differential Nonlinearity (DNL) DNL is the difference between an actual step height and the ideal value of 1 LSB. If the magnitude of the DNL is greater than -1 LSB, the DAC guarantees no missing codes and is monotonic. Table 3. MAX5139 Input Code vs. Output Voltage DAC LATCH CONTENTS MSB ANALOG OUTPUT, VOUT LSB 1111 1111 1111 XXX 1000 0000 0000 XXX VREF x (4095/4096) 0000 0000 0001 XXX 0000 0000 0000 XXX VREF x (1/4096) VREF x (2048/4096) 0 Maxim Integrated MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs Offset Error Digital-to-Analog Glitch Impulse Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point. Typically, the point at which the offset error is specified is at or near the zero-scale point of the transfer function. A major carry transition occurs at the midscale point where the MSB changes from low to high and all other bits change from high to low, or where the MSB changes from high to low and all other bits change from low to high. The duration of the magnitude of the switching glitch during a major carry transition is referred to as the digital-to-analog glitch impulse. Gain Error Gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Settling Time The settling time is the amount of time required from the start of a transition, until the DAC output settles to the new output value within the converter’s specified accuracy. Digital-to-Analog Power-Up Glitch Impulse The digital-to-analog power-up glitch is the duration of the magnitude of the switching glitch that occurs as the device exits power-down mode. Chip Information PROCESS: BiCMOS Digital Feedthrough Digital feedthrough is the amount of noise that appears on the DAC output when the DAC digital control lines are toggled. Functional Diagram AVDD MAX5138 MAX5139 M/Z DVDD AGND REFI REFO INTERNAL BIAS CKT REFERENCE POR CONTROL LOGIC POWER-DOWN CONTROL CS SCLK SERIAL-TOPARALLEL CONVERTER INPUT REGISTER DAC REGISTER 12-/16-BIT DAC DIN READY Maxim Integrated LDAC OUT BUFFER AGND 15 MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs Typical Operating Circuit DIGITAL POWER SUPPLY ANALOG POWER SUPPLY 100nF 100nF 100nF DVDD AVDD M/Z LDAC OUT DAC CS SCLK DIN READY MAX5138 MAX5139 REFO R1 R2 REFI 47pF AGND *SHOWN IN BIPOLAR CONFIGURATION Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 16 PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 16 TQFN-EP T1633+5 21-0136 90-0032 Maxim Integrated MAX5138/MAX5139 Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 3/09 Initial release — 1 4/09 Removed future product reference for MAX5139 1 2 10/12 Correct errors in data sheet 1–4, 9, 10 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2012 Maxim Integrated Products, Inc. 17 Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.