SNL320 16-Bit LCD Controller ======== CONTENTS ======== 1. INTRODUCTION.........................................................................................................................5 2. FEATURES ...................................................................................................................................5 3. PIN ASSIGNMENTS....................................................................................................................5 4. MEMORY .....................................................................................................................................6 4.1 INTERNAL ROM..........................................................................................................................6 4.2 INTERNAL RAM..........................................................................................................................6 5. CLOCK SYSTEM ........................................................................................................................7 5.1 NORMAL MODE...........................................................................................................................8 5.2 LOW-SPEED MODE .......................................................................................................................8 5.3 STOP MODE .................................................................................................................................8 5.4 SUSPEND MODE ..........................................................................................................................8 5.5 WATCH MODE ............................................................................................................................9 6. POWER ON RESET ....................................................................................................................9 7. I/O PORT.......................................................................................................................................9 8. TIMER/COUNTER ....................................................................................................................10 9. DA & PUSH-PULL.....................................................................................................................11 9.1 DAC .........................................................................................................................................11 9.2 PUSH-PULL ...............................................................................................................................11 10. INTERNAL REGULATOR ..................................................................................................12 11. LOW VOLTAGE DETECTOR............................................................................................13 12. EXTENSION BUS .................................................................................................................13 12.1 WORD MODE CONNECTION ......................................................................................................14 12.2 BYTE MODE CONNECTION ........................................................................................................14 12.3 MAXIMUM MEMORY EXPEND ...................................................................................................17 12.4 NAND FLASH INTERFACE ........................................................................................................17 13. USB INTERFACE .................................................................................................................18 14. LCD INTERFACE.................................................................................................................18 Ver: 1.4 1 April 18, 2006 SNL320 16-Bit LCD Controller 14.1 LCD CONTROLLER INTERFACE (8-BIT INTERFACE)...................................................................18 14.2 LCD DRIVER INTERFACE (1/4 BITS INTERFACE) .......................................................................21 14.3 CONTROL SIGNALS....................................................................................................................21 14.4 LCD RAM MAPPING ................................................................................................................21 15. APPLICATION CIRCUIT......................................................................................................4 16. ABSOLUTE MAXIMUM RATINGS ....................................................................................4 17. ELECTRICAL CHARACTERISTICS..................................................................................4 18. BONDING PAD .......................................................................................................................5 Ver: 1.4 2 April 18, 2006 SNL320 16-Bit LCD Controller AMENDENT HISTORY Version Date Description Ver 0.1 February 5, 2004 Preliminary spec first issue Ver 0.2 March 6, 2004 Modify RAM size from 6KW -> 10KW in Page3 Ver 0.3 June 13, 2004 Modify Pin assignment Modify RAM size from 10KW -> 11KW in Page3 Modify int. ROM size from 48KW->64KW in page3 Modify Pin assignments Modify extension bus descriptions, add byte/word mode connection Add new section “Low Voltage Detector” and “Internal Regulator” Ver 0.4 July 28, 2004 Wording modification of pin assignment in Page 4 Ver 0.5 December 7, 2004 1. Removed UART interface, added USB 1.1 interface 2. Reduce internal RAM size from 11KW to 8KW (4KW for general purpose, 4KW for LCD display buffer) 3. LCD display only support 120x240 / 4 gray-level LCD display. (LCD RAM: 0xB000~0xBFFF) 4. Move general purpose SRAM address to 0xA000~0xAFFF Ver 0.6 December 10, 2004 1. Page18 Correct word editing error on LCD RAM. Ver 0.7 December 14, 2004 1. Page21~22 Correct word editing error on LCD RAM. Ver 0.8 February 25, 2005 1. Correct LCD RAM description on Page 6 2. Modify interrupt sources of “Features” 3. Modify pin assignment 4. Added another 1K word SRAM (0x0000~0x03FF), Page4, 6, 7 5. Added pad information Ver 1.0 May 30, 2005 1. Modify USB descriptions Ver 1.1 June 29, 2005 1. Added application circuit 2. Correct some error editing on page9 3. Correct the clock source option table (page8) 4. Remove the RTC 0.125s option (page9) 5. Replace PWM instead of Push-Pull DAC (page11) Ver 1.2 July 22, 2005 1. Correct bonding pad information (P4.2) Ver 1.3 July 25, 2005 1. Correct bonding pad information, pin 113 is “CKSEL” and pin111 is “EDWS” Ver: 1.4 3 April 18, 2006 SNL320 16-Bit LCD Controller Version Ver 1.4 Date April 18 , 2006 Description 1. delete Low clock RC source describe (Page 5,7,8,9) 2. correct support 4-gray LCD (Page 5) 3. add PLL = 1 and CKSEL = 1 is reversed (Page 8) 4. add Note : If chip is halted , SNL320 internal Regulator will be disable (Page 13) 5. correct LCD RAM size 4K and add note: only support 4MHZ LCD clock source (Page 22) Ver: 1.4 4 April 18, 2006 SNL320 16-Bit LCD Controller 1. INTRODUCTION The SNL320 is a high performance 16-bit DSP base processor with 16MIPS CPU power. The internal 64K words hi-speed ROM already built-in a hi-performance software voice synthesizer to provides lot of voice effects. Such as hi-decompression engine to support from 1.5kbps ~ 29kbps compression rate for speech and music, multi-channel voice synthesizer to provides 8-channel wave-table melody, or support foreground 1.5kbps~29kbps and background 4-channel wave-table melody. The standard microprocessor interface allows SNL320 to extend its memory capability, or connect external device. We also built-in a Low Voltage Detector circuit for power management and a USB 1.1 interface for communication with PC. 2. ♦ FEATURES ♦ Power supply: RAM size: 9k*16 bits (including LCD RAM) 2.4V ~ 3.6V (for 2 batteries application) − 5K*16 SRAM size for general purpose 3.6V ~ 5.1V (for 3 batteries application) − 4K*16 for LCD display buffer ♦ Built-in regulator for DSP core ♦ Three 8-bit timers with auto-reload function ♦ Built-in 16-bit DSP core ♦ Programmable watchdog timer ♦ Software-based voice/melody processing ♦ LCD control interface ♦ Rich Function Instruction Set ♦ 16 MIPS CPU performances under 16MHz ♦ Clock system − − − external LCD driver − Share LCD display RAM with internal 16MHz crystal or R-C type oscillator SRAM, support 240x120 LCD display for hi-speed system clock screen − 32768HZ crystal oscillator for RTC H/W support maximum 4 gray-level LCD display and low-speed system clock ♦ Support 1-bit/4-bit LCD data bus for Extension bus ♦ Built-in 32768 crystal for Real Time Clock − ♦ Two voice/melody channels or 4 channels Standard Byte-mode and Word-Mode wave-table melody bus interface − 4 chip select pins for external devices ♦ fixed current D/A output (such as ROM, Flash, SRAM..etc) − Built in Push-Pull direct drive circuit and Maximum 128M-bit addressing ♦ Sampling Rate: 4KHz ~16KHz capability for signal external memory ♦ Built-in software voice synthesizer for multiple bit-rate solution device I/O Ports: 36 I/O pins (P1.0~P1.15, ♦ USB 1.1 interface provided P3.0~P3.15, P4.0~P4.3) ♦ Low Voltage Detector ♦ ROM size: 64K*16 bits ♦ Low Voltage Reset ♦ 9 Interrupt Sources ♦ − 5 internal interrupt (T0, T1, T2, RTC and USB) − 3 external interrupt (P3.0~P3.2) − 1 DA/Push-Pull output Ver: 1.4 5 April 18, 2006 SNL320 16-Bit LCD Controller 3. PIN ASSIGNMENTS Symbol VDDA VSSA VDDEBUS VSSEBUS VDDIO2 VSSIO2 PPVDD PPVSS VDDIO1 VSSIO1 CVDD CVSS RVDD VOUT PLLCAP XIN XOUT LXIN LXOUT CKSEL PLLEN BP0 BN0 VO0 RSTB TEST EA0~EA22 ED0~D15 WR\ RD\ EDWS D+ DPWR+ PWRP1.0~P1.15 Ver: 1.2 Descriptions No. of PIn Positive power for OSC 1 Negative power for OSC 1 Positive power for EA0~DA22 & ED0~ED15 2 Negative power for EA0~DA22 & ED0~ED15 3 Positive power for P3.3~P3.15 & P4.0~P4.3 1 Negative power for P3.3~P3.15 & P4.0~P4.3 1 Positive power for Push-Pull DAC 1 Negative power for P.P. DAC 2 Positive power for P1.0~P1.15 & P3.0~P3.2 1 Negative power for P1.0~P1.15 & P3.0~P3.2 1 Positive power for DSP core logic 2 Negative power for DSP core logic 1 Positive power for regulator 1 Regulator voltage output 1 Cap pin for PLL 1 High speed clock crystal input / RC-type 1 oscillator input High speed clock crystal output / RC-type 1 oscillator input Low speed clock crystal input 1 Low speed clock crystal output 1 Crystal/RC-type oscillator select for high speed 1 clock PLL Enable/Disable control 1 Push-Pull DA output 1 Push-Pull DA output 1 DAC output 1 Chip reset 1 For test only 1 Address bus of extension bus 23 Data bus of extension bus 16 Write signal of extension bus 1 Read signal of extension bus 1 Extension bus width select 1 0: 8-bit (byte mode) 1: 16-bit (word mode) USB Data + 1 USB Data 1 USB power + 1 USB power 1 General I/O port P1.0~P1.15 16 5 Pin Count 1 2 4 7 8 9 10 12 13 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 54 70 71 72 73 74 75 76 77 93 July 22, 2005 SNL320 16-Bit LCD Controller Symbol P3.0~P3.15 P4.0~P4.3 4. Descriptions General I/O port P3.0~P3.15 P3.0: INT0 P3.1: INT1 P3.2: INT2 / IR output P3.3: NCSB P3.4: CLE P3.5: ALE P3.6: R/B\ P3.7: WPB P3.8: CS3/EA23 P3.9: CS2 P3.10: CS1 P3.11: CS0 P3.12: LACD P3.13: LCLK P3.14: LP P3.15: FP General I/O port P4.0~P4.3 LCD data bus No. of PIn 16 Pin Count 109 4 113 MEMORY 4.1 Internal ROM SNL320 provides hi-compression algorithm to compress voice data in order to save more memory size. So all the de-compression program are built in the internal ROM of SNL320 and system will reserved some necessary ROM space for those de-compression program automatically once user active the de-compression function. There are totally 64K words of SNL320 internal ROM, user can built-in his own program in the internal ROM for his application except necessary space for de-compression program. 4.2 Internal RAM The internal totally 9K words RAM will be separated into two parts, the SRAM regions 0xA000~0xAFFF and 0x0000~0x03FF are reserved for system and user’s application, the SRAM regions 0xB000~0xBFFF is reserved for LCD display buffer. User has to define the actual LCD display buffer region by set LBUFL (LCD display buffer register). Ver: 1.2 6 July 22, 2005 SNL320 16-Bit LCD Controller 0x0000 : : Free for User 1KW 0x03FF 0x0400 : : : : : : No Used 0x0FFF 0xA000 : : : : : : Reserved for System & User 4KW LCD buffer start pointer 0xAFFF 0xB000 : : : : : : LCD Display Buffer 4KW 0xBFFF 5. Clock System SNL320 is a dual clock system that it both provides high-speed clock (16MHZ) and low-speed clock (32768HZ). There two different way to get the hi-speed clock, one is generate by external 16MHZ crystal and another way is through external 6MHZ pumping to 16MHZ by the internal PLL circuit. The pin option “PLLEn” is used to enable/disable internal PLL circuit. PLLEn LCD driver clock source PCR.STPCK RCTune CKSEL PCR.STPCK PLLEn system clock low-speed clock XIN XOUT 6MHZ Rosc/ X'tal 16MHZ /512 PLL RTC clock cource PCR.MCS PCR.STPMD PCR.RTCCKS CAP Figure-1 Clock system block diagram Ver: 1.2 7 July 22, 2005 SNL320 16-Bit LCD Controller 5.1 Normal Mode The normal mode means CPU main clock source is comes from 16MHZ Rosc or crystal hi-speed clock source, so SNL320 is run in full speed. There are two pins option “CKSEL” and “PLLEn” to select Rosc/crystal and enable/disable PLL circuit. The detail setting of hi-speed clock is shown as following table. CKSEL 0 0 1 1 PLLEn Descriptions 0 16MHZ X’tal for hi-speed clock source 1 6MHZ X’tal and pumping to 16MHZ for hi-speed clock source. (for USB application) 0 16MHZ Rosc for hi-speed clock source 1 reserved 5.2 Low-speed mode This is a special operation mode of SNL320, the hi-speed clock is disable and main clock of SNL320 is comes from low-speed clock source (32768HZ). It will save more power consumption when chip works on this low-speed mode and this low-speed clock can select 32768HZ crystal for clock source. In additional, this low-speed clock also used to calibrate the hi-speed clock once the high-speed clock source is comes from Rosc. 5.3 Stop Mode In stop mode, all the system clocks are stop (16MZH & 32768HZ) and chip entry a very low power consumption state. Chip will wake-up from stop mode once any IO state change or external interrupt occurs. 5.4 Suspend Mode In suspend mode, the hi-speed clock still working but chip is hold until any IO toggle or external interrupt occurs. That means, the power consumption only come from HXOSC circuit and LCD driver interface refresh circuit. Ver: 1.2 8 July 22, 2005 SNL320 16-Bit LCD Controller 5.5 Watch Mode This mode is for some real time clock application, users have to add a 32768HZ crystal to realize RTC function. Considering to saving power consumption, user should stop the hi-speed clock source (16MHZ) and enable the low-speed clock source. Then chip will entry power down mode but the low-speed clock still working and wake-up chip once the RTC period is happened in order to fresh the RTC timer. There are four options for RTC interrupt period, users can select 0.25sec/0.5sec and 1sec through the RTC control register. If chip is in power-down mode and interrupt enable is active for RTC, then chip will be wake-up from power-down mode per 0.25/0.5/1 second. 6. POWER ON RESET When “L” level appears on RESET PIN, the chip will enter RESET state. After reset, the chip does not execute the first instruction until counting 217 clock cycles. It takes around 8.2ms at 16MHz. (crystal for clock source), and the location of the first instruction after RESET is 0x000000. In additional, all the contents of SRAM will be unchanged during RESET stage. 7. I/O PORT SNL320 provides totally 36 I/O pins (P1.0~P1.15, P3.0~P3.15, P4.0~P4.3). The input pull-high resistor of each pin can be programmed by port pull-high register and the direction of I/O port is selected by port direction register. The I/O port P1.0~P1.15 can wake the chip up from the stop mode and watch mode. These 36 programmable I/O pins provides not only a simply input/output function but also can configure to be chip select pins of extension bus, LCD driver interface and NAND flash interface. For the detail please refer to following sections. The internal structure of I/O pins is showed in Figure-2. Ver: 1.2 9 July 22, 2005 SNL320 16-Bit LCD Controller Pull-Up Resister In/Out Control Pull-Up Select I/O PAD Data Latch to internal bus In/Out Control I/O Configuration of Port1, Port3 and Port4 Figure-2 In some applications (e.g., Infra Red, IR), an output port needs to be modulated a carry signal. In the cases, the routine of modulation will occupy too many CPU computations. Thus, a modulation circuit is built in chip to reduce CPU’s loading. IREN P3.2 I/O Pad overflow Timer2 Figure-3 The modulation function will be active when the control bit “IREN” set to “1”. And setting timer2 can generate the frequency of carry signal. 8. TIMER/COUNTER SNL320 provides three 8-bit timer/event counters (T0/T1/T2). Each timer is 8-bit binary up-count timer with pre-scalar and auto-reload function. Timer 0 (T0) was used when voice playing, so user should avoid to use T0. Ver: 1.2 10 July 22, 2005 SNL320 16-Bit LCD Controller (8-bit) /2 TnC /4 system clock /2 /8 MUX Time Out 8-bit Up-Counter comparator /256 Pre-scalar clear Enable Auto-reload Figure-4 9. DA & Push-Pull To play out voices, SNL320 contains two different solutions for the user’s applications, DAC and Push-Pull. The user can choose one of these two solutions in this design. Only one function can be activated at one time. 9.1 DAC A 10-bit current type digital-to-analog converter is built-in SNL320. The relationship between input digital data and output analog current signal is listed in the following table. Also, the recommended application circuit is illustrated as follows. Input data 0 1 … n … 1024 Typical value of output current (mA) 0 3/1024 n*(3/1024) 3 9.2 Push-Pull A Push-Pull Direct Drive circuit is built-in SNL330. The maximum resolution of Push-Pull is 10 bits. Two huge output stage circuits are designed in SNL330. With this advanced circuit, the chip is capable of driving speaker directly without external transistors. Ver: 1.2 11 July 22, 2005 SNL320 16-Bit LCD Controller VCC BUO1/VO BUO1/VO BUO2 1K DAC output Push-Pull output 10. Internal Regulator The power system of SNL320 can be separated into two groups, one is 3V and another one is 5V. The power of core logic and SRAM, ROM is comes from 3V power group. And the power of all I/O, DA/Push-Pull, clock system is comes from 5V power group. Considering user’s application, SNL320 built-in a regulator to solve the different power problem. Please refer to the following connection diagram. SNL320 VDDIO SNL320 3V 5V VDDIO CVDD CVDD VOUT_REG VOUT_REG C1 3V power system 5V power system For 3V power system (2 batteries application), all the power pins should be connected together. Ver: 1.2 12 July 22, 2005 SNL320 16-Bit LCD Controller For 5V power system (3 batteries application), the power pin of core logic CVDD pin should be connected to VOUR_REG in order to get an accurate 2.8V power. Once chip entry power down mode, the regulator will also turn off automatically. And this regulator also built-in a LVD circuit to detect the power dropping of VOUT_REG. The regulator will auto turn on to re-charge the power of external CAP C1 when the voltage of VOUT_REG is lower then 2.2V, it will make sure to provides enough power for CVDD to keep the value of SRAM. Note : If chip is halted , SNL320 internal Regulator will be disable 11. Low Voltage Detector SNL320 built in a low voltage detector for power management. It provides four different detect level, 2.3V, 2.5V, 2.8V and 3.1V. User can set an expect detect level through the PCR control register and polling the acknowledge bit to get the current power level is higher or lower then the detect level. Each detect level is designed by schmitt trigger architecture, that’s means each detect level has a detect window. For example, the detect window of detect level 2.3V is 2.24V ~ 2.36V. When the VDD power down below 2.24V, the detect bit of PCR register will be set to 1. Once VDD power is recovered and must be higher then 2.36V, then detect bit is clear by system. Detect level Voltage window of schmitt trigger 2.3V 2.24V ~ 2.36V 2.5V 2.44V ~ 2.57V 2.8V 2.72V ~ 2.88V 3.1V 3.01V ~ 3.19V 12. EXTENSION BUS SNL320 built-in a standard micro-controller interface extends the memory capability through the extension bus. In additional, SNL320 both provides byte mode and word mode access bus for external memory device in order to improve the efficiency. This extension bus also allows users to connect different external devices for his own application, such as ROM, RAM, NAND flash, 8-bit interface LCD controller etc. There are 4 chip select pins for external devices, so totally SNL320 can connect 4 different devices. The maximum addressing capability of each external device is 64M-bit except CS0. Because the ROM bank of CS0 is shared with internal ROM of SNL320, so the maximum addressing capability of CS0 is only 32M-bit. In additional, user can put his program into each external memory device not only data. Ver: 1.2 13 July 22, 2005 SNL320 16-Bit LCD Controller 12.1 Word Mode Connection Most of hi-density memory both provides word mode access, so SNL320 also support word mode access bus by the pin option “EDSW”. Once the pin “EDSW” is connected to VDD, means the bus width of extension bus will turn to be 16-bit width, the connection diagram is shown as bellow. In word mode bus access, SNL320 can fetch a complete OP code or data through the 16-bit width bus at one time, and it is helpful to improved the CPU efficiency when CPU running the program from external memory device. Most important, once the word access is selected, all the data access will fixed at 16-bit mode. So if user connected a 8-bit width external device, the bus pin ED[8..15] of extension bus don’t need to be connected. SNL320 64M FLASH EA0~EA21 EA[0..21] A0~A21 ED0~ED15 ED[0..15] Q[0..15] RD\ OE\ CS1\ CE\ EDWS VDD BYTE\ VDD Flash Memory Word Mode Connection Note: The bit14 of EBCR control register MUST set to be “1”. 12.2 Byte Mode Connection Considering the bus interface of some external devices and memory are also only 8-bit bus width, so SNL320 also support the byte mode access bus for this kind of device. In byte mode, only data pins ED[0..7] are valid and ED[8..15] are no used. In byte mode connection, SNL320 provides two different modes for data access, one is 8-bit mode and another is 16-bit mode. The detail description is shown as following section. Ver: 1.2 14 July 22, 2005 SNL320 16-Bit LCD Controller 12.2.1 16-bit Mode In 16-bit mode, all the data and OP code fetch are base on 16-bit data width. In another hand, SNL320 will fetch data or OP code from external memory two times automatically, in order to get a complete 16-bit width data. SNL320 64M FLASH EA0~EA22 A[-1~A21] EA[0..22] ED0~ED7 Q[0..7] ED[0..7] ED[8..15] RD\ OE\ CS1\ CE\ EDWS BYTE\ DSP 16-bit mode (for flash Byte mode connection) Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Word 1 Word 2 Read from SNL320 0x000000 0x000001 0x000002 0x000003 0x000004 0x000005 : : : : : : : : ROM/Flash/SRAM Note: The bit14 of EBCR control register MUST set to be “1”. 12.2.2 8-bit Mode SNL320 also reserved a 8-bit mode data access for user’s application. The only one different is the addressing capability of 8-bit and 16-bit mode. In 16-bit mode, the maximum addressing capability of each chip select pin (CS1~CS3) is 64M-bit (CS0 is only 32M-bit) because the address pin EA[22]. In 8-bit mode, the EA[22] is a invalid address pin, so all the addressing capability calculation is only a half of 16-bit mode. Ver: 1.2 15 July 22, 2005 SNL320 16-Bit LCD Controller SNL320 MX29LV064 EA0~EA22 A[-1~A21] EA[0..22] ED0~ED7 Q[0..7] ED[0..7] ED[8..15] RD\ OE\ CS1\ CE\ EDWS BYTE\ DSP 8-bit mode (for flash Byte mode connection) Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte1 Byte2 Read from SNL320 0x000000 0x000001 0x000002 0x000003 0x000004 0x000005 : : : : : : : : ROM/Flash/SRAM Note: The bit14 of EBCR control register MUST set to be “0”. Device No. Start address End Address Memory Size Internal ROM 0x0000000 0x000FFFF 64K words Reserved 0x0010000 0x01FFFFF 1984K words st 1 external device 0x0200000 0x03FFFFF 2M words nd 0x0400000 0x07FFFFF 4M words rd 0x0800000 0x0BFFFFF 4M words th 0x0C00000 0x0FFFFFF 4M words 2 external device 3 external device 4 external device Table-1 Addressing Capability (16-Bit Mode) Ver: 1.2 16 July 22, 2005 SNL320 16-Bit LCD Controller 12.3 Maximum Memory Expend SNL320 also provides a special function extend the memory size from 64M-bit up to 128M-bit for single external device. The chip select pin “CS3” can be turn to the address pin “A23” once user enable the control bit of “CS3” & “EA23” of extension bus control register. Data Bus ED[0..15] DEVICE #3 EA23 (CS3\) DEVICE #2 DEVICE #1 A23 CE\ CE\ CE\ Address Bus EA[0..22] CS2\ CS1\ CS0\ SNL320 12.4 NAND Flash Interface SNL320 provides a special function to access data from the external NAND flash memory. The following table is shown the relative pins of NAND flash memory interface. P3.3~P3.7 will becomes to be the control signal of NAND flash memory once the property control register was setting, and data bus of NAND flash memory are shared with the data bus D0~D7 of extension bus. All the data read/write are easy to implement by the software. I/O Pin Pin Name Direction Descriptions P3.3 NCSB O NAND flash memory chip enable pin P3.4 CLE O Command latch enable P3.5 ALE O Address latch enable P3.6 R/B\ I NAND Flash memory Ready / Busy output P3.7 WPB O Write protect RD\ RD\ O Read signal WR\ WR\ O Write signal IO Data bus D0~D7 ED0~ED7 D0~D7 Ver: 1.2 17 July 22, 2005 SNL320 16-Bit LCD Controller SNL320 NAND Flash I/O0~I/O7 ED0~ED7 RD\ RE\ WR\ WE\ NCS\ CE\ ALE ALE CLE CLE R/B\ R/B\ WP\ WP\ 13. USB INTERFACE The SNL320 provides a USB 1.1 interface, user can download/upload data from/to PC through this USB interface. It is support control transfer and bulk transfer. SNL320 provides twin buffers for data or command transition and the buffer size of those twin buffers is 64bytes. 14. LCD INTERFACE 14.1 LCD Controller Interface (8-bit interface) The extension bus of SNL320 supports not only external memory device but also 8-bit 8080/6800 microprocessor interface for external LCD controller which already built-in LCD display RAM. User should enable extension bus before driving external LCD driver, and define the chip select pin you used to connect to LCD driver in EBC register. In 8-bit interface LCD controller, LCD display data is stored in LCD controller. Any change of LCD display is sent out to external LCD driver’s RAM by addressing different SRAM space. The interface emulates the 8080/6800-series interface to speed up the interface data moving processing. Figure-5 and Figure-6 are the timing diagrams between SNL320 and LCD controller by using 8-bit 8080/6800 interface. Ver: 1.2 18 July 22, 2005 SNL320 16-Bit LCD Controller 8080-series Interface: A0 CS WR, RD D0~D7 (WRITE) D0~D7 (READ) Figure-5 6800-series Interface: A0 R/W CS E D0~D7 (WRITE) D0~D7 (READ) Figure-6 Ver: 1.2 19 July 22, 2005 SNL320 16-Bit LCD Controller Figure-7 and Figure-8 show out the system connection of 8080/6800 LCD interfaces between SNL320 and LCD controller. SNL320 RD\ WR\ CS1 A0 RD WR CE\ D[0..15] A[0..21] D[0..7] LCD Controller Memory address bus EA[0..21] data bus ED[0..7] RD\ WR\ CS0 CS1 CS2 CS3 8080 LCD controller interface Figure-7 SNL320 E WR CS1 A0 RD\ WR\ CE\ D[0..15] A[0..21] D[0..7] LCD Controller Memory address bus EA[0..21] data bus D[0..15] RD\ WR\ CS0 CS1 CS2 CS3 6800 LCD controller interface Figure-8 Ver: 1.2 20 July 22, 2005 SNL320 16-Bit LCD Controller 14.2 LCD Driver Interface (1/4 bits interface) SNL320 supports not just 8-bit interface but also 1-bit/4-bit interface for LCD driver. For this kind LCD driver doesn’t include display RAM. All the display data is stored in host CPU. So SNL320 has to specify a dedicate interface to drive LCD driver. Besides, SNL320 reserves 4K words LCD Buffer (0xB000~0xBFFF) for LCD display. Hardware circuit will send accurate signal to LCD driver automatically once the 1-bit/4-bit LCD driver interface is enabled. The internal 4K words SRAM can support maximum 240x120 dots LCD display with 4-grey level effect. Note : only support 4MHZ LCD clock source 14.3 Control Signals P3.12~P3.15 & P4.0~P4.3 can be configured to be 1-bit/4-bit interface for LCD driver just by property setting control register. Table-2 shows the relation between P3.12~P3.15, P4.0~P4.3 and LCD driver interface. I/O Pin Pin Name Descriptions P3.12 LACD LCD alternating signal P3.13 LCLK Dot clock P3.14 LP Line signal P3.15 FP First line marker P4.0 LD0 LCD data output D0 P4.1 LD1 LCD data output D1 P4.2 LD2 LCD data output D2 P4.3 LD3 LCD data output D3 Table-2 14.4 LCD RAM Mapping The RAM region from 0xB000 to 0xBFFF totally 4K*16 is reserved for LCD display buffer, user just need to copy the LCD display pattern data into this area then chip will display the pattern on LCD panel automatically. There is a special register LBUF to specify the LCD display buffer start address. Calculating formula of start address 49152-(SEG numbe/16)*COM number => for B/W 49152-(SEG numbe/16)*COM number*2 => for 4 gray levels NOTE: SEG number must be the multiple by 8. Ver: 1.2 21 July 22, 2005 SNL320 16-Bit LCD Controller For B/W LCD display, each bit of display memory mapping to a pixel in the LCD panel. Please refer to following diagram, the display data of SEG0 ~ SEG15 at COM0 is mapping to bit0~bit15 of display memory 0xB000 SEGm SEG31 SEG19 SEG18 SEG17 SEG16 SEG15 0xB001 SEG3 SEG2 SEG1 SEG0 0xB000 COM0 COM1 COMn LCD screen format (B/W) For 4-gray level LCD display, each display pixel takes two bits space to store the gray level display data. Please refer to following diagram, the display data of SEG0 ~ SEG7 at COM0 is mapping to bit0~bit15 of display memory 0xB000. SEGm SEG15 SEG11 SEG10 SEG9 SEG8 0xB001 SEG7 SEG3 SEG2 SEG1 SEG0 0xB000 COM0 COM1 COMn LCD screen format (4-gray level) Ver: 1.2 22 July 22, 2005 SNL320 16-Bit LCD Controller 15. Application Circuit VDD3V 113 112 C7 0.1uF 8 C4 0.1uF 3 CVDD C15 47uF C16 0.1uF CGND 76 75 77 74 78 VDD4.5V C17 0.1uF C18 47uF SPEAKER VDD3V 92 C19 0.1uF VDD4.5V VDD3V U3 RT9169 4.7uF VOUT 3 GND C21 C20 0.1uF VIN C22 0.1uF 1 2 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 82 83 84 85 86 87 88 90 91 93 94 95 96 97 98 99 C23 47uF 89 TR2 P1.0 VDDIO1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.8 P1.9 P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 VSSIO1 WR RD EDWS VSSEBUS VSSEBUS VSSEBUS PWR+ D+ DPWR- TR4 P1.2 Ver: 1.2 PPVDD BP0 BN0 PPVSS PPVSS P1.3 VDD3V TR3 P1.1 VO0 61 TR1 LXOUT 4 CS1\ R5 10 ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 ED8 ED9 ED10 ED11 ED12 ED13 ED14 ED15 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 EA17 EA18 EA19 EA20 EA21 EA22 9 10 11 12 13 14 15 16 19 20 21 22 23 24 25 26 ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 ED8 ED9 ED10 ED11 ED12 ED13 ED14 ED15 27 28 WR\ RD\ 111 C2 VDD3V EA21 VDD3V EA18 EA17 EA7 EA6 EA5 EA4 EA3 EA2 EA1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MX29LV640T/B A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE_ RESET_ A21 WP_/ACC RY/BY_ A18 A17 A7 A6 A5 A4 A3 A2 A1 A16 BYTE_ GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 Vcc Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE_ GND CE_ A0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD3V R6 1.5K DD+ C24 0.1uF J1 R7 27 R8 27 1 USBD2 USBD+ 3 USBPWR- 4 USB Connector C25 0.1uF VDD3V 18 33 49 101 102 103 104 C3 0.1uF 0.1uF U4 VDD3V D+ DUSBPWR- VSSIO2 5 7 GND LXIN 29 30 31 32 34 35 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 EA19 EA20 WR\ LCD Display 4-Bit LCM 64 VDD3V XOUT Y2 32768HZ C12 C14 15pF 4 15pF R4 10 TEST XIN P4.0/LD0 P4.1/LD1 P4.2/LD2 P4.3/LD3 C10 0.1uF GNDA PLLCAP Y1 C11 15pF C9 47uF 6MHZ VDDA R3 10 GND C8 15pF R2 10 VDD3V 110 2 PLLEN CKSEL 58 57 56 55 VDDA RSTB LD0 LD1 LD2 LD3 C6 0.1uF LACD LCLK LP FP CGND P3.0/INT0 P3.1/INT1 P3.2/INT2 P3.3/NCSB P3.4/CLE P3.5/ALE P3.6/RB P3.7/WPB P3.8/CS3 P3.9/CS2 P3.10/CS1 P3.11/CS0 P3.12/LACD P3.13/LCLK P3.14/LP P3.15/FP 0.1uF RSTB VDDIO2 C5 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 EA17 EA18 EA19 EA20 EA21 EA22 81 80 79 73 72 71 70 69 68 67 66 65 63 62 60 59 0.1uF R1 220K VDDEBUS VDDEBUS LD0 LD1 LD2 LD3 GND 109 VDD3V VDD3V C1 U2 CVDD CVDD VOUT REGVDD VSSIO VDDA VSSA 17 48 VCC LACD LCLK LP FP RSTB VDD3V SNL320 VDD3V LACD LCLK LP FP VDDA GNDA 106 100 107 105 108 6 1 C26 0.1uF July 22, 2005 LD0 LD1 LD2 LD3 U1 CVDD EA16 VDD3V ED15 ED7 ED14 ED6 ED13 ED5 ED12 ED4 ED11 ED3 ED10 ED2 ED9 ED1 ED8 ED0 RD\ CS1\ EA0 VDD3V C13 0.1uF SNL320 16-Bit LCD Controller 16. ABSOLUTE MAXIMUM RATINGS Items Supply Voltage Input Voltage Operating Temperature Storage Temperature Symbol VDD-V VIN TOP TSTG Min -0.3 GND-0.3 0 -55.0 Max 6.0 VDD+0.3 55 125.0 Unit. V V o C o C 17. ELECTRICAL CHARACTERISTICS Item Operating Voltage Sym. Min. Typ. Max. Unit Condition VDD 2.4 3.6 V VDD 3.6 5.1 V Standby current ISBY 2.0 uA VDD=3V, no load Operating Current IOPR 10 mA VDD=3V, no load Pull-Up resistor of P1, P3, RPU 800 KΩ VDD=3V, no load P4 Input current of P1, P3, P4 IIH 10.0 uA VDD=3V,VIN=3V Drive current of P1, P3, P4 IOD 6 mA VDD=3V,VO=2.4V Sink Current of P1, P3, P4 IOS 8 mA VDD=3V,VO=0.4V Drive current of Buo1 IOD mA VDD=3V,Buo1=1.5V Sink Current of Buo1 IOS mA VDD=3V,Buo1=1.5V Drive Current of Buo2 Sink Current of Buo2 Oscillation Freq. (crystal) Ver: 1.2 IOD IOS FOSC - 4 16.0 - mA VDD=3V,Buo2=1.5V mA VDD=3V,Buo2=1.5V MHz VDD=3V July 22, 2005 SNL320 16-Bit LCD Controller 18. Bonding Pad 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 VSSA 1 XIN 2 XOUT 3 83 LXIN 4 82 LXOUT 5 VDDA 6 VO0 7 PLLCAP 8 ED0 9 85 84 81 80 79 78 77 76 ED1 10 ED2 11 75 ED3 12 74 ED4 13 (0.00,0.00) 73 ED5 14 72 ED6 15 71 ED7 16 70 VDDEBUS 17 69 VSSEBUS 18 68 ED8 19 ED9 20 ED10 21 ED11 22 ED12 23 ED13 24 ED14 25 ED15 26 WR\ 27 RD\ 28 67 66 65 64 63 62 61 60 59 Ver: 1.2 41 42 43 44 45 46 47 48 49 50 51 52 53 54 EA15 EA16 EA17 VDDEBUS VSSEBUS EA18 EA19 EA20 EA21 EA22 EA8 40 EA14 EA7 39 EA13 38 EA12 37 EA11 36 EA9 35 EA10 34 EA6 EA2 33 EA5 EA1 32 EA4 31 EA3 30 VSSEBUS 29 EA0 58 5 55 56 57 July 22, 2005 SNL320 16-Bit LCD Controller DISCLAIMER The information appearing in SONiX web pages (“this publication”) is believed to be accurate. However, this publication could contain technical inaccuracies or typographical errors. The reader should not assume that this publication is error-free or that it will be suitable for any particular purpose. SONiX makes no warranty, express, statutory implied or by description in this publication or other documents which are referenced by or linked to this publication. In no event shall SONiX be liable for any special, incidental, indirect or consequential damages of any kind, or any damages whatsoever, including, without limitation, those resulting from loss of use, data or profits, whether or not advised of the possibility of damage, and on any theory of liability, arising out of or in connection with the use or performance of this publication or other documents which are referenced by or linked to this publication. This publication was developed for products offered in Taiwan. SONiX may not offer the products discussed in this document in other countries. Information is subject to change without notice. Please contact SONiX or its local representative for information on offerings available. Integrated circuits sold by SONiX are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. The application circuits illustrated in this document are for reference purposes only. SONIX DISCLAIMS ALL WARRANTIES, INCLUDING THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SONIX reserves the right to halt production or alter the specifications and prices, and discontinue marketing the Products listed at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SONIX for such application. Ver: 1.2 6 July 22, 2005