360μΩ, 5 V/60 A N-Channel MOSFET PI5101-01-LGIZ

μRDS(on) FET™ Series
PI5101-01-LGIZ
360μΩ, 5 V/60 A N-Channel MOSFET
Product Description
Features
The PI5101μRDS(on) FET™ solution combines a highperformance 5 V, 360 μΩ lateral N-Channel MOSFET with a
thermally enhanced high density 4.1mm x 8mm x 2mm
land-grid-array (LGA) package to enable world class
performance in the footprint area of an industry standard
SO-8 package. The PI5101 offers unprecedented figure-ofmerits for DC & switching applications. The PI5101 will
replace up to 6 conventional “SO-8 form factor” devices for
the same on-state resistance, reducing board space by ~80%.
The PI5101 offers unprecedented figure-of-merit for
RDS(on) x QG, gate resistance (RG) and package inductance (LDS)
outperforming conventional Trench MOSFETs and enabling
very low loss operation.
• Ultra Low “micro-Ohm” RDS(on)
The PI5101 LGA package is fully compatible with industry
standard SMT assembly processes.
• Extremely Low Gate Charge
• Very Low Gate Resistance
• High Density, Low Profile
• Very Low Package Inductance
• Low Thermal Resistance
Applications
• Power Path Management Solutions
• Active ORing & Load Switches
• High Current DC-DC Converters
Product Summary
Package Information
Symbol
Condition
ID
TA = 25°C
60 ADC
Max
V(BR)DSS
ID = 5 mA
5V
360 μΩ
Min
380 μΩ
Typ
65 nC
Typ
RG
0.1 Ω
Typ
LDS
0.1 nH
Typ
RDS(ON)
QG
VGS = 4.5 V
VGS = 3.5 V
VGS = 4.5 V
μRDS(on) FET™ Series
Page 1 of 10
Value
• 4.1mm x 8mm x 2mm
Thermally Enhanced LGA
Typ
Rev 1.0
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PI5101-01-LGIZ
Order Information
Part Number
Package
Transport Media
PI5101-01-LGIZ
4.1mm x 8mm x 2mm 3-Lead LGA
T&R
Maximum Rating and Thermal Characteristics
TA = 25°C unless otherwise specified.
Parameter
Symbol
Limit
Unit
Drain-to-Source Voltage
VDS
5
V
Gate-to-Source Voltage
VGS
±5
V
ID
60
A
IDM
150
A
IAS
100
A
3.1
W
2
W
TJ, TSTG
-55 to 150
°C
RθJ-A
40
°C/W
6
°C/W
260
°C
Continuous
Drain Current
Pulsed
TAV <100 μs
Single Pulse Avalanche Current
TA = 25°C
Maximum Power Dissipation
PD
TA = 70°C
Operating Junction and Storage Temperature Range
Junction-to-Ambient
Thermal Resistance [1]
Junction-to-PCB
Lead Temperature (Soldering, 20 sec)
[1]
RθJ-PCB
The thermal resistance is measured when the device is mounted on 1 inch square 4-layer 2-oz copper FR-4 PCB at 0LFM and 40A drain current
μRDS(on) FET™ Series
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Electrical Characteristics
TA = 25°C unless otherwise specified.
Parameter
Symbol
Drain-to-Source Breakdown Voltage
Breakdown Voltage
Temperature Coefficient
Drain-to-Source Leakage Current
Gate-to-Source Leakage
Gate Threshold Voltage
V(BR)DSS
∆V(BR)DSS
∆TJ
IDSS
IGSS
VGS(th)
Drain-to-Source On-State Resistance
RDS(on)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Forward Transconductance
Conditions
Input Specifications
VGS = 0 V, ID = 5 mA
Min
Typ
Max
5.0
Unit
V
Reference to 25°C, VGS = 0 V, ID = 5 mA
3.1
0.2
10
td(on)
tr
td(off)
tf
gfs
VDS = 4.8 V, VGS = 0 V
VGS = 5 V, VDS = 0 V
VDS = VGS, ID = 1 mA
VGS = 4.5 V, ID = 60 A
VGS = 3.5 V, ID = 60 A
VGS = 4.5 V, ID = 60 A, RG = 0.1Ω
VGS = 4.5 V, ID = 60 A, RG = 0.1Ω
VGS = 4.5 V, ID = 60 A, RG = 0.1Ω
VGS = 4.5 V, ID = 60 A, RG = 0.1Ω
ID = 60 A, VDS = 4 V
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Ciss
Coss
Crss
Gate Capacitance
VDS = 5 V, VGS = 0 V, f = 1MHz; See Figure 6
VDS = 5 V, VGS = 0 V, f = 1MHz; See Figure 6
VDS = 5 V, VGS = 0 V, f = 1MHz
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Gate Resistance
Qg
Qgs
Qgd
RG
0.4
360
380
14
4.5
23
3.5
620
mV/℃
2
200
0.8
450
475
μA
nA
V
μΩ
μΩ
ns
ns
ns
ns
S
7600
5200
1100
pF
pF
pF
65
7.7
9.0
0.1
nC
nC
nC
Ω
IS = 16 A, di⁄dt = 33 A⁄μs
300
ns
IS = 16 A, VGS = 0 V (Pulse Test)
0.63
0.1
Gate Charge
VGS = 4.5 V, VDD = 4.4 V, ID = 60 A; See Figure 3
VGS = 4.5 V, VDD = 4.4 V, ID = 60 A
VGS = 4.5 V, VDD = 4.4 V, ID = 60 A
Reverse Diode
Source-to-Drain Reverse
Recovery Time
Diode Forward Voltage
Package Inductance
μRDS(on) FET™ Series
Page 3 of 10
trr
VSD
LDS
Rev 1.0
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1.0
V
nH
PI5101-01-LGIZ
Typical Characteristics
TA = 25°C unless otherwise specified.
200
160
180
VGS = 3 V, 2 V, 1.4 V
140
V GS
100
.2 V
=1
ID, Drain Current (A)
ID - Drain Current (A)
160
120
80
60
40
140
120
TJA = 125°C
100
25°C
80
-55°C
60
40
VGS = 1.0 V
20
0
0.0
0.2
0.4
0.6
20
0
0.5
0.8
0.6
0.7
VDS - Drain-to-Source Voltage (V)
VGS = 4.5 V
ID = 60 A
1.2
1.1
1.0
0.9
-25
0
25
50
75
100
125
150
RDS(on), Drain-to-Source On-Resistance (mΩ)
RDS(on), Normalized on State Resistance
1.4
0.8
-50
1.2
1.5
1.0
0.5
0.0
0
1
2
3
4
5
Figure 5 — On-Resistance vs. Gate Voltage
9000
ID = 60 A
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd: while Cds Shorted
Ciss
8000
4
Capacitance (pF)
VGS, Gate-to-Source Voltage (V)
1.1
VGS, Gate-to-Source Voltage (V)
Figure 2 — On-Resistance vs. Junction Temperature
3
2
7000
Coss
6000
5000
1
4000
0
0
10
20
30
40
50
60
70
0
QG, Total Gate Charge (nC)
Figure 3 — Gate Charge
μRDS(on) FET™ Series
Page 4 of 10
1.0
2.0
TJ, Junction Temperature (°C)
5
0.9
Figure 4 — Transfer Characteristics (Pulsed VGS)
Figure 1 — Output Characteristics (Pulsed VGS)
1.3
0.8
VGS, Gate-to-Source (V)
1
2
3
4
5
VDS, Drain-to_Source Voltage (V)
Figure 6 — Gate Capacitance vs. Drain-to Source Voltage
Rev 1.0
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PI5101-01-LGIZ
Typical Characteristics
TA = 25°C unless otherwise specified.
VGS(th), Normalized Gate Threshold Voltage
1.4
100
ID = 1 mA
IS, Source Current (A)
1.2
1.0
0.8
0.6
TJ = 150°C
TJ = 25°C
10
0.4
0.2
-50
-25
0
25
50
75
100
125
1
150
0
TJ, Junction Temperature (°C)
0.4
0.6
0.8
1
Figure 10 — Reverse Diode Forward Voltage (Pulsed Test)
Figure 7 — Gate Threshold Voltage vs. Temperature
700
1.00
VG S= 0 V
600
gfs, Transconductance (S)
Drain Current (µA)
0.2
VSD, Source-to-Drain Voltage (V)
0.10
500
400
300
200
100
0
0.01
0
1
2
3
4
0
5
10
20
Drain-to-Source Votage (V)
50
60
1.06
1000
VGS = 0 V
ID = 5 mA
1.05
1µ
s
10
µs
10
10
1.04
V(BR)DSS Normalized
100
ID, Drain Current (A)
40
Figure 11 — Forward Transconductance
Figure 8 — Drain-to-Source Leakage Current
0µ
s
DC
1
RDS(on) Limit
Package Limit
Thermal Limit
0.1
0.01
0.01
1.03
1.02
1.01
1.00
0.99
0.98
Single Pulse
VGS = 3.5V
0.97
0.96
0.1
1
-50
10
Figure 9 — Maximum Safe Operation Area
μRDS(on) FET™ Series
-25
0
25
50
75
100
125
150
TJ, Junction Temperature (°C)
VDS, Drain-to-Source Voltage (V)
Page 5 of 10
30
ID, Drain Current (A)
Figure 12 — Drain-to-Source Breakdown Voltage vs. temperature
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Typical Characteristics
Normalized Transient Thermal Impedance (Rθ-JA)
TA = 25°C unless otherwise specified.
1.00
1 = 0.5
0.2
0.1
0.10
0.05
PPK
0.02
ton
Single Pulse
τ
Duty Cycle:
δ=
0.01
10
10
-4
10
-3
10
-2
-1
1
10
10
1
t on
τ
103
2
ton On Time Pulse Duration (s)
Figure 13 — Normalized Transient Thermal Impedance, Junction-to-Ambient
60
60
ID Drain Current (A)
ID Drain Current (A)
40
35
30
RθJPCB = 6°C/W
25
20
20
45
55
65
75
85
95
105
115
100
125
Ambient Temperature (°C)
Figure 14 — PI5101 Drain current de-rating based on the maximum
TJ = 150°C vs. ambient temperature
μRDS(on) FET™ Series
Page 6 of 10
μΩ
25
= 36 0
RθJA = 40°C/W
45
μΩ
30
R DS(on)
35
4 50
40
50
n)=
μΩ
R DS(o
0
μΩ
45
45
60
=3
DS
(o
n) =
50
55
)
on
S(
R
RD
55
110
120
130
140
150
PCB Temperature (°C)
Figure 15 — PI5101 Drain current de-rating vs. PCB temperature,
for maximum TJ at 150°C
Rev 1.0
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MOSFET Power Dissipation
vs. Junction Temperature
150
145
130
Junction Temperature (°C)
RDS(on)=450μΩ
RθJA = 40°C/W
140
Junction Temperature (°C)
150
VGS = 4.5 V
120
110
100
90
80
70
60
50
100°C
90°C
80°C
70°C
60°C
5
135
130
125
120
140°C
130°C
120°C
115
110
110°C
105
100
95
TA = 50°C
0
140
VGS = 4.5 V
RDS(on)=450μΩ
RθJPCB = 6°C/W
90
100°C
TPCB = 90°C
0 5 10 15 20 25 30 35 40 45 50 55 60
10 15 20 25 30 35 40 45 50 55 60
Drain Current (A)
Drain Current (A)
Figure 16 — Junction Temperature vs. Drain Current for a given
ambient temperature (0LFM)
Figure 17 — Junction Temperature vs. Drain Current for a given
PCB temperature
In applications such as low loss ORing Diodes or circuit breakers
where the MOSFET is normally on during steady state operation, the
MOSFET power dissipation is derived from the total Drain current
and the on-state resistance of the MOSFET.
This may require iteration to get to the final junction temperature.
figure 16 and figure 17 are added to aid the user to find the final
junction temperature without the iterative calculations.
The PI5101 power dissipation can be calculated with the following
equation:
PD = ID2 • RDS(on)
To find the final junction temperature for a given drain continuous
DC or RMS current and a given ambient or PCB temperature; draw a
vertical line from the drain current at the X-axis to intersect the
ambient or PCB temperature line. At the intersection draw a
horizontal line towards the Y-axis (Junction Temperature).
Where:
PD:
ID :
RDS(on):
Figure 16 shows the MOSFETs final junction temperature curves
versus conducted current at maximum RDS(on), and at given ambient
temperatures at 0 LFM air flow. Figure 17 shows the MOSFETs final
junction temperature curves versus conducted current at maximum
RDS(on) at given PCB temperatures.
MOSFET power dissipation
Drain Current
MOSFET on-state resistance
Example:
Note: For the worst case condition, calculate with maximum rated RDS(on)
at the MOSFET maximum operating junction temperature because RDS(on)
is temperature dependent. Refer to figure 2 for normalized RDS(on) values
over temperature. The PI5101 maximum RDS(on) at 25°C is 450 µΩ and
will increase by 24% at 125°C junction temperature.
The junction temperature rise is a function of power dissipation and
thermal resistance.
Trise = RθJA • PD = R
JA
• ID2 • RDS(on)
Assume that the MOSFET maximum drain current is 50 A and
maximum operating ambient temperature is 70°C.
First use figure 16 to find the final junction temperature for 50 A
drain current at 70°C ambient temperature. In figure 16 (illustrated
in figure 18) draw a vertical line from 50 A to intersect the 70°C
ambient temperature line (dark blue). At the intersection draw a
horizontal line towards the Y-axis (Junction Temperature). The
typical junction temperature with maximum RDS(on), at load current
of 50 A and 70°C ambient is 126°C.
Where:
RθJA :
Junction-to-Ambient thermal resistance (40°C/W)
μRDS(on) FET™ Series
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As a check, recalculate the junction temperature to confirm the plot
results. Start from the final junction temperature, 126°C, and use the
following steps:
RDS(on) is 450μΩ maximum at 25°C and will increase as the
Junction temperature increases. From figure 2, at 126°C RDS(on)
will increase by 24%, then RDS(on) maximum at 126°C is:
RDS(on) = 450 µΩ • 1.24 = 558 µΩ
Maximum power dissipation is:
PDmax = ID2 • RDS(on) = 50 A • 558 µΩ = 1.39 W
Maximum junction temperature is:
TJmax = 70°C + 40°C 50 A2 • 558 µΩ = 125.8°C
W
150
VGS = 4.5 V
RDS(on)=450μΩ
RθJA = 40°C/W
Junction Temperature (°C)
140
130
126
120
110
100
90
80
70
60
50
100°C
90°C
80°C
70°C
60°C
TA = 50°C
0
5 10 15 20 25 30 35 40 45 50 55 60
Drain Current (A)
Figure 18 — Example graphing of MOSFET junction temperature at
ID = 50 A and TA = 70°C
μRDS(on) FET™ Series
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Package Drawing
Layout Recommendation
μRDS(on) FET™ Series
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email
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μRDS(on) FET™ Series
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