MAXIM 71M6541D

19-5376; Rev 2; 11/11
71M6541D/F/G and 71M6542F/G
Energy Meter ICs
DATA SHEET
GENERAL DESCRIPTION
FEATURES
The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are
Teridian™ 4th-generation single-phase metering SoCs with a 5MHz
8051-compatible MPU core, low-power RTC with digital temperature
compensation, flash memory, and LCD driver. Our Single Converter
Technology® with a 22-bit delta-sigma ADC, three or four analog
inputs, digital temperature compensation, precision voltage reference,
and a 32-bit computation engine (CE) supports a wide range of
metering applications with very few external components.
The 71M6541/2 devices support optional interfaces to the Teridian
71M6x01 series of isolated sensors, which offer BOM cost reduction,
immunity to magnetic tamper, and enhanced reliability. Other
features include an SPI interface, advanced power management,
ultra-low-power operation in active and battery modes, 3/5KB shared
RAM and 32/64/128KB of flash memory that can be programmed in
the field with code and/or data during meter operation and the ability
to drive up to six LCD segments per SEG driver pin. High
processing and sampling rates combined with differential inputs offer
a powerful metering platform for residential meters.
A complete array of code development tools, demonstration code,
and reference designs enable rapid development and certification of
meters that meet all ANSI and IEC electricity metering standards
worldwide.
NEUTRAL
Shunt
LOAD
Note:
This system is referenced to LINE
Shunt
LINE
NEUTRAL
POWER SUPPLY
LINE
Resistor Divider
LINE
• 0.1% Accuracy Over 2000:1 Current Range
• Exceeds IEC 62053/ANSI C12.20 Standards
• Two Current Sensor Inputs with Selectable
Differential Mode
• Selectable Gain of 1 or 8 for One Current Input to
Support Shunts
• High-Speed Wh/VARh Pulse Outputs with
Programmable Width
• 32KB Flash, 3KB RAM (71M6541D)
• 64KB Flash, 5KB RAM (71M6541F/42F)
• 128KB Flash, 5KB RAM (71M6541G/42G)
• Up to Four Pulse Outputs with Pulse Count
• Four-Quadrant Metering
• Digital Temperature Compensation:
Metrology Compensation
Accurate RTC for TOU Functions with
Automatic Temperature Compensation for
Crystal in All Power Modes
• Independent 32-Bit Compute Engine
• 46-64Hz Line Frequency Range with the Same
Calibration
• Phase Compensation (±10°)
• Three Battery-Backup Modes:
Brownout Mode (BRN)
LCD Mode (LCD)
Sleep Mode (SLP)
• Wake-Up on Pin Events and Wake-On Timer
• 1µA in Sleep Mode
TERIDIAN
71M6xx1
MUX and ADC
V3P3A V3P3SYS GNDA GNDD
• Flash Security
PWR MODE
CONTROL
IAP
IAN
Pulse
Transformer
TERIDIAN
WAKE-UP
71M6541D/F
REGULATOR
• In-System Program Update
BATTERY
VBAT
VA
VBAT_RTC
IBP
IBN
TEMPERATURE
SENSOR
VREF
SERIAL PORTS
AMR
IR
TX
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
HOST
RAM
COMPUTE
ENGINE
FLASH
MEMORY
MPU
RTC
TIMERS
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I C or µWire
EEPROM
32 kHz
SPI INTERFACE
ICE
• Full-Speed MPU Clock in Brownout Mode
• LCD Driver:
2
V3P3D
OSCILLATOR/
PLL
XIN
• 8-Bit MPU (80515), Up to 5 MIPS
XOUT
11/5/2010
Teridian is a trademark and Single Converter Technology is a registered trademark of
Maxim Integrated Products, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
- Up to 6 Commons/Up to 56 Pins
• 5V LCD Driver with DAC
• Up to 51 Multifunction DIO Pins
• Hardware Watchdog Timer (WDT)
2
• I C/MICROWIRE® EEPROM Interface
• SPI Interface with Flash Program Capability
• Two UARTs for IR and AMR
• IR LED Driver with Modulation
• Industrial Temperature Range
• 64-Pin (71M6541D/F/G) and 100-pin
(71M6542F/G) Lead(Pb)-Free LQFP Package
Rev 2
1
71M6541D/F/G and 71M6542F/G Data Sheet
Table of Contents
1
2
3
2
Introduction ................................................................................................................................. 10
Hardware Description .................................................................................................................. 11
2.1 Hardware Overview............................................................................................................... 11
2.2 Analog Front End (AFE) ........................................................................................................ 12
2.2.1 Signal Input Pins ....................................................................................................... 14
2.2.2 Input Multiplexer ........................................................................................................ 15
2.2.3 Delay Compensation ................................................................................................. 19
2.2.4 ADC Pre-Amplifier ..................................................................................................... 20
2.2.5 A/D Converter (ADC) ................................................................................................. 20
2.2.6 FIR Filter ................................................................................................................... 20
2.2.7 Voltage References ................................................................................................... 20
2.2.8 71M6x01 Isolated Sensor Interface (Remote Sensor Interface).................................. 22
2.3 Digital Computation Engine (CE) ........................................................................................... 24
2.3.1 CE Program Memory ................................................................................................. 24
2.3.2 CE Data Memory ....................................................................................................... 24
2.3.3 CE Communication with the MPU .............................................................................. 25
2.3.4 Meter Equations ........................................................................................................ 25
2.3.5 Real-Time Monitor (RTM) .......................................................................................... 25
2.3.6 Pulse Generators ...................................................................................................... 27
2.3.7 CE Functional Overview ............................................................................................ 28
2.4 80515 MPU Core .................................................................................................................. 31
2.4.1 Memory Organization and Addressing ....................................................................... 31
2.4.2 Special Function Registers (SFRs) ............................................................................ 33
2.4.3 Generic 80515 Special Function Registers ................................................................ 34
2.4.4 Instruction Set ........................................................................................................... 36
2.4.5 UARTs ...................................................................................................................... 36
2.4.6 Timers and Counters ................................................................................................. 39
2.4.7 WD Timer (Software Watchdog Timer) ...................................................................... 40
2.4.8 Interrupts................................................................................................................... 40
2.5 On-Chip Resources............................................................................................................... 48
2.5.1 Physical Memory ....................................................................................................... 48
2.5.2 Oscillator ................................................................................................................... 50
2.5.3 PLL and Internal Clocks............................................................................................. 50
2.5.4 Real-Time Clock (RTC) ............................................................................................. 51
2.5.5 71M654x Temperature Sensor .................................................................................. 56
2.5.6 71M654x Battery Monitor........................................................................................... 57
2.5.7 UART and Optical Interface ....................................................................................... 58
2.5.8 Digital I/O and LCD Segment Drivers......................................................................... 59
2.5.9 EEPROM Interface .................................................................................................... 70
2.5.10 SPI Slave Port ........................................................................................................... 73
2.5.11 Hardware Watchdog Timer ........................................................................................ 78
2.5.12 Test Ports (TMUXOUT and TMUX2OUT Pins)........................................................... 78
Functional Description ................................................................................................................ 80
3.1 Theory of Operation .............................................................................................................. 80
3.2 Battery Modes....................................................................................................................... 81
3.2.1 BRN Mode ................................................................................................................ 83
3.2.2 LCD Mode ................................................................................................................. 83
3.2.3 SLP Mode ................................................................................................................. 84
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
3.3
4
5
6
Fault and Reset Behavior ...................................................................................................... 85
3.3.1 Events at Power-Down .............................................................................................. 85
3.3.2 IC Behavior at Low Battery Voltage ........................................................................... 86
3.3.3 Reset Sequence ........................................................................................................ 86
3.3.4 Watchdog Timer Reset .............................................................................................. 86
3.4 Wake Up Behavior ................................................................................................................ 87
3.4.1 Wake on Hardware Events ........................................................................................ 87
3.4.2 Wake on Timer .......................................................................................................... 90
3.5 Data Flow and MPU/CE Communication ............................................................................... 91
Application Information ............................................................................................................... 92
4.1 Connecting 5 V Devices ........................................................................................................ 92
4.2 Direct Connection of Sensors ................................................................................................ 92
4.3 71M6541D/F/G Using Local Sensors..................................................................................... 93
4.4 71M6541D/F/G Using 71M6x01and Current Shunts .............................................................. 94
4.5 71M6542F/G Using Local Sensors ........................................................................................ 95
4.6 71M6542F/G Using 71M6x01 and Current Shunts................................................................. 96
4.7 Metrology Temperature Compensation.................................................................................. 97
4.7.1 Voltage Reference Precision ..................................................................................... 97
4.7.2 Temperature Coefficients for the 71M654x ................................................................ 97
4.7.3 Temperature Compensation for VREF with Local Sensors ......................................... 98
4.7.4 Temperature Compensation for VREF with Remote Sensor ....................................... 99
4.8 Connecting I2C EEPROMs .................................................................................................. 100
4.9 Connecting Three-Wire EEPROMs ..................................................................................... 101
4.10 UART0 (TX/RX) .................................................................................................................. 101
4.11 Optical Interface (UART1) ................................................................................................... 101
4.12 Connecting the Reset Pin.................................................................................................... 102
4.13 Connecting the Emulator Port Pins ...................................................................................... 102
4.14 Flash Programming ............................................................................................................. 104
4.14.1 Flash Programming via the ICE Port ........................................................................ 104
4.14.2 Flash Programming via the SPI Port ........................................................................ 104
4.15 MPU Firmware Library ........................................................................................................ 104
4.16 Crystal Oscillator ................................................................................................................. 104
4.17 Meter Calibration................................................................................................................. 104
Firmware Interface ..................................................................................................................... 105
5.1 I/O RAM Map –Functional Order ......................................................................................... 105
5.2 I/O RAM Map – Alphabetical Order ..................................................................................... 111
5.3 CE Interface Description ..................................................................................................... 125
5.3.1 CE Program ............................................................................................................ 125
5.3.2 CE Data Format ...................................................................................................... 125
5.3.3 Constants ................................................................................................................ 125
5.3.4 Environment ............................................................................................................ 126
5.3.5 CE Calculations....................................................................................................... 126
5.3.6 CE Front End Data (Raw Data)................................................................................ 127
5.3.7 FCE Status and Control ........................................................................................... 127
5.3.8 CE Transfer Variables ............................................................................................. 129
5.3.9 Pulse Generation..................................................................................................... 132
5.3.10 Other CE Parameters .............................................................................................. 134
5.3.11 CE Calibration Parameters ...................................................................................... 135
5.3.12 CE Flow Diagrams .................................................................................................. 136
Electrical Specifications ............................................................................................................ 138
Rev 2
3
71M6541D/F/G and 71M6542F/G Data Sheet
6.1
6.2
6.3
6.4
Absolute Maximum Ratings ................................................................................................. 138
Recommended External Components ................................................................................. 139
Recommended Operating Conditions .................................................................................. 139
Performance Specifications ................................................................................................. 140
6.4.1 Input Logic Levels ................................................................................................... 140
6.4.2 Output Logic Levels................................................................................................. 140
6.4.3 Battery Monitor ........................................................................................................ 141
6.4.4 Temperature Monitor ............................................................................................... 141
6.4.5 Supply Current ........................................................................................................ 142
6.4.6 V3P3D Switch ......................................................................................................... 143
6.4.7 Internal Power Fault Comparators ........................................................................... 143
6.4.8 2.5 V Voltage Regulator – System Power ................................................................ 143
6.4.9 2.5 V Voltage Regulator – Battery Power ................................................................. 144
6.4.10 Crystal Oscillator ..................................................................................................... 144
6.4.11 Phase-Locked Loop (PLL) ....................................................................................... 144
6.4.12 LCD Drivers ............................................................................................................ 145
6.4.13 VLCD Generator...................................................................................................... 146
6.4.14 VREF ...................................................................................................................... 148
6.4.15 ADC Converter ........................................................................................................ 149
6.4.16 Pre-Amplifier for IAP-IAN ......................................................................................... 150
6.5 Timing Specifications .......................................................................................................... 151
6.5.1 Flash Memory ......................................................................................................... 151
6.5.2 SPI Slave ................................................................................................................ 151
6.5.3 EEPROM Interface .................................................................................................. 151
6.5.4 RESET Pin .............................................................................................................. 152
6.5.5 RTC ........................................................................................................................ 152
6.6 Package Outline Drawings .................................................................................................. 153
6.6.1 64-Pin LQFP Outline Package Drawing ................................................................... 153
6.6.2 100-Pin LQFP Package Outline Drawing ................................................................. 154
6.7 Package Markings .............................................................................................................. 155
6.8 Pinout Diagrams ................................................................................................................. 156
6.8.1 71M6541D/F/G LQFP-64 Package Pinout ............................................................... 156
6.8.2 71M6542F/G LQFP-100 Package Pinout ................................................................. 157
6.9 Pin Descriptions .................................................................................................................. 158
6.9.1 Power and Ground Pins........................................................................................... 158
6.9.2 Analog Pins ............................................................................................................. 159
6.9.3 Digital Pins .............................................................................................................. 160
6.9.4 I/O Equivalent Circuits ............................................................................................. 162
7
Ordering Information ................................................................................................................. 163
7.1 71M6541D/F/G and 71M6542F/G ....................................................................................... 163
8
Related Information ................................................................................................................... 163
9
Contact Information ................................................................................................................... 163
Appendix A: Acronyms ..................................................................................................................... 164
Appendix B: Revision History ........................................................................................................... 165
4
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Figures
Figure 2. 71M6541D/F/G AFE Block Diagram (Local Sensors) ............................................................... 12
Figure 3. 71M6541D/F/G AFE Block Diagram with 71M6x01.................................................................. 13
Figure 4. 71M6542F/G AFE Block Diagram (Local Sensors) .................................................................. 13
Figure 5. 71M6542F/G AFE Block Diagram with 71M6x01 ..................................................................... 14
Figure 6: States in a Multiplexer Frame (MUX_DIV[3:0] = 3) .................................................................. 17
Figure 7: States in a Multiplexer Frame (MUX_DIV[3:0] = 4) .................................................................. 17
Figure 8: General Topology of a Chopped Amplifier ............................................................................... 21
Figure 9: CROSS Signal with CHOP_E = 00........................................................................................... 21
Figure 10: RTM Timing .......................................................................................................................... 26
Figure 11: Timing relationship between ADC MUX, CE, and RTM Serial Transfer .................................. 26
Figure 12. Pulse Generator FIFO Timing ............................................................................................... 28
Figure 13: Accumulation Interval ............................................................................................................ 29
Figure 14: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 3)............................................................. 30
Figure 15: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 4)............................................................. 30
Figure 16: Interrupt Structure ................................................................................................................. 47
Figure 17: Automatic Temperature Compensation ................................................................................. 54
Figure 18: Optical Interface.................................................................................................................... 58
Figure 19: Optical Interface (UART1) ..................................................................................................... 59
Figure 20: Connecting an External Load to DIO Pins ............................................................................. 60
Figure 21: LCD Waveforms ................................................................................................................... 68
Figure 22: 3-wire Interface. Write Command, HiZ=0. ............................................................................. 72
Figure 23: 3-wire Interface. Write Command, HiZ=1 .............................................................................. 72
Figure 24: 3-wire Interface. Read Command. ........................................................................................ 72
Figure 25: 3-Wire Interface. Write Command when CNT=0 ................................................................... 73
Figure 26: 3-wire Interface. Write Command when HiZ=1 and WFR=1. ................................................. 73
Figure 27: SPI Slave Port - Typical Multi-Byte Read and Write operations.............................................. 75
Figure 28: Voltage, Current, Momentary and Accumulated Energy......................................................... 80
Figure 29: Operation Modes State Diagram ........................................................................................... 81
Figure 30: MPU/CE Data Flow ............................................................................................................... 91
Figure 31: Resistive Voltage Divider (Voltage Sensing) .......................................................................... 92
Figure 32. CT with Single-Ended Input Connection (Current Sensing) .................................................... 92
Figure 33: CT with Differential Input Connection (Current Sensing) ........................................................ 92
Figure 34: Differential Resistive Shunt Connections (Current Sensing)................................................... 92
Figure 35. 71M6541D/F/G with Local Sensors ....................................................................................... 93
Figure 36: 71M6541D/F/G with 71M6x01 isolated Sensor ...................................................................... 94
Figure 39: I2C EEPROM Connection.................................................................................................... 101
Figure 40: Connections for UART0 ...................................................................................................... 101
Figure 41: Connection for Optical Components .................................................................................... 102
Figure 42: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) ......... 102
Figure 43: External Components for the Emulator Interface ................................................................. 103
Figure 44: CE Data Flow: Multiplexer and ADC .................................................................................... 136
Figure 45: CE Data Flow: Scaling, Gain Control, Intermediate Variables .............................................. 136
Figure 46: CE Data Flow: Squaring and Summation Stages ................................................................. 137
Figure 47: 64-pin LQFP Package Outline ............................................................................................. 153
Figure 48: 100-pin LQFP Package Outline ........................................................................................... 154
Figure 49. Package Markings (Examples) ............................................................................................ 155
Figure 50: Pinout for the 71M6541D/F/G (LQFP-64 Package) .............................................................. 156
Figure 52: I/O Equivalent Circuits......................................................................................................... 162
Rev 2
5
71M6541D/F/G and 71M6542F/G Data Sheet
Tables
Table 1. Required CE Code and Settings for Local Sensors................................................................... 15
Table 2. Required CE Code and Settings for 71M6x01 isolated Sensor ................................................. 16
Table 3: ADC Input Configuration ......................................................................................................... 17
Table 4: Multiplexer and ADC Configuration Bits ................................................................................... 19
Table 5. RCMD[4:0] Bits ........................................................................................................................ 22
Table 6: Remote Interface Read Commands ........................................................................................ 23
Table 7: I/O RAM Control Bits for Isolated Sensor ................................................................................. 23
Table 8: Inputs Selected in Multiplexer Cycles ....................................................................................... 25
Table 9: CKMPU Clock Frequencies ...................................................................................................... 31
Table 10: Memory Map .......................................................................................................................... 32
Table 11: Internal Data Memory Map ..................................................................................................... 33
Table 12: Special Function Register Map ............................................................................................... 33
Table 13: Generic 80515 SFRs - Location and Reset Values ................................................................. 34
Table 14: PSW Bit Functions (SFR 0xD0)................................................................................................. 35
Table 15: Port Registers (SEGDIO0-15) ................................................................................................ 36
Table 16: Stretch Memory Cycle Width .................................................................................................. 36
Table 17: Baud Rate Generation............................................................................................................ 37
Table 18: UART Modes ......................................................................................................................... 37
Table 19: The S0CON (UART0) Register (SFR 0x98) ............................................................................. 38
Table 20: The S1CON (UART1) Register (SFR 0x9B) ............................................................................. 38
Table 21: PCON Register Bit Description (SFR 0x87) ............................................................................ 39
Table 22: Timers/Counters Mode Description ........................................................................................ 39
Table 23: Allowed Timer/Counter Mode Combinations ........................................................................... 39
Table 24: TMOD Register Bit Description (SFR 0x89) ............................................................................ 40
Table 25: The TCON Register Bit Functions (SFR 0x88) ........................................................................ 40
Table 26: The IEN0 Bit Functions (SFR 0xA8)........................................................................................ 41
Table 27: The IEN1 Bit Functions (SFR 0xB8)........................................................................................ 41
Table 28: The IEN2 Bit Functions (SFR 0x9A)........................................................................................ 42
Table 29: TCON Bit Functions (SFR 0x88) ............................................................................................. 42
Table 30: The T2CON Bit Functions (SFR 0xC8) ................................................................................... 42
Table 31: The IRCON Bit Functions (SFR 0xC0) .................................................................................... 42
Table 32: External MPU Interrupts ......................................................................................................... 44
Table 33: Interrupt Enable and Flag Bits ............................................................................................... 44
Table 34: Interrupt Priority Level Groups ................................................................................................ 45
Table 35: Interrupt Priority Levels .......................................................................................................... 45
Table 36: Interrupt Priority Registers (IP0 and IP1) ................................................................................. 45
Table 37: Interrupt Polling Sequence ..................................................................................................... 46
Table 38: Interrupt Vectors .................................................................................................................... 46
Table 39: Flash Memory Access ............................................................................................................ 48
Table 40: Flash Security ........................................................................................................................ 49
Table 41: Clock System Summary ......................................................................................................... 51
Table 42: RTC Control Registers ........................................................................................................... 52
Table 43: I/O RAM Registers for RTC Temperature Compensation ........................................................ 53
Table 44: NV RAM Temperature Table Structure ................................................................................... 54
Table 45: I/O RAM Registers for RTC Interrupts .................................................................................... 55
Table 46: I/O RAM Registers for Temperature and Battery Measurement .............................................. 56
Table 47: Selectable Resources using the DIO_Rn[2:0] Bits................................................................... 59
Table 48: Data/Direction Registers for SEGDIO0 to SEGDIO14 (71M6541D/F/G) .................................. 61
Table 49: Data/Direction Registers for SEGDIO19 to SEGDIO27 (71M6541D/F/G) ................................ 62
Table 50: Data/Direction Registers for SEGDIO36-39 to SEGDIO44-45 (71M6541D/F/G) ...................... 62
Table 51: Data/Direction Registers for SEGDIO51 and SEGDIO55 (71M6541D/F/G) ............................. 62
Table 52: Data/Direction Registers for SEGDIO0 to SEGDIO15 (71M6542F/G) ..................................... 63
6
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 53: Data/Direction Registers for SEGDIO16 to SEGDIO31 (71M6542F/G) ................................... 64
Table 54: Data/Direction Registers for SEGDIO32 to SEGDIO45 (71M6542F/G) ................................... 64
Table 55: Data/Direction Registers for SEGDIO51 to SEGDIO55 (71M6542F/G) ................................... 64
Table 56: LCD_VMODE[1:0] Configurations .......................................................................................... 65
Table 57: LCD Configurations ............................................................................................................... 67
Table 58: 71M6541D/F/G LCD Data Registers for SEG46 to SEG50 ..................................................... 69
Table 59: 71M6542F/G LCD Data Registers for SEG46 to SEG50......................................................... 70
Table 60: EECTRL Bits for 2-pin Interface............................................................................................... 71
Table 61: EECTRL Bits for the 3-wire Interface ....................................................................................... 71
Table 62: SPI Transaction Fields ........................................................................................................... 74
Table 63: SPI Command Sequences ..................................................................................................... 75
Table 64: SPI Registers ......................................................................................................................... 76
Table 65: TMUX[5:0] Selections ............................................................................................................ 79
Table 66: TMUX2[4:0] Selections........................................................................................................... 79
Table 67: Available Circuit Functions ..................................................................................................... 82
Table 68: VSTAT[2:0] (SFR 0xF9[2:0]) .................................................................................................... 85
Table 69: Wake Enables and Flag Bits .................................................................................................. 87
Table 70: Wake Bits .............................................................................................................................. 89
Table 71: Clear Events for WAKE flags.................................................................................................. 90
Table 72: GAIN_ADJn Compensation Channels .................................................................................... 98
Table 73: GAIN_ADJn Compensation Channels .................................................................................. 100
Table 74: I/O RAM Map – Functional Order, Basic Configuration ......................................................... 105
Table 75: I/O RAM Map – Functional Order ......................................................................................... 107
Table 76: I/O RAM Map – Functional Order ......................................................................................... 111
Table 77. Standard CE Codes ............................................................................................................. 125
Table 78: CE EQU Equations and Element Input Mapping ................................................................... 126
Table 79: CE Raw Data Access Locations ........................................................................................... 127
Table 80: CESTATUS Register .............................................................................................................. 127
Table 81: CESTATUS (CE RAM 0x80) Bit Definitions .............................................................................. 128
Table 82: CECONFIG Register ............................................................................................................. 128
Table 83: CECONFIG (CE RAM 0x20) Bit Definitions ............................................................................. 128
Table 84: Sag Threshold and Gain Adjust Control................................................................................ 129
Table 85: CE Transfer Variables (with Local Sensors).......................................................................... 130
Table 86: CE Transfer Variables (with Remote Sensor) ....................................................................... 130
Table 87: CE Energy Measurement Variables (with Local Sensors) ..................................................... 131
Table 88: CE Energy Measurement Variables (with Remote Sensor) ................................................... 131
Table 89: Other Transfer Variables ...................................................................................................... 132
Table 90: CE Pulse Generation Parameters......................................................................................... 133
Table 91: CE Parameters for Noise Suppression and Code Version..................................................... 134
Table 92: CE Calibration Parameters ................................................................................................... 135
Table 93: Absolute Maximum Ratings .................................................................................................. 138
Table 95: Recommended Operating Conditions ................................................................................... 139
Table 96: Input Logic Levels ................................................................................................................ 140
Table 97: Output Logic Levels ............................................................................................................. 140
Table 98: Battery Monitor Performance Specifications (TEMP_BAT= 1) ................................................ 141
Table 99. Temperature Monitor............................................................................................................ 141
Table 100: Supply Current Performance Specifications ........................................................................ 142
Table 101: V3P3D Switch Performance Specifications ......................................................................... 143
Table 102. Internal Power Fault Comparator Specifications ................................................................. 143
Table 103: 2.5 V Voltage Regulator Performance Specifications .......................................................... 143
Table 104: Low-Power Voltage Regulator Performance Specifications ................................................. 144
Table 105: Crystal Oscillator Performance Specifications ..................................................................... 144
Table 106: PLL Performance Specifications ......................................................................................... 144
Rev 2
7
71M6541D/F/G and 71M6542F/G Data Sheet
Table 107: LCD Driver Performance Specifications .............................................................................. 145
Table 108: LCD Driver Performance Specifications .............................................................................. 146
Table 109: VREF Performance Specifications...................................................................................... 148
Table 110. ADC Converter Performance Specifications ....................................................................... 149
Table 111: Pre-Amplifier Performance Specifications ........................................................................... 150
Table 112: Flash Memory Timing Specifications .................................................................................. 151
Table 113. SPI Slave Timing Specifications ......................................................................................... 151
Table 114: EEPROM Interface Timing ................................................................................................. 151
Table 115: RESET Pin Timing ............................................................................................................. 152
Table 116: RTC Range for Date........................................................................................................... 152
Table 117. 71M6541 Package Markings .............................................................................................. 155
Table 118. 71M6542 Package Markings .............................................................................................. 155
Table 119: Power and Ground Pins ..................................................................................................... 158
Table 120: Analog Pins........................................................................................................................ 159
Table 121: Digital Pins ......................................................................................................................... 160
Table 122. Ordering Information .......................................................................................................... 163
8
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
VREF
IAP
IAN
IBP
IBN
V3P3A
GNDA GNDD
VLCD
V3P3SYS
∆Σ
AD CONVERTER
VBIAS
MUX
and
PREAMP
VBIAS
VLCD
Voltage
Boost
FIR
V3P3A
-
V3P3D
+
VREF
VA
VB*
VREF
VBAT
MUX
MUX CTRL
CROSS
Voltage
Regulator
CK32
XIN
XOUT
MCK
PLL
RTCLK (32KHz)
Oscillator
CK32
32KHz
32 KHz
DIV
ADC
4.9 MHZ
CKADC
VDD
4.9 MHz
CKFIR
22
2.5V to logic
CLOCK GEN
CK_4X
MUX
LCD_GEN
CKMPU_2x
WPULSE
STRT
VARPULSE
CKCE
< 4.9MHz
LCD DRIVER
RTM
32-bit Compute
Engine
TEST
MODE
CEDATA
32 0x000...0x2FF
CE CONTROL
0x0000...0x13FF
COM0..5
6
SPI
TEST
VLC2
VLC1
VLC0
MEMORY SHARE
MPU RAM
3/5 KB
CE
MUX_SYNC
SEG Pins
8
PROG
0x000...0x3FF
SEGDIO Pins
DIGITAL I/O
16
XFER BUSY
EEPROM
INTERFACE
CKMPU
2
VARPULSE
I/O RAM
CE_BUSY
WPULSE
PB
VBAT_RTC
RTC
< 4.9MHz
RTCLK
SDCK
RX
MPU
(80515)
UART0
SDOUT
Non-Volatile
CONFIGURATION
RAM
SDIN
TX
OPT_RX/
SEGDIO55
OPTICAL
INTERFACE
CONFIGURATION
RAM
(I/O RAM)
DATA
0x0000...0xFFFF
0x2000...0x20FF
8
OPT_TX/
SEGDIO51/
WPULSE/
VARPULSE
PROGRAM
0x0000...0xFFFF
VBIAS
8
MEMORY
SHARE
0x0000…
0xFFFF
MPU_RSTZ
CKMPU_2x
16
CONFIGURATION
PARAMETERS
EMULATOR
PORT
WAKE
RTM
FAULTZ
3
VSTAT
* 71M6542F/G only
TEMP
SENSOR
FLASH
32/64/128 KB
8
POWER FAULT
DETECTION
RESET
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
BAT
TEST
TEST MUX
TEST MUX
2
E_RXTX
E_TCLK
E_RST
ICE_E
10/11/2011
Figure 1: IC Functional Block Diagram
Rev 2
9
71M6541D/F/G and 71M6542F/G Data Sheet
1
Introduction
This data sheet covers the 71M6541D (32KB), 71M6541F (64KB), 71M6541G (128KB), 71M6542F
(64KB), and 71M6542G (128KB) fourth generation Teridian energy measurement SoCs. The term
“71M654x” is used when discussing a device feature or behavior that is applicable to all four part
numbers. The appropriate part number is indicated when a device feature or behavior is being discussed
that applies only to a specific part number. This data sheet also covers basic details about the companion
71M6x01 isolated current sensor device. For more complete information on the 71M6x01 sensors, refer
to the 71M6xxx Data Sheet.
This document covers the use of the 71M654x with locally connected sensors as well when it is used in
conjunction with the 71M6x01 isolated current sensor. The 71M654x and 71M6x01 chipset make it
possible to use one non-isolated and one isolated shunt current sensor to create single-phase and twophase energy meters using inexpensive shunt resistors, while achieving unprecedented performance with
this type of sensor technology. The 71M654x SoCs also support configurations involving one locally
connected shunt and one locally connected Current Transformer (CT), or two CTs.
To facilitate document navigation, hyperlinks are often used to reference figures, tables and section
headings that are located in other parts of the document. All hyperlinks in this document are highlighted in
blue. Hyperlinks are used extensively to increase the level of detail and clarity provided within each
section by referencing other relevant parts of the document. To further facilitate document navigation, this
document is published as a PDF document with bookmarks enabled.
The reader is also encouraged to obtain and review the documents listed in 8 Related Information on
page 163 of this document.
10
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
2
Hardware Description
2.1
Hardware Overview
The Teridian 71M6541D/F/G and 71M6542F/G single-chip energy meter ICs integrate all primary
functional blocks required to implement a solid-state residential electricity meter. Included on the chip
are:
•
•
•
•
•
•
•
•
•
•
•
•
•
An analog front end (AFE) featuring a 22-bit second-order sigma-delta ADC
An independent 32-bit digital computation engine (CE) to implement DSP functions
An 8051-compatible microprocessor (MPU) which executes one instruction per clock cycle (80515)
A precision voltage reference (VREF)
A temperature sensor for digital temperature compensation:
- Metrology digital temperature compensation (MPU)
- Automatic RTC digital temperature compensation operational in all power states
LCD drivers
RAM and Flash memory
A real time clock (RTC)
A variety of I/O pins
A power failure interrupt
A zero-crossing interrupt
Selectable current sensor interfaces for locally-connected sensors as well as isolated sensors (i.e.,
using the 71M6x01 companion IC with a shunt resistor sensor)
Resistive Shunt and Current Transformers are supported
Resistive Shunts and Current Transformers (CT) current sensors are supported. Resistive shunt current
sensors may be connected directly to the 71M654x device or isolated using a companion 71M6x01
isolator IC in order to implement a variety of single-phase / split-phase (71M6541D/F/G) or two-phase
(71M6542F/G) metering configurations. An inexpensive, small size pulse transformer is used to isolate
the 71M6x01 isolated sensor from the 71M654x. The 71M654x performs digital communications bidirectionally with the 71M6x01 and also provides power to the 71M6x01 through the isolating pulse
transformer. Isolated (remote) shunt current sensors are connected to the differential input of the
71M6x01. Included on the 71M6x01 companion isolator chip are:
•
•
•
•
•
•
•
Digital isolation communications interface
An analog front end (AFE)
A precision voltage reference (VREF)
A temperature sensor (for digital temperature compensation)
A fully differential shunt resistor sensor input
A pre-amplifier to optimize shunt current sensor performance
Isolated power circuitry obtains dc power from pulses sent by the 71M654x
In a typical application, the 32-bit compute engine (CE) of the 71M654x sequentially processes the samples
from the voltage inputs on analog input pins and from the external 71M6x01 isolated sensors and performs
2
2
calculations to measure active energy (Wh) and reactive energy (VARh), as well as A h, and V h for fourquadrant metering. These measurements are then accessed by the MPU, processed further and output
using the peripheral devices available to the MPU.
In addition to advanced measurement functions, the clock function allows the 71M6541D/F/G and
71M6542F/G to record time-of-use (TOU) metering information for multi-rate applications and to timestamp tamper or other events. Measurements can be displayed on 3.3 V LCDs commonly used in low-temperature environments. An on-chip charge pump is available to drive 5 V LCDs. Flexible mapping of LCD
display segments facilitate integration of existing custom LCDs. Design trade-off between the number of
LCD segments and DIO pins can be implemented in software to accommodate various requirements.
In addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature
compensation mechanism includes a temperature sensor and associated controls for correction of unwanted
temperature effects on measurement and RTC accuracy, e.g., to meet the requirements of ANSI and IEC
Rev 2
11
71M6541D/F/G and 71M6542F/G Data Sheet
standards. Temperature-dependent external components such as crystal oscillator, resistive shunts, current
transformers (CTs) and their corresponding signal conditioning circuits can be characterized and their
correction factors can be programmed to produce electricity meters with exceptional accuracy over the
industrial temperature range.
One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense configuration
and can also function as a standard UART. The optical output can be modulated at 38 kHz. This flexibility
makes it possible to implement AMR meters with an IR interface. A block diagram of the IC is shown in
Figure 1.
2.2
Analog Front End (AFE)
The AFE functions as a data acquisition system, controlled by the MPU. When used with locally
connected sensors, as seen in Figure 2, the analog input signals (IAP-IAN, VA and IBP-IBN) are
multiplexed to the ADC input and sampled by the ADC. The ADC output is decimated by the FIR filter
and stored in CE RAM where it can be accessed and processed by the CE.
See Figure 6 for the multiplexer sequence corresponding to Figure 2. See Figure 35 for the meter
configuration corresponding to Figure 2.
VREF
ILINE
ILINE
CT
Local
or
Shunt
IAP
MUX
VREF
∆Σ ADC
CONVERTER
VREF
IAN
VADC
FIR
CE RAM
22
VADC10 (VA)
IN*
IBP
CT
IBN
71M6541D/F
*IN = Optional Neutral Current
11/5/2010
Figure 2. 71M6541D/F/G AFE Block Diagram (Local Sensors)
12
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Figure 3 shows the 71M6541D/F/G multiplexer interface with one local and one remote resistive shunt
sensor. As seen in Figure 3, when a remote isolated shunt sensor is connected via the 71M6x01, the
samples associated with this current channel are not routed to the multiplexer, and are instead
transferred digitally to the 71M6541D/F/G via the digital isolation interface and are directly stored in CE
RAM.
See Figure 6 for the multiplexer timing sequence corresponding to Figure 3. See Figure 36 for the meter
configurations corresponding to Figure 3.
VREF
ILINE
IAP
Local
Shunt
∆Σ ADC
CONVERTER
MUX
VREF
VREF
IAN
FIR
VADC
VADC10 (VA)
22
CE RAM
IN*
INP
SP
Remote
Shunt
IBP
71M6x01
SN
IBN
Digital
Isolation
Interface
22
INN
71M6541D/F
11/5/2010
* IN = Optional Neutral Current
Figure 3. 71M6541D/F/G AFE Block Diagram with 71M6x01
Figure 4 shows the 71M6542F/G AFE with locally connected sensors. The analog input signals (IAP-IAN,
VA, IBP-IBN and VB) are multiplexed to the ADC input and sampled by the ADC. The ADC output is
decimated by the FIR filter and stored in CE RAM where it can be accessed and processed by the CE.
See Figure 7 for the multiplexer timing sequence corresponding to Figure 4. See Figure 37 for the meter
configuration corresponding to Figure 4.
VREF
IA
IA
IAP
CT
Local
Shunt
or
MUX
VREF
∆Σ ADC
CONVERTER
VREF
IAN
VADC
FIR
CE RAM
22
VADC10 (VA)
VADC9 (VB)
IB
IBP
CT
IBN
71M6542F
11/5/2010
Figure 4. 71M6542F/G AFE Block Diagram (Local Sensors)
Rev 2
13
71M6541D/F/G and 71M6542F/G Data Sheet
Figure 5 shows the 71M6542F/G multiplexer interface with one local and one remote resistive shunt
sensor. As seen in Figure 5, when a remote isolated shunt sensor is connected via the 71M6x01, the
samples associated with this current channel are not routed to the multiplexer, and are instead
transferred digitally to the 71M6542F/G via the digital isolation interface and are directly stored in CE
RAM.
See Figure 6 for the multiplexer timing sequence corresponding to Figure 5. See Figure 38 for the meter
configurations corresponding to Figure 5.
VREF
IA
IAP
Local
Shunt
MUX
VREF
∆Σ ADC
CONVERTER
VREF
IAN
FIR
VADC
VADC10 (VA)
22
VADC9 (VB)
CE RAM
IB
INP
Remote
Shunt
SP
IBP
71M6x01
SN
IBN
Digital
Isolation
Interface
22
INN
71M6542F
11/5/2010
Figure 5. 71M6542F/G AFE Block Diagram with 71M6x01
2.2.1
Signal Input Pins
The 71M6541D/F/G features five ADC inputs. The 71M6542F/G features six ADC inputs.
IAP-IAN and IBP-IBN are intended for use as current sensor inputs. These four current sensor inputs can be
configured as four single-ended inputs, or can be paired to form two differential inputs. For best
performance, it is recommended to configure the current sensor inputs as differential inputs (i.e., IAP-IAN
and IBP-IBN). The first differential input (IAP-IAN) features a pre-amplifier with a selectable gain of 1 or 8,
and is intended for direct connection to a shunt resistor sensor, and can also be used with a Current
Transformer (CT). The remaining differential pair (i.e., IBP-IBN) may be used with CTs, or may be enabled
to interface to a remote 71M6x01 isolated current sensor providing isolation for a shunt resistor sensor using
a low cost pulse transformer.
The remaining input in the 71M6541D/F/G (VA) is single-ended, and is intended for sensing the line voltage
in a single-phase meter application using Equation 0 or 1 (see 2.3.4 Meter Equations on page 25). The
71M6542F/G features an additional single-ended voltage sensing input (VB) to support bi-phase
applications using Equation 2. These single-ended inputs are referenced to the V3P3A pin.
All analog signal input pins measure voltage. In the case of shunt current sensors, currents are sensed as a
voltage drop in the shunt resistor sensor. Referring to Figure 3, shunt sensors can be connected directly to
the 71M654x (referred to as a ‘local’ shunt sensor) or connected via an isolated 71M6x01 (referred to as a
‘remote’ shunt sensor). In the case of Current Transformers (CT), the current is measured as a voltage
across a burden resistor that is connected to the secondary winding of the CT. Meanwhile, line voltages are
sensed through resistive voltage dividers. The VA and VB pins (VB is available in the 71M6542F/G only)
are single-ended and their common return is the V3P3A pin.
Pins IAP-IAN can be programmed individually to be differential or single-ended as determined by the
DIFFA_E (I/O RAM 0x210C[4]) control bit. However, for most applications, IAP-IAN are configured as a
differential input to work with a shunt or CT directly interfaced to the IAP-IAN differential input with the
appropriate external signal conditioning components (see 4.2 Direct Connection of Sensors on page 92).
14
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
The performance of the IAP-IAN pins can be enhanced by enabling a pre-amplifier with a fixed gain of 8,
using the I/O RAM control bit PRE_E (I/O RAM 0x2704[5]). When PRE_E = 1, IAP-IAN become the inputs
to the 8x pre-amplifier, and the output of this amplifier is supplied to the multiplexer. The 8x amplification
is useful when current sensors with low sensitivity, such as shunt resistors, are used. With PRE_E set, the
IAP-IAN input signal amplitude is restricted to 31.25 mV peak.
For the 71M654x application utilizing two shunt resistor sensors (Figure 3), the IAP-IAN pins are configured
for differential mode to interface to a local shunt by setting the DIFFA_E control bit. Meanwhile, the IBP-IBN
pins are re-configured as digital balanced pair to communicate with a Teridian 71M6x01 Isolated Sensor
interface by setting the RMT_E control bit (I/O RAM 0x2709[3]). The 71M6x01 communicates with the
71M654x using a bi-directional digital data stream through an isolating low-cost pulse transformer. The
71M654x also supplies power to the 71M6x01 through the isolating transformer. This type of interface is
further described at the end of this chapter (see 2.2.8 71M6x01 Isolated Sensor Interface (Remote Sensor
Interface)).
For use with Current Transformers (CTs), as shown in Figure 2, the RMT_E control bit is reset, so that the
IBP-IBN pins are configured as local analog inputs. The IAP-IAN pins cannot be configured as a remote
sensor interface.
2.2.2
Input Multiplexer
When operating with local sensors, the input multiplexer sequentially applies the input signals from the analog
input pins to the input of the ADC (see Figure 2 and Figure 4). One complete sampling sequence is called a
multiplexer frame. The multiplexer of the 71M6541D/F/G can select up to three input signals (IAP-IAN, VA,
and IBP-IBN) per multiplexer frame as controlled by the I/O RAM control field MUX_DIV[3:0] (I/O RAM
0x2100[7:4]) (see Figure 6). The multiplexer of the 71M6542F/G adds the VB signal to achieve a total
of four inputs (see Figure 7). The multiplexer always starts at state 1 and proceeds until as many
states as determined by MUX_DIV[3:0] have been converted.
The 71M6541D/F/G and 71M6542F/G each require a unique CE code that is written for the specific
application. Moreover, each CE code requires specific AFE and MUX settings in order to function
properly. Table 1 provides the CE code and settings corresponding to the local sensor configurations
shown in Figure 2 and Figure 4. Table 2 provides the CE code and settings corresponding to the
local/remote sensor configuration utilizing the 71M6x01 as shown in Figure 3 and Figure 5.
Table 1. Required CE Code and Settings for Local Sensors
71M6542F/G
I/O RAM
I/O RAM
71M6541D/F/G
(hex)
Mnemonic
Location
(hex)
Eq. 0 or 1
Eq. 2
FIR_LEN[1:0]
210C[2:1]
1
1
2
ADC_DIV
2200[5]
1
1
0
PLL_FAST
2200[4]
1
1
1
MUX_DIV[3:0]
2100[7:4]
3
3
4
MUX0_SEL[3:0]
2105[3:0]
0
0
0
MUX1_SEL[3:0]
2105[7:4]
A
A
A
MUX2_SEL[3:0]
2104[3:0]
2
2
2
MUX3_SEL[3:0]
2104[7:4]
1
1
9
RMT_E
2709[3]
0
0
0
DIFFA_E
210C[4]
1
1
1
DIFFB_E
210C[5]
1
1
1
EQU[2:0]
2106[7:5]
0 or 1
0 or 1
2
CE41A01
CE Code
-CE41A01
CE41A04
Equations
-0 or 1
0 or 1
2
1 Shunt and 1 CT
1 Shunt and 1 CT 1 Shunt and 1 CT
-or
or
or
Current Sensor Types
Applicable Figure
--
2 CTs
2 CTs
2 CTs
Figure 2
Figure 4
Figure 4
Notes:
Teridian updates the CE code periodically. Please contact your local Teridian representative to obtain the latest CE
code and the associated settings. The configuration presented in this table is set by the MPU demonstration code
during initialization.
Rev 2
15
71M6541D/F/G and 71M6542F/G Data Sheet
Table 2. Required CE Code and Settings for 71M6x01 isolated Sensor
I/O RAM
I/O RAM
71M6541D/F/G
71M6542F/G
Mnemonic
Location
(hex)
(hex)
FIR_LEN[1:0]
210C[2:1]
1
1
ADC_DIV
2200[5]
1
1
PLL_FAST
2200[4]
1
1
MUX_DIV[3:0]
2100[7:4]
3
3
MUX0_SEL[3:0]
2105[3:0]
0
0
MUX1_SEL[3:0]
2105[7:4]
A
A
MUX2_SEL[3:0]1
2104[3:0]
1
9
MUX3_SEL[3:0]1
2104[7:4]
1
1
RMT_E
2709[3]
1
1
DIFFA_E
210C[4]
1
1
DIFFB_E
210C[5]
0
0
EQU[2:0]
2106[7:5]
0 or 1
0, 1 or 2
CE41B0162012
CE Code
-3
CE41B016601
Equations
-0, 1
0, 1 and 2
1 Local Shunt
1 Local Shunt
Current Sensor Type
-and
and
1 Remote Shunt
1 Remote Shunt
Applicable Figure
-Figure 3
Figure 5
Notes:
1. Although not used, set to 1 (the sample data is ignored by the CE)
2. 71M654x with 71M6201 remote sensor (200 Amps)
3. 71M654x with 71M6601 remote sensor (60 Amps)
Teridian updates the CE code periodically. Please contact your local Teridian representative to
obtain the latest CE code and the associated settings. The configuration presented in this table is
set by the MPU demonstration code during initialization.
Using settings for the I/O RAM Mnemonics listed in Table 1 and Table 2 that do not match
those required by the corresponding CE code being used results in undesirable side effects
and must not be selected by the MPU. Consult your local Teridian representative to obtain
the correct CE code and AFE / MUX settings corresponding to the application.
For a basic single-phase application, the IAP-IAN current input is configured for differential mode,
whereas the VA pin is single-ended and is typically connected to the phase voltage via a resistor divider.
The IBP-IBN differential input may be optionally used to sense the Neutral current. This configuration
implies that the multiplexer applies a total of three inputs to the ADC. For this configuration, the
multiplexer sequence is as shown in Figure 6. In this configuration IAP-IAN, IBP-IBN and VA are
sampled, the extra conversion time slot (i.e., slot 2) is the optional Neutral current, and the physical
current sensor for the Neutral current measurement may be omitted if not required.
For a standard single-phase application with tamper sensor in the neutral path, two current inputs can be
configured for differential mode, using the pin pairs IAP-IAN and IBP-IBN. This means that the multiplexer
applies a total of three inputs to the ADC. In this application, the system design may use two locally
connected current sensors via IAP-IAN and IBP-IBN, as shown in Figure 2, and configured as differential
inputs. Alternately, the IAP-IAN pin pair is configured as a differential input and connected to a local current
shunt, and IBP-IBN is configured to connect to an isolated 71M6x01 isolated sensor (i.e., RMT_E = 1), as
shown in Figure 3. The VA pin is typically connected to the phase voltage via resistor dividers. For this
configuration, the multiplexer frame is also as shown in Figure 6 and time slot 2 is unused and ignored by
the CE, as the samples corresponding to the remote sensor (IBP-IBN) do not pass through the
multiplexer and are stored directly in CE RAM. The remote current sensor channel is sampled during the
second half of the multiplexer frame and its timing relationship to the VA voltage is precisely known so
that delay compensation can be properly applied.
The 71M6542F adds the ability to sample a second phase voltage (applied at the VB pin), which makes it
suitable for meters with two voltage and two current sensors, such as meters implementing Equation 2 for
dual-phase operation (P = VA*IA+VB*IB). Figure 7 shows the multiplexer sequence when four inputs are
16
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
processed with locally connected sensors, as shown in Figure 3. When using one local and one remote
sensor (Figure 5), the multiplexer sequence is also as shown in Figure 7.
For both multiplexer sequences shown in Figure 6 and Figure 7, the frame duration is 13 CK32 cycles
(where CK32 = 32768 Hz), therefore, the resulting sample rate is 32768 Hz / 13 = 2520.6 Hz.
Table 3 summarizes the various AFE input configurations.
Multiplexer Frame
Settle
MUX_DIV[3:0] = 3 Conversions
CK32
MUX STATE S
Fig. 2:
Fig. 3:
Fig. 5:
0
IA
IA
IA
1
VA
VA
VA
2
IB
Not Used
VB
S
0
CROSS
MUX_SYNC
11/5/2010
Figure 6: States in a Multiplexer Frame (MUX_DIV[3:0] = 3)
Multiplexer Frame
Settle
MUX_DIV = 4 Conversions
CK32
MUX STATE S
Fig. 4:
0
1
2
3
IA
VA
IB
VB
S
0
CROSS
MUX_SYNC
11/5/2010
Figure 7: States in a Multiplexer Frame (MUX_DIV[3:0] = 4)
Table 3: ADC Input Configuration
Rev 2
Pin
ADC
Channel
IAP
ADC0
IAN
ADC1
IBP
ADC2
IBN
ADC3
VA
ADC10
VB
ADC9
Required
Setting
Comment
Differential mode must be selected with DIFFA_E = 1 (I/O
RAM 0x210C[4]). The ADC results are stored in CE RAM
DIFFA_E = 1
location ADC0 (CE RAM 0x0), and ADC1 (CE RAM 0x1) is not
disturbed.
For locally connected sensors (Figure 2 and Figure 4), the
differential input must be enabled by setting DIFFB_E (I/O
RAM 0x210C[5].
DIFFB_E = 1 For the remote connected sensor (Figure 3 and Figure 5)
with a remote shunt sensor, RMT_E (I/O RAM 0x2709[3])
or
RMT_E = 1 must be set.
In both cases, the ADC results are stored in RAM location
ADC2 (CE RAM 0x2), and ADC3 (CE RAM 0x3) is not
disturbed.
Single-ended mode only. The ADC result is stored in RAM
-location ADC10 (CE RAM 0xA).
Single-ended mode only (71M6542F only). The ADC result
-is stored in RAM location ADC9 (CE RAM 0x9).
17
71M6541D/F/G and 71M6542F/G Data Sheet
Multiplexer advance, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS
signal, see 2.2.7 Voltage References) are controlled by the internal MUX_CTRL circuit. Additionally,
MUX_CTRL launches each pass of the CE through its code. Conceptually, MUX_CTRL is clocked by
CK32, the 32768 Hz clock from the PLL block. The behavior of the MUX_CTRL circuit is governed by:
•
•
•
•
CHOP_E[1:0] (I/O RAM 0x2106[3:2])
MUX_DIV[3:0] (I/O RAM 0x2100[7:4])
FIR_LEN[1:0] (I/O RAM 0x210C[2:1])
ADC_DIV (I/O RAM 0x2200[5])
The duration of each multiplexer state depends on the number of ADC samples processed by the FIR as
determined by the FIR_LEN[1:0] (I/O RAM 0x210C[2:1] control field. Each multiplexer state starts on the
rising edge of CK32, the 32-kHz clock.
It is recommended that MUX_DIV[3:0] (I/O RAM 0x2200[2:0]) be set to zero while changing the ADC
configuration. Although not required, it minimizes system transients that might be caused by momentary
shorts between the ADC inputs, especially when changing the DIFFn_E control bits (I/O RAM 0x210C[5:4]).
After the configuration bits are set, MUX_DIV[3:0] should be set to the required value.
Additionally, the ADC can be configured to operate at ½ rate (32768*75=2.46MHz). In this mode, the
bias current to the ADC amplifiers is reduced and overall system power is reduced. The ADC_DIV (I/O
RAM 0x2200[5]) bit selects full speed or half speed. At half speed, if FIR_LEN[1:0] is set to 01 (288),
each conversion requires 4 XTAL cycles, resulting in a 2520Hz sample rate when MUX_DIV[3:0] = 3.
Note that in order to work with these power-reducing settings, a corresponding CE code is required.
The duration of each time slot in CK32 cycles depends on FIR_LEN[1:0], ADC_DIV and PLL_FAST:
Time_Slot_Duration (PLL_FAST = 1) = (FIR_LEN[1:0]+1) * (ADC_DIV+1)
Time_Slot_Duration (PLL_FAST = 0) = 3*(FIR_LEN[1:0]+1) * (ADC_DIV+1)
The duration of a multiplexer frame in CK32 cycles is:
MUX_Frame_Duration = 3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV[3:0]
The duration of a multiplexer frame in CK_FIR cycles is:
MUX frame duration (CK_FIR cycles) =
[3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV] * (48+PLL_FAST*102)
The ADC conversion sequence is programmable through the MUXx_SEL control fields (I/O RAM 0x2100
to 0x2105). As stated above, there are three ADC time slots in the 71M6541D/F/G and four ADC time
slots in the 71M6542F/G, as set by MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). In the expression
MUXx_SEL[3:0] = n, ‘x’ refers to the multiplexer frame time slot number and n refers to the desired ADC input
number or ADC handle (i.e., ADC0 to ADC10, or simply 0 to 10 decimal). Thus, there are a total of 11 valid
ADC handles in the 71M654x devices. For example, if MUX0_SEL[3:0] = 0, then ADC0, corresponding to the
sample from the IAP-IAN input (configured as a differential input), is positioned in the multiplexer frame during
time slot 0. See Table 1 and Table 2 for the appropriate MUXx_SEL[3:0] settings and other settings
applicable to a particular CE code.
Note that when the remote sensor interface is enabled, and even though the samples corresponding to
the remote sensor current (IBP-IBN) do not pass through the multiplexer, the MUX2_SEL[3:0] and
MUX3_SEL[3:0] control fields must be written with a valid ADC handle that is not being used. Typically,
ADC1 is used for this purpose (see Table 2). In this manner, the ADC1 handle, which is not used in the
71M6541D/F/G or 71M6542F/G, is used as a place holder in the multiplexer frame, in order to generate
the correct multiplexer frame sequence and the correct sample rate. The resulting sample data stored
in CE RAM 0x1 is undefined and is ignored by the CE code. Meanwhile, the digital isolation interface
takes care of automatically storing the samples for the remote interface current (IBP-IBN) in CE RAM
0x2.
18
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Delay compensation and other functions in the CE code require the settings for MUX_DIV[3:0],
MUXx_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_DIV and PLL_FAST to be fixed for a given CE code.
Refer to Table 1 and Table 2 for the settings that are applicable to the 71M6541D/F/G and
71M6542F/G.
Table 4 summarizes the I/O RAM registers used for configuring the multiplexer, signals pins, and ADC.
All listed registers are 0 after reset and wake from battery modes, and are readable and writable.
Table 4: Multiplexer and ADC Configuration Bits
Name
MUX0_SEL[3:0]
MUX1_SEL[3:0]
MUX2_SEL[3:0]
MUX3_SEL[3:0]
MUX4_SEL[3:0]
MUX5_SEL[3:0]
MUX6_SEL[3:0]
MUX7_SEL[3:0]
MUX8_SEL[3:0]
MUX9_SEL[3:0]
MUX10_SEL[3:0]
ADC_DIV
MUX_DIV[3:0]
PLL_FAST
FIR_LEN[1:0]
DIFFA_E
DIFFB_E
Location
Description
Selects the ADC input converted during time slot 0.
Selects the ADC input converted during time slot 1.
Selects the ADC input converted during time slot 2.
Selects the ADC input converted during time slot 3.
Selects the ADC input converted during time slot 4.
Selects the ADC input converted during time slot 5.
Selects the ADC input converted during time slot 6.
Selects the ADC input converted during time slot 7.
Selects the ADC input converted during time slot 8.
Selects the ADC input converted during time slot 9.
Selects the ADC input converted during time slot 10.
Controls the rate of the ADC and FIR clocks.
The number of ADC time slots in each multiplexer frame (maximum = 11).
Controls the speed of the PLL and MCK.
Determines the number of ADC cycles in the ADC decimation FIR filter.
Enables the differential configuration for analog input pins IAP-IAN.
Enables the differential configuration for analog input pins IBP-IBN.
Enables the remote sensor interface transforming pins IBP-IBN into a
RMT_E
digital balanced differential pair for communications with the 71M6x01
2709[3]
sensor.
PRE_E
2704[5]
Enables the 8x pre-amplifier.
Refer to Table 76 starting on page 111 for more complete details about these I/O RAM locations.
2.2.3
2105[3:0]
2105[7:4]
2104[3:0]
2104[7:4]
2103[3:0]
2103[7:4]
2102[3:0]
2102[7:0]
2101[3:0]
2101[7:0]
2100[3:0]
2200[5]
2100[7:4]
2200[4]
210C[1]
210C[4]
210C[5]
Delay Compensation
When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that
phase must be sampled at the same instant. Otherwise, the phase difference, Ф, introduces errors.
φ=
t delay
T
⋅ 360 o = t delay ⋅ f ⋅ 360 o
Where f is the frequency of the input signal, T = 1/f and tdelay is the sampling delay between current and
voltage.
Traditionally, sampling is accomplished by using two A/D converters per phase (one for voltage and the
other one for current) controlled to sample simultaneously. Maxim’s Teridian Single-Converter
Technology, however, exploits the 32-bit signal processing capability of its CE to implement “constant
delay” all-pass filters. The all-pass filter corrects for the conversion time difference between the voltage
and the corresponding current samples that are obtained with a single multiplexed A/D converter.
o
The “constant delay” all-pass filter provides a broad-band delay 360 – θ, which is precisely matched to
the difference in sample time between the voltage and the current of a given phase. This digital filter
does not affect the amplitude of the signal, but provides a precisely controlled phase response.
The recommended ADC multiplexer sequence samples the current first, immediately followed by
sampling of the corresponding phase voltage, thus the voltage is delayed by a phase angle Ф relative to
Rev 2
19
71M6541D/F/G and 71M6542F/G Data Sheet
the current. The delay compensation implemented in the CE aligns the voltage samples with their
corresponding current samples by first delaying the current samples by one full sample interval (i.e.,
o
360 ), then routing the voltage samples through the all-pass filter, thus delaying the voltage samples by
360o - θ, resulting in the residual phase error between the current and its corresponding voltage of θ – Ф.
The residual phase error is negligible, and is typically less than ±1.5 milli-degrees at 100Hz, thus it does
not contribute to errors in the energy measurements.
When using remote sensors, the CE performs the same delay compensation described above to align
each voltage sample with its corresponding current sample. Even though the remote current samples do
not pass through the 71M654x multiplexer, their timing relationship to their corresponding voltages is
fixed and precisely known, provided that the MUXn_SEL[3:0] slot assignment fields are programmed as
shown in Table 1 and Table 2.
2.2.4
ADC Pre-Amplifier
The ADC pre-amplifier is a low-noise differential amplifier with a fixed gain of 8 available only on the IAPIAN sensor input pins. A gain of 8 is enabled by setting PRE_E = 1 (I/O RAM 0x2704[5]). When disabled,
the supply current of the pre-amplifier is <10 nA and the gain is unity. With proper settings of the PRE_E
and DIFFA_E (I/O RAM 0x210C[4]) bits, the pre-amplifier can be used whether differential mode is
selected or not. For best performance, the differential mode is recommended. In order to save power, the
bias current of the pre-amplifier and ADC is adjusted according to the ADC_DIV control bit (I/O RAM
0x2200[5]).
2.2.5
A/D Converter (ADC)
A single 2nd order delta-sigma A/D converter digitizes the voltage and current inputs to the device. The
resolution of the ADC, including the sign bit, is 21 bits (FIR_LEN[1:0] = 1, I/O RAM 0x210C[2:1]), or 22 bits
(FIR_LEN[1:0] = 2). The ADC is clocked by CKADC.
Initiation of each ADC conversion is controlled by MUX_CTRL internal circuit as described above. At the
end of each ADC conversion, the FIR filter output data is stored into the CE RAM location determined by
the multiplexer selection. FIR data is stored LSB justified, but shifted left 9 bits.
2.2.6
FIR Filter
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer.
The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of each
ADC conversion, the output data is stored into the fixed CE RAM location determined by the multiplexer
selection as shown in Table 1 and Table 2.
2.2.7
Voltage References
A bandgap circuit provides the reference voltage to the ADC. The amplifier within the reference is chopper
stabilized, i.e., the chopper circuit can be enabled or disabled by the MPU using the I/O RAM control field
CHOP_E[1:0] (I/O RAM 0x2106[3:2]). The two bits in the CHOP_E[1:0] field enable the MPU to operate the
chopper circuit in regular or inverted operation, or in toggling modes (recommended). When the
chopper circuit is toggled in between multiplexer cycles, dc offsets on VREF are automatically be
averaged out, therefore the chopper circuit should always be configured for one of the toggling modes.
Since the VREF band-gap amplifier is chopper-stabilized, the dc offset voltage, which is the most
significant long-term drift mechanism in the voltage references (VREF), is automatically removed by the
chopper circuit. Both the 71M654x and the 71M6x01 feature chopper circuits for their respective VREF
voltage reference.
The general topology of a chopped amplifier is shown in Figure 8. The CROSS signal is an internal onchip signal and is not accessible on any pin or register.
20
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
A
Vinp
B
A
Vinn
B
A
+
G
-
Voutp
B
A
Voutn
B
CROSS
Figure 8: General Topology of a Chopped Amplifier
It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as
controlled by CROSS (an internal signal), in the A position, the output voltage is:
Voutp – Voutn = G (Vinp + Voff – Vinn) = G (Vinp – Vinn) + G Voff
With all switches set to the B position by applying the inverted CROSS signal, the output voltage is:
Voutn – Voutp = G (Vinn – Vinp + Voff) = G (Vinn – Vinp) + G Voff, or
Voutp – Voutn = G (Vinp – Vinn) - G Voff
Thus, when CROSS is toggled, e.g., after each multiplexer cycle, the offset alternately appears on the
output as positive and negative, which results in the offset effectively being eliminated, regardless of its
polarity or magnitude.
When CROSS is high, the connection of the amplifier input devices is reversed. This preserves the overall
polarity of that amplifier gain; it inverts its input offset. By alternately reversing the connection, the amplifier’s
offset is averaged to zero. This removes the most significant long-term drift mechanism in the voltage
reference. The CHOP_E[1:0] (I/O RAM 0x2106[3:2]) control field controls the behavior of CROSS. The
CROSS signal reverses the amplifier connection in the voltage reference in order to negate the effects of its
offset. On the first CK32 rising edge after the last multiplexer state of its sequence, the multiplexer waits
one additional CK32 cycle before beginning a new frame. At the beginning of this cycle, the value of
CROSS is updated according to the CHOP_E[1:0] field. The extra CK32 cycle allows time for the
chopped VREF to settle. During this cycle, MUXSYNC is held high. The leading edge of MUXSYNC initiates
a pass through the CE program sequence. The beginning of the sequence is the serial readout of the four
RTM words.
CHOP_E[1:0] has four states: positive, reverse, and two toggle states. In the positive state, CHOP_E[1:0]
= 01, CROSS is held low. In the reverse state, CHOP_E[1:0] = 10, CROSS is held high.
Figure 9: CROSS Signal with CHOP_E = 00
Figure 9 shows CROSS over two accumulation intervals when CHOP_E[1:0] = 00: At the end of the
first interval, CROSS is high, at the end of the second interval, CROSS is low. Operation with
CHOP_E[1:0] = 00 does not require control of the chopping mechanism by the MPU.
In the second toggle state, CHOP_E[1:0] = 11, CROSS does not toggle at the end of the last multiplexer
cycle in an accumulation interval.
A second, low-power voltage reference is used in the LCD system and for the comparators that support
transitions to and from the battery modes.
Rev 2
21
71M6541D/F/G and 71M6542F/G Data Sheet
2.2.8
71M6x01 Isolated Sensor Interface (Remote Sensor Interface)
2.2.8.1 General Description
Non-isolating sensors, such as shunt resistors, can be connected to the inputs of the 71M654x via a
combination of a pulse transformer and a 71M6x01 IC (a top-level block diagram of this sensor interface
is shown in Figure 36). The 71M6x01 receives power directly from the 71M654x via a pulse transformer
and does not require a dedicated power supply circuit. The 71M6x01 establishes 2-way communication
with the 71M654x, supplying current samples and auxiliary information such as sensor temperature via a
serial data stream.
One 71M6x01 Isolated Sensor can be supported by the 71M6541D/F/G and 71M6542F/G. When
remote interface IBP-IBN is enabled, the two analog current inputs pins IBP and IBN become a digital
balanced differential interface to the remote sensor. See Table 3 for details.
Each 71M6x01 Isolated Sensor consists of the following building blocks:
•
•
•
•
•
•
Power supply for power pulses received from the 71M654x
Digital communications interface
Shunt signal pre-amplifier
Delta-Sigma ADC Converter with precision bandgap reference (chopping amplifier)
Temperature sensor
Fuse system containing part-specific information
During an ordinary multiplexer cycle, the 71M654x internally determines which other channels are
enabled with MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). At the same time, it decimates the modulator output
from the 71M6x01 Isolated Sensors. Each result is written to CE RAM during one of its CE access time
slots. See Table 3 for the CE RAM locations of the sampled signals.
2.2.8.2 Communication between 71M654x and 71M6x01 Isolated Sensor
The ADC of the 71M6x01 derives its timing from the power pulses generated by the 71M654x and as a
result, operates its ADC slaved to the frequency of the power pulses. The generation of power pulses, as
well as the communication protocol between the 71M654x and 71M6x01 Isolated Sensor is automatic and
transparent to the user. Details are not covered in this data sheet.
2.2.8.3 Control of the 71M6x01 Isolated Sensor
The 71M654x can read or write certain types of information from each 71M6x01 isolated sensor.
The data to be read is selected by a combination of the RCMD[4:0] and TMUXRn[2:0]. To perform a read
transaction from one of the 71M6x01 devices, the MPU first writes the TMUXRn[2:0] field (where n = 2, 4, 6,
located at I/O RAM 0x270A[2:0], 0x270A[6:4] and 0x2709[2:0], respectively). Next, the MPU writes
RCMD[4:0] (SFR 0xFC[4:0]) with the desired command and phase selection. When the RCMD[4:2] bits
have cleared to zero, the transaction has been completed and the requested data is available in
RMT_RD[15:0] (I/O RAM 0x2602[7:0] is the MSB and 0x2603[7:0] is the LSB). The read parity error bit,
PERR_RD (SFR 0xFC[6]) is also updated during the transaction. If the MPU writes to RCMD[4:0] before a
previously initiated read transaction is completed, the command is ignored. Therefore, the MPU must wait
for RCMD[4:2]=0 before proceeding to issue the next remote sensor read command.
The RCMD[4:0] field is divided into two sub-fields, COMMAND=RCMD[4:2] and PHASE=RCMD[1:0], as
shown in Table 5.
Command
RCMD[4:2]
000
Invalid
001
Command 1
100
Reserved
101
Invalid
110
Reserved
22
Table 5. RCMD[4:0] Bits
Phase Selector
RCMD[1:0]
00
Invalid
IBP-IBN
01
Associated TMUXRn
Control Field
--TMUXRB [2:0]
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
111
Reserved
Notes:
1. Only two codes of RCMD[4:2] (SFR 0xFC[4:2]) are relevant for normal
operation. These are RCMD[4:2] = 001 and 010. Codes 000 and 101
are invalid and will be ignored if used. The remaining codes are
reserved and must not be used.
2. For the RCMD[1:0] control field, codes 01, 10 and 11 are valid and 00
is invalid and must not be used.
Table 6 shows the allowable combinations of values in RCMD[4:2] and TMUXRn[2:0], and the
corresponding data type and format sent back by the 71M6x01 isolated sensor and how the data is stored
in RMT_RD[15:8] and RMT_RD[7:0]. The MPU selects which of the three phases is read by asserting the
proper code in the RCMD[1:0] field, as shown in Table 5.
Table 6: Remote Interface Read Commands
RCMD[4:2]
TMUXRn[2:0]
001
00X
Read Operation
TRIMT[7:0]
010
00X
STEMP[10:0]
010
01X
VSENSE[7:0]
010
10X
VERSION[7:0]
(trim fuse for all 71M6x01)
(sensed 71M6x01 temperature)
(sensed 71M6x01 supply voltage)
(chip version)
RMT_RD [15:8]
RMT_RD [7:0]
TRIMT[7]=RMT_RD[8]
TRIMT[6:0]=RMT_RD[7:1]
STEMP[10:8]=RMT_RD[10:8]
STEMP[7:0]
(RMT_RD[15:11] are sign extended)
All zeros
VSENSE[7:0]
VERSION[7:0]
All zeros
Notes:
1. TRIMT[7:0] is the VREF trim value for all 71M6x01 devices. Note that the TRIMT[7:0] 8-bit value is formed
by RMT_RD[8] and RMT_RD[7:1]. See the 71M6xxx Data sheet for more information on TRIMT[7:0]
2. See the 71M6xxx Data Sheet for the equation to calculate temperature from the STEMP[7:0] value read from
the 71M6x01.
3. See the 71M6xxx Data Sheet for the equation to calculate temperature from the VSENSE[7:0] value read from
the 71M6x01.
With hardware and trim-related information on each connected 71M6x01 Isolated Sensor available to the
71M6541D/F/G, the MPU can implement temperature compensation of the energy measurement based on
the individual temperature characteristics of the 71M6x01 Isolated Sensor. See 4.7 Metrology
Temperature Compensation on page 97 for details.
Table 7 shows all I/O RAM registers used for control of the external 71M6x01 Isolated Sensors. See the
71M6xxx Data Sheet for additional details.
Table 7: I/O RAM Control Bits for Isolated Sensor
Name
Address
RST
WAKE
Default Default
RCMD[4:0]
SFR
FC[4:0]
0
0
PERR_RD
PERR_WR
SFR FC[6]
SFR FC[5]
0
0
CHOPR[1:0]
2709[7:6]
00
00
Rev 2
R/W Description
When the MPU writes a non-zero value to RCMD,
the 71M654x issues a command to the corresponding isolated sensor selected with
R/W
RCMD[1:0]. When the command is complete, the
71M654x clears RCMD[4:2]. The command code
itself is in RCMD[4:2].
The 71M654x sets these bits to indicate that a
parity error on the isolated sensor has been deR/W
tected. Once set, the bits are remembered until
they are cleared by the MPU.
The CHOP settings for the isolated sensors.
00 – Auto chop. Change every multiplexer frame.
R/W 01 – Positive
10 – Negative
11 – Same as 00
23
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Address
TMUXRB[2:0] 270A[2:0]
RMT_RD[15:8] 2602[7:0]
RMT_RD[7:0] 2603[7:0]
RST
WAKE
Default Default
000
000
0
R/W Description
R/W The TMUX bits for control of the isolated sensor.
0
R
The read buffer for 71M6x01 read operations.
Controls how the 71M654x drives the 71M6x01
power pulse. When set, the power pulse is driven
210C[3]
RFLY_DIS
0
0
R/W
high and low. When cleared, it is driven high
followed by an open circuit flyback interval.
Enables the isolated remote sensor interface and
RMTB_E
2709[3]
0
0
R/W re-configures pins IBP-IBN as a balanced pair
digital remote interface.
Refer to Table 76 starting on page 111 for more complete details about these I/O RAM locations.
2.3
Digital Computation Engine (CE)
The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately
measure energy. The CE calculations and processes include:
•
•
•
•
•
•
•
•
Multiplication of each current sample with its associated voltage sample to obtain the energy per
sample (when multiplied with the constant sample time).
Frequency-insensitive delay cancellation on all four channels (to compensate for the delay between
samples caused by the multiplexing scheme).
90° phase shifter (for VAR calculations).
Pulse generation.
Monitoring of the input signal frequency (for frequency and phase information).
Monitoring of the input signal amplitude (for sag detection).
Scaling of the processed samples based on calibration coefficients.
Scaling of samples based on temperature compensation information.
2.3.1
CE Program Memory
The CE program resides in flash memory. Common access to flash memory by the CE and MPU is controlled
by a memory share circuit. Each CE instruction word is two bytes long. Allocated flash space for the CE
program cannot exceed 4096 16-bit words (8 KB). The CE program counter begins a pass through the
CE code each time multiplexer state 0 begins. The code pass ends when a HALT instruction is executed.
For proper operation, the code pass must be completed before the multiplexer cycle ends.
The CE program must begin on a 1 KB boundary of the flash address. The I/O RAM control field
CE_LCTN[5:0] (I/O RAM 0x2109[5:0]) defines which 1 KB boundary contains the CE code. Thus, the first
CE instruction is located at 1024*CE_LCTN[5:0].
2.3.2
CE Data Memory
The CE and MPU share data memory (RAM). Common access to XRAM by the CE and MPU is controlled
by a memory share circuit. The CE can access up to 3 KB of the 3 KB data RAM (XRAM), i.e., from RAM
address 0x0000 to 0x0C00.
The XRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time
slots are reserved for FIR and MPU, respectively, to prevent bus contention for XRAM data access by the CE.
The MPU reads and writes the XRAM shared between the CE and MPU as the primary means of data
communication between the two processors.
Table 3 shows the CE addresses in XRAM allocated to analog inputs from the AFE.
The CE is aided by support hardware to facilitate implementation of equations, pulse counters, and
accumulators. This hardware is controlled through the I/O RAM control field EQU[2:0], equation assist
(I/O RAM 0x2106[7:5]), bit DIO_PV (I/O RAM 0x2457[6]), bit DIO_PW, pulse count assist (I/O RAM
0x2457[7]), and SUM_SAMPS[12:0], accumulation assist (I/O RAM 0x2107[4:0] and 0x2108[7:0]).
24
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
SUM_SAMPS[12:0] supports an accumulation scheme where the incremental energy values from up to
SUM_SAMPS[12:0] multiplexer frames are added up over one accumulation interval. The integration time
for each energy output is, for example, SUM_SAMPS[12:0]/2520.6 (with MUX_DIV[3:0] = 011, I/O RAM
0x2100[7:4] and FIR_LEN[1:0] = 10, I/O RAM 0x210C[2:1]). CE hardware issues the XFER_BUSY interrupt
when the accumulation is complete.
2.3.3
CE Communication with the MPU
The CE outputs six signals to the MPU: CE_BUSY, XFER_BUSY, XPULSE, YPULSE, WPULSE and
VPULSE. These are connected to the MPU interrupt service. CE_BUSY indicates that the CE is actively
processing data. This signal occurs once every multiplexer frame. XFER_BUSY indicates that the CE is
updating to the output region of the CE RAM, which occurs whenever an accumulation cycle has been
completed. Both, CE_BUSY and XFER_BUSY are cleared when the CE executes a HALT instruction.
XPULSE, YPULSE, VPULSE and WPULSE can be configured to interrupt the MPU and indicate sag
failures, zero crossings of the mains voltage, or other significant events. Additionally, these signals can
be connected directly to DIO pins to provide direct outputs for the CE. Interrupts associated with these
signals always occur on the leading edge (see “External” interrupt source No. 2 in Figure 16).
2.3.4
Meter Equations
The 71M6541D/F/G and 71M6542F/G provide hardware assistance to the CE in order to support various
meter equations. This assistance is controlled through I/O RAM register EQU[2:0] (equation assist). The
Compute Engine (CE) firmware for industrial configurations can implement the equations listed in Table 8.
EQU[2:0] specifies the equation to be used based on the meter configuration and on the number of
phases used for metering.
Table 8: Inputs Selected in Multiplexer Cycles
Wh and VARh formula
EQU
Description
0
1-element, 2-W, 1φ with
neutral current sense
1
1-element, 3-W, 1φ
2†
2-element, 3-W, 3φ Delta
Element 0
Element 1
Element 2
Recommended
Multiplexer
Sequence
VA ∙ IA
VA ∙ IB1
N/A
IA VA IB1
VA(IA-IB)/2
N/A
N/A
IA VA IB
VA ∙ IA
VB ∙ IB
N/A
IA VA IB VB
Note:
1. Optionally, IB may be used to measure neutral current
† 71M6542F/G only
2.3.5
Real-Time Monitor (RTM)
The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable
XRAM locations at full sample rate. The four monitored locations, as selected by the I/O RAM registers
RTM0[9:8], RTM0[7:0], RTM1[9:8], RTM1[7:0], RTM2[9:8], RTM2[7:0], RTM3[9:8], and RTM3[7:0], are
serially output to the TMUXOUT pin via the digital output multiplexer at the beginning of each CE code
pass. The RTM can be enabled and disabled with control bit RTM_E (I/O RAM 0x2106[1]). The RTM
output is clocked by CKTEST. Each RTM word is clocked out in 35 CKCE cycles (1 CKCE cycle is
equivalent to 203 ns) and contains a leading flag bit. See Figure 10 for the RTM output format. RTM is
low when not in use.
Figure 11 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and
the RTM serial output stream. In this example, MUX_DIV[3:0] = 4 (I/O RAM 0x2100[7:4]) and
FIR_LEN[1:0] = 10 (I/O RAM 0x210C[1]), (384), resulting in 4 ADC conversions. An ADC conversion
always consumes an integer number of CK32 clocks. Followed by the conversions is a single CK32
cycle.
Figure 11 also shows that the RTM serial data stream begins transmitting at the beginning of state S.
RTM, consisting of 140 CK cycles, always finishes before the next CE code pass starts.
Rev 2
25
71M6541D/F/G and 71M6542F/G Data Sheet
CK32
MUX_SYNC
MUX_STATE
S
CKTEST
0
31
FLAG
1
30
31
0
FLAG
1
30
31
SIG
N
30
L SB
1
SIG
N
0
FLAG
L SB
RTM DATA0 (32 bits)
RTM DATA1 (32 bits)
RTM DATA2 (32 bits)
RTM DATA3 (32 bits)
31
SIG
N
30
L SB
1
L SB
0
FLAG
SIG
N
RTM
Figure 10: RTM Timing
ADC MUX Frame
ADC TIMING
MUX_DIV Conversions, MUX_DIV=4 is shown
Settle
CK32
150
MUX_SYNC
MUX STATE
0
S
1
2
S
3
ADC EXECUTION
ADC0
CE TIMING
0
ADC1
450
900
ADC2
ADC3
1350
1800
CE_EXECUTION
CK COUNT = CE_CYCLES + 1CK for each ADC transfer
MAX CK COUNT
CE_BUSY
XFER_BUSY
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
RTM TIMING
140
RTM
NOTES:
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY SUM_SAMPS CODE PASSES.
Figure 11: Timing relationship between ADC MUX, CE, and RTM Serial Transfer
26
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
2.3.6
Pulse Generators
The 71M6541D/F/G and 71M6542F/G provide four pulse generators, VPULSE, WPULSE, XPULSE and
YPULSE, as well as hardware support for the VPULSE and WPULSE pulse generators. The pulse
generators can be used to output CE status indicators, SAG for example, to DIO pins. All pulses can be
configured to generate interrupts to the MPU.
The polarity of the pulses may be inverted with control bit PLS_INV (I/O RAM 0x210C[0]). When this bit is
set, the pulses are active high, rather than the more usual active low. PLS_INV inverts all four pulse
outputs.
The function of each pulse generator is determined by the CE code and the MPU code must configure the
corresponding pulse outputs in agreement with the CE code. For example, standard CE code produces a
mains zero-crossing pulse on XPULSE and a SAG pulse on YPULSE.
A common use of the zero-crossing pulses is to generate interrupt in order to drive real-time clock software
in places where the mains frequency is sufficiently accurate to do so and also to adjust for crystal aging.
A common use for the SAG pulse is to generate an interrupt that alerts the MPU when mains power is about
to fail, so that the MPU code can store accumulated energy and other data to EEPROM before the
V3P3SYS supply voltage actually drops.
2.3.6.1 XPULSE and YPULSE
Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse output pins. Pins
SEGDIO6 and SEGDIO7 are used for these pulses, respectively. Generally, the XPULSE and YPULSE
outputs can be updated once on each pass of the CE code.
See 5.3 CE Interface Description on page 125 for details.
2.3.6.2 VPULSE and WPULSE
Referring to Figure 12, during each CE code pass the hardware stores exported WPULSE and VPULSE sign
bits in an 8-bit FIFO and outputs them at a specified interval. This permits the CE code to calculate the
VPULSE and WPULSE outputs at the beginning of its code pass and to rely on hardware to spread them
over the multiplexer frame. As seen in Figure 12, the FIFO is reset at the beginning of each multiplexer
frame. As also seen in Figure 12, the I/O RAM register PLS_INTERVAL[7:0] (I/O RAM 0x210B[7:0])
controls the delay to the first pulse update and the interval between subsequent updates. The LSB of
the PLS_INTERVAL[7:0] register is equivalent to 4 CK_FIR cycles (CK_FIR is typically 4.9152MHz if
PLL_FAST=1 and ADC_DIV=0, but other CK_FIR frequencies are possible; see the ADC_DIV definition in
Table 76.) If PLS_INTERVAL[7:0]=0, the FIFO is deactivated and the pulse outputs are updated immediately.
The MUX frame duration in units of CK_FIR clock cycles is given by:
If PLL_FAST=1:
MUX frame duration in CK_FIR cycles = [1 + (FIR_LEN+1) * (ADC_DIV+1) * (MUX_DIV)] * [150 / (ADC_DIV+1)]
If PLL_FAST=0:
MUX frame duration in CK_FIR cycles = [3 + 3*(FIR_LEN+1) * (ADC_DIV+1) * (MUX_DIV)] * [48 / (ADC_DIV+1)]
PLS_INTERVAL[7:0] in units of CK_FIR clock cycles is calculated by:
PLS_INTERVAL[7:0] = floor (Mux frame duration in CK_FIR cycles / CE pulse updates per Mux frame / 4 )
Since the FIFO resets at the beginning of each multiplexer frame, the user must specify
PLS_INTERVAL[7:0] so that all of the possible pulse updates occurring in one CE execution are output
before the multiplexer frame completes. For instance, the 71M654x CE code outputs six updates per
multiplexer interval, and if the multiplexer interval is 1950 CK_FIR clock cycles long, the ideal value for
the interval is 1950/6/4 = 81.25. However, if PLS_INTERVAL[7:0] = 82, the sixth output occurs too late and
would be lost. In this case, the proper value for PLS_INTERVAL[7:0] is 81 (i.e., round down the result).
Since one LSB of PLS_INTERVAL[7:0] is equal to 4 CK_FIR clock cycles, the pulse time interval TI in units of
CK_FIR clock cycles is:
TI = 4*PLS_INTERVAL[7:0]
Rev 2
27
71M6541D/F/G and 71M6542F/G Data Sheet
If the FIFO is enabled (i.e., PLS_INTERVAL[7:0] ≠ 0), hardware also provides a maximum pulse width feature
in control register PLS_MAXWIDTH[7:0] (I/O RAM 0x210A) . By default, WPULSE and VPULSE are negative
pulses (i.e., low level pulses, designed to sink current through an LED). PLS_MAXWIDTH[7:0] determines the
maximum negative pulse width TMAX in units of CK_FIR clock cycles based on the pulse interval TI
according to the formula:
TMAX = (2 * PLS_MAXWIDTH[7:0] + 1) * TI
If PLS_MAXWIDTH = 255 or PLS_INTERVAL=0, no pulse width checking is performed, and the pulses
default to 50% duty cycle. TMAX is typically programmed to 10 ms., which works well with most calibration
systems.
The polarity of the pulses may be inverted with the control bit PLS_INV (I/O RAM 0x210C[0]). When
PLS_INV is set, the pulses are active high. The default value for PLS_INV is zero, which selects active low
pulses.
The WPULSE and VPULSE pulse generator outputs are available on pins SEGDIO0/WPULSE and
SEGDIO1/VPULSE, respectively (pins 45 and 44). The pulses can also be output on OPT_TX pin 53
(see OPT_TXE[1:0], I/O RAM 0x2456[3:2] for details).
ADC MUX Frame
Settle
MUX_DIV Conversions (MUX_DIV=4 is shown)
CK32
150
MUX_SYNC
CE CODE
S0
S1
S2
S3
S4
S5
W_FIFO
RST
WPULSE
S0
S1
S0
4*PLS_INTERVAL
4*PLS_INTERVAL
S2
S1
4*PLS_INTERVAL
S3
S2
4*PLS_INTERVAL
S4
S3
4*PLS_INTERVAL
S5
S4
S5
4*PLS_INTERVAL
1. This example shows how the FIFO distributes 6 pulse generator updates over one MUX frame.
2. If WPULSE is low longer than (2*PLS_MAXWIDTH+1) updates, WPULSE will be raised until the next
low-going pulse begins.
3. Only the WPULSE circuit is shown. The VARPULSE circuit behaves identically.
4. All dimensions are in CK_FIR cycles (4.92MHz).
5. If PLS_INTERVAL=0, FIFO does not perform delay.
Figure 12. Pulse Generator FIFO Timing
2.3.7
CE Functional Overview
The 71M654x provides an ADC and multiplexer to sample the analog currents and voltages as seen in
Figure 2 and Figure 3. The VA and VB voltage sensors are formed by resistive voltage dividers directly
connected to the 71M654x device, and therefore always use the ADC and multiplexer facilities in the
71M654x device. Current sensors, however, may be connected directly to the 71M654x or remotely
connected through an isolated 71M6x01 device. The remote 71M6x01 sensor has its own separate ADC
and voltage reference. When a current sensor is connected via a 71M6x01 isolated sensor, the 71M654x
places the sample data received digitally over the isolation interface (via the pulse transformer) in the
appropriate CE RAM location, as shown in Figure 3. The ADCs (i.e., ADC in the 71M654x and the ADC in
the 71M6x01) process their corresponding sensor channels providing one sample per channel per
multiplexer cycle.
Figure 14 (71M6541D/F/G) and Figure 15 (71M6542F/G) show the sampling sequence when both current
sensors (IA and IB) are connected directly to the 71M6541D/F/G as seen in Figure 2. However, when the
28
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
IB channel is a 71M6x01 isolated sensor, the sample data does not pass through the 71M6541D/F/G
multiplexer, as seen in Figure 3. In this case, the sample is taken during the second half of the multiplexer
cycle and the data is directly stored in the corresponding CE RAM location as indicated in Figure 3. The
timing relationship between the remote current sensor channel and its corresponding voltage is precisely
defined so that delay compensation can be properly applied by the CE.
Referring to Figure 15, the 71M6542F/G features an additional voltage input (VB) permitting the
implementation of a two-phase meter. As with VA, the VB voltage divider is directly connected to the
71M6542F/G and uses the ADC and multiplexer facilities in the 71M6542F/G. MUX_DIV[3:0] = 4
configures the multiplexer to provide an additional time slot to accommodate the additional VB voltage
sample. As with the 71M6541D/F/G, IA samples are obtained from a current sensor that is directly
connected to the 71M6542F/G, while IB samples may be obtained from a directly connected CT or a
remotely connected shunt using a 71M6x01 isolated device as seen in Figure 2 and Figure 3.
The number of samples processed during one accumulation cycle is controlled by the I/O RAM register
SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0], 0x2108[7:0]). The integration time for each energy output is:
SUM_SAMPS / 2520.6, where 2520.6 is the sample rate in Hz
For example, SUM_SAMPS = 2100 establishes 2100 samples per accumulation cycle, which has a
duration of 833 ms. After an accumulation cycle is completed, the XFER_BUSY interrupt signals to the
MPU that accumulated data are available.
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each
multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.
Figure 13 shows the accumulation interval resulting from SUM_SAMPS = 2100, consisting of 2100
samples of 397 µs each, followed by the XFER_BUSY interrupt. The sampling in this example is applied
to a 50 Hz signal. There is no correlation between the line signal frequency and the choice of
SUM_SAMPS. Furthermore, sampling does not have to start when the line voltage crosses the zero line,
and the length of the accumulation interval need not be an integer multiple of the signal cycles.
833ms
20ms
XFER_BUSY
Interrupt to MPU
Figure 13: Accumulation Interval
Rev 2
29
71M6541D/F/G and 71M6542F/G Data Sheet
IB
VA
IA
122.07 µs
30.5
µs
122.07 µs
122.07 µs
Multiplexer Frame (13 x 30.518 µs = 396.7 µs -> 2520.6 Hz)
MUX_DIV[3:0] = 3 Conversions
Settle
CK32
(32768 Hz)
MUX STATE
S
0
1
S
2
Figure 14: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 3)
VB
IB
VA
IA
91.5 µs
91.5 µs
91.5 µs
30.5 µs
91.5 µs
Multiplexer Frame (13 x 30.518 µs = 396 µs à2520Hz)
MUX_DIV[3:0] = 4 Conversions
Settle
CK32
(32768 Hz)
MUX STATE S
0
1
2
3
S
Figure 15: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 4)
30
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
2.4
80515 MPU Core
The 71M6541D/F/G and 71M6542F/G include an 80515 MPU (8-bit, 8051-compatible) that processes
most instructions in one clock cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS.
The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and
execution phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte
instructions are performed in a single machine cycle (MPU clock cycle). This leads to an 8x average
performance improvement (in terms of MIPS) over the Intel 8051 device running at the same clock
frequency.
Table 9 shows the CKMPU frequency as a function of the MCK clock (19.6608 MHz) divided by the MPU
clock divider which is set in the I/O RAM control field MPU_DIV[2:0] (I/O RAM 0x2200[2:0]). Actual processor
clocking speed can be adjusted to the total processing demand of the application (metering calculations,
AMR management, memory management, LCD driver management and I/O management) using
MPU_DIV[2:0], as shown in Table 9.
Table 9: CKMPU Clock Frequencies
MPU_DIV [2:0]
000
001
010
011
100
101
110
111
CKMPU Frequency
4.9152 MHz
2.4576 MHz
1.2288 MHz
614.4 kHz
307.2 kHz
Typical measurement and metering functions based on the results provided by the internal 32-bit compute
engine (CE) are available for the MPU as part of the Teridian standard library. Teridian provides
demonstration source code to help reduce the design cycle.
2.4.1
Memory Organization and Addressing
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memory
organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas:
Program memory (Flash, shared by MPU and CE), external RAM (Data RAM, shared by the CE and MPU,
Configuration or I/O RAM), and internal data memory (Internal RAM). Table 10 shows the memory map.
Program Memory
The 80515 can address up to 64 KB of program memory space (0x0000 to 0xFFFF). Program memory is
read when the MPU fetches instructions or performs a MOVC operation.
After reset, the MPU starts program execution from program memory location 0x0000. The lower part of
the program memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte
intervals, starting from 0x0003.
MPU External Data Memory (XRAM)
Both internal and external memory is physically located on the 71M654x device. The external memory
referred in this documentation is only external to the 80515 MPU core.
3 KB of RAM starting at address 0x0000 is shared by the CE and MPU. The CE normally uses the first
1 KB, leaving 2 KB for the MPU. Different versions of the CE code use varying amounts. Consult the
documentation for the specific code version being used for the exact limit.
If the MPU overwrites the CE’s working RAM, the CE’s output may be corrupted. If the CE is
disabled, the first 0x40 bytes of RAM are still unusable while MUX_DIV[3:0] ≠ 0 because the
71M654x ADC writes to these locations. Setting MUX_DIV[3:0] = 0 disables the ADC output
preventing the CE from writing the first 0x40 bytes of RAM.
In addition, MUXn_SEL[3:0] values must be written only after writing MUX_DIV[3:0].
Rev 2
31
71M6541D/F/G and 71M6542F/G Data Sheet
The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX
@DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX
A,@DPTR instruction (PDATA, SFR 0xBF, provides the upper 8 bytes for the MOVX A,@Ri instruction).
Internal and External Memory Map
Table 10 shows the address, type, use and size of the various memory components.
Table 10: Memory Map
Address
(hex)
0000-7FFF
Memory
Technology
Flash Memory
Memory
Type
Name
Program memory
Non-volatile
for MPU and CE
Typical Usage
Memory Size
(bytes)
MPU Program and
non-volatile data
64/32 KB †
CE program (on 1
KB boundary)
3 KB max.
0000-0BFF
Static RAM
Volatile
External RAM
(XRAM)
Shared by CE and
MPU
5/3 KB †
2000-27FF
Static RAM
Volatile
Configuration
RAM (I/O RAM)
Hardware control
2 KB
2800-287F
Static RAM
Non-volatile
(battery)
Configuration
RAM (I/O RAM)
Battery-buffered
memory
128
0000-00FF
Static RAM
Volatile
Internal RAM
Part of 80515 Core
256
† Memory size depends on IC. See 2.5.1 Physical Memory for details.
MOVX Addressing
There are two types of instructions differing in whether they provide an 8-bit or 16-bit indirect address to
the external data RAM.
In the first type, MOVX A,@Ri, the contents of R0 or R1 in the current register bank provide the eight
lower-ordered bits of address. The eight high-ordered bits of the address are specified with the PDATA
SFR. This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the
external data RAM.
In the second type of MOVX instruction, MOVX A,@DPTR, the data pointer generates a 16-bit address.
This form is faster and more efficient when accessing very large data arrays (up to 64 KB), since no
additional instructions are needed to set up the eight high ordered bits of the address.
It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two
with direct access and two with paged access, to the entire external memory range.
Dual Data Pointer
The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that
is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called
DPTR, the second data pointer is called DPTR1. The data pointer select bit, located in the LSB of the DPS
register (DPS[0], SFR 0x92), chooses the active pointer. DPTR is selected when DPS[0] = 0 and DPTR1 is
selected when DPS[0] = 1.
The user switches between pointers by toggling the LSB of the DPS register. The values in the data pointers
are not affected by the LSB of the DPS register. All DPTR related instructions use the currently selected
DPTR for any activity.
The second data pointer may not be supported by certain compilers.
DPTR1 is useful for copy routines, where it can make the inner loop of the routine two instructions faster
compared to the reloading of DPTR from registers. Any interrupt routine using DPTR1 must save and
restore DPS, DPTR and DPTR1, which increases stack usage and slows down interrupt latency.
By selecting the R80515 core in the Keil compiler project settings and by using the compiler directive
“MODC2”, dual data pointers are enabled in certain library routines.
32
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
An alternative data pointer is available in the form of the PDATA register (SFR 0xBF), sometimes referred
to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction
MOVX A,@Ri or MOVX @Ri,A.
Internal Data Memory Map and Access
The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory
address is always 1 byte wide. Table 11 shows the internal data memory map.
The Special Function Registers (SFR) occupy the upper 128 bytes. The SFR area of internal data memory
is available only by direct addressing. Indirect addressing of this area accesses the upper 128 bytes of
Internal RAM. The lower 128 bytes contain working registers and bit addressable memory. The lower 32
bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW, SFR
0xD0 ) select which bank is in use. The next 16 bytes form a block of bit addressable memory space at
addresses 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect
addressing.
Table 11: Internal Data Memory Map
Address Range
2.4.2
Direct Addressing
Indirect Addressing
Special Function Registers (SFRs)
RAM
0x80
0xFF
0x30
0x7F
Byte addressable area
0x20
0x00
0x2F
0x1F
Bit addressable area
Register banks R0…R7
Special Function Registers (SFRs)
A map of the Special Function Registers is shown in Table 12.
Only a few addresses in the SFR memory space are occupied, the others are not implemented. A read
access to unimplemented addresses returns undefined data, while a write access has no effect. SFRs
specific to the 71M654x are shown in bold print on a shaded field. The registers at 0x80, 0x88, 0x90,
etc., are bit addressable, all others are byte addressable.
Table 12: Special Function Register Map
Hex/
Bin
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
Rev 2
Bit
Addressable
X000
Byte Addressable
X001
X010
INTBITS
VSTAT
B
IFLAGS
A
WDCON
PSW
T2CON
IRCON
IEN1
IP1
S0RELH
P3 (DIO12:15)
FLSHCTL
IEN0
IP0
S0RELL
P2 (DIO8:11)
S0CON
S0BUF
IEN2
DPS
P1(DIO4:7)
TCON
TMOD
TL0
P0 (DIO0:3)
SP
DPL
X011
X100
X101
RCMD
SPI_CMD
X110
S1RELH
S1CON
TL1
DPH
X111
PDATA
FLSHPG
S1BUF
ERASE
TH0
DPL1
S1RELL
TH1
DPH1
EEDATA EECTRL
CKCON
PCON
Bin/
Hex
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
8F
87
33
71M6541D/F/G and 71M6542F/G Data Sheet
2.4.3
Generic 80515 Special Function Registers
Table 13 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional
descriptions of the registers can be found at the page numbers listed in the table.
Table 13: Generic 80515 SFRs - Location and Reset Values
Name
P0
SP
DPL
DPH
DPL1
DPH1
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
P1
DPS
S0CON
S0BUF
IEN2
S1CON
S1BUF
S1RELL
P2
IEN0
IP0
S0RELL
P3
IEN1
IP1
S0RELH
S1RELH
PDATA
IRCON
T2CON
PSW
WDCON
A
B
34
Address
(Hex)
0x80
0x81
0x82
0x83
0x84
0x85
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x90
0x92
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0xA0
0xA8
0xA9
0xAA
0xB0
0xB8
0xB9
0xBA
0xBB
0xBF
0xC0
0xC8
0xD0
0xD8
0xE0
0xF0
Reset value
Description
(Hex)
0xFF
Port 0
0x07
Stack Pointer
0x00
Data Pointer Low 0
0x00
Data Pointer High 0
0x00
Data Pointer Low 1
0x00
Data Pointer High 1
0x00
UART Speed Control
0x00
Timer/Counter Control
0x00
Timer Mode Control
0x00
Timer 0, low byte
0x00
Timer 1, high byte
0x00
Timer 0, low byte
0x00
Timer 1, high byte
0x01
Clock Control (Stretch=1)
0xFF
Port 1
0x00
Data Pointer select Register
0x00
Serial Port 0, Control Register
0x00
Serial Port 0, Data Buffer
0x00
Interrupt Enable Register 2
0x00
Serial Port 1, Control Register
0x00
Serial Port 1, Data Buffer
0x00
Serial Port 1, Reload Register, low byte
0xFF
Port 2
0x00
Interrupt Enable Register 0
0x00
Interrupt Priority Register 0
0xD9
Serial Port 0, Reload Register, low byte
0xFF
Port 3
0x00
Interrupt Enable Register 1
0x00
Interrupt Priority Register 1
0x03
Serial Port 0, Reload Register, high byte
0x03
Serial Port 1, Reload Register, high byte
High address byte for MOVX@Ri - also called USR2
0x00
0x00
Interrupt Request Control Register
0x00
Polarity for INT2 and INT3
0x00
Program Status Word
0x00
Baud Rate Control Register (only WDCON[7] bit used)
0x00
Accumulator
0x00
B Register
Page
36
35
35
35
35
35
39
42
40
39
39
39
39
36
36
32
38
36
42
38
36
36
36
41
45
36
36
41
45
36
36
32
42
42
35
36
35
35
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Accumulator (ACC, A, SFR 0x E0):
ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The
mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC.
B Register (SFR 0xF0):
The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register
to hold temporary data.
Program Status Word (PSW, SFR 0xD0 ):
This register contains various flags and control bits for the selection of the register banks (see Table 14).
Table 14: PSW Bit Functions (SFR 0xD0)
PSW Bit
Symbol
7
6
5
CV
AC
F0
Function
Carry flag.
Auxiliary Carry flag for BCD operations.
General purpose Flag 0 available for user.
F0 is not to be confused with the F0 flag in the CESTATUS register.
4
RS1
3
RS0
2
1
0
OV
–
P
Register bank select control bits. The contents of RS1 and RS0 select the
working register bank:
Bank selected
Location
RS1/RS0
00
Bank 0
0x00 – 0x07
01
Bank 1
0x08 – 0x0F
10
Bank 2
0x10 – 0x17
11
Bank 3
0x18 – 0x1F
Overflow flag.
User defined flag.
Parity flag, affected by hardware to indicate odd or even number of one bits in
the Accumulator, i.e., even parity.
Stack Pointer (SP, SFR 0x81):
The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before
PUSH and CALL instructions, causing the stack to begin at location 0x08.
Data Pointer:
The data pointers (DPTR and DPRT1) are 2 bytes wide. The lower part is DPL (SFR 0x82) and DPL1 (SFR
0x84), respectively. The highest is DPH (SFR 0x83) and DPH1 (SFR 0x85), respectively. The data pointers
can be loaded as two registers (e.g., MOV DPL,#data8). They are generally used to access external
code or data space (e.g., MOVC A,@A+DPTR or MOVX A,@DPTR respectively).
Program Counter:
The program counter (PC) is 2 bytes wide and initialized to 0x0000 after reset. This register is incremented
when fetching operation code or when operating on data from program memory.
Port Registers:
SEGDIO0 through SEGDIO15 are controlled by Special Function Registers P0, P1, P2 and P3 as shown in
Table 15. Above SEGDIO15, the LCD_SEGDIOn[ ] registers in I/O RAM are used. Since the direction bits
are contained in the upper nibble of each SFR Pn register and the DIO bits are contained in the lower nibble,
it is possible to configure the direction of a given DIO pin and set its output value with a single write operation,
thus facilitating the implementation of bit-banged interfaces. Writing a 1 to a DIO_DIR bit configures the
corresponding DIO as an output, while writing a 0 configures it as an input. Writing a 1 to a DIO bit causes
the corresponding pin to be at high level (V3P3), while writing a 0 causes the corresponding pin to be held
at a low level (GND). See 2.5.8 Digital I/O for additional details.
Rev 2
35
71M6541D/F/G and 71M6542F/G Data Sheet
Table 15: Port Registers (SEGDIO0-15)
SFR
Name
P0
P1
P2
P3
SFR
Address
D7
0x80
0x90
0xA0
0xB0
D6
D5
D4
D3
DIO_DIR[3:0]
DIO_DIR[7:4]
DIO_DIR[11:8]
DIO_DIR[15:12]
D2
D1
D0
DIO[3:0]
DIO[7:4]
DIO[11:8]
DIO[15:11]
Ports P0-P3 on the chip are bi-directional and control SEGDIO0-15. Each port consists of a Latch (SFR
P0 to P3), an output driver and an input buffer, therefore the MPU can output or read data through any of
these ports. Even if a DIO pin is configured as an output, the state of the pin can still be read by the
MPU, for example when counting pulses issued via DIO pins that are under CE control.
At power-up SEGDIO0-15 are configured as inputs. It is necessary to write PORT_E = 1 (I/O RAM
0x270C[5]) to enable SEGDIO0-15. The default PORT_E = 0 blocks any momentary output
transient pulses that would otherwise occur when SEGDIO0-15 are reset on power-up.
Clock Stretching (CKCON)
The three low order bits of the CKCON[2:0] (SFR 0x8E) register define the stretch memory cycles that
are used for MOVX instructions when accessing external peripherals. The practical value of this register
for the 71M6541D/F/G and 71M6542F/G is to guarantee access to XRAM between CE, MPU, and SPI.
The default setting of CKCON[2:0] (001) should not be changed.
Table 16 shows how the signals of the External Memory Interface change when stretch values are set
from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the
CKCON[2:0] (001), which is shown in bold in the table, performs the MOVX instructions with a stretch
value equal to 1.
Table 16: Stretch Memory Cycle Width
2.4.4
Read Signal Width
Write Signal Width
CKCON[2:0]
Stretch
Value
memaddr
memrd
memaddr
memwr
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
1
1
2
3
4
5
6
7
Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set
and of the associated op-codes is contained in the 71M654X Software User’s Guide (SUG).
2.4.5
UARTs
The 71M6541D/F/G and 71M6542F/G include a UART (UART0) that can be programmed to
communicate with a variety of AMR modules and other external devices. A second UART (UART1) is
connected to the optical port, as described in 2.5.7 UART and Optical Interface.
The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor
at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0 pins is as
follows:
36
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
•
•
UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are
input LSB first.
UART0 TX: This pin is used to output the serial data. The bytes are output LSB first.
Several UART-related registers are available for the control and buffering of serial data.
A single SFR register serves as both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0
and S1BUF, SFR 0x9C for UART1). When written by the MPU, SxBUF acts as the transmit buffer, and
when read by the MPU, it acts as the receive buffer. Writing data to the transmit buffer starts the
transmission by the associated UART. Received data are available by reading from the receive buffer.
Both UARTs can simultaneously transmit and receive data.
WDCON[7] (SFR 0xD8) selects whether timer 1 or the internal baud rate generator is used. All UART
transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for
variable communication baud rates from 300 to 38400 bps. Table 17 shows how the baud rates are
calculated. Table 18 shows the selectable UART operation modes.
Table 17: Baud Rate Generation
Using Timer 1
(WDCON[7] = 0)
smod
UART0
2
UART1
N/A
* f CKMPU/ (384 * (256-TH1))
Using Internal Baud Rate Generator
(WDCON[7] = 1)
smod
2
10
* f CKMPU/(64 * (2 -S0REL))
fCKMPU/(32 * (210-S1REL))
S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers.
(S0RELL, S0RELH, S1RELL, S1RELH are SFR 0xAA, SFR 0xBA, SFR 0x9D and SFR 0xBB, respectively) SMOD
is the SMOD bit in the SFR PCON register (SFR 0x87). TH1(SFR 0x8D) is the high byte of timer 1.
Table 18: UART Modes
UART 0
Mode 0
Mode 1
Mode 2
Mode 3
N/A
Start bit, 8 data bits, stop bit, variable
baud rate (internal baud rate generator
or timer 1)
Start bit, 8 data bits, parity, stop bit,
fixed baud rate 1/32 or 1/64 of fCKMPU
Start bit, 8 data bits, parity, stop bit,
variable baud rate (internal baud rate
generator or timer 1)
UART 1
Start bit, 8 data bits, parity, stop bit, variable
baud rate (internal baud rate generator)
Start bit, 8 data bits, stop bit, variable baud
rate (internal baud rate generator)
N/A
N/A
Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with
parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of
8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant
th
1. 8-bit serial modes with parity can be simulated by setting and reading the 9 bit, using the
control bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (SFR 0x9B)
registers for transmit and RB81 bit in S1CON[2] for receive operations.
The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals
for inter-processor communication in multi-processor systems. In this case, the slave processors have bit
SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master processor outputs
th
the slave’s address, it sets the 9 bit to 1, causing a serial port receive interrupt in all the slaves. The
slave processors compare the received byte with their address. If there is a match, the addressed slave
clears SM20 or SM21 and receive the rest of the message. The rest of the slave’s ignores the
th
message. After addressing the slave, the host outputs the rest of the message with the 9 bit set to 0, so
no additional serial port receive interrupts are generated.
Rev 2
37
71M6541D/F/G and 71M6542F/G Data Sheet
UART Control Registers:
The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON
and S1CON shown in Table 19 and Table 20, respectively, and the PCON register shown in Table 21.
Since the TI0, RI0, TI1 and RI1 bits are in an SFR bit addressable byte, common practice
would be to clear them with a bit operation, but this must be avoided. The hardware implements
bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after
the read, but before the write, its flag is cleared unintentionally.
The proper way to clear these flag bits is to write a byte mask consisting of all ones except for
a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
Table 19: The S0CON (UART0) Register (SFR 0x98)
Bit
S0CON[7]
Symbol
SM0
S0CON[6]
SM1
S0CON[5]
S0CON[4]
S0CON[3]
SM20
REN0
TB80
S0CON[2]
RB80
S0CON[1]
TI0
S0CON[0]
RI0
Function
The SM0 and SM1 bits set the UART0 mode:
Mode
Description
SM0
SM1
0
N/A
0
0
1
8-bit UART
0
1
2
9-bit UART
1
0
3
9-bit UART
1
1
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the
MPU, depending on the function it performs (parity check, multiprocessor
communication etc.)
th
In Modes 2 and 3 it is the 9 data bit received. In Mode 1, SM20 is 0,
RB80 is the stop bit. In mode 0, this bit is not used. Must be cleared by
software.
Transmit interrupt flag; set by hardware after completion of a serial transfer.
Must be cleared by software (see Caution above).
Receive interrupt flag; set by hardware after completion of a serial reception.
Must be cleared by software (see Caution above).
Table 20: The S1CON (UART1) Register (SFR 0x9B)
Bit
S1CON[7]
Symbol
SM
Function
Sets the baud rate and mode for UART1.
SM
0
1
S1CON[5]
S1CON[4]
S1CON[3]
SM21
REN1
TB81
S1CON[2]
RB81
S1CON[1]
TI1
S1CON[0]
RI1
38
Mode
A
B
Description
9-bit UART
8-bit UART
Baud Rate
variable
variable
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Mode A. Set or cleared by the MPU,
depending on the function it performs (parity check, multiprocessor
communication etc.)
th
In Modes A and B, it is the 9 data bit received. In Mode B, if SM21 is 0,
RB81 is the stop bit. Must be cleared by software
Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software (see Caution above).
Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software (see Caution above).
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 21: PCON Register Bit Description (SFR 0x87)
Bit
PCON[7]
2.4.6
Symbol
SMOD
Function
The SMOD bit doubles the baud rate when set
Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured
for counter or timer operations.
In timer mode, the register is incremented every machine cycle, i.e., it counts up once for every 12 periods
of the MPU clock. In counter mode, the register is incremented when the falling edge is observed at the
corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins,
see 2.5.8 Digital I/O). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input
count rate is 1/2 of the clock frequency (CKMPU). There are no restrictions on the duty cycle, however
to ensure proper recognition of the 0 or 1 state, an input should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1, as shown in Table 22 and Table 23. The
TMOD (SFR 0x89) Register, shown in Table 24, is used to select the appropriate mode. The timer/counter
operation is controlled by the TCON (SFR 0x88) Register, which is shown in Table 25. Bits TR1 (TCON[6])
and TR0 (TCON[4]) in the TCON register start their associated timers when set.
Table 22: Timers/Counters Mode Description
M1
M0
Mode
0
0
Mode 0
0
1
1
0
Mode 1
Mode 2
1
1
Mode 3
Function
13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 (SFR
0x8A or SFR 0x8B) register and the remaining 8 bits in the TH0 or TH1
(SFR 0x8C or SFR 0x8D) register (for Timer 0 and Timer 1, respectively).
The 3 high order bits of TL0 and TL1 are held at zero.
16-bit Counter/Timer mode.
8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or
TH1, while TL0 or TL1 is incremented every machine cycle. When
TL(x) overflows, a value from TH(x) is copied to TL(x) (where x is 0
for counter/timer 0 or 1 for counter/timer 1.
If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops.
If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent
8-bit Timer/Counters.
In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on overflow, while TH0
is affected by the TR1 bit, and the TF1 flag is set on overflow.
Table 23 specifies the combinations of operation modes allowed for Timer 0 and Timer 1.
Table 23: Allowed Timer/Counter Mode Combinations
Timer 1
Timer 0 - mode 0
Timer 0 - mode 1
Timer 0 - mode 2
Rev 2
Mode 0
Yes
Yes
Not allowed
Mode 1
Yes
Yes
Not allowed
Mode 2
Yes
Yes
Yes
39
71M6541D/F/G and 71M6542F/G Data Sheet
Table 24: TMOD Register Bit Description (SFR 0x89)
Bit
Symbol Function
Timer/Counter 1
TMOD[7]
Gate
If TMOD[7] is set, external input signal control is enabled for Counter 1. The
TR1 bit in the TCON register (SFR 0x88) must also be set in order for Counter 1 to
increment. With these settings, Counter 1 increments on every falling edge of the
logic signal applied to one or more of the SEGDIO2-11 pins, as specified by the
contents of the DIO_R2 through DIO_R11 registers. See 2.5.8 Digital I/O and
LCD Segment Drivers and Table 47.
TMOD[6]
C/T
Selects timer or counter operation. When set to 1, a counter operation is performed.
When cleared to 0, the corresponding register functions as a timer.
TMOD[5:4] M1:M0
Selects the mode for Timer/Counter 1, as shown in Table 22.
Timer/Counter 0:
TMOD[3]
Gate
If TMOD[3] is set, external input signal control is enabled for Counter 0. The
TR0 bit in the TCON register (SFR 0x88) must also be set in order for Counter 0 to
increment. With these settings, Counter 0 is incremented on every falling edge of
the logic signal applied to one or more of the SEGDIO2-11 pins, as specified by
the contents of the DIO_R2 through DIO_R11 registers. See 2.5.8 Digital I/O and
LCD Segment Drivers and Table 47.
TMOD[2]
C/T
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register functions as a timer.
TMOD[1:0] M1:M0
Selects the mode for Timer/Counter 0 as shown in Table 22.
Table 25: The TCON Register Bit Functions (SFR 0x88)
Bit
TCON[7]
TCON[6]
TCON[5]
TCON[4]
TCON[3]
TCON[2]
TCON[1]
TCON[0]
2.4.7
Symbol Function
TF1
The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag
can be cleared by software and is automatically cleared when an interrupt is
processed.
TR1
Timer 1 run control bit. If cleared, Timer 1 stops.
TF0
Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be
cleared by software and is automatically cleared when an interrupt is processed.
TR0
Timer 0 Run control bit. If cleared, Timer 0 stops.
IE1
Interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is
observed. Cleared when an interrupt is processed.
IT1
Interrupt 1 type control bit. Selects either the falling edge or low level on input pin
to cause an interrupt.
IE0
Interrupt 0 edge flag is set by hardware when the falling edge on external pin int0 is
observed. Cleared when an interrupt is processed.
IT0
Interrupt 0 type control bit. Selects either the falling edge or low level on input pin
to cause interrupt.
WD Timer (Software Watchdog Timer)
There is no internal software watchdog timer. Use the standard hardware watchdog timer instead (see
2.5.11 Hardware Watchdog Timer).
2.4.8
Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own interrupt request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by
40
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
the corresponding interrupt flag can be individually enabled or disabled by the interrupt enable bits in the
IEN0 (SFR 0xA8), IEN1 (SFR 0xB8), and IEN2 (SFR 0x9A).
Figure 16 shows the device interrupt structure.
Referring to Figure 16, interrupt sources can originate from within the 80515 MPU core (referred to as
Internal Sources) or can originate from other parts of the 71M654x SoC (referred to as External Sources).
There are seven external interrupt sources, as seen in the leftmost part of Figure 16, and in Table 26 and
Table 27 (i.e., EX0-EX6).
Interrupt Overview
When an interrupt occurs, the MPU vectors to the predetermined address as shown in Table 38. Once
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service
is terminated by a return from interrupt instruction, RETI. When a RETI instruction is performed, the
processor returns to the instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the processor also indicates this by setting a flag bit. This bit is set
regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, and then samples are polled by the hardware. If the sample indicates a pending interrupt
when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the
interrupt is acknowledged by hardware forcing an LCALL to the appropriate vector address, if the
following conditions are met:
•
•
•
No interrupt of equal or higher priority is already in progress.
An instruction is currently being executed and is not completed.
The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
Special Function Registers for Interrupts
The following SFR registers control the interrupt functions:
•
•
•
•
•
The interrupt enable registers: IEN0, IEN1 and IEN2 (see Table 26, Table 27 and Table 28).
The Timer/Counter control registers, TCON and T2CON (see
Table 29 and Table 30).
The interrupt request register, IRCON (see Table 31).
The interrupt priority registers: IP0 and IP1 (see Table 36).
Table 26: The IEN0 Bit Functions (SFR 0xA8)
Bit
IEN0[7]
IEN0[6]
IEN0[5]
IEN0[4]
IEN0[3]
IEN0[2]
IEN0[1]
IEN0[0]
Symbol
EAL
WDT
–
ES0
ET1
EX1
ET0
EX0
Function
EAL = 0 disables all interrupts.
Not used for interrupt control.
Not Used.
ES0 = 0 disables serial channel 0 interrupt.
ET1 = 0 disables timer 1 overflow interrupt.
EX1 = 0 disables external interrupt 1: DIO status change
ET0 = 0 disables timer 0 overflow interrupt.
EX0 = 0 disables external interrupt 0: DIO status change
Table 27: The IEN1 Bit Functions (SFR 0xB8)
Rev 2
Bit
IEN1[7]
IEN1[6]
IEN1[5]
Symbol
–
–
EX6
IEN1[4]
IEN1[3]
EX5
EX4
Function
Not used.
Not used.
EX6 = 0 disables external interrupt 6:
XFER_BUSY, RTC_1S, RTC_1M or RTC_T
EX5 = 0 disables external interrupt 5: EEPROM or SPI
EX4 = 0 disables external interrupt 4: VSTAT
41
71M6541D/F/G and 71M6542F/G Data Sheet
IEN1[2]
IEN1[1]
IEN1[0]
Bit
IEN2[0]
EX3 = 0 disables external interrupt 3: CE_BUSY
EX2 = 0 disables external interrupt 2:
XPULSE, YPULSE, WPULSE or VPULSE
–
Not Used.
Table 28: The IEN2 Bit Functions (SFR 0x9A)
EX3
EX2
Symbol
ES1
Function
ES1 = 0 disables the serial channel 1 interrupt.
Table 29: TCON Bit Functions (SFR 0x88)
Bit
TCON[7]
TCON[6]
TCON[5]
TCON[4]
TCON[3]
TCON[2]
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
TCON[1]
TCON[0]
IE0
IT0
Function
Timer 1 overflow flag.
Not used for interrupt control.
Timer 0 overflow flag.
Not used for interrupt control.
External interrupt 1 flag: DIO status changed
External interrupt 1 type control bit:
0 = interrupt on low level.
1 = interrupt on falling edge.
External interrupt 0 flag: DIO status changed
External interrupt 0 type control bit:
0 = interrupt on low level.
1 = interrupt on falling edge.
Table 30: The T2CON Bit Functions (SFR 0xC8)
Bit
T2CON[7]
T2CON[6]
Symbol
–
I3FR
T2CON[5]
I2FR
T2CON[4:0]
–
Function
Not used.
Polarity control for external interrupt 3: CE_BUSY
0 = falling edge.
1 = rising edge.
Polarity control for external interrupt 2:
XPULSE, YPULSE, WPULSE and VPULSE
0 = falling edge.
1 = rising edge.
Not used.
Table 31: The IRCON Bit Functions (SFR 0xC0)
42
Bit
IRCON[7]
Symbol
–
Function
Not used
IRCON[6]
–
Not used
IRCON[5]
IEX6
IRCON[4]
IEX5
IRCON[3]
IEX4
IRCON[2]
IEX3
1 = External interrupt 6 occurred and has not been cleared:
XFER_BUSY, RTC_1S, RTC_1M or RTC_T
1 = External interrupt 5 occurred and has not been cleared:
EEPROM or SPI
1 = External interrupt 4 occurred and has not been cleared:
VSTAT
1 = External interrupt 3 occurred and has not been cleared:
CE_BUSY
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
IRCON[1]
IEX2
IRCON[0]
–
1 = External interrupt 2 occurred and has not been cleared:
XPULSE, YPULSE, WPULSE or VPULSE
Not used.
TF0 and TF1 (Timer 0 and Timer 1 overflow flags) are automatically cleared by hardware when the
service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service
routine is called).
Rev 2
43
71M6541D/F/G and 71M6542F/G Data Sheet
External MPU Interrupts
The seven external interrupts are the interrupts external to the 80515 core, i.e., signals that originate in
other parts of the 71M654x, for example the CE, DIO, RTC, or EEPROM interface.
The external interrupts are connected as shown in Table 32. The polarity of interrupts 2 and 3 is
programmable in the MPU via the I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should be
programmed for falling sensitivity (I3FR = I2FR = 0). The generic 8051 MPU literature states that interrupts 4
through 6 are defined as rising-edge sensitive. Thus, the hardware signals attached to interrupts 5
and 6 are inverted to achieve the edge polarity shown in Table 32.
Table 32: External MPU Interrupts
External
Interrupt
0
1
2
3
4
5
6
Connection
Polarity
Digital I/O
Digital I/O
CE_PULSE
CE_BUSY
VSTAT (VSTAT[2:0] changed)
EEPROM busy (falling), SPI (rising)
XFER_BUSY (falling), RTC_1SEC, RTC_1MIN, RTC_T
see 2.5.8
see 2.5.8
rising
falling
rising
falling
Flag Reset
automatic
automatic
automatic
automatic
automatic
automatic
manual
External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps. See 2.5.8
Digital I/O for more information.
SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own
flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. XFER_BUSY,
RTC_1SEC, RTC_1MIN, RTC_T, SPI, PLLRISE and PLLFALL have their own enable and flag bits in
addition to the interrupt 6, 4 and enable and flag bits (see Table 33: Interrupt Enable and Flag Bits).
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler.
The other flags, IE_XFER through IE_VPULSE, are cleared by writing a zero to them.
Since these bits are in an SFR bit addressable byte, common practice would be to clear them
with a bit operation, but this must be avoided. The hardware implements bit operations as a
byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before
the write, its flag cleared unintentionally.
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a
zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
Table 33: Interrupt Enable and Flag Bits
Interrupt Enable
Name
EX0
EX1
EX2
EX3
EX4
EX5
EX6
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
44
Location
SFR 0xA8[[0]
SFR 0xA8[2]
SFR 0xB8[1]
SFR 0xB8[2]
SFR 0xB8[3]
SFR 0xB8[4]
SFR 0xB8[5]
0x2700[0]
0x2700[1]
0x2700[2]
0x2700[4]
Interrupt Flag
Name
IE0
IE1
IEX2
IEX3
IEX4
IEX5
IEX6
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
Location
SFR 0x88[1]
SFR 0x88[3]
SFR 0xC0[1]
SFR 0xC0[2]
SFR 0xC0[3]
SFR 0xC0[4]
SFR 0xC0[5]
SFR 0xE8[0]
SFR 0xE8[1]
SFR E0x8[2]
SFR 0xE8[4]
Interrupt Description
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
XFER_BUSY interrupt (int 6)
RTC_1SEC interrupt (int 6)
RTC_1MIN interrupt (int 6)
RTC_T alarm clock interrupt (int 6)
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Interrupt Enable
Name
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
Interrupt Flag
Location
0x2701[7]
0x2700[7]
0x2700[6]
0x2700[5]
0x2701[6]
0x2701[5]
Name
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
Location
SFR 0xF8[7]
SFR 0xE8[7]
SFR 0xE8[6]
SFR 0xE8[5]
SFR 0xF8[4]
SFR 0xF8[3]
Interrupt Description
SPI interrupt
EEPROM interrupt
CE_XPULSE interrupt (int 2)
CE_YPULSE interrupt (int 2)
CE_WPULSE interrupt (int 2)
CE_VPULSE interrupt (int 2)
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 34.
Table 34: Interrupt Priority Level Groups
Group
0
1
2
3
4
5
Group Members
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
–
Serial channel 1 interrupt
–
–
–
–
–
–
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table 35) by setting or clearing one bit in the SFR interrupt priority register IP0 (SFR 0xA9) and one in IP1
(SFR 0xB9) (Table 36). If requests of the same priority level are received simultaneously, an internal polling
sequence as shown in Table 37 determines which request is serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Table 35: Interrupt Priority Levels
IP1[x]
0
0
1
1
IP0[x]
0
1
0
1
Priority Level
Level 0 (lowest)
Level 1
Level 2
Level 3 (highest)
Table 36: Interrupt Priority Registers (IP0 and IP1)
Register
Address
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IP0
IP1
SFR 0xA9
SFR 0xB9
–
–
–
–
IP0[5]
IP1[5]
IP0[4]
IP1[4]
IP0[3]
IP1[3]
IP0[2]
IP1[2]
IP0[1]
IP1[1]
Rev 2
Bit 0
(LSB)
IP0[0]
IP1[0]
45
71M6541D/F/G and 71M6542F/G Data Sheet
External interrupt 0
Serial channel 1 interrupt
Timer 0 interrupt
External interrupt 2
External interrupt 1
External interrupt 3
Timer 1 interrupt
External interrupt 4
Serial channel 0 interrupt
External interrupt 5
External interrupt 6
Polling sequence
Table 37: Interrupt Polling Sequence
Interrupt Sources and Vectors
Table 38 shows the interrupts with their associated flags and vector addresses.
Table 38: Interrupt Vectors
Interrupt
Request Flag
IE0
TF0
IE1
TF1
RI0/TI0
RI1/TI1
IEX2
IEX3
IEX4
IEX5
IEX6
46
Description
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
Serial channel 1 interrupt
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Interrupt Vector
Address
0x0003
0x000B
0x0013
0x001B
0x0023
0x0083
0x004B
0x0053
0x005B
0x0063
0x006B
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
0
External
Source
Internal
Source
Individual
Enable Bits
Individual Flags
DIO
DIO status
changed
DIO_Rn
TCON.1 (IE0)
byte received
UART1
(optical)
Logic and Polarity
Selection
Interrupt
Flags
Interrupt Enable
IEN0.7
(EAL)
IEN0.0
(EX0)
Priority
Assignment
IT0
IEN2.0
(ES1)
S1CON.0 (RI1)
IP1.0/
IP0.0
>=1
byte transmitted
S1CON.1 (TI1)
IEN0.1
(ET0)
Timer 0
XPULSE
YPULSE
2
1
3
overflow occurred
CE detected zero
crossing
CE detected sag
EX_XPULSE
TCON.5 (TF0)
EX_YPULSE
IE_YPULSE
WPULSE
Wh pulse
EX_WPULSE
IE_WPULSE
VPULSE
VARh pulse
EX_VPULSE
IE_VPULSE
DIO_Rn
TCON.3 (IE1)
DIO
CE_BUSY
DIO status
changed
IEN1.1
(EX2)
IE_XPULSE
>=1
I3FR
overflow occurred
VSTAT
IEN0.3
(ET1)
TCON.7 (TF1)
>=1
byte transmitted
5
command
received
XFER_BUSY
accumulation
cycle completed
RTC_1M
RTC_T
EX_EEX
S0CON.0 (TI0)
IEN1.4
(EX5)
IE_EEX
>=1
SPI
RTC_1S
6
BUSY fell
IEN0.4
(ES0)
S0CON.0 (RI0)
UART0
EEPROM
every second
every minute
alarm clock
EX_SPI
IP1.4/
IP0.4
IRCON.4
(IEX5)
IE_SPI
EX_XFER
IE_XFER
EX_RTC1S
IE_RTC1S
EX_RTC1M
IE_RTC1M
IEN1.5
(EX6)
IP1.5/
IP0.5
IRCON.5
(IEX6)
>=1
EX_RTCT
IE_RTCT
Flag=1
means that
an interrupt
has occurred
and has not
been cleared
EX0 – EX6 are cleared
automaticallywhen the
hardware vectors to the
interrupt handler
Interrupt
Vector
3/19/2010
“Internal Source” refers to interrupt sources originating within the 80515 MPU core.
“External Source” refers to interrupt sources outside the 80515 MPU core originating from other parts of the 71M654x SoC.
Figure 16: Interrupt Structure
Rev 2
IP1.3/
IP0.3
IRCON.3
(IEX4)
Supply status changed
byte received
IP1.2/
IP0.2
IRCON.2
(IEX3)
IEN1.3
(EX4)
4
IP1.1/
IP0.1
IEN0.2
(EX1)
IEN1.2
(EX3)
CE completed code run and
has new status information
Timer 1
I2FR
IRCON.1
(IEX2)
Polling Sequence
No.
47
71M6541D/F/G and 71M6542F/G Data Sheet
2.5
On-Chip Resources
2.5.1
Physical Memory
2.5.1.1 Flash Memory
The device includes 128KB (71M6541G, 71M6542G), 64KB (71M6542F, 71M6541F) or 32KB
(71M6541D) of on-chip flash memory. The flash memory primarily contains MPU and CE program code.
It also contains images of the CE RAM and I/O RAM. On power-up, before enabling the CE, the MPU
copies these images to their respective locations.
Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must
begin on a 1-KB boundary of the flash address space. The CE_LCTN[5:0] field (I/O RAM 0x2109[5:0])
defines which 1 KB boundary contains the CE code. Thus, the first CE instruction is located at
1024*CE_LCTN[5:0].
Flash memory can be accessed by the MPU, the CE, and by the SPI interface (R/W).
Table 39: Flash Memory Access
Access by
MPU
CE
SPI
Access
Type
R/W/E
R
R/W/E
Condition
W/E only if CE is disabled.
Access only when SFM is invoked (MPU halted).
Flash Write Procedures
If the FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4] key is correctly programmed, the MPU may write to the
flash memory. This is one of the non-volatile storage options available to the user in addition to external
EEPROM.
The flash program write enable bit, FLSH_PWE (SFR 0xB2[0]), differentiates 80515 data store instructions
(MOVX@DPTR,A) between Flash and XRAM writes. This bit is automatically cleared by hardware
after each byte write operation. Write operations to this bit are inhibited when interrupts are enabled.
If the CE bit is enabled (CE_E = 1, I/O RAM 0x2106[0]), flash write operations must not be attempted unless
FLSH_PSTWR (SFR 0xB2[2]) is set. This bit enables the “posted flash write” capability. FLSH_PSTWR has
no effect when CE_E = 0). When CE_E = 1, however, FLSH_PSTWR delays a flash write until the time
interval between the CE code passes. During this delay time, the FLSH_PEND bit (SFR 0xB2[3]) is high, and
the MPU continues to execute commands. When the CE code pass ends (CE_BUSY falls), the FLSH_PEND
bit falls and the write operation occurs. The MPU can query the FLSH_PEND bit to determine when the
write operation has been completed. While FLSH_PEND = 1, further flash write requests are ignored.
Updating Individual Bytes in Flash Memory
The original state of a flash byte is 0xFF (all bits are 1). Once a value other than 0xFF is written to a flash
memory cell, overwriting with a different value usually requires that the cell be erased first. Since cells
cannot be erased individually, the page has to be copied to RAM, followed by a page erase. After this,
the page can be updated in RAM and then written back to the flash memory.
Flash Erase Procedures
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence.
These special pattern/sequence requirements prevent inadvertent erasure of the flash memory.
The mass erase sequence is:
•
•
Write 1 to the FLSH_MEEN bit (SFR 0xB2[1]).
Write the pattern 0xAA to the FLSH_ERASE register (SFR 0x94).
The mass erase cycle can only be initiated when the ICE port is enabled.
48
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
The page erase sequence is:
•
•
Write the page address to FLSH_PGADR[5:0] (SFR 0xB7[7:2]).
Write the pattern 0x55 to the FLSH_ERASE register (SFR 0x94).
Program Security
When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE
operations are blocked. This guarantees the security of the user’s MPU and CE program code. Security
is enabled by MPU code that is executed in a 64 CKMPU cycle pre-boot interval before the primary boot
sequence begins. Once security is enabled, the only way to disable it is to perform a global erase of the
flash, followed by a chip reset.
The first 64 cycles of the MPU boot code are called the pre-boot phase because during this phase the
ICE is inhibited. A read-only status bit, PREBOOT (SFR 0xB2[7]), identifies these cycles to the MPU.
Upon completion of pre-boot, the ICE can be enabled and is permitted to take control of the MPU.
The security enable bit, SECURE (SFR 0xB2[6]), is reset whenever the chip is reset. Hardware associated
with the bit permits only ones to be written to it. Thus, pre-boot code may set SECURE to enable the security
feature but may not reset it. Once SECURE is set, the pre-boot code is protected and no external read of
program code is possible.
Specifically, when the SECURE bit is set, the following applies:
•
•
•
The ICE is limited to bulk flash erase only.
Page zero of flash memory, the preferred location for the user’s pre-boot code, may not be
page-erased by either MPU or ICE. Page zero may only be erased with global flash erase.
Write operations to page zero, whether by MPU or ICE are inhibited.
The 71M6541D/F/G and 71M6542F/G also include hardware to protect against unintentional Flash write
and erase. To enable flash write and erase operations, a 4-bit hardware key that must be written to the
FLSH_UNLOCK[3:0] field. The key is the binary number ‘0010’. If FLSH_UNLOCK[3:0] is not ‘0010’, the
Flash erase and write operation is inhibited by hardware. Proper operation of this security key requires
that there be no firmware function that writes ‘0010’ to FLSH_UNLOCK[3:0]. The key should be written by
the external SPI master, in the case of SPI flash programming (SFM mode), or through the ICE interface
in the case of ICE flash programming. When a boot loader is used, the key should be sent to the boot
load code which then writes it to FLSH_UNLOCK[3:0]. FLSH_UNLOCK[3:0] is not automatically reset. It
should be cleared when the SPI or ICE has finished changing the Flash. Table 40 summarizes the I/O
RAM registers used for flash security.
Table 40: Flash Security
Name
FLSH_UNLOCK[3:0]
Location
2702[7:4]
Rst
0
Wk
0
SECURE
SFR B2[6]
0
0
Dir Description
R/W Must be a 2 to enable any flash modification.
See the description of Flash security for
more details.
R/W Inhibits erasure of page 0 and flash addresses
above the beginning of CE code as defined by
CE_LCTN[5:0] (I/O RAM 0x2109[5:0]). Also
inhibits the read of flash via the ICE and SPI
ports.
SPI Flash Mode
In normal operation, the SPI slave interface cannot read or write the flash memory. However, the
71M6541D/F/G and 71M6542F/G contain a Special Flash Mode (SFM) that facilitates initial
(production) programming of the flash memory. When the 71M654x is in SFM mode, the SPI interface can
erase, read, and write the flash. Other memory elements such as XRAM and I/O RAM are not
accessible to the SPI in this mode. In order to protect the flash contents, several operations are required
before the SFM mode is successfully invoked.
Details on the SFM are in 2.5.10 (SPI Slave Port).
Rev 2
49
71M6541D/F/G and 71M6542F/G Data Sheet
2.5.1.2 MPU/CE RAM
The 71M6541D includes 3 KB of static RAM memory on-chip (XRAM) plus 256 bytes of internal RAM in
the MPU core. The 71M6541D/F/G and the 71M6542F/G include 5 KB of static RAM memory on-chip
(XRAM) plus 256 bytes of internal RAM in the MPU core. The static RAM is used for data storage for
both MPU and CE operations.
2.5.1.3 I/O RAM (Configuration RAM)
The I/O RAM can be seen as a series of hardware registers that control basic hardware functions. I/O
RAM address space starts at 0x2000. The registers of the I/O RAM are listed in Table 74.
The 71M6541D/F/G and 71M6542F/G include 128 bytes non-volatile RAM memory on-chip in the I/O
RAM address space (addresses 0x2800 to 0x287F). This memory section is supported by the voltage
applied at VBAT_RTC and the data in it are preserved in BRN, LCD, and SLP modes as long as the
voltage at VBAT_RTC is within specification.
2.5.2
Oscillator
The oscillator drives a standard 32.768 kHz watch crystal. This type of crystal is accurate and does not
require a high-current oscillator circuit. The oscillator has been designed specifically to handle watch
crystals and is compatible with their high impedance and limited power handling capability. The oscillator
power dissipation is very low to maximize the lifetime of any battery attached to VBAT_RTC.
Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to 2.5.4, Real-Time
Clock (RTC) for more information.
The oscillator is powered from the V3P3SYS pin or from the VBAT_RTC pin, depending on the V3OK
internal bit (i.e., V3OK = 1 if V3P3SYS ≥ 2.8 VDC and V3OK = 0 if V3P3SYS < 2.8 VDC). The oscillator
requires approximately 100 nA, which is negligible compared to the internal leakage of a battery.
2.5.3
PLL and Internal Clocks
Timing for the device is derived from the 32.768 kHz crystal oscillator output that is multiplied by a PLL by
600 to produce 19.660800 MHz, the master clock (MCK). All on-chip timing, except for the RTC clock, is
derived from MCK. Table 41 provides a summary of the clock functions and their controls.
The two general-purpose counter/timers contained in the MPU are controlled by CKMPU (see 2.4.6
Timers and Counters).
The master clock can be boosted to 19.66 MHz by setting the PLL_FAST bit = 1 (I/O RAM 0x2200[4]) and
can be reduced to 6.29 MHz by PLL_FAST = 0. The MPU clock frequency CKMPU is determined by
another divider controlled by the I/O RAM control field MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) and can be
-(MPU_DIV+2)
, where MPU_DIV[2:0] may vary from 0 to 4. The 71M654x V3P3SYS supply
set to MCK*2
current is reduced by reducing the MPU clock frequency. When the ICE_E pin is high, the circuit also
generates the 9.83 MHz clock for use by the emulator.
The PLL is only turned off in SLP mode or in LCD mode when LCD_BSTE is disabled. The LCD_BSTE
value depends on the setting of the LCD_VMODE [1:0] field (see Table 56).
When the part is waking up from SLP or LCD modes, the PLL is turned on in 6.29 MHz mode, and the PLL
frequency is not be accurate until the PLL_OK flag (SFR 0xF9[4]) rises. Due to potential overshoot, the MPU
should not change the value of PLL_FAST until PLL_OK is true.
50
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 41: Clock System Summary
Clock
OSC
Crystal
MCK
Crystal/PLL
CKCE
MCK
CKADC
MCK
CKMPU
MCK
CKICE
MCK
CKOPTMOD
MCK
CK32
MCK
2.5.4
Fixed Frequency or Range
Derived
From
PLL_FAST=1
PLL_FAST=0
Controlled by
Function
32.768 kHz
–
Crystal clock
19.660800 MHz
6.291456 MHz
PLL_FAST
Master clock
(600*CK32)
(192*CK32)
4.9152 MHz
1.5728 MHz
–
CE clock
1.572864 MHz,
4.9152 MHz,
ADC_DIV
ADC clock
2.4576 MHz
0.786432 MHz
4.9152 MHz … 1.572864 MHz…
MPU_DIV[2:0] MPU clock
307.2 kHz
98.304 kHz
9.8304 MHz… 3.145728 MHz …
MPU_DIV[2:0]
ICE clock
196.608 kHz
614.4 kHz
Optical
UART
38.40 kHz
38.6 kHz
–
Modulation
32.768 kHz
–
32 kHz clock
Real-Time Clock (RTC)
2.5.4.1 RTC General Description
The RTC is driven directly by the crystal oscillator and is powered by either the V3P3SYS pin or the
VBAT_RTC pin, depending on the V3OK internal bit. The RTC consists of a counter chain and output
registers. The counter chain consists of registers for seconds, minutes, hours, day of week, day of
month, month, and year. The chain registers are supported by a shadow register that facilitates read
and write operations.
Table 42 shows the I/O RAM registers for accessing the RTC.
2.5.4.2 Accessing the RTC
Two bits, RTC_RD (I/O RAM 0x2890[6]) and RTC_WR (I/O RAM 0x2890[7]), control the behavior of the
shadow register.
When RTC_RD is low, the shadow register is updated by the RTC after each two milliseconds. When
RTC_RD is high, this update is halted and the shadow register contents become stationary and are suitable
to be read by the MPU. Thus, when the MPU wishes to read the RTC, it freezes the shadow register by
setting the RTC_RD bit, reads the shadow register, and then lowers the RTC_RD bit to let updates to the
shadow register resume. Since the RTC clock is only 500Hz, there may be a delay of approximately 2 ms
from when the RTC_RD bit is lowered until the shadow register receives its first update. Reads to RTC_RD
continue to return a one until the first shadow update occurs.
When RTC_WR is high, the update of the shadow register is also inhibited. During this time, the MPU may
overwrite the contents of the shadow register. When RTC_WR is lowered, the shadow register is written into
the RTC counter on the next 500Hz RTC clock. A change bit is included for each word in the shadow
register to ensure that only programmed words are updated when the MPU writes a zero to RTC_WR.
Reads of RTC_WR returns one until the counter has actually been updated by the register.
The sub-second register of the RTC, RTC_SBSC (I/O RAM 0x2892), can be read by the MPU after the one
second interrupt and before reaching the next one second boundary. The RTC_SBSC register is expressed
as a count of 1/128 second periods remaining until the next one second boundary. Writing 0x00 to
RTC_SBSC resets the counter re-starting the count from 0 to 127. Reading and resetting the sub-second
counter can be used as part of an algorithm to accurately set the RTC.
The RTC is capable of processing leap years. Each counter has its own output register. The RTC chain
registers are not affected by the reset pin, watchdog timer resets, or by transitions between the battery
modes and mission mode.
Rev 2
51
71M6541D/F/G and 71M6542F/G Data Sheet
Table 42: RTC Control Registers
Name
RTC_ADJ[6:0]
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
RTC_Q[1:0]
Location
Rst
Wk
Dir
Description
2504[6:0]
289B[2:0]
289C[7:0]
289D[7:2]
289D[1:0]
00
4
0
0
0
–
4
0
0
0
R/W Register for analog RTC frequency adjustment.
R/W
Registers for digital RTC adjustment.
0x0FFBF ≤ RTC_P ≤ 0x10040
RTC_RD
2890[6]
0
0
RTC_WR
2890[7]
0
0
RTC_FAIL
2890[4]
0
0
RTC_SBSC[7:0]
2892[7:0]
R/W Register for digital RTC adjustment.
Freezes the RTC shadow register so it is suitable for
R/W MPU reads. When RTC_RD is read, it returns the
status of the shadow register: 0 = up to date, 1 = frozen.
Freezes the RTC shadow register so it is suitable for
MPU write operations. When RTC_WR is cleared,
the contents of the shadow register written to the RTC
R/W counter on the next RTC clock (~500 Hz). When
RTC_WR is read, it returns 1 as long as RTC_WR is
set. It continues to return one until the RTC counter is
updated.
Indicates that a count error has occurred in the RTC
R/W and that the time is not trustworthy. This bit can be
cleared by writing a 0.
Time remaining since the last 1 second boundary.
R
LSB = 1/128 second.
2.5.4.3 RTC Rate Control
Two rate adjustment mechanisms are available:
•
•
The first rate adjustment mechanism is an analog rate adjustment, using the I/O RAM register
RTCA_ADJ[6:0] (I/O RAM 0x2504[6:0]), that trims the crystal load capacitance.
The second rate adjustment mechanism is a digital rate adjust that affects the way the clock frequency
is processed in the RTC.
Setting RTCA_ADJ[6:0] to 00 minimizes the load capacitance, maximizing the oscillator frequency. Setting
RTCA_ADJ[6:0] to 7F maximizes the load capacitance, minimizing the oscillator frequency. The adjustable
capacitance is approximately:
C ADJ =
RTCA _ ADJ
⋅ 16.5 pF
128
The precise amount of adjustment depends on the crystal properties, the PCB layout and the value of the
external crystal capacitors. The adjustment may occur at any time, and the resulting clock frequency should
be measured over a one-second interval.
The second rate adjustment is digital, and can be used to adjust the clock rate up to ±988ppm, with a
resolution of 3.8 ppm (±1.9 ppm). Note that 3.8 ppm corresponds to 1-LSB of the 19-bit quantity formed
by 4*RTCP+RTCQ and 1.9 ppm corresponds to ½-LSB. The rate adjustment is implemented starting at
the next second-boundary following the adjustment. Since the LSB results in an adjustment every four
seconds, the frequency should be measured over an interval that is a multiple of four seconds.
The clock rate is adjusted by writing the appropriate values to RTC_P[16:0] (I/O RAM 0x289B[2:0], 0x289C,
0x289D[7:2]) and RTC_Q[1:0] (I/O RAM 0x289D[1:0]). Updates to RTC rate adjust registers, RTC_P and
RTC_Q, are done through the shadow register described above. The new values are loaded into the
counters when RTC_WR (I/O RAM 0x2890[7]) is lowered.
The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency by ∆ ppm,
RTC_P and RTC_Q are calculated using the following equation:
52
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
 32768 ⋅ 8

+ 0.5 
4 ⋅ RTC_P + RTC_Q = floor 
−6
 1 + ∆ ⋅10

Conversely, the amount of ppm shift for a given value of 4RTC_P+RTC_Q is:
32768 ∙ 8
− 1� 106
∆ () = �
4 ∗  + 
For example, for a shift of -988 ppm, 4⋅RTC_P + RTC_Q = 262403 = 0x40103. RTC_P = 0x10040, and
RTC_Q = 0x03. The default values of RTC_P and RTC_Q, corresponding to zero adjustment, are 0x10000
and 0x0, respectively.
Two settings for the TMUX2OUT test pin, PULSE_1S and PULSE_4S, are available for measuring and
calibrating the RTC clock frequency. These are waveforms of approximately 25% duty cycle with 1s or 4s
period.
Default values for RTCA_ADJ, RTC_P and RTC_Q should be nominal values, at the center of
the adjustment range. Un-calibrated extreme values (zero, for example) can cause incorrect
operation.
If the crystal temperature coefficient is known, the MPU can integrate temperature and correct the RTC
time as necessary. Alternatively, the characteristics can be loaded into an NV RAM and the OSC_COMP
bit (I/O RAM 0x28A0[5]) may be set. In this case, the oscillator is adjusted automatically, even in SLP
mode. See the Real Time RTC Temperature Compensation section for details.
2.5.4.4 RTC Temperature Compensation
The 71M6541D/F/G and 71M6542F/G can be configured to regularly measure die temperature, including
in SLP and LCD modes and while the MPU is halted. If enabled by the OSC_COMP bit, the temperature
information is automatically used to correct for the temperature variation of the crystal. A table look-up
method is used which generates the required digital compensation without involvement from the MPU.
Storage for the look-up table is in a dedicated 128 byte NV RAM.
Table 43 shows the I/O RAM registers involved in automatic RTC temperature compensation.
Table 43: I/O RAM Registers for RTC Temperature Compensation
Name
OSC_COMP
Location
28A0[5]
Rst
Wk
Dir
0
0
R/W
STEMP[10:3]
STEMP[2:0]
2881[7:0]
2882[7:5]
–
–
R
LKPADDR[6:0]
2887[6:0]
0
0
R/W
LKPAUTOI
2887[7]
0
0
R/W
LKPDAT[7:0]
2888[7:0]
0
0
R/W
LKP_RD
LKP_WR
2889[1]
2889[0]
0
0
0
0
R/W
R/W
Rev 2
Description
Enables the automatic update of RTC_P and RTC_Q
every time the temperature is measured.
The result of the temperature measurement (10-bits of
magnitude data plus a sign bit).
The complete STEMP[10:0] value can be read and
shifted right in a single 16-bit read operation as shown
in the following code fragment.
volatile int16_t xdata STEMP _at_0x2881;
fa = (float)(STEMP/32);
The address for reading and writing the RTC lookup RAM.
Auto-increment flag. When set, LKPADDR[6:0] auto
increments every time LKP_RD or LKP_WR is pulsed.
The incremented address can be read at
LKPADDR[6:0].
The data for reading and writing the RTC lookup RAM.
Strobe bits for the RTC lookup RAM read and write.
When set, the LKPADDR and LKPDAT registers are
used in a read or write operation. When a strobe is
set, it stays set until the operation completes, at which
time the strobe is cleared and LKPADDR is
incremented if LKPAUTOI is set.
53
71M6541D/F/G and 71M6542F/G Data Sheet
Referring to Figure 17, the table lookup method uses the 10-bits plus sign-bit value in STEMP[10:0] rightshifted by two bits to obtain an 8-bit plus sign value (i.e., NV RAM Address = STEMP/4). A limiter ensures
that the resulting look-up address is in the 6-bit plus sign range of -64 to +63 (decimal). The 8-bit NV RAM
content pointed to by the address is added as a 2’s complement value to 0x40000, the nominal value of
4*RTC_P + RTC_Q.
Refer to 2.5.4.3 RTC Rate Control for information on the rate adjustments performed by registers
RTC_P[16:0] (I/O RAM 0x289B[2:0], 0x289C, 0x289D[7:2]) and RTC_Q[1:0] (I/O RAM 0x2891[1:0]. The 8-bit
values loaded in to NV RAM must be scaled correctly to produce rate adjustments that are consistent
with the equations given in 2.5.4.3 RTC Rate Control for RTC_P and RTC_Q. Note that the sum of the
8-bit 2’s complement value looked-up and 0x40000 form a 19-bit value, which is equal to
4*RTC_P+RTC_Q, as shown in Figure 17. The output of the Temperature Compensation is automatically
loaded into the RTC_P[16:0] and RTC_Q[1:0] locations after each look-up and summation operation.
LIMIT
STEMP
10+S
>>2
8+S
Look Up
RAM
63
ADDR
-256
-64
63
255
6+S
Q
-64
Σ
7+S
19
4*RTC_P+RTC_Q
19
0x40000
Figure 17: Automatic Temperature Compensation
The 128 NV RAM locations are organized in 2’s complement format as shown in Table 44. As mentioned
above, the STEMP[10:0] digital temperature values are scaled such that the corresponding NV RAM
addresses are equal to STEMP[10:0]/4 (limited in the range of -64 to +63). See 2.5.5 71M654x Temperature
Sensor on page 56 for the equations to calculate temperature in degrees °C from the STEMP[10:0] reading.
The temperature equation is used to calculate the two temperature columns in Table 44 (the second
column and the rightmost column). The second column uses the full 11-bit values of STEMP[10:0], while
the values in the rightmost column are calculated using the post-limiter (6+S) values multiplied by 4.
Since each look-up table address step corresponds to a 4 x 0.325 °C temperature step, two is added to
the post-limiter 6+S value after multiplying by 4 to calculate the temperature values in the rightmost
column. This method ensures that the compensation data is loaded into the look-up table in a manner
that minimizes quantization error. Table 44 shows the numerical values corresponding to each node in
Figure 17. The values of STEMP[10:0] outside the -256 to +255 range are not shown in this table. The
limiter output is confined to the range of -64 to +63, which is directly the desired address of the 128-byte
look-up table. The rightmost column gives the nominal temperature corresponding to each address cell in
the 128-byte compensation table
Table 44: NV RAM Temperature Table Structure
STEMP[10:0]
(10+S)
(decimal)
54
o
Temp ( C)
(Equation)
-256
-61.71
-255
-61.39
-254
-61.06
-253
…
-4
-60.73
…
20.69
-3
21.02
-2
21.35
-1
21.67
STEMP[10:0]>>2
(8+S)
(decimal)
Limiter Output
(6+S)
(decimal)
Temp ( C)
(LU Table)
-64
-64
-61.06
…
…
…
-1
-1
21.35
o
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
0
22.00
1
22.33
2
22.65
3
22.98
4
23.31
5
23.64
6
23.96
7
…
252
24.29
…
104.40
253
104.73
254
105.06
255
105.39
0
0
22.65
1
1
23.96
…
…
…
63
63
105.06
For proper operation, the MPU must load the lookup table with values that reflect the crystal properties
with respect to temperature, which is typically done once during initialization. Since the lookup table is
not directly addressable, the MPU uses the following procedure to load the entire NV RAM table:
1.
2.
3.
4.
5.
6.
Set the LKPAUTOI bit (I/O RAM 0x2887[7]) to enable address auto-increment.
Write zero into the I/O RAM register LKPADDR[6:0] (I/O RAM 0x2887[6:0]).
Write the 8-bit datum into I/O RAM register LKPDAT (I/O RAM 0x2888).
Set the LKP_WR bit (I/O RAM 0x2889[0]) to write the 8-bit datum into NV_RAM
Wait for LKP_WR to clear (LKP_WR auto-clears when the data has been copied to NV RAM).
Repeat steps 3 through 5 until all data has been written to NV RAM.
The NV RAM table can also be read by writing a 1 into the LKP_RD bit (I/O RAM 0x2889[1]). The process of
reading from and writing to the NV RAM is accelerated by setting the LKPAUTOI bit (I/O RAM 0x2887[7]).
When LKPAUTOI is set, LKPADDR[6:0] auto-incremented every time LKP_RD or LKP_WR is pulsed. It is
also possible to perform random access of the NV RAM by writing a 0 to the LKPAUTOI bit and loading the
desired address into LKPADDR[6:0].
If the oscillator temperature compensation feature is not being used, it is possible to use the NV
RAM storage area as ordinary NV storage space using the procedure described above to read and
write NV RAM data. In this case, keep the OSC_COMP bit (I/O RAM 0x28A0[5]) reset to disable the
automatic oscillator temperature compensation feature.
2.5.4.5 RTC Interrupts
The RTC generates interrupts each second and each minute. These interrupts are called RTC_1SEC and
RTC_1MIN. In addition, the RTC functions as an alarm clock by generating an interrupt when the minutes
and hours registers both equal their respective target counts as defined in Table 45. The alarm clock
interrupt is called RTC_T. All three interrupts appear in the MPU’s external interrupt 6. See Table 33
in the interrupt section for the enable bits and flags for these interrupts.
The target registers for minutes and hours are listed in Table 45.
Table 45: I/O RAM Registers for RTC Interrupts
Name
RTC_TMIN[5:0]
RTC_THR[4:0]
Rev 2
Location Rst
289E[5:0] 0
289F[4:0] 0
Wk
0
0
Dir Description
R/W The target minutes register. See RTC_THR[4:0] below.
R/W The target hours register. The RTC_T interrupt occurs
when RTC_MIN becomes equal to RTC_TMIN and
RTC_HR becomes equal to RTC_THR.
55
71M6541D/F/G and 71M6542F/G Data Sheet
2.5.5
71M654x Temperature Sensor
The 71M654x includes an on-chip temperature sensor for determining the temperature of its bandgap
reference. The primary use of the temperature data is to determine the magnitude of compensation
required to offset the thermal drift in the system for the compensation of current, voltage and energy
measurement and the RTC. See 4.7 Metrology Temperature Compensation on page 97. Also see 2.5.4.4
RTC Temperature Compensation on page 53.
Unlike earlier generation Teridian SoCs, the 71M654x does not use the ADC to read the temperature
sensor. Instead, it uses a technique that is operational in SLP and LCD mode, as well as BRN and MSN
modes. This means that the temperature sensor can be used to compensate for the frequency variation
of the crystal, even in SLP mode while the MPU is halted. See 2.5.4.4 RTC Temperature Compensation
on page 53.
In MSN and BRN modes, the temperature sensor is awakened on command from the MPU by setting the
TEMP_START (I/O RAM 0x28B4[6]) control bit. The MPU must wait for the TEMP_START bit to clear before
reading STEMP[10:0] and before setting the TEMP_START bit once again. In SLP and LCD modes, it is
awakened at a regular rate set by TEMP_PER[2:0] (I/O RAM 0x28A0[2:0]).
The result of the temperature measurement can be read from the two I/O RAM locations STEMP[10:3]
(I/O RAM 0x2881) and STEMP[2:0] (I/O RAM 0x2882[7:5]). Note that both of these I/O RAM locations must
be read and properly combined to form the STEMP[10:0] 11-bit value (see STEMP in Table 46). The
resulting 11-bit value is in 2’s complement form and ranges from -1024 to +1023 (decimal). The equations
below are used to calculate the sensed temperature from the 11-bit STEMP[10:0] reading.
The equations below are used to calculate the sensed temperature. The first equation applies when the
71M654x is in MSN mode and TEMP_PWR = 1. The second equation applies when the 71M654x is in
BRN mode, and in this case, the TEMP_PWR and TEMP_BSEL bits must both be set to the same value, so
that the battery that supplies the temperature sensor is also the battery that is measured and reported in
BSENSE. Thus, the second equation requires reading STEMP and BSENSE. In the second equation,
BSENSE (the sensed battery voltage) is used to obtain a more accurate temperature reading when the IC
is in BRN mode.
For the 71M654x in MSN Mode (with TEMP_PWR = 1):
Temp(°C ) = 0.325 ⋅ STEMP + 22
For the 71M654x in BRN Mode, (with TEMP_PWR=TEMP_BSEL):
Temp(oC ) = 0.325 ⋅ STEMP + 0.00218 ⋅ BSENSE 2 − 0.609 ⋅ BSENSE + 64.4
Table 46 shows the I/O RAM registers used for temperature and battery measurement.
If TEMP_PWR selects VBAT_RTC when the battery is nearly discharged, the temperature
measurement may not finish. In this case, firmware may complete the measurement by selecting
V3P3D (TEMP_PWR = 1).
Table 46: I/O RAM Registers for Temperature and Battery Measurement
Name
TBYTE_BUSY
TEMP_PER[2:0]
56
Location
Rst
Wk
Dir
28A0[3]
0
0
R
28A0[2:0]
0
–
R/W
Description
Indicates that hardware is still writing the 0x28A0
byte. Additional writes to this byte are locked out
while it is one. Write duration could be as long as 6 ms.
Sets the period between temperature measurements.
Automatic measurements can be enabled in any
mode (MSN, BRN, LCD, or SLP).
TEMP_PER
0
1-6
7
Time
Manual updates (see TEMP_START)
2 ^ (3+TEMP_PER) (seconds)
Continuous
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Location
Rst
Wk
Dir
TEMP_BAT
28A0[4]
0
–
R/W
TEMP_START
28B4[6]
0
–
R/W
TEMP_PWR
28A0[6]
0
–
R/W
TEMP_BSEL
28A0[7]
0
–
R/W
0
–
R/W
TEMP_TEST[1:0] 2500[1:0]
STEMP[10:3]
STEMP[2:0]
2881[7:0]
2882[7:5]
BSENSE[7:0]
2885[7:0]
–
–
2704[3]
0
0
BCURR
Description
Causes VBAT to be measured whenever a
temperature measurement is performed.
TEMP_PER[2:0] must be zero in order for TEMP_START
to function. If TEMP_PER[2:0] = 0, then setting
TEMP_START starts a temperature measurement.
Ignored in SLP and LCD modes. Hardware clears
TEMP_START when the temperature measurement is
complete. The MPU must wait for TEMP_START to
clear before reading STEMP[10:0] and before setting
TEMP_START again.
Selects the power source for the temperature sensor:
1 = V3P3D, 0 = VBAT_RTC. This bit is ignored in
SLP and LCD modes, where the temperature sensor is
always powered by VBAT_RTC.
Selects which battery is monitored by the
temperature sensor: 1 = VBAT, 0 = VBAT_RTC
Test bits for the temperature monitor VCO.
TEMP_TEST must be 00 in regular operation. Any
other value causes the VCO to run continuously with
the control voltage described below.
TEMP_TEST
00
01
1X
Function
Normal operation
Reserved for factory test
Reserved for factory test
R
R
The result of the temperature measurement.
To correctly form STEMP[10:0], the MPU must read
0x2881[7:0], shift it left by three bit positions (padding
LSBs with zeros), then read 0x2882[7:5], shift it right
by 5-bits (padding the 5 MSBs with zeros), and then
logically OR the two quantities together.
R The result of the battery measurement.
Connects a 100 µA load to the battery selected by
R/W
TEMP_BSEL.
Refer to the 71M6xxx Data Sheet for information on reading the temperature sensor in the 71M6x01
devices.
2.5.6
71M654x Battery Monitor
The 71M654x temperature measurement circuit can also monitor the batteries at the VBAT and
VBAT_RTC pins. The battery to be tested (i.e., VBAT or VBAT_RTC pin) is selected by TEMP_BSEL (I/O
RAM 0x28A0[7]).
When TEMP_BAT (I/O RAM 0x28A0[4]) is set, a battery measurement is performed as part of each
temperature measurement. The value of the battery reading is stored in register BSENSE[7:0] (I/O RAM
0x2885). The following equation is used to calculate the voltage measured on the VBAT pin (or VBAT_RTC
pin) from the BSENSE[7:0] and STEMP[10:0] values. The result of the equation below is in volts.
VBAT (orVBAT _ RTC ) = 3.293V + ( BSENSE[7 : 0] − 142) ⋅ 0.0246V + STEMP[10 : 0] ⋅ 0.000276V
In MSN mode, a 100 µA de-passivation load can be applied to the selected battery (i.e., selected by the
TEMP_BSEL bit) by setting the BCURR (I/O RAM 0x2704[3]) bit. Battery impedance can be measured by
taking a battery measurement with and without BCURR. Regardless of the BCURR bit setting, the battery
load is never applied in BRN, LCD, and SLP modes.
Rev 2
57
71M6541D/F/G and 71M6542F/G Data Sheet
Refer to the 71M6xxx Data Sheet for information on reading the VCC sensor in the 71M6x01 devices.
2.5.7
UART and Optical Interface
The 71M6541D/F/G and 71M6542F/G provide two asynchronous interfaces, UART0 and UART1. Both
can be used to connect to AMR modules, user interfaces, etc., and also support a mechanism for
programming the on-chip flash memory.
Referring to Figure 19, UART1 includes an interface to implement an IR/optical port. The pin OPT_TX is
designed to directly drive an external LED for transmitting data on an optical link. The pin OPT_RX has
the same threshold as the RX pin, but can also be used to sense the input from an external photo detector
used as the receiver for the optical link. OPT_TX and OPT_RX are connected to a dedicated UART port
(UART1).
The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV (I/O RAM 0x2456[0])
and OPT_RXINV (I/O RAM 0x2457[1]), respectively. Additionally, the OPT_TX output may be modulated at
38 kHz. Modulation is available in MSN and BRN modes (see Table 67). The OPT_TXMOD bit (I/O RAM
0x2456[1]) enables modulation. The duty cycle is controlled by OPT_FDC[1:0] (I/O RAM 0x2457[5:4]) ,
which can select 50%, 25%, 12.5%, and 6.25% duty cycle. A 6.25% duty cycle means that OPT_TX is
low for 6.25% of the period.
When not needed for UART1, OPT_TX can alternatively be configured as SEGDIO51. Configuration is
via the OPT_TXE[1:0] (I/O RAM 0x2456[3:2]) field and LCD_MAP[51] (I/O RAM 0x2405[0]). The
OPT_TXE[1:0] field allows the MPU to select VPULSE, WPULSE, SEGDIO51 or the output of the pulse
modulator to be sourced onto the OPT_TX pin. Likewise, the OPT_RX pin can alternately be configured
as SEGDIO55, and its control is OPT_RXDIS (I/O RAM 0x2457[2]) and LCD_MAP[55] (I/O RAM 0x2405[4]).
VARPULSE
from
OPT_TX UART
OPT_TXINV
3
2
V3P3
Internal
WPULSE
1
DIO2
A
MOD
B
0
EN DUTY
OPT_TXE[1:0]
OPT_TXMOD
OPT_FDC
2
OPT_TX
OPT_TXMOD = 1,
OPT_FDC = 2 (25%)
OPT_TXMOD = 0
A
A
B
B
1/38kHz
Figure 18: Optical Interface
Bit Banged Optical UART (Third UART)
As shown in Figure 19, the 71M654x can also be configured to drive the optical UART with a DIO signal
in a bit banged configuration. When control bit OPT_BB (I/O RAM 0x2022[0]) is set, the optical port is
driven by DIO5 and the SEGDIO5 pin is driven by UART1_TX. This configuration is typically used when
the two dedicated UARTs must be connected to high speed clients and a slower optical UART is
permissible.
58
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Internal
SEG55
DIO55
1
1
OPT_RXDIS
UART1_TX
0
DIO5
1
EN
0
SEG51
VARPULSE
DIO51
B
0
V3P3
SEGDIO51/
OPT_TX
1
2
DUTY
LCD_MAP[55]
3
WPULSE
MOD
A
OPT_TXMOD
OPT_FDC
OPT_TXINV
SEGDIO55/
OPT_RX
0
0
UART1_RX
0
LCD_MAP[51]
1
OPT_TXE[1:0]
SEG5
2
1
0
SEGDIO5/TX2
1
LCD_MAP[5]
OPT_BB
OPT_TXMOD=1,
OPT_FDC=2 (25%)
OPT_TXMOD=0
A
B
1/38kHz
Figure 19: Optical Interface (UART1)
2.5.8
Digital I/O and LCD Segment Drivers
2.5.8.1 General Information
The 71M6541D/F/G and 71M6542F/G combine most DIO pins with LCD segment drivers. Each
SEG/DIO pin can be configured as a DIO pin or as a segment (SEG) driver pin.
On reset or power-up, all DIO pins are DIO inputs (except for SEGDIO0-15, see caution note below) until
they are configured as desired under MPU control. The pin function can be configured by the I/O RAM
registers LCD_MAPn (0x2405 – 0x240B). Setting the bit corresponding to the pin in LCD_MAPn to 1
configures the pin for LCD, setting LCD_MAPn to 0 configures it for DIO.
After reset or power up, pins SEGDIO0 through SEGDIO15 are initially DIO outputs, but are
disabled by PORT_E = 0 (I/O RAM 0x270C[5]) to avoid unwanted pulses during reset. After
configuring pins SEGDIO0 through SEGDIO15 the MPU must enable these pins by setting
PORT_E.
Once a pin is configured as DIO, it can be configured independently as an input or output. For SEGDIO0
to SEGDIO15, this is done with the SFR registers P0 (SFR 0x80), P1 (SFR 0x90), P2 (SFR 0xA0) and P3
(SFR 0xB0), as shown in Table 48 (71M6541D/F/G) and Table 52 (71M6542F/G).
The PB pin is a dedicated digital input and is not part of the SEGDIO system.
The CE features pulse counting registers and each pulse counter interrupt output is internally
routed to the pulse interrupt logic. Thus, no routing of pulse signals to external pins is required in
order to generate pulse interrupts. See interrupt source No. 2 in Figure 16.
A 3-bit configuration word, I/O RAM register DIO_Rn (I/O RAM 0x2009[2:0] through 0x200E[6:4]) can be
used for pins SEGDIO2 through SEGDIO11 (when configured as DIO) and PB to individually assign an
internal resource such as an interrupt or a timer control (DIO_RPB[2:0], I/O RAM 0x2450[2:0], configures
the PB pin). This way, DIO pins can be tracked even if they are configured as outputs. Table 47 lists
the internal resources which can be assigned using DIO_R2[2:0] through DIO_R11[2:0] and DIO_RPB[2:0].
If more than one input is connected to the same resource, the resources are combined using a logical OR.
Table 47: Selectable Resources using the DIO_Rn[2:0] Bits
Value in DIO_Rn[2:0]
Rev 2
Resource Selected for SEGDIOn or PB Pin
0
None
1
Reserved
2
T0 (counter0 clock)
3
T1 (counter1 clock)
4
High priority I/O interrupt (INT0)
59
71M6541D/F/G and 71M6542F/G Data Sheet
Value in DIO_Rn[2:0]
5
Resource Selected for SEGDIOn or PB Pin
Low priority I/O interrupt (INT1)
Note:
Resources are selectable only on SEGDIO2 through SEGDIO11 and the
PB pin. See Table 48 (71M6541D/F/G) and Table 52 (71M6542F/G).
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as
shown in Figure 20, right), not source it from V3P3D (as shown in Figure 20, left). This is due
to the resistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT. See
6.4.6 V3P3D Switch on page 143.
Sourcing current in or out of DIO pins other than those dedicated for wake functions, for
example with pull-up or pull-down resistors, must be avoided. Violating this rule leads to
increased quiescent current in sleep and LCD modes.
MISSION
LCD/SLEEP
BROWNOUT
V3P3SYS
MISSION
LCD/SLEEP
BROWNOUT
VBAT
DIO
HIGH
HIGH-Z
LOW
GNDD
Not recommended
VBAT
V3P3D
V3P3D
HIGH
HIGH-Z
LOW
V3P3SYS
DIO
GNDD
Recommended
Figure 20: Connecting an External Load to DIO Pins
60
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
2.5.8.2 Digital I/O for the 71M6541D/F/G
A total of 32 combined SEG/DIO pins plus 5 SEG outputs are available for the 71M6541D/F/G. These
pins can be categorized as follows:
17 combined SEG/DIO segment pins:
o
o
o
o
SEGDIO4…SEGDIO5 (2 pins)
SEGDIO9…SEGDIO14 (6 pins)
SEGDIO19…SEGDIO25 (7 pins)
SEGDIO44…SEGDIO45 (2 pins)
15 combined SEG/DIO segment pins shared with other functions:
o
o
o
o
o
o
o
SEGDIO0/WPULSE, SEGDIO1/VPULSE (2 pins)
SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins)
SEGDIO6/XPULSE, SEGDIO7/YPULSE (2 pins)
SEGDIO8/DI (1 pin)
SEGDIO26/COM5, SEGDIO27/COM4 (2 pins)
SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)
SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins)
5 dedicated SEG segment pins are available:
o
o
ICE Inteface pins: SEG48/E_RXTX, SEG49/E_TCLK, SEG50/E_RST (3 pins)
Test Port pins: SEG46/TMUX2OUT, SEG47/TMUXOUT (2 pins)
There are four dedicated common segment outputs (COM0…COM3) plus the two additional shared common
segment outputs that are listed under combined SEG/DIO shared pins (SEGDIO26/COM5,
SEGDIO27/COM4).
Thus, in a configuration where none of these pins are used as DIOs, there can be up to 37 LCD segment
pins with 4 commons, or 35 LCD segment pins with 6 commons. And in a configuration where LCD
segment pins are not used, there can be up to 32 DIO pins.
The configuration for pins SEGDIO19 to SEGDIO27 is shown in Table 49, and the configuration for pins
SEGDIO36-39 and SEGDIO44-45 is shown in Table 50. SEG46 to SEG50 cannot be configured for DIO.
The configuration for pins SEGDIO51 and SEGDIO55 is shown in Table 51.
Table 48: Data/Direction Registers for SEGDIO0 to SEGDIO14 (71M6541D/F/G)
SEGDIO
Pin #
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
Internal Resources
Configurable
(see Table 47)
Rev 2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
–
–
1
2
3
4
5
6
LCD_MAP[14:8] (I/O RAM 0x240A)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 –
LCD_SEG0[5:0] to LCD_SEG14[5:0] (I/O RAM 0x2410[5:0] to 0x241E[5:0]
–
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
P0 (SFR 0x80)
P1 (SFR 0x90)
P2 (SFR 0xA0)
P3 (SFR 0xB0)
–
4
5
6
7
4
5
6
7
4
5
6
7
4
5
6
P0 (SFR 0x80)
P1 (SFR 0x90)
P2 (SFR 0xA0)
P3 (SFR 0xB0)
0
–
1
2
3
4
5
6
7
LCD_MAP[7:0] (I/O RAM 0x240B)
–
Y
Y
Y
Y
Y
Y
0
Y
Y
Y
Y
–
–
–
–
61
71M6541D/F/G and 71M6542F/G Data Sheet
Table 49: Data/Direction Registers for SEGDIO19 to SEGDIO27 (71M6541D/F/G)
SEGDIO
–
–
–
19
20
21
22
23
24
25
26
27
–
–
–
–
Pin #
–
–
–
16
15
14
13
12
11
10
9
8
–
–
–
–
–
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
–
–
–
–
–
–
3
4
5
6
7
0
1
2
3
LCD_MAP[23:19] (I/O RAM 0x2409)
LCD_MAP[27:24] (I/O RAM 0x2408)
–
–
– 19 20 21 22 23 24 25 26 27 –
–
–
–
LCD_SEGDIO19[5:0] to LCD_SEGDIO27[5:0]
(I/O RAM 0x2423[5:0] to 0x242C[5:0])
–
–
– 19 20 21 22 23 24 25 26 27 –
–
–
–
LCD_SEGDIO19[0] to LCD_SEGDIO27[0]
(I/O RAM 0x2423[0] to 0x242C[0])
–
–
– 19 20 21 22 23 24 25 26 27 –
–
–
–
LCD_SEGDIO19[1] to LCD_SEGDIO27[1]
(I/O RAM 0x2423[1] to 0x242C[1])
Table 50: Data/Direction Registers for SEGDIO36-39 to SEGDIO44-45 (71M6541D/F/G)
SEGDIO
Pin #
Configuration:
0 = DIO, 1 = LCD
–
–
–
–
–
–
44
63
45
62
–
–
5
–
–
–
–
–
–
–
–
4
5
6
7
–
–
–
–
4
LCD_MAP[39:36]
LCD_MAP[45:44]
(I/O RAM 0x2407)
(I/O RAM 0x2406)
–
–
36 37 38 39
–
–
–
–
44
LCD_SEGDIO36[5:0] to LCD_SEGDIO45[5:0]
(I/O RAM 0x2434-2437[5:0] to 0x243C-243D[5:0])
–
–
36 37 38 39
–
–
–
–
44
LCD_SEGDIO32[0] to LCD_SEGDIO45[0]
(I/O RAM 0x2434-2437[0] to 0x243C-243D[0])
–
–
36 37 38 39
–
–
–
–
44
LCD_SEGDIO32[1] to LCD_SEGDIO45[1]
(I/O RAM 0x2434-2437[1] to 0x243C-243D[1])
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
36
3
–
–
37
2
38
1
39
64
–
–
–
–
–
–
–
–
45
45
45
Table 51: Data/Direction Registers for SEGDIO51 and SEGDIO55 (71M6541D/F/G)
SEGDIO
51
–
–
–
55
–
–
–
Pin #
33
–
–
–
32
–
–
–
3
–
–
–
7
–
–
–
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
62
LCD_MAP[55], LDC_MAP[51]
(I/O RAM 0x2405)
–
–
–
–
–
55
–
51
LCD_SEGDIO51[5:0], LCD_SEGDIO55[5:0]
(I/O RAM 0x2443[5:0] and 0x2447[5:0])
–
–
–
–
–
–
51
55
LCD_SEGDIO51[0] to LCD_SEGDIO55[0]
(I/O RAM 0x2443[0] and 0x2447[0])
–
–
–
–
–
–
51
55
LCD_SEGDIO51[1] to LCD_SEGDIO55[1]
(I/O RAM 0x2443[1] and 0x2447[1])
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
2.5.8.3 Digital I/O for the 71M6542F/G
A total of 55 combined SEG/DIO pins are available for the 71M6542D/F. These pins can be categorized
as follows:
35 combined DIO/LCD segment pins:
o SEGDIO4…SEGDIO5 (2 pins)
o SEGDIO9…SEGDIO25 (17 pins)
o SEGDIO28…SEGDIO35 (8 pins)
o SEGDIO40…SEGDIO45 (6 pins)
o SEGDIO52…SEGDIO53 (2 pins)
15 combined DIO/LCD segment pins shared with other functions:
o
o
o
o
o
o
o
SEGDIO0/WPULSE, SEGDIO1/VPULSE (2 pins)
SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins)
SEGDIO6/XPULSE, SEGDIO7/YPULSE (2 pins)
SEGDIO8/DI (1 pin)
SEGDIO26/COM5, SEGDIO27/COM4 (2 pins)
SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)
SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins)
5 dedicated SEG segment pins are available:
o
o
ICE Inteface pins: SEG48/E_RXTX, SEG49/E_TCLK, SEG50/E_RST (3 pins)
Test Port pins: SEG46/TMUX2OUT, SEG47/TMUXOUT (2 pins)
There are four dedicated common segment outputs (COM0…COM3) plus the two additional shared common
segment outputs that are listed under combined SEG/DIO shared pins (SEGDIO26/COM5,
SEGDIO27/COM4).
Thus, in a configuration where none of these pins are used as DIOs, there can be up to 55 LCD segment
pins with 4 commons, or 53 LCD segment pins with 6 commons. And in a configuration where LCD
segment pins are not used, there can be up to 50 DIO pins.
Example: SEGDIO12 (see pin 32 in Table 52) is configured as a DIO output pin with a value of 1 (high) by
writing 0 to bit 4 of LCD_MAP[15:8], and writing 1 to both P3[4]and P3[0]. The same pin is configured as
an LCD driver by writing 1 to bit 4 of LCD_MAP[15:8]. The display information is written to bits 0 to 5 of
LCD_SEG12.
The configuration for pins SEGDIO16 to SEGDIO31 is shown in Table 53, the configuration for pins
SEGDIO32 to SEGDIO45 is shown in Table 54. SEG46 through SEG50 cannot be configured as DIO
pins. The configuration for pins SEGDIO51 to SEGDIO55 is shown in Table 55.
Table 52: Data/Direction Registers for SEGDIO0 to SEGDIO15 (71M6542F/G)
SEGDIO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin #
45
44
43
42
41
39
38
37
36
35
34
33
32
31
30
29
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
Internal Resources
Configurable
(see Table 47)
Rev 2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LCD_MAP[7:0] (I/O RAM 0x240B)
LCD_MAP[15:8] (I/O RAM 0x240A)
10
11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
LCD_SEG0[5:0] to LCD_SEG15[5:0] (I/O RAM 0x2410[5:0] to 0x241F[5:0]
0
1
2
3
P0 (SFR 0x80)
0
1
2
3
P1 (SFR 0x90)
0
1
2
3
P2 (SFR 0xA0)
0
1
2
3
P3 (SFR 0xB0)
4
5
6
7
P0 (SFR 0x80)
4
5
6
7
P1 (SFR 0x0)
4
5
6
7
P2 (SFR 0xA0)
4
5
6
7
P3 (SFR 0xB0)
–
–
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
–
–
–
–
63
71M6541D/F/G and 71M6542F/G Data Sheet
Table 53: Data/Direction Registers for SEGDIO16 to SEGDIO31 (71M6542F/G)
SEGDIO
Pin #
16
28
Configuration:
0 = DIO, 1 = LCD
0
SEG Data Register
17
27
18
25
20
23
21
22
22
21
23
20
24
19
25
18
26
17
27
16
28
11
29
10
30
9
31
8
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LCD_MAP[23:16] (I/O RAM 0x2409)
LCD_MAP[31:24] (I/O RAM 0x2408)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LCD_SEGDIO16[5:0] to LCD_SEGDIO31[5:0]
(I/O RAM 0x2420[5:0] to 0x242F[5:0])
16
17
18
19
27
28
29
30
31
18
LCD_SEGDIO16[0] to LCD_SEGDIO31[0]
(I/O RAM 0x2420[0] to 0x242F[0])
19 20 21 22 23 24 25 26 27
LCD_SEGDIO16[1] to LCD_SEGDIO31[1]
(I/O RAM 0x2420[1] to 0x242F[1])
28
29
30
31
DIO Data Register
Direction Register:
0 = input, 1 = output
19
24
16
17
20
21
22
23
24
25
26
Table 54: Data/Direction Registers for SEGDIO32 to SEGDIO45 (71M6542F/G)
SEGDIO
Pin #
Configuration:
0 = DIO, 1 = LCD
32
7
33
6
34
5
44
95
45
94
0
1
5
32
33
32
33
32
33
2
3
4
5
6
7
0
1
2
3
4
LCD_MAP[39:32]
LCD_MAP[45:40]
(I/O RAM 0x2407)
(I/O RAM 0x2406[5:0])
34 35 36 37 38 39 40 41 42 43 44
LCD_SEGDIO32[5:0] to LCD_SEGDIO45[5:0]
(I/O RAM 0x2430[5:0] to 0x243D[5:0])
34 35 36 37 38 39 40 41 42 43 44
LCD_SEGDIO32[0] to LCD_SEGDIO45[0]
(I/O RAM 0x2430[0] to 0x243D[0])
34 35 36 37 38 39 40 41 42 43 44
LCD_SEGDIO32[1] to LCD_SEGDIO45[1]
(I/O RAM 0x2430[1] to 0x243D[1])
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
35
4
36
3
37
2
38
1
39
100
40
99
41
98
42
97
43
96
45
45
45
Table 55: Data/Direction Registers for SEGDIO51 to SEGDIO55 (71M6542F/G)
SEGDIO
51
52
53
54
55
–
–
–
Pin #
53
52
51
47
46
–
–
–
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
64
–
–
–
2
3
4
LCD_MAP[55:51]
(I/O RAM 0x2405[7:3])
–
–
–
51 52 53 54 55
LCD_SEGDIO51[5:0] to LCD_SEGDIO55[5:0]
(I/O RAM 0x2443[5:0] to 0x2447[5:0])
–
–
–
51 52 53 54 55
LCD_SEGDIO51[0] to LCD_SEGDIO55[0]
(I/O RAM 0x2443[0] to 0x2447[0])
–
–
–
51 52 53 54 55
LCD_SEGDIO51[1] to LCD_SEGDIO55[1]
(I/O RAM 0x2443[1] to 0x2447[1])
0
1
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
2.5.8.4 LCD Drivers
The LCD drivers are grouped into up to six commons (COM0 – COM5) and up to 56 segment drivers.
The LCD interface is flexible and can drive 7-segment digits, 14-segments digits or enunciator symbols.
A voltage doubler and a contrast DAC generate VLCD from either VBAT or V3P3SYS, depending on the
V3P3SYS voltage. The voltage doubler, while capable of driving into a 500 kΩ load, is able to generate a
maximum LCD voltage that is within 1 V of twice the supply voltage. The doubler and DAC operate from
a trimmed low-power reference.
The configuration of the VLCD generation is controlled by the I/O RAM field LCD_VMODE[1:0] (I/O RAM
0x2401[7:6]). It is decoded into the LCD_EXT, LDAC_E, and LCD_BSTE internal signals. Table 56
details the LCD_VMODE[1:0] configurations.
Table 56: LCD_VMODE[1:0] Configurations
LCD_VMODE [1:0] LCD_EXT LDAC_E LCD_BSTE
11
1
0
0
10
0
1
1
01
0
1
0
00
0
0
0
Description
External VLCD connected to the VLCD pin.
See note 2 below for the definition of V3P3L.
LCD boost is enabled. The maximum VLCD pin
voltage is 2*V3P3L-1.
In general, the VLCD pin voltage is as follows:
VLCD = max(2*V3P3L-1, 2.5(1+LCD_DAC[4:0]/31)
LCD boost is disabled. The maximum VLCD
voltage is V3P3L.
VLCD = max(V3P3L, 2.5V+2.5*LCD_DAC[4:0]/31)
VLCD=V3P3L, LCD DAC and LCD boost are
disabled. In LCD mode, this setting causes the
lowest battery current.
Notes:
1. LCD_EXT, LDAC_E and LCD_BSTE are 71M654x internal signals which are decoded from
the LCD_VMODE[1:0] control field setting (I/O RAM 0x2401[7:6]). Each of these decoded
signals, when asserted, has the effect indicated in the description column above, and as
summarized below.
LCD_EXT : When set, the VLCD pin expects an external supply voltage
LDAC_E : When set, LCD DAC is enabled
LCD_BSTE : When set, the LCD boost circuit is enabled
2. V3P3L is an internal supply rail that is supplied from either the VBAT pin or the V3P3SYS
pin, depending on the V3P3SYS pin voltage. When the V3P3SYS pin drops below 3.0 VDC,
the 71M654x switches to BRN mode and V3P3L is sourced from the VBAT pin, otherwise
V3P3L is sourced from the V3P3SYS pin while in MSN mode.
When using the VLCD boost circuit, use care when setting the LCD_DAC[4:0] (I/O RAM 0x240D[4:0])
value to ensure that the LCD manufacturer’s recommended operating voltage specification is not
exceeded.
The voltage doubler is active in all LCD modes including the LCD mode when LCD_BSTE = 1. Current
dissipation in LCD mode can be reduced if the boost circuit is disabled and the LCD system is operated
directly from VBAT.
The LCD DAC uses a low-power reference and, within the constraints of VBAT and the voltage doubler,
generates a VLCD voltage of 2.5 VDC + 2.5 * LCD_DAC[4:0]/31.
The LCD_BAT bit (I/O RAM 0x2402[7]) causes the LCD system to use the battery voltage in all power
modes. This may be useful when an external supply is available for the LCD system. The advantage of
connecting the external supply to VBAT, rather than VLCD is that the LCD DAC is still active.
If LCD_EXT = 1, the VLCD pin must be driven from an external source. In this case, the LCD DAC has
no effect.
Rev 2
65
71M6541D/F/G and 71M6542F/G Data Sheet
The LCD system has the ability to drive up to six segments per SEG driver. If the display is configured with
six back planes, the 6-way multiplexing compresses the number of SEG pins required to drive a display and
therefore enhance the number of DIO pins available to the application. Refer to the LCD_MODE[2:0] field
(I/O RAM 0x2400[6:4]) settings (Table 57) for the different LCD multiplexing choices. If 5-state
multiplexing is selected, SEGDIO27 is converted to COM4. If 6-state multiplexing is selected, SEGDIO26
is converted to COM5. These conversions override the SEG/DIO mapping of SEGDIO26 and SEGDIO27.
Additionally, independent of LCD_MODE[2:0], if LCD_ALLCOM = 1, then SEGDIO26 and SEGDIO27
become COM4 and COM5 if their LCD_MAP[ ] bits are set.
The LCD_ON (I/O RAM 0x240C[0]) and LCD_BLANK (I/O RAM 0x240C[1]) bits are an easy way to either
blank the LCD display or turn it fully on. Neither bit affects the contents of the LCD data stored in the
LCDSEG_DIO[ ] registers. In comparison, LCD_RST (I/O RAM 0x240C[2]) clears all LCD data to zero.
LCD_RST affects only pins that are configured as LCD.
A small amount of power can be saved by programming the LCD frequency to the lowest value
that provides satisfactory LCD visibility over the required temperature range.
66
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 57 shows all I/O RAM registers that control the operation of the LCD interface.
Table 57: LCD Configurations
Name
Location Rst
Wk Dir
LCD_ALLCOM
2400[3]
0
–
R/W
LCD_BAT
2402[7]
0
–
R/W
LCD_E
2400[7]
0
–
R/W
LCD_ON
LCD_BLANK
240C[0]
240C[1]
0
0
–
R/W
R/W
LCD_RST
240C[2]
0
–
R/W
LCD_DAC[4:0]
240D[4:0]
0
–
R/W
LCD_CLK[1:0]
2400[1:0]
0
–
R/W
LCD_MODE[2:0] 2400[6:4]
0
–
R/W
LCD_VMODE[1:0] 2401[7:6]
00
00
R/W
Description
Configures all 6 SEG/COM pins as COM. Has no effect
on pins whose LCD_MAP bit is zero.
Connects the LCD power supply to VBAT in all modes.
Enables the LCD display. When disabled, VLC2,
VLC1, and VLC0 are ground as are the COM and SEG
outputs if their LCD_MAP bit is 1.
LCD_ON = 1 turns on all LCD segments without
affecting the LCD data. Similarly, LCD_BLANK = 1
turns off all LCD segments without affecting the LCD
data. If both bits are set, all LCD segments are turned
on.
Clear all bits of LCD data. These bits affect SEGDIO
pins that are configured as LCD drivers.
This register controls the LCD contrast DAC, which
adjusts the VLCD voltage and has an output range of
2.5 VDC to 5 VDC. The VLCD voltage is
VLCD = 2.5 + 2.5 * LCD_DAC[4:0]/31
Thus, the LSB of the DAC is 80.6 mV. The maximum
DAC output voltage is limited by V3P3SYS, VBAT, and
whether LCD_BSTE is set.
Sets the LCD clock frequency (1/T). See definition of T
in Figure 21.
Note: fw = 32768 Hz
00-fw/2^9, 01-fw/2^8, 10-fw/2^7, 11-fw/2^6
The LCD bias and multiplex mode.
Output
LCD_MODE
000
4 states, 1/3 bias
001
3 states, 1/3 bias
010
2 states, ½ bias
011
3 states, ½ bias
100
Static display
101
5 states, 1/3 bias
110
6 states, 1/3 bias
This register specifies how VLCD is generated.
LCD_VMODE Description
11
External VLCD
LCD boost and LCD DAC
10
enabled
01
LCD DAC enabled
No boost and no DAC. VLCD
00
= VBAT or V3P3SYS
The LCD can be driven in static, ½ bias, and 1/3 bias modes. Figure 21 defines the COM waveforms.
Note that COM pins that are not required in a specific mode maintain a ‘segment off’ state rather than
GND, VCC, or high impedance.
The segment drivers SEGDIO22 and SEGDIO23 can be configured to blink at either 0.5 Hz or 1 Hz.
The blink rate is controlled by LCD_Y (I/O RAM 0x2400[2]). There can be up to six pixels/segments
connected to each of these driver pins. The I/O RAM fields LCD_BLKMAP22[5:0] (I/O RAM 0x2402[5:0])
and LCD_BLKMAP23[5:0] (I/O RAM 0x2401[5:0]) identify which pixels, if any, are to blink.
LCD_BLKMAP22[5:0] and LCD_BLKMAP23[5:0] are non-volatile.
Rev 2
67
71M6541D/F/G and 71M6542F/G Data Sheet
The LCD bias may be compensated for temperature using the LCD_DAC[4:0] field (I/O RAM 0x240D[4:0]).
The bias may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in MSN mode and VBAT in BRN
and LCD modes). When the LCD_DAC[4:0] field is set to 000, the DAC is bypassed and powered
down. This can be used to reduce current in LCD mode.
STATIC (LCD_MODE=100)
1/2 BIAS, 2 STATES (LCD_MODE = 010 )
0
1
COM0
COM0
1/2 BIAS, 3 STATES (LCD_MODE = 011 )
0
1
2
COM0
COM1
(1/2)
COM1
COM2
(1/2)
COM2
(1/2)
COM2
COM3
(1/2)
COM3
(1/2)
COM3
(1/2)
COM4
(1/2)
COM4
(1/2)
COM4
(1/2)
COM5
(1/2)
COM5
(1/2)
COM5
(1/2)
COM1
SEG_ON
SEG_ON
SEG_ON
SEG_OFF
SEG_OFF
SEG_OFF
T
1/3 BIAS, 3 STATES (LCD_MODE = 011 )
0
1
2
COM0
1/3 BIAS, 4 STATES (LCD_MODE = 000 )
3
0
1
2
COM0
1/3 BIAS, 6 STATES (LCD_MODE = 110 )
3
4
5
0
1
2
COM0
COM1
COM1
COM1
COM2
COM2
COM2
COM3
COM3
COM4
COM4
COM4
COM5
COM5
COM5
SEG_ON
SEG_ON
SEG_ON
SEG_OFF
SEG_OFF
SEG_OFF
COM3
(2/3)
(1/3)
Figure 21: LCD Waveforms
68
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
LCD Drivers (71M6541D/F/G)
With a maximum of 35 LCD driver pins available, the 71M6541D/F/G is capable of driving up to 6 x 35 =
210 pixels of an LCD display when using the 6 x multiplex mode. At eight pixels per digit, this
corresponds to 26 digits.
LCD segment data is written to the LCD_SEGn[5:0] I/O RAM registers as described in 2.5.8.2 and 2.5.8.3.
SEG46 through SEG50 cannot be configured as DIO pins. Display data for these pins are written to I/O
RAM registers LCD_SEG46[5:0] through LCD_SEG50[5:0] (see Table 58). When the ICE_E pin is pulled
high, it overrides the SEG functionality, and pins E_RXTX/SEG48, E_TCLK/SEG49 and E_RST/SEG50
function as ICE interface pins.
LCD_MAP[46] and LCD_MAP[47] (I/O RAM 0x2406[6] and 0x2407[7]) must be set to 1 in order to permit
TMUX2OUT/SEG46 and TMUXOUT/SEG47 to operate as SEG drivers, otherwise. If LCD_MAP[46] and
LCD_MAP[47] are 0, these pins operate as TMU2XOUT and TMUXOUT (see 2.5.12 Test Ports
(TMUXOUT and TMUX2OUT Pins) on page 78).
Rev 2
49
50
Pin #
61
60
38
37
36
Configuration
Always LCD pins, except
when used for ICE interface
or TMUXOUT/TMUX2OUT.
SEG Data Register
LCD_SEG50[5:0]
48
LCD_SEG49[5:0]
47
LCD_SEG48[5:0]
46
LCD_SEG47[5:0]
SEG
LCD_SEG46[5:0]
Table 58: 71M6541D/F/G LCD Data Registers for SEG46 to SEG50
69
71M6541D/F/G and 71M6542F/G Data Sheet
LCD Drivers (71M6542F/G)
With a maximum of 56 LCD driver pins available, the 71M6542D/F is capable of driving up to 6 x 56 = 336
pixels of an LCD display when using the 6 x multiplex mode. At eight pixels per digit, this corresponds to
42 digits.
LCD segment data is written to the LCD_SEGn[5:0] I/O RAM registers as described in 2.5.8.3 Digital I/O
for the .
SEG46 through SEG50 cannot be configured as DIO pins. Display data for these pins are written to I/O
RAM fields LCD_SEG46[5:0] (I/O RAM 0x243E[5:0]) through LCD_SEG50[5:0] (I/O RAM 0x2442[5:0]); see
Table 59. The associated pins function as ICE interface pins, and the ICE functionality overrides the LCD
function whenever ICE_E is pulled high.
Table 59: 71M6542F/G LCD Data Registers for SEG46 to SEG50
SEG
46
47
48
49
50
Pin #
93
92
58
57
56
2.5.9
LCD_SEGDIO50[5:0]
LCD_SEGDIO49[5:0]
LCD_SEGDIO48[5:0]
LCD_SEGDIO47[5:0]
SEG Data Register
Always LCD pins, except
when used for ICE interface
or TMUXOUT/TMUX2OUT.
LCD_SEGDIO46[5:0]
Configuration:
EEPROM Interface
The 71M6541D/F/G provides hardware support for either a two-pin or a three-wire (µ-wire) type of
EEPROM interface. The interfaces use the SFR EECTRL (SFR 0x9F) and EEDATA (SFR 0x9E)
registers for communication.
2.5.9.1 Two-pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices and is intended for
2
use with I C devices. The interface is multiplexed onto the SEGDIO2 (SDCK) and SEGDIO3 (SDATA)
pins and is selected by setting DIO_EEX[1:0] = 01 (I/O RAM 0x2456[7:6]). The MPU communicates with
the interface through the SFR registers EEDATA and EECTRL. If the MPU wishes to write a byte of data
to the EEPROM, it places the data in EEDATA and then writes the Transmit code to EECTRL. This
initiates the transmit operation which is finished when the BUSY bit falls. INT5 is also asserted when
BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged the transmission.
A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon
completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each
transmission, and then holds in a high state until the next transmission. The EECTRL bits when the
two-pin interface is selected are shown in Table 60.
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Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 60: EECTRL Bits for 2-pin Interface
Status
Bit
Name
Read/
Write
Reset
State
Polarity
Description
7
6
5
ERROR
BUSY
RX_ACK
R
R
R
0
0
1
Positive
Positive
Positive
4
TX_ACK
R
1
Positive
1 when an illegal command is received.
1 when serial data bus is busy.
1 indicates that the EEPROM sent an ACK bit.
1 indicates that an ACK bit has been sent to the
EEPROM.
CMD[3:0]
0000
0010
3:0
CMD[3:0]
W
0000
Positive
0011
0101
0110
1001
Others
Operation
No-op command.
Receive a byte from the EEPROM
and send ACK.
Transmit a byte to the EEPROM.
Issue a STOP sequence.
Receive the last byte from the
EEPROM and do not send ACK.
Issue a START sequence.
No operation, set the ERROR bit.
The EEPROM interface can also be operated by controlling the DIO2 and DIO3 pins directly. The
direction of the DIO line can be changed from input to output and an output value can be written
with a single write operation, thus avoiding collisions (see Table 15 Port Registers (SEGDIO0-15)).
Therefore, no resistor is required in series SDATA to protect against collisions.
2.5.9.2 Three-wire (µ-Wire) EEPROM Interface with Single Data Pin
A 500 kHz three-wire interface, using SDATA, SDCK, and a DIO pin for CS is available. The interface is
selected by setting DIO_EEX[1:0] = 10. The EECTRL bits when the three-wire interface is selected are
shown in Table 61. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM
or read from the EEPROM, depending on the values of the EECTRL bits.
2.5.9.3 Three-wire (µ-Wire/SPI) EEPROM Interface with Separate Di/DO Pins
If DIO_EEX[1:0]=11, the three-wire interface is the same as above, except DI and DO are separate pins.
In this case, SEGDIO3 becomes DO and SEGDIO8 becomes DI. The timing diagrams are the same as
for DIO_EEX[1:0]=10 except that all output data appears on DO and all input data is expected on DI. In
this mode, DI is ignored while data is being received on DO. This mode is compatible with SPI modes 0,0
and 1,1 where data is shifted out on the falling edge of the clock and is strobed in on the rising edge of
the clock.
Table 61: EECTRL Bits for the 3-wire Interface
Control
Bit
Name
Read/
Write
7
WFR
W
6
BUSY
R
5
HiZ
W
Rev 2
Description
Wait for Ready. If this bit is set, the trailing edge of BUSY is delayed until
a rising edge is seen on the data line. This bit can be used during the
last byte of a Write command to cause the INT5 interrupt to occur when
the EEPROM has finished its internal write sequence. This bit is ignored
if Hi-Z=0.
Asserted while the serial data bus is busy. When the BUSY bit falls, an
INT5 interrupt occurs.
Indicates that the SD signal is to be floated to high impedance immediately
after the last SDCK rising edge.
71
71M6541D/F/G and 71M6542F/G Data Sheet
4
RD
W
3:0
CNT[3:0]
W
Indicates that EEDATA (SFR 0x9E) is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD=1, CNT bits of data are read MSB first, and right
justified into the low order bits of EEDATA. If RD=0, CNT bits are sent
MSB first to the EEPROM, shifted out of the MSB of EEDATA. If
CNT[3:0] is zero, SDATA simply obeys the HiZ bit.
The timing diagrams in Figure 22 through Figure 26 describe the 3-wire EEPROM interface behavior. All
commands begin when the EECTRL (SFR 0x9F) register is written. Transactions start by first raising the
DIO pin that is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 22
through Figure 26 are then sent via EECTRL and EEDATA.
When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM is
driving SDATA, but transitions to Hi-Z (high impedance) when CS falls. The firmware should then
immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to a
low-Z state.
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- No HiZ
SCLK (output)
SDATA (output)
D7
D6
D5
SDATA output Z
D4
D3
D2
(LoZ)
BUSY (bit)
Figure 22: 3-wire Interface. Write Command, HiZ=0.
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ
SCLK (output)
SDATA (output)
D7
D6
D5
SDATA output Z
D4
D3
D2
(LoZ)
(HiZ)
BUSY (bit)
Figure 23: 3-wire Interface. Write Command, HiZ=1
EECTRL Byte Written
INT5
CNT Cycles (8 shown)
READ
SCLK (output)
SDATA (input)
SDATA output Z
D7
D6
D5
D4
D3
D2
D1
D0
(HiZ)
BUSY (bit)
Figure 24: 3-wire Interface. Read Command.
72
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
EECTRL Byte Written
INT5 not issued
CNT Cycles (0 shown)
Write -- No HiZ
EECTRL Byte Written
Write -- HiZ
INT5 not issued
CNT Cycles (0 shown)
SCLK (output)
SCLK (output)
SDATA (output)
SDATA (output)
D7
SDATA output Z
SDATA output Z
(LoZ)
(HiZ)
BUSY (bit)
BUSY (bit)
Figure 25: 3-Wire Interface. Write Command when CNT=0
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ and WFR
SCLK (output)
SDATA (out/in)
D7
D6
D5
(From 654x)
SDATA output Z
(LoZ)
D4
D3
D2
BUSY
READY
(From EEPROM)
(HiZ)
BUSY (bit)
Figure 26: 3-wire Interface. Write Command when HiZ=1 and WFR=1.
2.5.10 SPI Slave Port
The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM
and I/O RAM locations. It is also able to send commands to the MPU. The interface to the slave port
consists of the SPI_CSZ, SPI_CKI, SPI_DI and SPI_DO pins. These pins are multiplexed with the
combined DIO/LCD segment driver pins SEGDIO36 to SEGDIO39.
Additionally, the SPI interface allows flash memory to be read and to be programmed. To facilitate flash
programming, cycling power or asserting RESET causes the SPI port pins to default to SPI mode. The
SPI port is disabled by clearing the SPI_E bit (I/O RAM 0x270C[4]).
Possible applications for the SPI interface are:
1) An external host reads data from CE locations to obtain metering information. This can be used in
applications where the 71M654x function as a smart front-end with preprocessing capability. Since
the addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU, I/O RAM, but
not SFRs or the 80515-internal register bank.
2) A communication link can be established via the SPI interface: By writing into MPU memory locations,
the external host can initiate and control processes in the 71M654x MPU. Writing to a CE or MPU
location normally generates an interrupt, a function that can be used to signal to the MPU that the
byte that had just been written by the external host must be read and processed. Data can also be
inserted by the external host without generating an interrupt.
3) An external DSP can access front-end data generated by the ADC. This mode of operation uses the
71M654x as an analog front-end (AFE).
4) Flash programming by the external host (SPI Flash Mode).
SPI Transactions
A typical SPI transaction is as follows. While SPI_CSZ is high, the port is held in an initialized/reset state.
During this state, SPI_DO is held in Hi-Z state and all transitions on SPI_CLK and SPI_DI are ignored.
When SPI_CSZ falls, the port begins the transaction on the first rising edge of SPI_CLK. As shown in
Table 62, a transaction consists of an optional 16 bit address, an 8 bit command, an 8 bit status byte,
followed by one or more bytes of data. The transaction ends when SPI_CSZ is raised. Some transactions
may consist of a command only.
Rev 2
73
71M6541D/F/G and 71M6542F/G Data Sheet
When SPI_CSZ rises, SPI command bytes that are not of the form x000 0000 update the SPI_CMD (SFR
0xFD) register and then cause an interrupt to be issued to the MPU. The exception is if the transaction was
a single byte. In this case, the SPI_CMD byte is always updated and the interrupt issued. SPI_CMD is not
cleared when SPI_CSZ is high.
The SPI port supports data transfers up to 10 Mb/s. A serial read or write operation requires at least 8
clocks per byte, guaranteeing SPI access to the RAM is no faster than 1.25 MHz, thus ensuring that SPI
access to DRAM is always possible.
Table 62: SPI Transaction Fields
Field
Name
Address
Command
Required
Yes, except for
single-byte
transaction
Yes
Size
(bytes)
2
1
Status
Yes, if transaction
includes DATA
1
Data
Yes, if transaction
includes DATA
1 or
more
Description
16-bit address. The address field is not required if the
transaction is a simple SPI command.
8-bit command. This byte can be used as a command to the
MPU. In multi-byte transactions, the MSB is the R/W bit.
Unless the transaction is multi-byte and SPI_CMD is exactly
0x80 or 0x00, the SPI_CMD register is updated and an SPI
interrupt is issued. Otherwise, the SPI_CMD register is
unchanged and the interrupt is not issued.
8-bit status field, indicating the status of the previous
transaction. This byte is also available in the MPU memory
map as SPI_STAT (I/O RAM 0x2708) register. See Table 64
for the contents.
The read or write data. Address is auto incremented for
each new byte.
The SPI_STAT byte is output on every SPI transaction and indicates the parity of the previous transaction
and the error status of the previous transaction. Potential error sources are:
•
•
71M654x not ready.
Transaction not ending on a byte boundary.
SPI Safe Mode
Sometimes it is desirable to prevent the SPI interface from writing to arbitrary RAM locations and thus
disturbing MPU and CE operation. This is especially true in AFE applications. For this reason, the SPI
SAFE mode was created. In SPI SAFE mode, SPI write operations are disabled except for a 16 byte transfer
region at address 0x400 to 0x40F. If the SPI host needs to write to other addresses, it must use the
SPI_CMD register to request the write operation from the MPU. SPI SAFE mode is enabled by the
SPI_SAFE bit (I/O RAM 0x270C[3]).
Single-Byte Transaction
If a transaction is a single byte, the byte is interpreted as SPI_CMD. Regardless of the byte value, singlebyte transactions always update the SPI_CMD register and cause an SPI interrupt to be generated.
Multi-Byte Transaction
As shown in Figure 27, multi-byte operations consist of a 16 bit address field, an 8 bit CMD, a status byte,
and a sequence of data bytes. A multi byte transaction is three or more bytes.
74
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
SERIAL READ
16 bit Address
Status Byte
8 bit CMD
DATA[ADDR]
DATA[ADDR+1]
(From Host) SPI_CSZ
Extended Read . . .
0
15
16
A0
C7
23
31
24
32
39
40
D0
D7
47
(From Host) SPI_CK
(From Host) SPI_DI
A15
A14
A1
C6
C5
C0
HI Z
(From 654x) SPI_DO
SERIAL WRITE
x
ST7
16 bit Address
ST6
ST5
ST0
D7
D6
Status Byte
8 bit CMD
D1
DATA[ADDR]
D6
D1
D0
DATA[ADDR+1]
(From Host) SPI_CSZ
Extended Write . . .
0
15
16
A0
C7
23
31
24
32
39
40
D0
D7
47
(From Host) SPI_CK
(From Host) SPI_DI
x
A15
A14
A1
HI Z
(From 654x) SPI_DO
C6
C5
D7
C0
ST7
ST6
ST5
D6
D1
D6
D1
D0
x
ST0
Figure 27: SPI Slave Port - Typical Multi-Byte Read and Write operations
Table 63: SPI Command Sequences
Command Sequence
ADDR 1xxx xxxx STATUS
Byte0 ... ByteN
0xxx xxxx ADDR Byte0 ...
ByteN
Rev 2
Description
Read data starting at ADDR. ADDR auto-increments until SPI_CSZ is
raised. Upon completion, SPI_CMD (SFR 0xFD) is updated to 1xxx xxxx
and an SPI interrupt is generated. The exception is if the command byte
is 1000 0000. In this case, no MPU interrupt is generated and SPI_CMD
is not updated.
Write data starting at ADDR. ADDR auto-increments until SPI_CSZ is
raised. Upon completion, SPI_CMD is updated to 0xxx xxxx and an SPI
interrupt is generated. The exception is if the command byte is 0000
0000. In this case, no MPU interrupt is generated and SPI_CMD is not
updated.
75
71M6541D/F/G and 71M6542F/G Data Sheet
Table 64: SPI Registers
Name
EX_SPI
SPI_CMD
Location
Rst
Wk
Dir
Description
2701[7]
SFR FD[7:0]
0
–
0
–
R/W
R
SPI_E
270C[4]
1
1
R/W
IE_SPI
SFR F8[7]
0
0
R/W
SPI_SAFE
270C[3]
0
0
R/W
SPI_STAT
2708[7:0]
0
0
R
SPI interrupt enable bit.
SPI command. The 8-bit command from the bus master.
SPI port enable bit. It enables the SPI interface on pins
SEGDIO36 – SEGDIO39.
SPI interrupt flag. Set by hardware, cleared by writing a 0.
Limits SPI writes to SPI_CMD and a 16 byte region in
DRAM when set. No other write operations are permitted.
SPI_STAT contains the status results from the previous
SPI transaction.
Bit 7: Ready error: The 71M654x was not ready to read
or write as directed by the previous command.
Bit 6: Read data parity: This bit is the parity of all bytes
read from the 71M654x in the previous command. Does
not include the SPI_STAT byte.
Bit 5: Write data parity: This bit is the overall parity of the
bytes written to the 71M654x in the previous command.
It includes CMD and ADDR bytes.
Bit 4-2: Bottom 3 bits of the byte count. Does not include
ADDR and CMD bytes. One, two, and three byte
instructions return 111.
Bit 1: SPI FLASH mode: This bit is zero when the TEST
pin is zero.
Bit 0: SPI FLASH mode ready: Used in SPI FLASH
mode. Indicates that the flash is ready to receive
another write instruction.
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71M6541D/F/G and 71M6542F/G Data Sheet
SPI Flash Mode (SFM)
In normal operation, the SPI slave interface cannot read or write the flash memory. However, the
71M6541D/F/G and 71M6542F/G support an SPI Flash Mode (SFM) which facilitates initial programming
of the flash memory. When in SFM mode, the SPI can erase, read, and write the flash memory. Other
memory elements such as XRAM and I/O RAM are not accessible in this mode. In order to protect the
flash contents, several operations are required before the SFM mode is successfully invoked.
In SFM mode, n byte reads and dual-byte writes to flash memory are supported. See the SPI Transactions
description on Page 73 for the format of read and write commands. Since the flash write operation is always
based on a two-byte word, the initial address must always be even. Data is written to the 16-bit flash
memory bus after the odd word is written.
In SFM mode, the MPU is completely halted. For this reason, the interrupt feature described in the SPI
Transaction section above is not available in SFM mode. The 71M6541D/F/G and 71M6542F/G must be
reset by the WD timer or by the RESET pin in order to exit SFM mode.
Invoking SFM
The following conditions must be met prior to invoking SFM:
•
•
•
•
•
Pin ICE_E = 1. This disables the watchdog and adds another layer of protection against inadvertent
Flash corruption.
The external power source (V3P3SYS, V3P3A) is at the proper level (> 3.0 VDC).
PREBOOT = 0 (SFR 0xB2[7]). This validates the state of the SECURE bit (SFR 0xB2[6]).
SECURE = 0. This I/O RAM register indicates that SPI secure mode is not enabled. Operations are
limited to SFM Mass Erase mode if the SECURE bit = 1 (Flash read back is not allowed in Secure mode).
FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4]) = 0010.
The I/O RAM registers SFMM (I/O RAM 0x2080) and SFMS (I/O RAM 0x2081) are used to invoke SFM. Only
the SPI interface has access to these two registers. This eliminates an indirect path from the MPU for
disabling the watchdog. SFMM and SFMS need to be written to in sequence in order to invoke SFM. This
sequential write process prevents inadvertent entering of SFM.
The sequence for invoking SFM is:
•
First, write to the SFMM (I/O RAM 0x2080) register. The value written to this register defines the SFM
mode.
o 0xD1: Mass Erase mode. A Flash Mass erase cycle is invoked upon entering SFM.
o 0x2E: Flash Read back mode. SFM is entered for Flash read back purposes. Flash writes
are not be blocked and it is up to the user to guarantee that only previously unwritten
locations are written. This mode is not accessible when SPI secure mode is set.
o SFM is not invoked if any other pattern is written to the SFMM register.
•
Next, write 0x96 to the SFMS (I/O RAM 0x2081) register. This action invokes SFM provided that the
previous write operation to SFMM met the requirements. Writing any other pattern to this register does
not invoke SFM. Additionally, any write operations to this register automatically reset the previously
written SFMM register values to zero.
Rev 2
77
71M6541D/F/G and 71M6542F/G Data Sheet
SFM details
The following occurs upon entering SFM.
•
•
•
•
•
The CE is disabled.
The MPU is halted. Once the MPU is halted it can only be restarted with a reset. This reset can be
accomplished with the RESET pin, a watchdog reset, or by cycling power (without battery at the
VBAT pin).
The Flash control logic is reset in case the MPU was in the middle of a Flash write operation or Erase
cycle.
Mass erase is invoked if specified in the SFMM register, I/O RAM 0x2080 (see Invoking SFM, above).
The SECURE bit (SFR 0xB2[6]) is cleared at the end of this and all Mass Erase cycles.
All SPI read and write operations now refer to Flash instead of XRAM space.
The SPI host can access the current state of the pending multi-cycle Flash access by performing a 4-byte
SPI write of any address and checking the status field.
All SPI write operations in SFM mode must be 6-byte write transaction that writes two bytes to an even
address. The write transactions must contain a command byte of the form 0xxx xxxx. Auto incrementing
is disabled for write operations.
SPI read transactions can make use of auto increment and may access single bytes. The command byte
must always be of the form 1xxx xxxx in SFM read transactions.
SPI commands in SFM
Interrupts are not generated in SFM since the MPU is halted. The format of the commands is described in
the SPI Transactions description on Page 73.
2.5.11 Hardware Watchdog Timer
An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6541D/F/G and
71M6542F/G. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU
firmware at least every 1.5 seconds. When not refreshed on time, the WDT overflows and the part is
reset as if the RESET pin were pulled high, except that the I/O RAM bits are in the same state as after a
wake-up from SLP or LCD modes (see the I/O RAM description in 5.2 I/O RAM Map – Alphabetical Order
for a list of I/O RAM bit states after RESET and wake-up). After 4100 CK32 cycles (or 125 ms) following
the WDT overflow, the MPU is launched from program address 0x0000.
The watchdog timer is also reset when the internal signal WAKE=0 (see 3.4 Wake Up Behavior).
For details, see 3.3.4 Watchdog Timer Reset.
2.5.12 Test Ports (TMUXOUT and TMUX2OUT Pins)
Two independent multiplexers allow the selection of internal analog and digital signals for the TMUXOUT
and TMUX2OUT pins. These pins are multiplexed with the SEG47 and SEG46 function. In order to function
as test pins, LCD_MAP[46] (I/O RAM 0x2406[6]) and LCD_MAP[47] (I/O RAM 0x2406[7]) must be 0.
One of the digital or analog signals listed in
Table 65 can be selected to be output on the TMUXOUT pin. The function of the multiplexer is controlled
with the I/O RAM register TMUX[5:0] (I/O RAM 0x2502[5:0], as shown in
Table 65.
One of the digital or analog signals listed in Table 66 can be selected to be output on the TMUX2OUT pin.
The function of the multiplexer is controlled with the I/O RAM register TMUX2[4:0] (I/O RAM 0x2503[4:0]), as
shown in Table 66.
The TMUX[5:0] and TMUX2[4:0] I/O RAM locations are non-volatile and their contents are preserved
by battery power and across resets.
78
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
The TMUXOUT and TMUX2OUT pins may be used for diagnostics purposes during the product
development cycle or in the production test. The RTC 1-second output may be used to calibrate the
crystal oscillator. The RTC 4-second output provides higher precision for RTC calibration. RTCLK may
also be used to calibrate the RTC.
Table 65: TMUX[5:0] Selections
Signal Name
Description
1
RTCLK
9
WD_RST
A
CKMPU
D
V3AOK bit
E
V3OK bit
1B
MUX_SYNC
32.768 kHz clock waveform
Indicates when the MPU has reset the watchdog timer. Can be
monitored to determine spare time in the watchdog timer.
MPU clock – see Table 9
Indicates that the V3P3A pin voltage is ≥ 3.0 V. The V3P3A and
V3P3SYS pins are expected to be tied together at the PCB level.
The 71M654x monitors the V3P3A pin voltage only.
Indicates that the V3P3A pin voltage is ≥ 2.8 V. The V3P3A and
V3P3SYS pins are expected to be tied together at the PCB level.
The 71M654x monitors the V3P3A pin voltage only.
Internal multiplexer frame SYNC signal. See Figure 6 and Figure
7.
1C
1D
1F
CE_BUSY interrupt
CE_XFER interrupt
RTM output from CE
TMUX[5:0]
See 2.3.3 on page 25 and Figure 16 on page 47
See 2.3.5 on page 25
Note:
All TMUX[5:0] values which are not shown are reserved.
Table 66: TMUX2[4:0] Selections
Signal Name
Description
0
WD_OVF
1
PULSE_1S
2
PULSE_4S
3
RTCLK
SPARE[1] bit – I/O RAM
0x2704[1]
SPARE[2] bit – I/O RAM
0x2704[2]
Indicates when the watchdog timer has expired (overflowed).
One second pulse with 25% Duty Cycle. This signal can be used
to measure the deviation of the RTC from an ideal 1 second
interval. Multiple cycles should be averaged together to filter out
jitter.
Four second pulse with 25% Duty Cycle. This signal can be used
to measure the deviation of the RTC from an ideal 4 second
interval. Multiple cycles should be averaged together to filter out
jitter. The 4 second pulse provides a more precise measurement
than the 1 second pulse.
32.768 kHz clock waveform
Copies the value of the bit stored in 0x2704[1]. For general
purpose use.
Copies the value of the bit stored in 0x2704[2]. For general
purpose use.
Indicates when a WAKE event has occurred.
Internal multiplexer frame SYNC signal. See Figure 6 and Figure
7.
See 2.5.3 on page 50
Digital GND. Use this signal to make the TMUX2OUT pin static.
TMUX2[4:0]
8
9
A
WAKE
B
MUX_SYNC
C
E
12
13
14
15
16
17
18
1F
MCK
GNDD
INT0 – DIG I/O
INT1 – DIG I/O
INT2 – CE_PULSE
INT3 – CE_BUSY
INT4 - VSTAT
INT5 – EEPROM/SPI
INT6 – XFER, RTC
RTM_CK (flash)
Interrupt 0. See 2.4.8 on page 40. Also see Figure 16 on page 47.
See 2.3.5 on page 25.
Note:
All TMUX2[4:0] values which are not shown are reserved.
Rev 2
79
71M6541D/F/G and 71M6542F/G Data Sheet
3
Functional Description
3.1
Theory of Operation
The energy delivered by a power source into a load can be expressed as:
t
E = ∫ V (t ) I (t )dt
0
Assuming phase angles are constant, the following formulae apply:


P = Real Energy [Wh] = V * A * cos φ* t

S = Apparent Energy [VAh] =
Q = Reactive Energy [VARh] = V * A * sin φ * t
P2 + Q2
For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content
may change constantly. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state
electricity meter IC such as the Teridian 71M654x functions by emulating the integral operation above,
i.e., it processes current and voltage samples through an ADC at a constant frequency. As long as the
ADC resolution is high enough and the sample frequency is beyond the harmonic range of interest, the
current and voltage samples, multiplied with the time period of sampling yield an accurate quantity for the
momentary energy. Summing up the momentary energy quantities over time results in very accurate
results for accumulated energy.
500
400
300
200
100
0
0
5
10
15
20
-100
-200
Current [A]
-300
Voltage [V]
Energy per Interval [Ws]
-400
Accumulated Energy [Ws]
-500
Figure 28: Voltage, Current, Momentary and Accumulated Energy
Figure 28 shows the shapes of V(t), I(t), the momentary power and the accumulated power, resulting from
50 samples of the voltage and current signals over a period of 20 ms. The application of 240 VAC and
100 A results in an accumulation of 480 Ws (= 0.133 Wh) over the 20 ms period, as indicated by the
accumulated power curve. The described sampling method works reliably, even in the presence of dynamic
phase shift and harmonic distortion.
80
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
3.2
Battery Modes
Shortly after system power (V3P3SYS) is applied, the part is in mission mode (MSN mode). MSN mode
means that the part is operating with system power and that the internal PLL is stable. This mode is the
normal operating mode where the part is capable of measuring energy.
When system power is not available, the 71M654x is in one of three battery modes:
•
•
•
BRN mode (brownout mode)
LCD mode (LCD-only mode)
SLP mode (sleep mode).
An internal comparator monitors the voltage at the V3P3SYS pin (note that V3P3SYS and V3P3A are
typically connected together at the PCB level). When the V3P3SYS dc voltage drops below 3.0 VDC, the
comparator resets an internal power status bit called V3OK . As soon as system power is removed and
V3OK = 0, the 71M654x switches to battery power (VBAT pin), notifies the MPU by issuing an interrupt and
updates the VSTAT[2:0] register (SFR 0xF9[2:0], see Table 68). The MPU continues to execute code when
the system transitions from MSN to BRN mode. Refer to 3.2.1 BRN Mode for the settings that result in the
lowest possible power during BRN mode. Depending on the MPU code, the MPU can choose to stay in
BRN mode, or transition to LCD or to SLP mode (via the I/O RAM bits LCD_ONLY, I/O RAM 0x28B2[6] and
SLEEP, I/O RAM 0x28B2[7]). BRN mode is similar to MSN mode except that resources powered by V3P3A
power, such as the ADC are inaccurate. In BRN mode the CE continues to run and should be turned off
to conserve VBAT power. Also, the PLL continues to function at the same frequency as in MSN mode
and its frequency should be reduced to save power (CKGN = 0x24 (I/O RAM 0x2200).
When system power is restored, the 71M654x automatically transitions from any of the battery modes
(BRN, LCD, SLP) back to MSN mode, switches back to using system power (V3P3SYS, V3P3A), issues
an interrupt and updates VSTAT[1:0]. The MPU software should restore MSN mode operation by issuing
a soft reset to restore system settings to values appropriate for MSN mode.
Figure 29 shows a state diagram of the various operating modes, with the possible transitions between modes.
When the part wakes-up under battery power, the part automatically enters BRN mode (see 3.4 Wake Up
Behavior). From BRN mode, the part may enter either LCD mode or SLP mode, as controlled by the MPU.
RESET
MSN
V3P3SYS
falls
VSTAT=00X
V3P3SYS
rises
System Power
Battery Power
VSTAT=001
V3P3SYS
rises
LCD_ONLY
BRN
V3P3SYS
rises
RESET &
VBAT
sufficient
Wake Flags
SLEEP or
VBAT
insufficient
Wake
event
LCD
Wake
event
VBAT
insufficient
VBAT
insufficient
RESET &
VBAT
insufficient
SLP
Figure 29: Operation Modes State Diagram
Rev 2
81
71M6541D/F/G and 71M6542F/G Data Sheet
Transitions from both LCD and SLP mode to BRN mode can be initiated by the following events:
• Wake-up timer timeout.
• Pushbutton (PB) is activated.
• A rising edge on SEGDIO4, SEGDIO52 (71M6542F/G only) or SEGDIO55.
• Activity on the RX or OPT_RX pins.
The MPU has access to a variety of registers that signal the event that caused the wake up. See 3.4
Wake Up Behavior for details.
Table 67 shows the circuit functions available in each operating mode.
Table 67: Available Circuit Functions
Circuit Function
CE (Computation Engine)
FIR
ADC, VREF
PLL
Battery Measurement
Temperature sensor
Max MPU clock rate
System Power
MSN (Mission Mode)
PLL_FAST=1 PLL_FAST=0
Yes
Yes
Yes
Yes
Yes
Yes
4.92MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.4kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1.57MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.9kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Battery Power
BRN (Brownout Mode)
LCD
PLL_FAST=1 PLL_FAST=0
Note 1
--Yes
Yes
Yes
4.92MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.4kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note 1
--Yes
Yes
Yes
1.57MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.9kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2
SLEEP
---2
Boost
-Yes
-----Yes
--
--
MPU_DIV clk. divider
--ICE
--DIO Pins
--Watchdog Timer
--LCD
Yes
-LCD Boost
Yes
EEPROM Interface (2-wire)
--EEPROM Interface (3-wire)
--UART (full speed)
--Optical TX modulation
--Flash Read
--Flash Page Erase
--Flash Write
--RAM Read and Write
--Wakeup Timer
Yes
Yes
OSC and RTC
Yes
Yes
DRAM data preservation
--NV RAM data preservation
Yes
Yes
Notes:
1. The CE is active in BRN mode, but ADC data is inaccurate. The MPU should halt the CE to conserve power (CE_E = 0,
I/O RAM 0x2106[0]).
2. “--“ indicates that the corresponding circuit is not active
3. “Boost” implies that the LCD boost circuit is active (i.e., LCD_VMODE[1:0] = 10 (I/O RAM 0x2401[7:6]). The LCD boost
circuit requires a clock from the PLL to function. Thus, the PLL is automatically kept active if LCD boost is active while in
LCD mode, otherwise the PLL is de-activated.
82
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
3.2.1
BRN Mode
In BRN mode, most non-metering digital functions are active (as shown in Table 67) including ICE, UART,
EEPROM, LCD and RTC. In BRN mode, the PLL continues to function at the same frequency as MSN
mode. It is up to the MPU to scale down the PLL (using PLL_FAST, I/O RAM 0x2200[4]) or the MPU
frequency (using MPU_DIV[2:0], I/O RAM 0x2200[2:0]) in order to save power.
From BRN mode, the MPU can choose to enter LCD or SLP modes. When system power is restored
while the 71M654x is in BRN mode, the part automatically transitions to MSN mode.
The recommended minimum power configuration for BRN mode is as follows:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
RCE0 = 0x00 (I/O RAM 0x2709[7:0]) - remote sensors disabled
LCD_BAT = 1 (I/O RAM 0x2402[7]) - LCD powered from VBAT
LCD_VMODE[1:0] = 0 (I/O RAM 0x2401[7:6]) - 5V LCD boost disabled
CE6 = 0x00 (I/O RAM 0x2106) - CE, RTM and CHOP are disabled
MUX_DIV[3:0] = 0 (I/O RAM 0x2100[7:4]) - the ADC multiplexer is disabled
ADC_E = 0 (I/O RAM 0x2704[4]) - ADC disabled
VREF_CAL = 0 (I/O RAM 0x2704[7]) – Vref not driven out
VREF_DIS = 1 (I/O RAM 0x2704[6]) - Vref disabled
PRE_E = 0 (I/O RAM 0x2704[5] - pre-amp disabled
BCURR = 0 (I/O RAM 0x2704[3]) - battery 100µA current load OFF
TMUX[5:0] = 0x0E (I/O RAM 0x2502[5:0]) – TMUXOUT output set to a dc value
TMUX2[4:0] = 0x0E (I/O RAM 0x2503[4:0]) – TMUXOUT2 output set to a dc value
CKGN = 0x24 (I/O RAM 0x2200) - PLL set slow, MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) set to maximum
TEMP_PER[2:0] = 6 (I/O RAM 0x28A0[2:0]) - temp measurement set to automatic every 512 s
TEMP_BSEL = 1 (I/O RAM 0x28A0[7]) - temperature sensor monitors VBAT
PCON = 1 (SFR 0x87) - at the end of the main BRN loop, halt the MPU and wait for an interrupt
The baud rate registers are adjusted as desired
All unused interrupts are disabled
3.2.2
LCD Mode
LCD mode may be commanded by the MPU at any time by setting the LCD_ONLY control bit (I/O RAM
0x28B2[6]). However, it is recommended that the LCD_ONLY control bit be set by the MPU only after the
71M654x has entered BRN mode. For example, if the 71M654x is in MSN mode when LCD_ONLY is set,
the duration of LCD mode is very brief and the 71M654x immediately 'wakes'.
In LCD mode, V3P3D is disabled, thus removing all current leakage from the VBAT pin. Before asserting
LCD_ONLY mode, it is recommended that the MPU minimize PLL current by reducing the output
frequency of the PLL to 6.2 MHz (i.e., write PLL_FAST = 0, I/O RAM 0x2200[4]). The LCD boost system
requires a clock from the PLL for its operation. Thus, if the LCD boost system is enabled (i.e.,
LCD_VMODE[1:0] = 10, I/O RAM 0x2401[7:6]), then the PLL is automatically kept active during LCD
mode, otherwise the PLL is de-activated.
In LCD mode, the data contained in the LCD_SEG registers is displayed using the segment driver pins.
Up to two LCD segments connected to the pins SEGDIO22 and SEGDIO23 can be made to blink without
the involvement of the MPU, which is disabled in LCD mode. To minimize battery power consumption,
only segments that are used should be enabled.
After the transition from LCD mode to MSN or BRN mode, the PC (Program Counter) is at 0x0000, the
XRAM is in an undefined state, and configuration I/O RAM bits are reset (see Table 76 for I/O RAM state
upon wake). The data stored in non-volatile I/O RAM locations is preserved in LCD mode (the shaded
locations in Table 76 are non-volatile).
Rev 2
83
71M6541D/F/G and 71M6542F/G Data Sheet
3.2.3
SLP Mode
When the V3P3SYS pin voltage drops below 2.8 VDC, the 71M654x enters BRN mode and the V3P3D
pin obtains power from the VBAT pin instead of the V3P3SYS pin. Once in BRN mode, the MPU may
invoke SLP mode by setting the SLEEP bit (I/O RAM 0x28B2[7]). The purpose of SLP mode is to
consume the least amount power while still maintaining the RTC (Real Time Clock), temperature
compensation of the RTC, and the non-volatile portions of the I/O RAM.
In SLP mode, the V3P3D pin is disconnected, removing all sources of current leakage from the VBAT pin.
The non-volatile I/O RAM locations and the SLP mode functions, such as the temperature sensor,
oscillator, RTC, and the RTC temperature compensation are powered by the VBAT_RTC pin. SLP mode
can be exited only by a system power-up event or one of the wake methods described in 3.4 Wake Up
Behavior.
If the SLEEP bit is asserted when V3P3SYS pin power is present (i.e., while in MSN mode), the 71M654x
enters SLP mode, resetting the internal WAKE signal, at which point the 71M654x begins the standard
wake from sleep procedures as described in 3.4 Wake Up Behavior.
When power is restored to the V3P3SYS pin, the 71M654x transitions from SLP mode to MSN mode and
the MPU PC (Program Counter) is initialized to 0x0000. At this point, the XRAM is in an undefined state,
but non-volatile I/O RAM locations are preserved (the shaded locations in Table 76 are non-volatile).
84
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
3.3
Fault and Reset Behavior
3.3.1
Events at Power-Down
Power fault detection is performed by internal comparators that monitor the voltage at the V3P3A pin and
also monitor the internally generated VDD pin voltage (2.5 VDC). The V3P3SYS and V3P3A pins must be
tied together at the PCB level, so that the comparators, which are internally connected only to the V3P3A
pin, are able to simultaneously monitor the common V3P3SYS and V3P3A pin voltage. The following
discussion assumes that the V3P3A and V3P3SYS pins are tied together at the PCB level.
During a power failure, as V3P3A falls, two thresholds are detected:
•
•
The first threshold, at 3.0 VDC (VSTAT[2:0] = 001), warns the MPU that the analog modules are no
longer accurate. Other than warning the MPU, the hardware takes no action when this threshold is
crossed.
The second threshold, at 2.8 VDC, causes the 71M654x to switch to battery power. This switching
happens while the FLASH and RAM systems are still able to read and write.
The power quality is reflected by the SFR VSTAT[2:0] field, as shown in Table 68. The VSTAT[2:0] field is
located at SFR address 0xF9 and occupies bits [2:0], and it is read-only.
In addition to the state of the main power, the VSTAT[2:0] register provides information about the internal
VDD voltage under battery power. Note that if system power (V3P3A) is above 2.8 VDC, the
71M6541D/F/G and 71M6542F/G always switch from battery to system power.
Table 68: VSTAT[2:0] (SFR 0xF9[2:0])
VSTAT[2:0]
000
001
010
011
101
Description
System Power OK. V3P3A > 3.0 VDC. Analog modules are functional and accurate.
System Power is low. 2.8 VDC < V3P3A < 3.0 VDC. Analog modules not accurate.
Switch over to battery power is imminent.
The IC is on battery power and VDD is OK. VDD > 2.25 VDC. The IC has full digital
functionality.
The IC is on battery power and 2.25 VDC > VDD > 2.0 VDC. Flash write operations are
inhibited.
The IC is on battery power and VDD < 2.0, which means that the MPU is nearly out of
voltage. A reset occurs in 4 cycles of the crystal clock CK32.
The response to a system power fault is almost entirely controlled by firmware. During a power failure,
system power slowly falls. This is monitored by internal comparators that cause the hardware to
automatically switch over to taking power from the VBAT input. An interrupt notifies the MPU that the part
is now battery powered. At this point, it is the MPU’s responsibility to reduce power by slowing the clock
rate, disabling the PLL, etc.
Precision analog components such as the bandgap reference, the bandgap buffer, and the ADC are
powered only by the V3P3A pin and become inaccurate and ultimately unavailable as the V3P3A pin
voltage continues to drop (i.e., circuits powered by the V3P3A pin are not backed by the VBAT pin).
When the V3P3A pin falls below 2.8 VDC, the ADC clocks are halted and the amplifiers are unbiased.
Meanwhile, control bits such as ADC_E bit (I/O RAM 0x2704[4]) are not affected, since their I/O RAM
storage is powered from the VDD pin (2.5 VDC). The VDD pin is supplied with power through an internal
2.5 VDC regulator that is connected to the V3P3D pin. In turn, the V3P3D pin is switched to receive
power from the VBAT pin when the V3P3SYS pin drops below 3.0 VDC. Note that the V3P3SYS and
V3P3A pins are typically tied together at the PCB level.
Rev 2
85
71M6541D/F/G and 71M6542F/G Data Sheet
3.3.2
IC Behavior at Low Battery Voltage
When system power is not present, the 71M6541D/F/G and 71M6542F/G rely on the VBAT pin for power.
If the VBAT voltage is not sufficient to maintain VDD at 2.0 VDC or greater, the MPU cannot operate
reliably. Low VBAT voltage can occur while the part is operating in BRN mode, or while it is dormant in
SLP or LCD mode. Two cases can be distinguished, depending on MPU code:
•
•
Case 1: System power is not present, and the part is waking from SLP or LCD mode. In this case,
the hardware checks the value of VDD to determine if processor operation is possible. If it is not
possible, the part configures itself for BRN operation, and holds the processor in reset (WAKE=0). In
this mode, VBAT powers the 1.0 VDC reference for the LCD system, the VDD regulator, the PLL, and
the fault comparator. The part remains in this waiting mode until VDD becomes high due to system
power being applied or the VBAT battery being replaced or recharged.
Case 2: The part is operating under VBAT power and VSTAT[2:0] (SFR 0xF9[2:0]) becomes 101,
indicating that VDD falls below 2.0 VDC. In this case, the firmware has two choices:
1) One choice is to assert the SLEEP bit (I/O RAM 0x28B2[7]) immediately. This assertion
preserves the remaining charge in VBAT. Of course, if the battery voltage is not increased, the
71M654x enters Case 1 as soon as it tries to wake up.
2) The alternative choice is to enter the waiting mode described in Case 1 immediately. Specifically, if the
firmware does not assert the SLEEP bit, the hardware resets the processor four CE32 clock cycles (i.e.,
122 µs) after VSTAT[2:0] becomes 101 and, as described in Case 1, it begins waiting for VDD to
become greater than 2.0 VDC. The MPU wakes up when system power returns, or when VDD
becomes greater than 2.0 VDC.
In either case, when VDD recovers, and when the MPU wakes up, the WF_BADVDD flag (I/O RAM 0x28B0[2])
can be read to determine that the processor is recovering from a bad VBAT condition. The WF_BADVDD
flag remains set until the next time WAKE falls. This flag is independent of the other WF flags.
In all cases, low VBAT voltage does not corrupt RTC operation, the state of NV memory, or the state of
non-volatile memory. These circuits depend on the VBAT_RTC pin for power.
3.3.3
Reset Sequence
When the RESET pin is pulled high, all digital activity in the chip stops, with the exception of the oscillator
and RTC. Additionally, all I/O RAM bits are forced to their RST state. Reliable reset does not occur until
RESET has been high at least for 2 µs. Note that TMUX and the RTC do not reset unless the TEST pin
is pulled high while RESET is high.
The RESET control bit (I/O RAM 0x 2200[3]) performs an identical reset to the RESET pin except that a
significantly shorter reset timer is used.
Once initiated, the reset sequence waits until the reset timer times out. The time-out occurs in 4100
CE32 cycles (125 ms), at which time the MPU begins executing its pre-boot and boot sequences from
address 0x0000. See 2.5.1.1 Hardware Watchdog Timer for a detailed description of the pre-boot and
boot sequences.
If system power is not present, the reset timer duration is two CE32 cycles, at which time the MPU begins
executing in BRN mode, starting at address 0x0000.
A softer form of reset is initiated when the E_RST pin of the ICE interface is pulled low. This event
causes the MPU and other registers in the MPU core to be reset but does not reset the remainder of the
IC, for example the I/O RAM. It does not trigger the reset sequence. This type of reset is intended to reset
the MPU program, but not to make other changes to the chip’s state.
3.3.4
Watchdog Timer Reset
The watchdog timer (WDT) is described in 2.5.11 Hardware Watchdog Timer.
A status bit, WF_OVF (I/O RAM 0x28B0[4]), is set when a WDT overflow occurs. Similar to the other wake
flags, this bit is powered by the non-volatile supply and can be read by the MPU to determine if the part is
initializing after a WD overflow event or after a power up. The WF_OVF bit is cleared by the RESET pin.
86
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
There is no internal digital state that could deactivate the WDT. For debug purposes, however, the WDT
can be disabled by raising the ICE_E pin to 3.3 VDC.
In normal operation, the WDT is reset by periodically writing a one to the WD_RST control bit (I/O RAM
0x28B4[7]). The watchdog timer is also reset when the 71M654x wakes from LCD or SLP mode, and
when ICE_E = 1.
3.4
Wake Up Behavior
As described above, the part always wakes-up in MSN mode when system power is restored. As
described in 3.2 Battery Modes, transitions from both LCD and SLP mode to BRN mode can be initiated
by a wake-up timer timeout, when the pushbutton (PB) input is high, a high level on SEGDIO4,
SEGDIO52 or SEGDIO55, or by activity on the RX or OPT_RX pins.
3.4.1
Wake on Hardware Events
The following pin signal events wake the 71M654x from SLP or LCD mode: a high level on the PB pin, either
edge on the RX pin, a rising edge on the SEGDIO4 pin, a high level on the SEGDIO52 pin (71M6542F/G
only), or a high level on the SEGDIO55 pin or either edge on the OPT_RX pin. See Table 69 for de-bounce
details on each pin and for further details on the OPT_RX/SEGDIO55 pin. The SEGDIO4, SEGDIO52
(71M6542F/G only), and SEGDIO55 pins must be configured as DIO inputs and their wake enable (EW_x
bits) must be set. In SLP and LCD modes, the MPU is held in reset and cannot poll pins or react to
interrupts. When one of the hardware wake events occurs, the internal WAKE signal rises and within
three CK32 cycles the MPU begins to execute. The MPU can determine which one of the pins
awakened it by checking the WF_PB, WF_RX, WF_SEGDIO4, WF_DIO52 (71M6542F/G only), or
WF_DIO55 flags (see Table 69).
If the part is in SLP or LCD mode, it can be awakened by a high level on the PB pin. This pin is normally
pulled to GND and can be connected externally so it may be pulled high by a push button depression.
Some pins are de-bounced to reject EMI noise. Detection hardware ignores all transitions after the initial
transition. Table 69 shows which pins are equipped with de-bounce circuitry.
Pins that do not have de-bounce circuits must still be high for at least 2 µs to be recognized.
The wake enable and flag bits are also shown in Table 69. The wake flag bits are set by hardware when
the MPU wakes from a wake event. Note that the PB flag is set whenever the PB is pushed, even if the
part is already awake.
Table 71 lists the events that clear the WF flags.
In addition to push buttons and timers, the part can also reboot due to the RESET pin, the RESET bit (I/O
RAM 0x2200[3]), the WDT, the cold start detector, and E_RST. As seen in Table 69, each of these
mechanisms has a flag bit to alert the MPU to the source of the wakeup. If the wake-up is caused by
return of system power, there is no active WF flag and the VSTAT[2:0] field (SFR 0xF9[2:0]) indicate that
system power is stable.
Table 69: Wake Enables and Flag Bits
Wake Enable
Wake Flag
De-bounce Description
Name
Location
Name
Location
WAKE_ARM
28B2[5]
WF_TMR
28B1[5]
No
Wake on Timer.
EW_PB
28B3[3]
WF_PB
28B1[3]
Yes
Wake on PB*.
EW_RX
28B3[4]
WF_RX
28B1[4]
2 µs
Wake on either edge of RX.
EW_DIO4
28B3[2]
WF_DIO4
28B1[2]
2 µs
Wake on SEGDIO4.
EW_DIO52†
28B3[1]
WF_DIO52
28B1[1]
Yes
Wake on SEGDIO52*.
EW_DIO55
28B3[0]
WF_DIO55
28B1[0]
Yes
OPT_RXDIS = 1: Wake on DIO55*
with 64 ms de-bounce.
OPT_RXDIS = 0: Wake on either
Rev 2
87
71M6541D/F/G and 71M6542F/G Data Sheet
Wake Enable
Name
Location
Wake Flag
Name
Location
De-bounce Description
Always Enabled
Always Enabled
WF_RST
WF_RSTBIT
28B0[6]
28B0[5]
2 µs
No
Always Enabled
WF_ERST
28B0[3]
2 µs
Always Enabled
WF_OVF
28B0[4]
No
Always Enabled
WF_CSTART
28B0[7]
No
Always Enabled
WF_BADVDD
28B0[2]
No
edge of OPT_RX with 2 µs debounce.
OPT_RXDIS: I/O RAM 0x2457[2]
Wake after RESET.
Wake after RESET bit.
Wake after E_RST.
(ICE must be enabled)
Wake after WD reset.
Wake after cold start - the first
application of power.
Wake after insufficient VBAT
voltage.
† 71M6542F/G only.
*This pin is sampled every 2 ms and must remain high for 64 ms to be declared a valid high level. This
pin is high-level sensitive.
88
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 70: Wake Bits
Name
Location
RST
WK
Dir
EW_DIO4
28B3[2]
0
–
R/W
EW_DIO52
28B3[1]
0
–
R/W
EW_DIO55
28B3[0]
0
–
R/W
WAKE_ARM
28B2[5]
0
–
R/W
EW_PB
28B3[3]
0
–
R/W
EW_RX
28B3[4]
0
–
R/W
WF_DIO4
28B1[2]
0
–
R
WF_DIO52
28B1[1]
0
–
R
WF_DIO55
28B1[0]
0
–
R
WF_TMR
WF_PB
WF_RX
WF_RST
WF_RSTBIT
WF_ERST
WF_CSTART
WF_BADVDD
28B1[5]
28B1[3]
28B1[4]
28B0[6]
28B0[5]
28B0[3]
28B0[7]
28B0[2]
0
0
0
*
*
*
*
*
–
–
–
R
R
R
Rev 2
–
R
Description
Connects SEGDIO4 to the WAKE logic and permits
SEGDIO4 rising to wake the part. This bit has no effect
unless SEGDIO4 is configured as a digital input.
Connects DIO52 to the WAKE logic and permits DIO52
high-level to wake the part (71M6542F/G only). This bit
has no effect unless DIO52 is configured as a digital
input.
Connects DIO55 to the WAKE logic and permits DIO55
high-level to wake the part. This bit has no effect unless
DIO55 is configured as a digital input.
Arms the WAKE timer and loads it with the value in the
WAKE_TMR register (I/O RAM 0x2880). When SLP
mode or LCD mode is asserted by the MPU, the WAKE
timer becomes active.
Connects the PB pin to the WAKE logic and permits PB
high-level to wake the part. PB is always configured as
an input.
Connects the RX pin to the WAKE logic and permits RX
rising to wake the part. See 3.4.1 for de-bounce issues.
SEGDIO4 flag bit. If SEGDIO4 is configured to wake
the part, this bit is set whenever SEGDIO4 rises. It is
held in reset if SEGDIO4 is not configured for wakeup.
SEGDIO52 flag bit. If SEGDIO52 is configured to wake
the part, this bit is set whenever SEGDIO52 is a high
level. It is held in reset if SEGDIO52 is not configured
for wakeup (71M6542F/G only).
SEGDIO55 flag bit. If SEGDIO55 is configured to wake
the part, this bit is set whenever SEGDIO55 is a high
level. It is held in reset if SEGDIO55 is not configured
for wakeup.
Indicates that the Wake timer caused the part to wake up.
Indicates that the PB pin caused the part to wake.
Indicates that RX pin caused the part to wake.
Indicates that the RST pin, E_RST pin, RESET bit (I/O
RAM 0x2200[3]), the cold start detector, or low voltage
on the VBAT pin caused the part to reset.
*See Table 71 for details.
89
71M6541D/F/G and 71M6542F/G Data Sheet
Table 71: Clear Events for WAKE flags
Flag
Wake on:
Clear Events
WF_TMR
Timer expiration
WAKE falls
WF_PB
PB pin high level
WAKE falls
WF_RX
Either edge RX pin
WAKE falls
WF_DIO4
SEGDIO4 rising edge
WAKE falls
WF_DIO52
SEGDIO52 high level (71M6542F/G only)
If OPT_RXDIS = 1 (I/O RAM 0x2457[2]),
wake on SEGDIO55 high
If OPT_RXDIS = 0
wake on either edge of OPT_RX
WAKE falls
WF_DIO55
WF_RST
WF_RSTBIT
WF_ERST
WF_OVF
WF_CSTART
WAKE falls
RESET pin driven high
WAKE falls, WF_CSTART, WF_RSTBIT,
WF_OVF, WF_BADVDD
RESET bit is set (I/O RAM 0x2200[3])
WAKE falls, WF_CSTART, WF_OVF,
WF_BADVDD, WF_RST
E_RST pin driven high and the ICE
interface must be enabled by driving the
ICE_E pin high.
Watchdog (WD) reset
Coldstart (i.e., after the application of first
power)
WAKE falls, WF_CSTART, WF_RST,
WF_OVF, WF_RSTBIT
WAKE falls, WF_CSTART, WF_RSTBIT,
WF_BADVDD, WF_RST
WAKE falls, WF_RSTBIT, WF_OVF,
WF_BADVDD, WF_RST
Note:
“WAKE falls” implies that the internal WAKE signal has been reset, which happens automatically upon
entry into LCD mode or SLEEP mode (i.e., when the MPU sets the LCD_ONLY bit (I/O RAM 0x28B2[6]) or
the SLEEP (I/O RAM 0x28B2[7]) bit). When the internal WAKE signal resets, all wake flags are reset.
Since the various wake flags are automatically reset when WAKE falls, it is not necessary for the MPU to
reset these flags before entering LCD mode or SLEEP mode. Also, other wake events can cause the
wake flag to reset, as indicated above (e.g., the WF_RST flag can also be reset by any of the following
flags setting: WF_CSTART, WS_RSTBIT, WF_OVF, WF_BADVDD)
3.4.2
Wake on Timer
If the part is in SLP or LCD mode, it can be awakened by the Wake Timer. Until this timer times out, the
MPU is in reset due to the internal WAKE signal being low. When the Wake Timer times out, WAKE rises
and within three CK32 cycles, the MPU begins to execute. The MPU can determine that the timer woke it
by checking the WF_TMR wake flag (I/O RAM 0x28B1[2]).
The Wake Timer begins timing when the part enters LCD or SLP mode. Its duration is controlled by the
value in the WAKE_TMR[7:0] register (I/O RAM 0x2880). The timer duration is WAKE_TMR +1 seconds.
The Wake Timer is armed by setting WAKE_ARM = 1 (I/O RAM 0x28B2[5]). It must be armed at least
three RTC cycles before either SLP or LCD modes are initiated. Setting WAKE_ARM presets the timer
with the value in WAKE_TMR and readies the timer to start when the MPU writes to the SLEEP (I/O RAM
0x28B2[7]) or LCD_ONLY (I/O RAM 0x28B2[6]) bits. The timer is neither reset nor disarmed when the
MPU wakes-up. Thus, once armed and set, the MPU continues to be awakened WAKE_TMR[7:0]
seconds after it requests SLP mode or LCD mode (i.e., once written, the WAKE_TMR[7:0] register holds
its value and does not have to be re-written each time the MPU enters SLP or LCD mode. Also, since
WAKE_TMR[7:0] is non-volatile, it also holds its value through resets and power failures).
90
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
3.5
Data Flow and MPU/CE Communication
The data flow between the Compute Engine (CE) and the MPU is shown in Figure 30. In a typical
application, the 32-bit CE sequentially processes the samples from the voltage inputs on pins IA, VA,
2
2
IB, etc., performing calculations to measure active power (Wh), reactive power (VARh), A h, and V h
for four-quadrant metering. These measurements are then accessed by the MPU, processed further and
output using the peripheral devices available to the MPU.
Both the CE and multiplexer are controlled by the MPU via shared registers in the I/O RAM and in RAM.
The CE outputs a total of six discrete signals to the MPU. These consist of four pulses and two interrupts:
•
•
•
•
CE_BUSY
XFER_BUSY
WPULSE, VPULSE (pulses for active and reactive energy)
XPULSE, YPULSE (auxiliary pulses)
These interrupts are connected to the MPU interrupt service inputs as external interrupts. CE_BUSY
indicates that the CE is actively processing data. This signal occurs once every multiplexer cycle (typically
396 µs), and indicates that the CE has updated status information in its CESTATUS register (CE RAM 0x80).
XFER_BUSY indicates that the CE is updating data to the output region of the RAM. This indication
occurs whenever the CE has finished generating a sum by completing an accumulation interval
determined by SUM_SAMPS[12:0], I/O RAM 0x2107[4:0], 2108[7:0], (typically every 1000 ms). Interrupts to
the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals.
WPULSE and VPULSE are typically used to signal energy accumulation of real (Wh) and reactive (VARh)
energy. Tying WPULSE and VPULSE into the MPU interrupt system can support pulse counting.
XPULSE and YPULSE can be used to signal events such as sags and zero crossings of the mains voltage
to the MPU. Tying these outputs into the MPU interrupt system relieves the MPU from having to read the
CESTATUS register at every occurrence of the CE_BUSY interrupt in order to detect sag or zero crossing
events.
Pulses
XPULSE
YPULSE
Interrupts
VPULSE
WPULSE
CE_BUSY
XFER_BUSY
CE
Samples
Processed
Metering
Data
CESTATUS
CECONFIG
MUX
Control
MPU
Control
Control
XRAM
I/O RAM (Configuration RAM)
Figure 30: MPU/CE Data Flow
Refer to 5.3 CE Interface Description for additional information on setting up the device using the MPU
firmware.
Rev 2
91
71M6541D/F/G and 71M6542F/G Data Sheet
4
Application Information
4.1
Connecting 5 V Devices
All digital input pins of the 71M654x are compatible with external 5 V devices. I/O pins configured as
inputs do not require current-limiting resistors when they are connected to external 5 V devices.
4.2
Direct Connection of Sensors
Figure 31 through Figure 34 show voltage-sensing resistive dividers, current-sensing current transformers
(CTs) and current-sensing resistive shunts and how they are connected to the voltage and current inputs
of the 71M654x. All input signals to the 71M654x sensor inputs are voltage signals providing a scaled
representation of either a sensed voltage or current.
The analog input pins of the 71M654x are designed for sensors with low source impedance.
RC filters with resistance values higher than those implemented in the Teridian Demo Boards
must not be used. Please refer to the Demo Board schematics for complete sensor input
circuits and corresponding component values.
RIN
VA
VIN
ROUT
V3P3A
Figure 31: Resistive Voltage Divider (Voltage Sensing)
IIN
IOUT
IAP
CT
RBURDEN
VOUT
V3P3A
Noise Filter
1:N
Figure 32. CT with Single-Ended Input Connection (Current Sensing)
IIN
IOUT
IAP
V3P3A
CT
RBURDEN
VOUT
IAN
Bias Network and Noise Filter
1:N
Figure 33: CT with Differential Input Connection (Current Sensing)
IIN
IAP
V3P3A
RSHUNT
VOUT
IAN
Bias Network and Noise Filter
Figure 34: Differential Resistive Shunt Connections (Current Sensing)
92
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
4.3
71M6541D/F/G Using Local Sensors
Figure 35 shows a 71M6541D/F/G configuration using locally connected current sensors. The IAP-IAN
current channel may be directly connected to either a shunt resistor or a CT, while the IBP-IBN channel is
connected to a CT and is therefore isolated. This configuration implements a single-phase measurement
with tamper-detection using one current sensor to measure the neutral current. This configuration can
also be used to create a split phase meter (e.g., ANSI Form 2S). For best performance, both the IAP-IAN
and IBP-IBN current sensor inputs are configured for differential mode (i.e., DIFFA_E = 1 and DIFFB_E =
1, I/O RAM 0x210C[4] and 0x210C[5]). The IBP-IBN input must be configured as an analog differential
input disabling the remote sensor interface (i.e., RMT_E = 0, I/O RAM 0x2709[3]). See Figure 2 for the AFE
configuration corresponding to Figure 35.
NEUTRAL
CT
CT or
LOAD
Shunt
LINE
NEUTRAL
Note:
This system is referenced to LINE
POWER SUPPLY
Resistor Divider
LINE
MUX and ADC
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
LINE
IAP
IAN
TERIDIAN
WAKE-UP
71M6541D/F
REGULATOR
BATTERY
VBAT
VA
VBAT_RTC
IBP
IBN
TEMPERATURE
SENSOR
VREF
SERIAL PORTS
AMR
IR
TX
COMPUTE
ENGINE
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
HOST
RAM
FLASH
MEMORY
MPU
RTC
TIMERS
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
SPI INTERFACE
ICE
XOUT
11/5/2010
Figure 35. 71M6541D/F/G with Local Sensors
Rev 2
93
71M6541D/F/G and 71M6542F/G Data Sheet
4.4
71M6541D/F/G Using 71M6x01and Current Shunts
Figure 36 shows a typical connection for one isolated and one non-isolated shunt sensor, using the
71M6x01 Isolated Sensor Interface. This configuration implements a single-phase measurement with
tamper-detection using the second current sensor. This configuration can also be used to create a split
phase meter (e.g., ANSI Form 2S). For best performance, the IAP-IAN current sensor input is configured
for differential mode (i.e., DIFFA_E = 1, I/O RAM 0x210C[4]). The outputs of the 71M6x01 Isolated Sensor
Interface are routed through a pulse transformer, which is connected to the pins IBP-IBN. The IBP-IBN
pins must be configured for remote sensor communication (i.e., RMT_E =1, I/O RAM 0x2709[3]). See
Figure 3 for the AFE configuration corresponding to Figure 36.
NEUTRAL
Shunt
LOAD
Note:
This system is referenced to LINE
Shunt
LINE
NEUTRAL
POWER SUPPLY
LINE
Resistor Divider
LINE
TERIDIAN
71M6xx1
MUX and ADC
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
IAP
IAN
Pulse
Transformer
TERIDIAN
WAKE-UP
71M6541D/F
REGULATOR
BATTERY
VBAT
VA
VBAT_RTC
IBP
IBN
TEMPERATURE
SENSOR
VREF
SERIAL PORTS
AMR
IR
TX
COMPUTE
ENGINE
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
HOST
RAM
FLASH
MEMORY
MPU
RTC
TIMERS
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
SPI INTERFACE
ICE
XOUT
11/5/2010
Figure 36: 71M6541D/F/G with 71M6x01 isolated Sensor
94
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
4.5
71M6542F/G Using Local Sensors
Figure 38 shows a 71M6542F/G configuration using locally connected current sensors. The IAP-IAN
current channel may be directly connected to either a shunt resistor or a CT, while the IBP-IBN channel is
connected to a CT and is therefore isolated. This configuration implements a dual-phase measurement
utilizing Equation 2. For best performance, both the IAP-IAN and IBP-IBN current sensor inputs are
configured for differential mode (i.e., DIFFA_E = 1 and DIFFB_E = 1, I/O RAM 0x210C[4] and 0x210C[5]).
The IBP-IBN input must be configured as an analog differential input disabling the remote sensor
interface (i.e., RMT_E = 0, I/O RAM 0x2709[3]). See Figure 4 for the AFE configuration corresponding to
Figure 38.
CT or
Shunt
PHASE A
LOAD
NEUTRAL
Shunt
Note:
This system is referenced to PHASE A
LOAD
PHASE B
NEUTRAL
POWER SUPPLY
Resistor Dividers
PHASE A
MUX and ADC
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
IAP
IAN
PHASE A
TERIDIAN
71M6542F
WAKE-UP
REGULATOR
VB
VA
VBAT
VBAT_RTC
IBP
IBN
TEMPERATURE
SENSOR
VREF
SERIAL PORTS
AMR
IR
TX
RAM
COMPUTE
ENGINE
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
HOST
BATTERY
FLASH
MEMORY
MPU
RTC
TIMERS
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
SPI INTERFACE
ICE
XOUT
11/5/2010
Figure 37: 71M6542F/G with Local Sensors
Rev 2
95
71M6541D/F/G and 71M6542F/G Data Sheet
4.6
71M6542F/G Using 71M6x01 and Current Shunts
Figure 38 shows a typical two-phase connection for the 71M6542F/G using one isolated and one nonisolated sensor. For best performance, the IAP-IAN current sensor input is configured for differential mode
(i.e., DIFFA_E = 1, I/O RAM 0x210C[4]). The 71M6x01 Isolated Sensor Interface is used to isolate phase B.
The outputs of the 71M6x01 Isolated Sensor Interface are routed through a pulse transformer, which is
connected to the pins IBP-IBN. The IBP-IBN pins must be configured for remote sensor communication
(i.e., RMT_E =1, I/O RAM 0x2709[3]). See Figure 5 for the AFE configuration corresponding to Figure 38.
Shunt
PHASE A
LOAD
NEUTRAL
Shunt
Note:
This system is referenced to PHASE A
LOAD
PHASE B
NEUTRAL
POWER SUPPLY
PHASE A
Resistor Dividers
PHASE A
TERIDIAN
71M6XX1
MUX and ADC
Pulse
Transformer
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
IAP
IAN
TERIDIAN
71M6542F
VB
VA
VBAT_RTC
TEMPERATURE
SENSOR
VREF
SERIAL PORTS
IR
TX
RAM
COMPUTE
ENGINE
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
HOST
REGULATOR
BATTERY
VBAT
IBP
IBN
AMR
WAKE-UP
FLASH
MEMORY
MPU
RTC
TIMERS
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
SPI INTERFACE
ICE
XOUT
Figure 38: 71M6542F/G with 71M6x01 Isolated Sensor
96
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
4.7
Metrology Temperature Compensation
4.7.1
Voltage Reference Precision
Since the VREF band-gap amplifier is chopper-stabilized, as set by the CHOP_E[1:0] (I/O RAM 0x2106[3:2])
control field, the dc offset voltage, which is the most significant long-term drift mechanism in the voltage
references (VREF), is automatically removed by the chopper circuit. Both the 71M654x and the 71M6x01
feature chopper circuits for their respective VREF voltage reference.
Teridian implements a trimming procedure of the VREF voltage reference during the device
manufacturing process.
The reference voltage (VREF) is trimmed to a target value of 1.195V. During this trimming process, the
TRIMT[7:0] (I/O RAM 0x2309) value is stored in non-volatile fuses. TRIMT[7:0] is trimmed to a value that
results in minimum VREF variation with temperature.
For the 71M654x device (±0.5% energy accuracy), the TRIMT[7:0] value can be read by the MPU
during initialization in order to calculate parabolic temperature compensation coefficients suitable for
each individual 71M654x device. The resulting temperature coefficient for VREF in the 71M654x is ±40
ppm/°C.
Considering the factory calibration temperature of VREF to be +22°C and the industrial temperature
range (-40°C to +85°C), the VREF error at the temperature extremes for the 71M654x device can be
calculated as:
(85o C − 22 o C ) ⋅ 40 ppm / oC = +2520 ppm = +0.252%
and
(−40 o C − 22 o C ) ⋅ 40 ppm / oC = −2480 ppm = −0.248%
The above calculation implies that both the voltage and the current measurements are individually
subject to a theoretical maximum error of approximately ±0.25%. When the voltage sample and current
sample are multiplied together to obtain the energy per sample, the voltage error and current error
combine resulting in approximately ±0.5% maximum energy measurement error. However, this
theoretical ±0.5% error considers only the voltage reference (VREF) as an error source. In practice,
other error sources exist in the system. The principal remaining error sources are the current sensors
(shunts or CTs) and their corresponding signal conditioning circuits, and the resistor voltage divider
used to measure the voltage. The 71M654x 0.5% grade devices should be used in Class 1% designs,
allowing sufficient margin for the other error sources in the system.
4.7.2
Temperature Coefficients for the 71M654x
The equations provided below for calculating TC1 and TC2 apply to the 71M654x (0.5% energy accuracy). In
order to obtain TC1 and TC2, the MPU reads TRIMT[7:0] (I/O RAM 0x2309) and uses the TC1 and TC2
equations provided. PPMC and PPMC2 are then calculated from TC1 and TC2, as shown. The resulting
tracking of the reference voltage (VREF) is within ±40 ppm/°C, corresponding to a ±0.5% energy
measurement accuracy. See 4.7.1 Voltage Reference Precision.
TC1 = 275 − 4.95 ⋅ TRIMT [7 : 0]
TC 2 = −0.557 + 2.8 ⋅ 10 −4 ⋅ TRIMT [7 : 0]
PPMC =
PPMC 2 =
2 21
57 ⋅ 1.195
2 29
5 8 ⋅1.195
⋅ TC1 = 22.4632 ⋅ TC1
⋅ TC 2 = 1150.116 ⋅ TC 2
The coefficients multiplying TC1 and TC2 to obtain PPMC and PPMC2 are derived from the 1.195V ADC
voltage reference and scaling performed in the CE, as shown above.
Rev 2
97
71M6541D/F/G and 71M6542F/G Data Sheet
See 4.7.3 and 4.7.4 below for further temperature compensation details.
4.7.3
Temperature Compensation for VREF with Local Sensors
This section discusses metrology temperature compensation for the meter designs where local sensors
are used, as shown in Figure 35 and Figure 37.
In these configurations where all sensors are directly connected to the 71M654x, each sensor channel’s
accuracy is affected by the voltage variation in the 71M654x VREF due to temperature. The VREF in the
71M654x can be compensated digitally using a second-order polynomial function of temperature. The
71M654x features an on-chip temperature sensor for the purpose of temperature compensating its VREF.
There are also error sources external to the 71M654x. The voltage sensor resistor dividers and the shunt
current sensor and/or CT and their corresponding signal conditioning circuits also have a temperature
dependency, which also may require compensation, depending on the required accuracy class. The
compensation for these external error sources may be optionally lumped with the compensation for VREF by
incorporating their compensation into the PPMC and PPMC2 coefficients for each corresponding channel.
The MPU has the responsibility of computing the necessary compensation values required for each sensor
channel based on the sensed temperature. Teridian provides demonstration code that implements the
GAIN_ADJn compensation equation shown below. The resulting GAIN_ADJn values are stored by the
MPU in three CE RAM locations GAIN_ADJ0-GAIN_ADJ2 (CE RAM 0x40-0x42). The demonstration code
thus provides a suitable implementation of temperature compensation, but other methods are possible in
MPU firmware by utilizing the on-chip temperature sensors and the CE RAM GAIN_ADJn storage locations.
The demonstration code maintains three separate sets of PPMC and PPMC2 coefficients and computes
three separate GAIN_ADJn values based on the sensed temperature using the equation below:
GAIN _ ADJ = 16385 +
10 ⋅ TEMP _ X ⋅ PPMC
214
+
100 ⋅ TEMP _ X 2 ⋅ PPMC 2
2 23
Where, TEMP_X is the deviation from nominal or calibration temperature expressed in multiples of
0.1 °C. For example, since the 71M654x calibration (reference) temperature is 22 oC and the measured
temperature is 27 oC, then TEMP_X = (27-22) x 10 = 50 (decimal), which represents a +5 oC deviation
from 22 oC.
Table 73 shows the three GAIN_ADJn equation output values and the voltage or current measurements
for which they compensate.
•
•
•
GAIN_ADJ0 compensates for the VA and VB (71M6542F/G only) voltage measurements in the
71M654x and is used to compensate the VREF in the 71M654x. The designer may optionally add
compensation for the resistive voltage dividers into the PPMC and PPMC2 coefficients for this
channel.
GAIN_ADJ1 provides compensation for the IA current channel and compensates for the 71M654x
VREF. The designer may optionally add compensation for the shunt or CT and its corresponding
signal conditioning circuit into the PPMC and PPMC2 coefficients for this channel.
GAIN_ADJ2 provides compensation for the IB current channel and compensates for the 71M654x VREF.
The designer may optionally add compensation for the CT and its signal conditioning circuit into the
PPMC and PPMC2 coefficients for this channel.
Table 72: GAIN_ADJn Compensation Channels
Gain Adjustment Output
GAIN_ADJ0
GAIN_ADJ1
GAIN_ADJ2
CE RAM Address
0x40
0x41
0x42
71M6541D/F/G
VA
IA
IB
71M6542F/G
VA, VB
IA
IB
In the demonstration code, temperature compensation behavior is determined by the values stored in the
PPMC and PPMC2 coefficients for each of the three channels, which are setup by the MPU demo code at
initialization time from values that are previously stored in EEPROM.
98
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero
for each of the three GAIN_ADJn channels. To enable temperature compensation, the PPMC and PPMC2
coefficients are set with values that match the expected temperature variation of each corresponding
sensor channel.
For VREF compensation, both the linear coefficient PPMC and the quadratic coefficient PPMC2, are
determined as described in 4.7.2 Temperature Coefficients for the 71M654x.
The compensation for the external error sources is accomplished by summing the PPMC value
associated with VREF with the PPMC value associated with the external error source to obtain the final
PPMC value for the sensor channel. Similarly, the PPMC2 value associated with VREF is summed with
the PPMC2 value associated with the external error source.
To determine the contribution of the current shunt sensor or CT to the PPMC and PPMC2 coefficients,
the designer must either know the temperature coefficients of the shunt or the CT from its data sheet or
obtain them by laboratory measurement. The designer must consider component variation across mass
production to ensure that the product will meet its accuracy requirement across production.
4.7.4
Temperature Compensation for VREF with Remote Sensor
This section discusses metrology temperature compensation for the meter designs where current shunt
sensors are used in conjunction with the Teridian 71M6x01 isolated sensors, as shown in Figure 36 and
Figure 38.
Any sensors that are directly connected to the 71M654x are affected by the voltage variation in the
71M654x VREF due to temperature. On the other hand, sensors that are connected to the 71M6x01
isolated sensor, are affected by the VREF in the 71M6x01. The VREF in both the 71M654x and
71M6x01 can be compensated digitally using a second-order polynomial function of temperature. The
71M654x and 71M6x01 feature temperature sensors for the purposes of temperature compensating their
corresponding VREF.
Referring to Figure 36 and Figure 38, the VA voltage sensor is available in both the 71M6541D/F/G and
71M6542F/G and is directly connected to the 71M654x. The VB voltage sensor is available only in the
71M6542F/G and is also directly connected to it. Thus, the precision of these directly connected voltage
sensors is affected by VREF in the 71M654x. The 71M654x also has one shunt current sensor (IA) which is
connected directly to it, and therefore is also affected by the VREF in the 71M654x. The external current
sensor and its corresponding signal conditioning circuit also has a temperature dependency, which
also may require compensation, depending on the required accuracy class. Finally, the second current
sensor (IB) is isolated by the 71M6x01 and depends on the VREF of the 71M6x01, plus the variation of the
corresponding shunt resistance with temperature.
The MPU has the responsibility of computing the necessary compensation values required for each sensor
channel based on the sensed temperature. Teridian provides demonstration code that implements the
GAIN_ADJn compensation equation shown below. The resulting GAIN_ADJn values are stored by the
MPU in three CE RAM locations GAIN_ADJ0-GAIN_ADJ2 (CE RAM 0x40-0x42). The demonstration code
thus provides a suitable implementation of temperature compensation, but other methods are possible in
MPU firmware by utilizing the on-chip temperature sensors and the CE RAM GAIN_ADJn storage locations.
The demonstration code maintains three separate sets of PPMC and PPMC2 coefficients and computes
three separate GAIN_ADJn values based on the sensed temperature using the equation below:
GAIN _ ADJ = 16385 +
10 ⋅ TEMP _ X ⋅ PPMC
214
+
100 ⋅ TEMP _ X 2 ⋅ PPMC 2
2 23
Where, TEMP_X is the deviation from nominal or calibration temperature expressed in multiples of
o
0.1 °C. For example, since the 71M654x calibration (reference) temperature is 22 C and the measured
o
temperature is 27 C, then TEMP_X = (27-22) x 10 = 50 (decimal), which represents a +5 oC deviation
from 22 oC.
Table 73 shows the three GAIN_ADJn equation output values and the voltage or current measurements
for which they compensate.
•
GAIN_ADJ0 compensates for the VA and VB (71M6542F/G only) voltage measurements in the
71M654x and is used to compensate the VREF in the 71M654x. The designer may optionally add
Rev 2
99
71M6541D/F/G and 71M6542F/G Data Sheet
•
•
compensation for the resistive voltage dividers into the PPMC and PPMC2 coefficients for this
channel.
GAIN_ADJ1 provides compensation for the IA current channel and compensates for the 71M654x
VREF. The designer may optionally add compensation for the shunt and its corresponding signal
conditioning circuit into the PPMC and PPMC2 coefficients for this channel.
GAIN_ADJ2 provides compensation for the remotely connected IB shunt current sensor and compensates
for the 71M6x01 VREF. The designer may optionally add compensation for the shunt connected to the
71M6x01 into the PPMC and PPMC2 coefficients for this channel.
Table 73: GAIN_ADJn Compensation Channels
Gain Adjustment Output
GAIN_ADJ0
GAIN_ADJ1
GAIN_ADJ2
CE RAM Address
71M6541D/F/G
71M6542F/G
0x40
0x41
0x42
VA
IA
IB
VA, VB
IA
IB
In the demonstration code, temperature compensation behavior is determined by the values stored in the
PPMC and PPMC2 coefficients, which are setup by the MPU demo code at initialization time from values
that are previously stored in EEPROM.
To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero
for each of the three GAIN_ADJn channels. To enable temperature compensation, the PPMC and PPMC2
coefficients are set with values that match the expected temperature variation of the corresponding
channel.
For VREF compensation, both the linear coefficient PPMC and the quadratic coefficient PPMC2, are
determined for the 71M654x as described in 4.7.2 Temperature Coefficients for the 71M654x. For
information on determining the PPMC and PPMC2 coefficients for the 71M6x01 VREF, refer to the
71M6xxx Data Sheet.
The compensation for the external error sources is accomplished by summing the PPMC value
associated with VREF with the PPMC value associated with the external error source to obtain the final
PPMC value for the sensor channel. Similarly, the PPMC2 value associated with VREF is summed with
the PPMC2 value associated with the external error source.
To determine the contribution of the current shunt sensor to the PPMC and PPMC2 coefficients, the
designer must either know the temperature coefficients of the shunt from its data sheet or obtain it by
laboratory measurement. The designer must consider component variation across mass production to
ensure that the product will meet its accuracy requirement across production.
4.8
Connecting I2C EEPROMs
I2C EEPROMs or other I2C compatible devices should be connected to the DIO pins SEGDIO2 and
SEGDIO3, as shown in Figure 39.
Pull-up resistors of roughly 10 kΩ to V3P3D (to ensure operation in BRN mode) should be used for both
SDCK and SDATA signals. The DIO_EEX[1:0] (I/O RAM 0x2456[7:6]) field in I/O RAM must be set to 01
2
in order to convert the DIO pins SEGDIO2 and SEGDIO3 to I C pins SDCK and SDATA.
100
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
10 kΩ
V3P3D
10 kΩ
EEPROM
SEGDIO2/SDCK
SDCK
SEGDIO3/SDATA
SDATA
71M654x
Figure 39: I2C EEPROM Connection
4.9
Connecting Three-Wire EEPROMs
µWire EEPROMs and other compatible devices should be connected to the DIO pins SEGDIO2/SDCK
and SEGDIO3/SDATA, as described in 2.5.9 EEPROM Interface.
4.10
UART0 (TX/RX)
The UART0 RX pin should be pulled down by a 10 kΩ resistor and additionally protected by a 100 pF
ceramic capacitor, as shown in Figure 40.
71M654x
RX
TX
100 pF 10 k Ω
RX
TX
Figure 40: Connections for UART0
4.11
Optical Interface (UART1)
The OPT_TX and OPT_RX pins can be used for a regular serial interface (by connecting a RS_232
transceiver for example), or they can be used to directly operate optical components (for example, an infrared
diode and phototransistor implementing a FLAG interface). Figure 41 shows the basic connections for
UART1. The OPT_TX pin becomes active when the I/O RAM control field OPT_TXE (I/O RAM 0x2456[3:2])
is set to 00.
The polarity of the OPT_TX and OPT_RX pins can be inverted with the configuration bits, OPT_TXINV
(I/O RAM 0x2456[0]) and OPT_RXINV (I/O RAM 0x2457[1]), respectively.
The OPT_TX output may be modulated at 38 kHz when system power is present. Modulation is not
available in BRN mode. The OPT_TXMOD bit (I/O RAM 0x2456[1]) enables modulation. The duty cycle is
controlled by OPT_FDC[1:0] (I/O RAM 0x2457[5:4]), which can select 50%, 25%, 12.5%, and 6.25% duty
cycle. A 6.25% duty cycle means OPT_TX is low for 6.25% of the period. The OPT_RX pin uses digital
signal thresholds. It may need an analog filter when receiving modulated optical signals.
With modulation, an optical emitter can be operated at higher current than nominal, enabling it to
increase the distance along the optical path.
Rev 2
101
71M6541D/F/G and 71M6542F/G Data Sheet
If operation in BRN mode is desired, the external components should be connected to V3P3D. However,
it is recommended to limit the current to a few mA.
V3P3SYS
R1
71M654x
OPT_RX
100 pF
10 kΩ
Phototransistor
V3P3SYS
R2
LED
OPT_TX
Figure 41: Connection for Optical Components
4.12
Connecting the Reset Pin
Even though a functional meter does not necessarily need a reset switch, it is useful to have a reset
pushbutton for prototyping as shown in Figure 42, left side. The RESET signal may be sourced from
V3P3SYS (functional in MSN mode only), V3P3D (MSN and BRN modes), or VBAT (all modes, if a
battery is present), or from a combination of these sources, depending on the application.
For a production meter, the RESET pin should be protected by the external components shown in
Figure 42, right side. R1 should be in the range of 100Ω and mounted as closely as possible to the IC.
Since the 71M6541D/F/G and 71M6542F/G generate their own power-on reset, a reset button or circuitry, as
shown in Figure 42, is only required for test units and prototypes.
VBAT/
V3P3D
V3P3D
R2
71M654x
71M654x
1k Ω
Reset
Switch
RESET
0.1µF
10kΩ
R1
GNDD
GNDD
Figure 42: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right)
4.13
Connecting the Emulator Port Pins
Even when the emulator is not used, small shunt capacitors to ground (22 pF) should be used for
protection from EMI as illustrated in Figure 43. Production boards should have the ICE_E pin connected
to ground.
102
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
LCD Segments
(optional)
V3P3D
71M654x
ICE_E
62 Ω
E_RST
62 Ω
E_RXT
E_TCLK
62 Ω
22 pF 22 pF 22 pF
Figure 43: External Components for the Emulator Interface
Rev 2
103
71M6541D/F/G and 71M6542F/G Data Sheet
4.14
Flash Programming
4.14.1 Flash Programming via the ICE Port
Operational or test code can be programmed into the flash memory using either an in-circuit emulator or
the Flash Programmer Module (TFP-2) available from Teridian. The flash programming procedure uses
the E_RST, E_RXTX, and E_TCLK pins.
4.14.2 Flash Programming via the SPI Port
It is possible to erase, read and program the flash memory of the via the SPI port. See 2.5.10 SPI Slave
Port for a detailed description.
4.15
MPU Firmware Library
All application-specific MPU functions mentioned in 4 Application Information are featured in the
demonstration C source code supplied by Teridian. The code is available as part of the Demonstration Kit
for the 71M6541D/F/G and 71M6542F/G. The Demonstration Kits come with the preprogrammed with
demo firmware and mounted on a functional sample meter Demo Board. The Demo Boards allow for quick
and efficient evaluation of the IC without having to write firmware or having to supply an in-circuit
emulator (ICE).
4.16
Crystal Oscillator
The oscillator of the 71M6541D/F/G and 71M6542F/G drives a standard 32.768 kHz watch crystal. The
oscillator has been designed specifically to handle these crystals and is compatible with their high
impedance and limited power handling capability. The oscillator power dissipation is very low to
maximize the lifetime of any battery backup device attached to the VBAT_RTC pin.
Board layouts with minimum capacitance from XIN to XOUT require less battery current. Good layouts
have XIN and XOUT shielded from each other and from LCD and digital signals.
Since the oscillator is self-biasing, an external resistor must not be connected across the crystal.
4.17
Meter Calibration
Once the Teridian 71M654x energy meter device has been installed in a meter system, it must be
calibrated. A complete calibration includes the following:
•
•
Establishment of the reference temperature (e.g., typically 22 ⁰C)
Calibration of the metrology section, i.e., calibration for tolerances of the current sensors, voltage
dividers and signal conditioning components as well as of the internal reference voltage (VREF) at
the reference temperature (e.g., typically 22 ⁰C).
•
Calibration of the oscillator frequency using the RTCA_ADJ[7:0] I/O RAM register (I/O RAM 0x2504).
The metrology section can be calibrated using the gain and phase adjustment factors accessible to the
CE. The gain adjustment is used to compensate for tolerances of components used for signal conditioning,
especially the resistive components. Phase adjustment is provided to compensate for phase shifts
introduced by the current sensors or by the effects of reactive power supplies.
Due to the flexibility of the MPU firmware, any calibration method, such as calibration based on energy, or
current and voltage can be implemented. It is also possible to implement segment-wise calibration
(depending on current range).
The 71M6541D/F/G and 71M6542F/G support common industry standard calibration techniques, such
as single-point (energy-only), multi-point (energy, Vrms, Irms), and auto-calibration.
Teridian provides a calibration spreadsheet file to facilitate the calibration process. Contact your Teridian
representative to obtain a copy of the latest calibration spreadsheet file for the 71M654x.
104
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5
Firmware Interface
5.1
I/O RAM Map –Functional Order
In Table 74 and Table 75, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’.
Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits are identified with
an ‘R’, and must always be written with a zero. Writing values other than zero to reserved bits may have undesirable side effects and must be
avoided. Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected
to the VBAT pin.
The I/O RAM locations listed in Table 74 have sequential addresses to facilitate reading by the MPU (e.g., in order to verify their contents). These
I/O RAM locations are usually modified only at boot-up. The addresses shown in Table 74 are an alternative sequential address to the addresses
from Table 75 which are used throughout document. For instance, EQU[2:0] can be accessed at I/O RAM 0x2000[7:5] or at I/O RAM 0x2106[7:5].
Table 74: I/O RAM Map – Functional Order, Basic Configuration
Name
Addr
CE6
CE5
CE4
CE3
CE2
CE1
CE0
RCE0
RTMUX
Reserved
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
TEMP
LCD0
LCD1
LCD2
LCD_MAP6
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
200A
200B
200C
200D
200E
200F
2010
2011
2012
2013
2014
Rev 2
Bit 7
Bit 6
EQU[2:0]
U
Bit 5
Bit 4
U
Bit 3
Bit 2
Bit 1
Bit 0
CHOP_E[1:0]
RTM_E
CE_E
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
U
U
CE_LCTN[5:0]
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
R
R
DIFFB_E
DIFFA_E
RFLY_DIS
FIR_LEN[1:0]
PLS_INV
CHOPR[1:0]
R
R
RMT_E
R
R
R
U
TMUXRB[2:0]
U
TMUXRA[2:0]
U
U
R
U
U
U
U
U
MUX_DIV[3:0]
MUX10_SEL
MUX9_SEL
MUX8_SEL
MUX7_SEL
MUX6_SEL
MUX5_SEL
MUX4_SEL
MUX3_SEL
MUX2_SEL
MUX1_SEL
MUX0_SEL
TEMP_BSEL
TEMP_PWR
OSC_COMP
TEMP_BAT TBYTE_BUSY
TEMP_PER[2:0]
LCD_E
LCD_MODE[2:0]
LCD_ALLCOM
LCD_Y
LCD_CLK[1:0]
LCD_VMODE[1:0]
LCD_BLNKMAP23[5:0]
LCD_BAT
R
LCD_BLNKMAP22[5:0]
LCD_MAP[55:48]
105
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
LCD_MAP[47:40]
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
U
U
U
DIO_R11[2:0]
U
DIO_R9[2:0]
U
DIO_R7[2:0]
U
DIO_R5[2:0]
U
DIO_R3[2:0]
U
U
U
OPT_TXE[1:0]
OPT_FDC[1:0]
U
OPT_RXDIS
U
U
U
U
EX_YPULSE
EX_RTCT
U
EX_RTC1M
EX_VPULSE
EW_RX
EW_PB
EW_DIO4
SFMM[7:0]*
SFMS[7:0]*
LCD_MAP5 2015
LCD_MAP4 2016
LCD_MAP3 2017
LCD_MAP2 2018
LCD_MAP1 2019
LCD_MAP0 201A
U
U
DIO_R5
201B
U
DIO_R4
201C
U
DIO_R3
201D
U
DIO_R2
201E
U
DIO_R1
201F
U
DIO_R0
2020
DIO_EEX[1:0]
DIO0
2021
DIO_PW
DIO_PV
DIO1
2022
DIO_PX
DIO_PY
DIO2
2023
EX_EEX
EX_XPULSE
INT1_E
2024
EX_SPI
EX_WPULSE
INT2_E
2025
WAKE_E
2026
SFMM
2080
SFMS
2081
Notes:
*SFMM and SFMS are accessible only through the SPI slave port. See Invoking SFM (page 77) for details.
†
Bit 1
Bit 0
DIO_RPB[2:0]
DIO_R10[2:0]
DIO_R8[2:0]
DIO_R6[2:0]
DIO_R4[2:0]
DIO_R2[2:0]
OPT_TXMOD
OPT_RXINV
U
EX_RTC1S
OPT_TXINV
OPT_BB
U
EX_XFER
EW_DIO52†
EW_DIO55
71M6542F/G only.
106
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 75 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile bits
have a darker gray background.
Table 75: I/O RAM Map – Functional Order
Name
Addr
CE and ADC
MUX5
2100
MUX4
2101
MUX3
2102
MUX2
2103
MUX1
2104
MUX0
2105
CE6
2106
CE5
2107
CE4
2108
CE3
2109
CE2
210A
CE1
210B
CE0
210C
RTM0
210D
RTM0
210E
RTM1
210F
RTM2
2110
RTM3
2111
CLOCK GENERATION
CKGN
2200
LCD/DIO
VREF TRIM FUSES
TRIMT
2309
LCD/DIO
LCD0
2400
LCD1
2401
LCD2
2402
LCD_MAP6
2405
LCD_MAP5
2406
Rev 2
Bit 7
U
Bit 6
Bit 5
MUX_DIV[3:0]
MUX9_SEL[3:0]
MUX7_SEL[3:0]
MUX5_SEL[3:0]
MUX3_SEL[3:0]
MUX1_SEL[3:0]
EQU[2:0]
U
U
U
U
R
U
R
U
DIFFB_E
U
U
U
ADC_DIV
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MUX10_SEL[3:0]
MUX8_SEL[3:0]
MUX6_SEL[3:0]
MUX4_SEL[3:0]
MUX2_SEL[3:0]
MUX0_SEL[3:0]
U
CHOP_E[1:0]
RTM_E
CE_E
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
CE_LCTN[5:0]
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
DIFFA_E
RFLY_DIS
FIR_LEN[1:0]
PLS_INV
U
U
U
RTM0[9:8]
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
PLL_FAST
RESET
MPU_DIV[2:0]
TRIMT[7:0]
LCD_E
LCD_VMODE[1:0]
LCD_BAT
R
LCD_MODE[2:0]
LCD_ALLCOM
LCD_Y
LCD_BLNKMAP23[5:0]
LCD_BLNKMAP22[5:0]
LCD_MAP[55:48]
LCD_MAP[47:40]
LCD_CLK[1:0]
107
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Addr
Bit 7
Bit 6
Bit 5
LCD_MAP4
LCD_MAP3
LCD_MAP2
LCD_MAP1
LCD_MAP0
LCD4
LCD_DAC
SEGDIO0
…
SEGDIO15
SEGDIO16
…
SEGDIO45
SEGDIO46
…
SEGDIO50
SEGDIO51
…
SEGDIO55
2407
2408
2409
240A
240B
240C
240D
2410
…
241F
2420
…
243D
243E
…
2442
2443
…
2447
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
DIO_R5
DIO_R4
DIO_R3
DIO_R2
DIO_R1
DIO_R0
DIO0
DIO1
DIO2
NV BITS
RESERVED
RESERVED
TMUX
2450
2451
2452
2453
2454
2455
2456
2457
2458
108
2500
2501
2502
U
U
U
U
U
U
U
DIO_EEX[1:0]
DIO_PW
DIO_PV
DIO_PX
DIO_PY
U
U
U
U
U
U
Bit 4
Bit 3
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
U
U
Bit 1
LCD_RST
LCD_BLANK
LCD_DAC[4:0]
LCD_SEG0[5:0]
…
LCD_SEG15[5:0]
LCD_SEGDIO16[5:0]
…
LCD_SEGDIO45[5:0]
LCD_SEG46[5:0]
…
LCD_SEG50[5:0]
LCD_SEGDIO51[5:0]
…
LCD_SEGDIO55[5:0]
U
U
DIO_R11[2:0]
DIO_R9[2:0]
DIO_R7[2:0]
DIO_R5[2:0]
DIO_R3[2:0]
U
U
OPT_FDC[1:0]
U
U
U
R
Bit 2
U
U
U
U
U
U
U
U
OPT_TXE[1:0]
U
OPT_RXDIS
U
U
R
U
R
U
Bit 0
LCD_ON
DIO_RPB[2:0]
DIO_R10[2:0]
DIO_R8[2:0]
DIO_R6[2:0]
DIO_R4[2:0]
DIO_R2[2:0]
OPT_TXMOD
OPT_RXINV
U
OPT_TXINV
OPT_BB
U
R
U
R
U
TMUX[5:0]
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Addr
TMUX2
2503
RTC1
2504
71M6x01 Interface
REMOTE2
2602
REMOTE1
2603
RBITS
INT1_E
2700
INT2_E
2701
SECURE
2702
Analog0
2704
VERSION
2706
INTBITS
2707
FLAG0
SFR E8
FLAG1
SFR F8
STAT
SFR F9
REMOTE0 SFR FC
SPI1
SFR FD
SPI0
2708
RCE0
2709
RTMUX
270A
INFO_PG
270B
DIO3
270C
NV RAM and RTC
2800NVRAMxx
287F
WAKE
2880
STEMP1
2881
STEMP0
2882
BSENSE
2885
LKPADDR
2887
LKPDATA
2888
LKPCTRL
2889
RTC0
2890
Rev 2
Bit 7
U
U
Bit 6
U
Bit 5
U
Bit 4
Bit 3
Bit 2
TMUX2[4:0]
Bit 1
Bit 0
EX_RTC1M
U
FLSH_RDE
EX_RTC1S
U
FLSH_WRE
SPARE[2:0]
EX_XFER
U
R
INT2
IE_RTC1M
U
INT1
IE_RTC1S
U
VSTAT[2:0]
INT0
IE_XFER
PB_STATE
R
U
U
R
TMUXRA[2:0]
U
U
INFO_PG
U
U
U
U
U
U
LKP_RD
U
LKP_WR
U
RTCA_ADJ[6:0]
RMT_RD[15:8]
RMT_RD[7:0]
EX_EEX
EX_SPI
VREF_CAL
U
IE_EEX
IE_SPI
U
EX_XPULSE EX_YPULSE
EX_WPULSE EX_VPULSE
FLSH_UNLOCK[3:0]
VREF_DIS
PRE_E
INT6
IE_XPULSE
IE_WPULSE
U
PERR_RD
CHOPR[1:0]
U
U
U
R
U
U
INT5
IE_YPULSE
IE_VPULSE
U
PERR_WR
R
R
U
PORT_E
EX_RTCT
U
U
U
R
ADC_E
BCURR
VERSION[7:0]
INT4
INT3
IE_RTCT
U
U
U
PLL_OK
U
RCMD[4:0]
SPI_CMD[7:0]
SPI_STAT[7:0]
R
RMT_E
R
U
U
U
SPI_E
SPI_SAFE
R
NVRAM[0] – NVRAM[7F] – Direct Access
STEMP[2:0]
LKPAUTOI
U
RTC_WR
U
RTC_RD
U
U
WAKE_TMR[7:0]
STEMP[10:3]
U
U
BSENSE[7:0]
LKPADDR[6:0]
LKPDAT[7:0]
U
U
RTC_FAIL
U
109
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RTC_SBSC[7:0]
RTC_SEC[5:0]
RTC_MIN[5:0]
U
RTC_HR[4:0]
U
U
U
RTC_DAY[2:0]
U
RTC_DATE[4:0]
U
U
RTC_MO[3:0]
RTC_YR[7:0]
U
U
U
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
RTC_Q[1:0]
RTC_TMIN[5:0]
U
RTC_THR[4:0]
OSC_COMP
TEMP_BAT TBYTE_BUSY
TEMP_PER[2:0]
WF_RSTBIT
WF_OVF
WF_ERST
WF_BADVDD
WF_TMR
WF_RX
WF_PB
WF_DIO4
WF_DIO52
WF_DIO55
WAKE_ARM
U
EW_RX
EW_PB
EW_DIO4
EW_DIO52 †
EW_DIO55
U
U
U
U
U
U
RTC2
2892
U
U
RTC3
2893
U
U
RTC4
2894
U
U
RTC5
2895
U
U
RTC6
2896
U
U
RTC7
2897
U
U
RTC8
2898
RTC9
2899
U
U
RTC10
289B
RTC11
289C
RTC12
289D
U
U
RTC13
289E
U
U
RTC14
289F
TEMP_BSEL
TEMP_PWR
TEMP
28A0
WF_RST
WF1
28B0 WF_CSTART
U
U
WF2
28B1
SLEEP
LCD_ONLY
MISC
28B2
U
U
WAKE_E
28B3
WD_RST
TEMP_START
WDRST
28B4
MPU PORTS
DIO_DIR[15:12]
P3
SFR B0
DIO_DIR[11:8]
P2
SFR A0
DIO_DIR[7:4]
P1
SFR 90
DIO_DIR[3:0]
P0
SFR 80
FLASH
FLSH_ERASE[7:0]
ERASE
SFR 94
SECURE
U
U
FLSH_PEND
FLSHCTL SFR B2 PREBOOT
FLSH_PGADR[5:0]
PGADR
SFR B7
I2C
EEDATA[7:0]
EEDATA
SFR 9E
EECTRL[7:0]
EECTRL
SFR 9F
†
71M6542F/G only
110
DIO[15:12]
DIO[11:8]
DIO[7:4]
DIO[3:0]
FLSH_PSTWR FLSH_MEEN
U
FLSH_PWE
U
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5.2
I/O RAM Map – Alphabetical Order
Table 76 lists I/O RAM bits and registers in alphabetical order.
Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and
copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The
remaining bits are mapped to the address space 0x2XXX. Bits with R (read) direction can be read by the MPU. Columns labeled Rst and Wk
describe the bit values upon reset and wake, respectively. No entry in one of these columns means the bit is either read-only or is powered by the
NV supply and is not initialized. Write-only bits return zero when they are read.
Locations that are shaded in grey are non-volatile (i.e., battery-backed).
Table 76: I/O RAM Map – Functional Order
Name
Location
ADC_E
2704[4]
ADC_DIV
2200[5]
BCURR
BSENSE[7:0]
CE_E
2704[3]
2885[7:0]
2106[0]
CE_LCTN[5:0]
2109[5:0]
CHIP_ID[15:8]
CHIP_ID[7:0]
2300[7:0]
2301[7:0]
CHOP_E[1:0]
2106[3:2]
Rev 2
Rst Wk Dir
0
Description
0
R/W Enables ADC and VREF. When disabled, reduces bias current.
ADC_DIV controls the rate of the ADC and FIR clocks.
The ADC_DIV setting determines whether MCK is divided by 4 or 8:
0 = MCK/4
1 = MCK/8
The
resulting
ADC and FIR clock is as shown below.
0 0 R/W
PLL_FAST = 0
PLL_FAST = 1
MCK
6.291456 MHz
19.660800 MHz
ADC_DIV = 0
1.572864 MHz
4.9152 MHz
ADC_DIV = 1
0.786432 MHz
2.4576 MHz
0 0 R/W Connects a 100 µA load to the battery selected by TEMP_BSEL.
– –
R The result of the battery measurement. See 2.5.6 71M654x Battery Monitor.
0 0 R/W CE enable.
CE program location. The starting address for the CE program is
31 31 R/W
1024*CE_LCTN.
0 0
R
These bytes contain the chip identification.
0 0
R
Chop enable for the reference bandgap circuit. The value of CHOP changes
on the rising edge of MUXSYNC according to the value in CHOP_E:
0 0 R/W
00 = toggle1 01 = positive 10 = reversed 11 = toggle
1
except at the mux sync edge at the end of an accumulation interval.
111
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Location
CHOPR[1:0]
2709[7:6]
DIFFA_E
DIFFB_E
DIO_R2[2:0]
DIO_R3[2:0]
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
DIO_RPB[2:0]
210C[4]
210C[5]
2455[2:0]
2455[6:4]
2454[2:0]
2454[6:4]
2453[2:0]
2453[6:4]
2452[2:0]
2452[6:4]
2451[2:0]
2451[6:4]
2450[2:0]
DIO_DIR[15:12]
DIO_DIR[11:8]
DIO_DIR[7:4]
DIO_DIR[3:0]
DIO[15:12]
DIO[11:8]
DIO[7:4]
DIO[3:0]
SFR B0[7:4]
SFR A0[7:4]
SFR 90[7:4]
SFR 80[7:4]
Rst Wk Dir
Description
The CHOP settings for the remote sensor.
00 = Auto chop. Change every MUX frame.
00 00 R/W 01 = Positive
10 = Negative
11 = Auto chop. Same as 00.
0 0 R/W Enables differential configuration for the IA current input (IAP-IAN).
0 0 R/W Enables differential configuration for the IB current input (IBP-IBN).
0
Connects PB and dedicated I/O pins DIO2 through DIO11 to internal resources.
If more than one input is connected to the same resource, the MULTIPLE
0
column below specifies how they are combined.
0
0
MULTIPLE
DIO_Rx Resource
0
0
NONE
–
0 – R/W
1
Reserved
OR
0
2
T0 (Timer0 clock or gate)
OR
0
3
T1 (Timer1 clock or gate)
OR
0
4
IO
interrupt
(int0)
OR
0
5
IO interrupt (int1)
OR
0
F
SFR B0[3:0]
SFR A0[3:0] SFR 90[3:0] F
SFR 80[3:0]
F
Programs the direction of the first 16 DIO pins. 1 indicates output. Ignored if
the pin is not configured as I/O. See DIO_PV and DIO_PW for special option
R/W for the SEGDIO0 and SEGDIO1 outputs. See DIO_EEX for special option for
SEGDIO2 and SEGDIO3. Note that the direction of DIO pins above 15 is set by
SEGDIOx[1]. See PORT_E to avoid power-up spikes.
F
The value on the first 16 DIO pins. Pins configured as LCD reads zero.
When written, changes data on pins configured as outputs. Pins configured
R/W
as LCD or input ignore writes. Note that the data for DIO pins above 15 is
set by SEGDIOx[0].
When set, converts pins SEGDIO3/SEGDIO2 to interface with external
EEPROM. SEGDIO2 becomes SDCK and SEGDIO3 becomes bi-directional
SDATA, but only if LCD_MAP[2] and LCD_MAP[3] are cleared.
DIO_EEX[1:0]
2456[7:6]
0
–
R/W
DIO_EEX[1:0]
00
01
10
11
112
Function
Disable EEPROM interface
2-Wire EEPROM interface
3-Wire EEPROM interface
3-Wire EEPROM interface with separate DO (DIO3)
and DI (DIO8) pins.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
DIO_PV
DIO_PW
DIO_PX
DIO_PY
EEDATA[7:0]
EECTRL[7:0]
Location
2457[6]
2457[7]
2458[7]
2458[6]
SFR 9E
SFR 9F
Rst Wk Dir
0
0
0
0
0
0
–
–
–
–
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Causes VARPULSE to be output on pin SEGDIO1, if LCD_MAP[1] = 0.
Causes WPULSE to be output on pin SEGDIO0, if LCD_MAP[0] = 0.
Causes XPULSE to be output on pin SEGDIO6 , if LCD_MAP[6] = 0.
Causes YPULSE to be output on pin SEGDIO7 , if LCD_MAP[7] = 0.
Serial EEPROM interface data.
Serial EEPROM interface control.
Status
Bit
Name
Read/
Write
Reset
State
7
ERROR
R
0
6
BUSY
R
0
5
RX_ACK
R
1
Polarity Description
1 when an illegal command
is received.
Positive 1 when serial data bus is
busy.
1 indicates that the
Positive
EEPROM sent an ACK bit.
Positive
Specifies the power equation.
EQU
0
EQU[2:0]
2106[7:5]
0
0
R/W
1
2†
Watt & VAR Formula
(WSUM/VARSUM)
VA*IA
1 element, 2W 1φ
VA*(IA-IB)/2
1 element, 3W 1φ
VA*IA + VB*IB
2 element, 3W 3φ Delta
Inputs Used for Energy/Current
Calculation
W0SUM/
W1SUM/
I0SQ I1SQ
VAR0SUM
VAR1SUM SUM SUM
VA*IA
VA*IB1
IA
IB1
VA*(IA-IB)/2
–
IA-IB
IB
VA*IA
VB*IB
IA
IB
Note:
1. Optionally, IB may be used to measure neutral current.
†
71M6542F/G only
Rev 2
113
71M6541D/F/G and 71M6542F/G Data Sheet
Name
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
Location
Rst Wk Dir
Description
2700[0]
2700[1]
2700[2]
2700[3]
2701[7]
2700[7]
2700[6]
2700[5]
2701[6]
2701[5]
0
0
Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC,
etc. The bits are set by hardware and cannot be set by writing a 1. The bits
R/W are reset by writing 0. Note that if one of these interrupts is to enabled, its
corresponding 8051 EX enable bit must also be set. See 2.4.8 Interrupts for
details.
EW_DIO4
28B3[2]
0
–
R/W
EW_DIO52
28B3[1]
0
–
R/W
EW_DIO55
28B3[0]
0
–
R/W
EW_PB
28B3[3]
0
–
R/W
EW_RX
28B3[4]
0
–
R/W
210C[2:1]
0
0
R/W
FIR_LEN[1:0]
114
Connects SEGDIO4 to the WAKE logic and permits SEGDIO4 rising to wake
the part. This bit has no effect unless DIO4 is configured as a digital input.
Connects SEGDIO52 to the WAKE logic and permits SEGDIO52 rising to
wake the part. This bit has no effect unless SEGDIO52 is configured as a
digital input.
The SEGDIO52 pin is only available in the 71M6542F/G.
Connects SEGDIO55 to the WAKE logic and permits SEGDIO55 rising to
wake the part. This bit has no effect unless SEGDIO55 is configured as a
digital input.
Connects PB to the WAKE logic and permits PB rising to wake the part. PB
is always configured as an input.
Connects RX to the WAKE logic and permits RX rising to wake the part. See
the WAKE description on page 87 for de-bounce issues.
Determines the number of ADC cycles in the ADC decimation FIR filter.
PLL_FAST = 1:
FIR_LEN[1:0]
ADC Cycles
00
141
01
288
10
384
PLL_FAST = 0:
FIR_LEN[1:0]
ADC Cycles
00
135
01
276
10
Not Allowed
The ADC LSB size and full-scale values depend on the FIR_LEN[1:0] setting.
Refer to 6.4.15 ADC Converter on page 149.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Location
Rst Wk Dir
SFR 94[7:0]
0
0
FLSH_MEEN
SFR B2[1]
0
0
FLSH_PEND
SFR B2[3]
0
0
SFR B7[7:2]
0
0
FLSH_PSTWR
SFR B2[2]
0
0
FLSH_PWE
SFR B2[0]
0
0
FLSH_RDE
2702[2]
–
–
2702[7:4]
0
0
2702[1]
–
–
FLSH_ERASE[7:0]
FLSH_PGADR[5:0]
FLSH_UNLOCK[3:0]
FLSH_WRE
Rev 2
Description
Flash Erase Initiate
FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash
Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order
to initiate the appropriate Erase cycle.
(default = 0x00).
W
0x55 = Initiate Flash Page Erase cycle. Must be proceeded by a write to
FLSH_PGADR[5:0] (SFR 0xB7[7:2]).
0xAA = Initiate Flash Mass Erase cycle. Must be proceeded by a write to
FLSH_MEEN and the ICE port must be enabled.
Any other pattern written to FLSH_ERASE has no effect.
Mass Erase Enable
0 = Mass Erase disabled (default).
W
1 = Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Indicates that a timed flash write is pending. If another flash write is attempted,
R
it is ignored.
Flash Page Erase Address
FLSH_PGADR[5:0] – Flash Page Address (page 0 thru 63) that is erased during
W
the Page Erase cycle. (default = 0x00).
Must be re-written for each new Page Erase cycle.
Enables timed flash writes. When 1, and if CE_E = 1, flash write requests are
stored in a one-element deep FIFO and are executed when CE_BUSY falls.
R/W
FLSH_PEND can be read to determine the status of the FIFO. If
FLSH_PSTWR = 0 or if CE_E = 0, flash writes are immediate.
Program Write Enable
0 = MOVX commands refer to External RAM Space, normal operation (default).
R/W 1 = MOVX @DPTR,A moves A to External Program Space (Flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes to this bit
are inhibited when interrupts are enabled.
Indicates that the flash may be read by ICE or SPI slave. FLSH_RDE =
R
(!SECURE)
Must be a ‘2’ to enable any flash modification. See the description of Flash
R/W
security for more details.
R Indicates that the flash may be written through ICE or SPI slave ports.
115
71M6541D/F/G and 71M6542F/G Data Sheet
Name
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
SFR E8[0]
SFR E8[1]
SFR E8[2]
SFR E8[4]
SFR F8[7]
SFR E8[7]
SFR E8[6]
SFR E8[5]
SFR F8[4]
SFR F8[3]
0
0
INTBITS
2707[6:0]
–
–
LCD_ALLCOM
2400[3]
0
–
LCD_BAT
2402[7]
0
–
2401[5:0]
2402[5:0]
0
–
LCD_BLNKMAP23[5:0]
LCD_BLNKMAP22[5:0]
Location
Rst Wk Dir
Description
Interrupt flags for external interrupts 2 and 6. These flags monitor the source
of the int6 and int2 interrupts (external interrupts to the MPU core). These
flags are set by hardware and must be cleared by the software interrupt
handler. The IEX2 (SFR 0xC0[1]) and IEX6 (SFR 0xC0[5]) interrupt flags are
R/W
automatically cleared by the MPU core when it vectors to the interrupt
handler. IEX2 and IEX6 must be cleared by writing zero to their corresponding
bit positions in SFR 0xC0, while writing ones to the other bit positions that are
not being cleared.
Interrupt inputs. The MPU may read these bits to see the input to external
interrupts INT0, INT1, up to INT6. These bits do not have any memory and
are primarily intended for debug use.
Configures SEG/COM bits as COM. Has no effect on pins whose LCD_MAP
R/W
bit is zero.
R/W Connects the LCD power supply to VBAT in all modes.
Identifies which segments connected to SEG23 and SEG22 should blink. 1
R/W means ‘blink.’ The most significant bit corresponds to COM5, the least
significant, to COM0.
Sets the LCD clock frequency. Note: fw = 32768 Hz
R
LCD_CLK LCD Clock Frequency
LCD_CLK[1:0]
2400[1:0]
0
–
R/W
00
01
LCD_DAC[4:0]
LCD_E
116
240D[4:0]
0
–
2400[7]
0
–
fW
= 64 Hz
29
fW
= 128 Hz
28
LCD_CLK
10
11
LCD Clock Frequency
fW
= 256 Hz
27
fW
= 512 Hz
26
The LCD contrast DAC. This DAC controls the VLCD voltage and has an
output range of 2.5 V to 5 V. The VLCD voltage is
VLCD = 2.5 + 2.5 * LCD_DAC[4:0]/31
R/W
Thus, the LSB of the DAC is 80.6 mV. The maximum DAC output voltage is
limited by V3P3SYS, VBAT, and whether LCD_BSTE = 1.
Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are
R/W
ground as are the COM and SEG outputs if their LCD_MAP bit is 1.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
LCD_MAP[55:48]
LCD_MAP[47:40]
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
Location
2405[7:0]
2406[7:0]
2407[7:0]
2408[7:0]
2409[7:0]
240A[7:0]
240B[7:0]
Rst Wk Dir
0
0
0
0
0
0
0
–
–
–
–
–
–
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Enables LCD segment driver mode of combined SEGDIO pins. Pins that
cannot be configured as outputs (SEG48 through SEG50) become inputs with
internal pull ups when their LCD_MAP bit is zero. Also, note that SEG48
through SEG50 are multiplexed with the in-circuit emulator signals. When the
ICE_E pin is high, the ICE interface is enabled, and SEG48 through SEG50
become E_RXTX, E_TCLK and E_RST, respectively.
Selects the LCD bias and multiplex mode.
LCD_MODE
000
001
010
011
Output
4 states, 1/3 bias
3 states, 1/3 bias
2 states, ½ bias
3 states, ½ bias
LCD_MODE
100
101
110
Output
Static display
5 states, 1/3 bias
6 states, 1/3 bias
2400[6:4]
0
–
R/W
LCD_ON
LCD_BLANK
240C[0]
240C[1]
0
0
–
–
LCD_ONLY
28B2[6]
0
0
LCD_RST
240C[2]
0
–
R/W Turns on or off all LCD segments without changing LCD data. If both bits are
R/W set, the LCD display is turned on.
Puts the IC to sleep, but with LCD display still active. Ignored if system power
W is present. It awakens when Wake Timer times out, when certain DIO pins
are raised, or when system power returns. See 3.2 Battery Modes.
Clear all bits of LCD data. These bits affect SEGDIO pins that are configured
R/W
as LCD drivers. This bit does not auto clear.
2410[5:0] to
241F[5:0]
0
–
R/W
2420[5:0] to
243D[5:0]
0
–
SEG and DIO data for SEGDIO16 through SEGDIO45. If configured as DIO,
R/W bit 1 is direction (1 is output, 0 is input), bit 0 is data, and the other bits are
ignored.
243E[5:0] to 2442[5:0]
0
–
R/W
–
SEG and DIO data for SEGDIO51 through SEGDIO55. If configured as DIO,
bit 1 is direction (1 is output, 0 is input), bit 0 is data, and the other bits are
R/W
ignored.
SEGDIO52 through SEDIO54 are available only on the 71M6542F/G.
LCD_MODE[2:0]
LCD_SEG0[5:0]
to
LCD_SEG15[5:0]
LCD_SEGDIO16[5:0]
to
LCD_SEGDIO45[5:0]
LCD_SEG46[5:0]
to
LCD_SEG50[5:0]
LCD_SEGDIO51[5:0]
to
LCD_SEGDIO55[5:0]
Rev 2
2443[5:0] to 2447[5:0]
0
SEG Data for SEG0 through SEG15. DIO data for these pins is in SFR
space.
SEG data for SEG46 through SEG50. These pins cannot be configured as
DIO.
117
71M6541D/F/G and 71M6542F/G Data Sheet
Name
LCD_VMODE[1:0]
LCD_Y
LKPADDR[6:0]
LKPAUTOI
LKPDAT[7:0]
LKP_RD
LKP_WR
Location
2401[7:6]
Rst Wk Dir
00 00 R/W
2400[2]
0
–
R/W
2887[6:0]
0
0
R/W
2887[7]
0
0
R/W
2888[7:0]
0
0
R/W
2889[1]
2889[0]
0
0
0
0
R/W
R/W
MPU_DIV[2:0]
2200[2:0]
0
0
R/W
MUX0_SEL[3:0]
MUX1_SEL[3:0]
MUX2_SEL[3:0]
MUX3_SEL[3:0]
MUX4_SEL[3:0]
MUX5_SEL[3:0]
MUX6_SEL[3:0]
MUX7_SEL[3:0]
MUX8_SEL[3:0]
MUX9_SEL[3:0]
MUX10_SEL[3:0]
2105[3:0]
2105[7:4]
2104[3:0]
2104[7:4]
2103[3:0]
2103[7:4]
2102[3:0]
2102[7:4]
2101[3:0]
2101[7:4]
2100[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
118
Description
Specifies how VLCD is generated. See 2.5.8.4 for the definition of V3P3L.
LCD_VMODE
11
10
01
00
Description
External VLCD
LCD boost and LCD DAC enabled
LCD DAC enabled
No boost and no DAC. VLCD=V3P3L.
LCD Blink Frequency (ignored if blink is disabled).
1 = 1 Hz, 0 = 0.5 Hz
The address for reading and writing the RTC lookup RAM
Auto-increment flag. When set, LKPADDR auto-increments every time
LKP_RD or LKP_WR is pulsed. The incremented address can be read at
LKPADDR[6:0].
The data for reading and writing the RTC lookup RAM.
Strobe bits for the RTC lookup RAM read and write. When set, the
LKPADDR[6:0] field and LKPDAT register is used in a read or write
operation. When a strobe is set, it stays set until the operation completes, at
which time the strobe is cleared and LKPADDR[6:0] is incremented if the
LKPAUTOI bit is set.
MPU clock rate is:
MPU Rate = MCK Rate * 2-(2+MPU_DIV[2:0]).
The maximum value for MPU_DIV[2:0] is 4. Based on the default values of
the PLL_FAST bit and MPU_DIV[2:0], the power up MPU rate is 6.29 MHz / 4
= 1.5725 MHz. The minimum MPU clock rate is 38.4 kHz when PLL_FAS T =
1.
Selects which ADC input is to be converted during time slot 0.
Selects which ADC input is to be converted during time slot 1.
Selects which ADC input is to be converted during time slot 2.
Selects which ADC input is to be converted during time slot 3.
Selects which ADC input is to be converted during time slot 4.
Selects which ADC input is to be converted during time slot 5.
Selects which ADC input is to be converted during time slot 6.
Selects which ADC input is to be converted during time slot 7.
Selects which ADC input is to be converted during time slot 8.
Selects which ADC input is to be converted during time slot 9.
Selects which ADC input is to be converted during time slot 10.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Location
MUX_DIV[3:0]
2100[7:4]
0
0
2457[0]
0
–
OPT_BB
Rst Wk Dir
Description
MUX_DIV[3:0] is the number of ADC time slots in each MUX frame. The
R/W
maximum number of time slots is 11.
Configures the input of the optical port to be a DIO pin to allow it to be
bit-banged. In this case, DIO5 becomes a third high speed UART. Refer to
R/W 2.5.7 UART and Optical Interface under the “Bit Banged Optical UART
(Third UART)” sub-heading on page 58.
Selects OPT_TX modulation duty cycle.
OPT_FDC[1:0]
2457[5:4]
0
–
R/W
OPT_RXDIS
2457[2]
0
–
R/W
OPT_RXINV
2457[1]
0
–
R/W
00 –
R/W
OPT_TXE [1:0]
2456[3:2]
OPT_TXINV
2456[0]
0
–
R/W
OPT_TXMOD
2456[1]
0
–
R/W
OSC_COMP
28A0[5]
0
–
R/W
PB_STATE
SFR F8[0]
0
0
R
PERR_RD
PERR_WR
SFR FC[6]
SFR FC[5]
0
0
R/W
PLL_OK
SFR F9[4]
0
0
R
Rev 2
OPT_FDC
00
01
10
11
Function
50% Low
25% Low
12.5% Low
6.25% Low
OPT_RX can be configured as an input to the optical UART or as SEGDIO55.
OPT_RXDIS = 0 and LCD_MAP[55] = 0: OPT_RX
OPT_RXDIS = 1 and LCD_MAP[55] = 0: DIO55
OPT_RXDIS = 0 and LCD_MAP[55] = 1: SEG55
OPT_RXDIS = 1 and LCD_MAP[55] = 1: SEG55
Inverts result from OPT_RX comparator when 1. Affects only the UART input.
Has no effect when OPT_RX is used as a DIO input.
Configures the OPT_TX output pin.
If LCD_MAP[51] = 0:
00 = DIO51, 01 = OPT_TX, 10 = WPULSE, 11 = VARPULSE
If LCD_MAP[51] = 1:
xx = SEG51
Invert OPT_TX when 1. This inversion occurs before modulation.
Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is
modulated when it would otherwise have been zero. The modulation is applied
after any inversion caused by OPT_TXINV.
Enables the automatic update of RTC_P and RTC_Q every time the temperature
is measured.
The de-bounced state of the PB pin.
The IC sets these bits to indicate that a parity error on the remote sensor has
been detected. Once set, the bits are remembered until they are cleared by
the MPU.
Indicates that the clock generation PLL is settled.
119
71M6541D/F/G and 71M6542F/G Data Sheet
Name
PLL_FAST
Location
2200[4]
PLS_MAXWIDTH[7:0]
210A[7:0]
PLS_INTERVAL[7:0]
210B[7:0]
Rst Wk Dir
Description
Controls the speed of the PLL and MCK.
R/W 1 = 19.66 MHz (XTAL * 600)
0 = 6.29 MHz (XTAL * 192)
PLS_MAXWIDTH[7:0] determines the maximum width of the pulse (low-going
pulse if PLS_INV=0 or high-going pulse if PLS_INV=1). The maximum pulse
width is (2*PLS_MAXWIDTH[7:0] + 1)*TI. Where TI is PLS_INTERVAL[7:0] in
FF FF R/W
units of CK_FIR clock cycles. If PLS_INTERVAL[7:0] = 0 or
PLS_MAXWIDTH[7:0] = 255, no pulse width checking is performed and the
output pulses have 50% duty cycle. See 2.3.6.2 VPULSE and WPULSE.
PLS_INTERVAL[7:0] determines the interval time between pulses. The time
between output pulses is PLS_INTERVAL[7:0]*4 in units of CK_FIR clock
cycles. If PLS_INTERVAL[7:0] = 0, the FIFO is not used and pulses are output
as soon as the CE issues them. PLS_INTERVAL[7:0] is calculated as follows:
PLS_INTERVAL[7:0] = Floor ( Mux frame duration in CK_FIR cycles / CE pulse
0
0
0
0
updates per Mux frame / 4 )
PLS_INV
210C[0]
0
0
PORT_E
270C[5]
0
0
PRE_E
PREBOOT
2704[5]
SFRB2[7]
0
–
0
–
RCMD[4:0]
SFR FC[4:0]
0
0
RESET
2200[3]
0
0
RFLY_DIS
210C[3]
0
0
120
R/W
For example, since the 71M654x CE code is written to generate 6 pulses in one
integration interval, when the FIFO is enabled (i.e., PLS_INTERVAL[7:0] ≠ 0)
and that the frame duration is 1950 CK_FIR clock cycles, PLS_INTERVAL[7:0]
should be written with Floor(1950 / 6 / 4) = 81 so that the five pulses are
evenly spaced in time over the integration interval and the last pulse is issued
just prior to the end of the interval. See 2.3.6.2 VPULSE and WPULSE.
Inverts the polarity of WPULSE, VARPULSE, XPULSE and YPULSE.
R/W Normally, these pulses are active low. When inverted, they become active
high.
Enables outputs from the pins SEGDIO0-SEGDIO15. PORT_E = 0 after reset
R/W and power-up blocks the momentary output pulse that would occur on
SEGDIO0 to SEGDIO15.
R/W Enables the 8x pre-amplifier.
R Indicates that pre-boot sequence is active.
When the MPU writes a non-zero value to RCMD[4:0], the IC issues a
R/W command to the appropriate remote sensor. When the command is complete,
the IC clears RCMD[4:0].
W When set, writes a one to WF_RSTBIT and then causes a reset.
Controls how the IC drives the power pulse for the 71M6x01. When set, the
R/W power pulse is driven high and low. When cleared, it is driven high followed
by an open circuit fly-back interval.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Location
RMT_E
2709[3]
0
0
2602[7:0]
2603[7:0]
0
0
R
2890[4]
0
0
R/W
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
289B[2:0]
289C[7:0]
289D[7:2]
4
0
0
4
0
0
R/W
RTC_Q[1:0]
289D[1:0]
0
0
R/W
2890[6]
0
0
R/W
RTC_SBSC[7:0]
RTC_TMIN[5:0]
2892[7:0]
289E[5:0]
–
0
–
–
R
R/W
RTC_THR[4:0]
289F[4:0]
0
–
R/W
2890[7]
0
0
R/W
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
2893[5:0]
2894[5:0]
2895[4:0]
2896[2:0]
2897[4:0]
2898[3:0]
2899[7:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
R/W
RTCA_ADJ[6:0]
2504[7:0]
40 –
R/W
RMT_RD[15:8]
RMT_RD[7:0]
RTC_FAIL
RTC_RD
RTC_WR
Rev 2
Rst Wk Dir
Description
Enables the remote digital isolation interface, which transforms the IBP-IBN
R/W pins into a digital balanced differential pair. Thus, enabling these pins to
interface to the 71M6x01 isolated sensor.
Response from remote read request.
Indicates that a count error has occurred in the RTC and that the time is not
trustworthy. This bit can be cleared by writing a 0.
RTC adjust. See 2.5.4 Real-Time Clock (RTC).
0x0FFBF ≤ RTC_P ≤ 0x10040
Note: RTC_P[16:0] and RTC_Q[1:0] form a single 19-bit RTC adjustment value.
RTC adjust. See 2.5.4 Real-Time Clock (RTC).
Note: RTC_P[16:0] and RTC_Q[1:0] form a single 19-bit RTC adjustment value.
Freezes the RTC shadow register so it is suitable for MPU reads. When
RTC_RD is read, it returns the status of the shadow register: 0 = up to date, 1
= frozen.
Time remaining until the next 1 second boundary. LSB = 1/256 second.
The target minutes register. See RTC_THR below.
The target hours register. The RTC_T interrupt occurs when RTC_MIN
becomes equal to RTC_TMIN and RTC_HR becomes equal to RTC_THR.
Freezes the RTC shadow register so it is suitable for MPU writes. When
RTC_WR is cleared, the contents of the shadow register are written to the
RTC counter on the next RTC clock (~500 Hz). When RTC_WR is read, it
returns 1 as long as RTC_WR is set. It continues to return one until the RTC
counter actually updates.
The RTC interface registers. These are the year, month, day, hour, minute
and second parameters for the RTC. The RTC is set by writing to these
registers. Year 00 and all others divisible by 4 are defined as a leap year.
SEC 00 to 59
MIN 00 to 59
HR
00 to 23 (00 = Midnight)
DAY 01 to 07 (01 = Sunday)
DATE 01 to 31
MO
01 to 12
YR
00 to 99
Each write operation to one of these registers must be preceded by a write to
0x20A0.
Analog RTC frequency adjust register.
121
71M6541D/F/G and 71M6542F/G Data Sheet
Name
RTM_E
RTM0[9:8]
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
2106[1]
210D[1:0]
210E[7:0]
210F[7:0]
2110[7:0]
2111[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
SECURE
SFR B2[6]
0
0
28B2[7]
0
0
SFR FD[7:0]
–
–
SPI_E
270C[4]
1
1
SPI_SAFE
270C[3]
0
0
SPI_STAT[7:0]
2708[7:0]
0
0
STEMP[10:3]
STEMP[2:0]
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
2881[7:0]
2882[7:5]
2107[4:0]
2108[7:0]
–
–
–
–
0
0
28A0[3]
0
0
SLEEP
SPI_CMD[7:0]
TBYTE_BUSY
122
Location
Rst Wk Dir
Description
R/W Real Time Monitor enable. When 0, the RTM output is low.
Four RTM probes. Before each CE code pass, the values of these registers
are serially output on the RTM pin. The RTM registers are ignored when
R/W
RTM_E = 0. Note that RTM0 is 10 bits wide. The others assume the upper
two bits are 00.
Inhibits erasure of page 0 and flash addresses above the beginning of CE code
R/W as defined by CE_LCTN[5:0]. Also inhibits the read of flash via the SPI and ICE
port.
Puts the part to SLP mode. Ignored if system power is present. The part
W wakes when the Wake timer times out, when push button is pushed, or when
system power returns.
R SPI command register for the 8-bit command from the bus master.
SPI port enable. Enables SPI interface on pins SEGDIO36 – SEGDIO39.
R/W
Requires that LCD_MAP[36-39] = 0.
Limits SPI writes to SPI_CMD and a 16-byte region in DRAM. No other
R/W
writes are permitted.
SPI_STAT contains the status results from the previous SPI transaction.
Bit 7: Ready error: The 71M654x was not ready to read or write as directed
by the previous command.
Bit 6: Read data parity: This bit is the parity of all bytes read from the
71M654x in the previous command. Does not include the SPI_STAT byte.
Bit 5: Write data parity: This bit is the overall parity of the bytes written to the
R 71M654x in the previous command. It includes CMD and ADDR bytes.
Bit 4-2: Bottom 3 bits of the byte count. Does not include ADDR and CMD
bytes. One, two, and three byte
instructions return 111.
Bit 1: SPI FLASH mode: This bit is zero when the TEST pin is zero.
Bit 0: SPI FLASH mode ready: Used in SPI FLASH mode. Indicates that the
flash is ready to receive another write instruction.
R
The result of the temperature measurement.
R
The number of multiplexer cycles per XFER_BUSY interrupt. Maximum value
R/W
is 8191 cycles.
Indicates that hardware is still writing the 0x28A0 byte. Additional writes to
R this byte are locked out while it is one. Write duration could be as long as
6ms.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
TEMP_22[10:8]
TEMP_22[7:0]
Location
Rst Wk Dir
230A[2:0]
230B[7:0]
0
–
R
TEMP_BAT
28A0[4]
0
–
R/W
TEMP_BSEL
28A0[7]
0
–
TBYTE_BUSY
28A0[3]
0
0
28A0[2:0]
0
–
TEMP_PER[2:0]
Description
Storage location for STEMP at 22C. STEMP is an 11-bit word.
Causes VBAT to be measured whenever a temperature measurement is
performed.
Selects which battery is monitored by the temperature sensor: 1 = VBAT,
R/W
0 = VBAT_RTC
Indicates that hardware is still writing the 0x28A0 byte. Additional writes to
R this byte will be locked out while it is one. Write duration could be as long as
6ms.
Sets the period between temperature measurements. Automatic measurements
can be enabled in any mode (MSN, BRN, LCD, or SLP). TEMP_PER = 0
disables automatic temperature updates, in which case TEMP_START may be
used by the MPU to initiate a one-shot temperature measurement.
R/W TEMP_PER Time (seconds)
0
1-6
7
TEMP_PWR
28A0[6]
TEMP_START
28B4[6]
TMUX[5:0]
TMUX2[4:0]
TMUXRA[2:0]
2502[5:0]
2503[4:0]
270A[2:0]
VERSION[7:0]
Selects the power source for the temp sensor:
R/W 1 = V3P3D, 0 = VBAT_RTC. This bit is ignored in SLP and LCD modes,
where the temp sensor is always powered by VBAT_RTC.
When TEMP_PER = 0 automatic temperature measurements are disabled,
and TEMP_START may be set by the MPU to initiate a one-shot temperature
0 0 R/W
measurement. TEMP_START is ignored in SLP and LCD modes. Hardware
clears TEMP_START when the temperature measurement is complete.
– – R/W Selects one of 32 signals for TMUXOUT. See 2.5.12 for details.
– – R/W Selects one of 32 signals for TMUX2OUT. See 2.5.12 for details.
000 000 R/W The TMUX setting for the remote isolated sensor (71M6x01).
The silicon version index. This word may be read by firmware to determine
the silicon version.
0
–
2706[7:0]
–
–
VREF_CAL
2704[7]
0
0
VREF_DIS
2704[6]
0
1
Rev 2
No temperature updates
2(3+TEMP_PER)
Continuous updates
R
VERSION[7:0]
0001 0011
0010 0010
Silicon Version
B01
B02
Brings the ADC reference voltage out to the VREF pin. This feature is disabled
when VREF_DIS=1.
R/W Disables the internal ADC voltage reference.
R/W
123
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Location
Rst Wk Dir
VSTAT[2:0]
SFR F9[2:0]
–
–
WAKE_ARM
28B2[5]
0
–
2880[7:0]
0
–
WD_RST
28B4[7]
0
0
WF_DIO4
28B1[2]
0
–
WF_DIO52
28B1[1]
0
–
WF_DIO55
28B1[0]
0
–
WF_TMR
WF_PB
WF_RX
WF_CSTART
WF_RST
WF_RSTBIT
WF_OVF
WF_ERST
WF_BADVDD
28B1[5]
28B1[3]
28B1[4]
28B0[7]
28B0[6]
28B0[5]
28B0[4]
28B0[3]
28B0[2]
0
0
0
0
1
0
0
0
0
–
–
–
WAKE_TMR[7:0]
124
–
Description
This word describes the source of power and the status of the VDD.
VSTAT Description
000
System Power OK. V3P3A>3.0v. Analog modules are functional
and accurate. [V3AOK,V3OK] = 11
001
System Power Low. 2.8v<V3P3A<3.0v. Analog modules not
accurate. Switch over to battery power is imminent.
[V3AOK,V3OK] = 01
010
Battery power and VDD OK. VDD>2.25v. Full digital functionality.
R
[V3AOK,V3OK] = 00, [VDDOK,VDDgt2] = 11
011
Battery power and VDD>2.0. Flash writes are inhibited. If the
TRIMVDD[5] fuse is blown, PLL_FAST (I/O RAM 0x2200[4]) is
cleared.
[V3AOK,V3OK] = 00, [VDDOK,VDDgt2] = 01
101
Battery power and VDD<2.0. When VSTAT=101, processor is
nearly out of voltage. Processor failure is imminent.
[V3AOK,V3OK] = 00, [VDDOK,VDDgt2] = 00
Arms the WAKE timer and loads it with WAKE_TMR[7:0]. When SLEEP or
R/W
LCD_ONLY is asserted by the MPU, the WAKE timer becomes active.
R/W Timer duration is WAKE_TMR+1 seconds.
Reset the WD timer. The WD is reset when a 1 is written to this bit. Writing a
W
one clears and restarts the watch dog timer.
DIO4 wake flag bit. If DIO4 is configured to wake the part, this bit is set
R whenever the de-bounced version of DIO4 rises. It is held in reset if DI04 is
not configured for wakeup.
DIO52 wake flag bit. If DIO52 is configured to wake the part, this bit is set
R whenever the de-bounced version of DIO52 rises. It is held in reset if DI052 is
not configured for wakeup.
DIO55 wake flag bit. If DIO55 is configured to wake the part, this bit is set
R whenever the de-bounced version of DIO55 rises. It is held in reset if DI055 is
not configured for wakeup.
R Indicates that the wake timer caused the part to wake up.
R Indicates that the PB caused the part to wake.
R Indicates that RX caused the part to wake.
R
Indicates that the Reset pin, Reset bit, ERST pin, Watchdog timer, the cold
start detector, or bad VBAT caused the part to reset.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5.3
CE Interface Description
5.3.1
CE Program
The CE performs the precision computations necessary to accurately measure energy. These computations
include offset cancellation, phase compensation, product smoothing, product summation, frequency
detection, VAR calculation, sag detection and voltage phase measurement. All data computed by the CE
is dependent on the selected meter equation as given by EQU[2:0] (I/O RAM 0x2106[7:5]).
The CE program is supplied by Teridian as a data image that can be merged with the MPU operational
code for meter applications. Typically, the CE program provided with the demonstration code covers
most applications and does not need to be modified. Other variations of CE code are available from
Teridian. The descriptions provided in this section apply to the CE code revisions shown in Table 77.
Please contact the local Teridian representative to obtain the appropriate CE code required for a specific
application.
Table 77. Standard CE Codes
Device
Local Sensors
Remote Sensor
71M6541D/F/G
CE41A01 (Eq. 0 or 1)
CE41B016601
CE41A01 (Eq. 0 or 1)
CE41B016201
CE41A04 (Eq. 2)
(Eq. 0, 1 or 2)
71M6542F/G
5.3.2
CE Data Format
All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two’s complement format
(-1 = 0xFFFFFFFF). Calibration parameters are defined in flash memory (or external EEPROM) and
must be copied to CE data memory by the MPU before enabling the CE. Internal variables are used in
internal CE calculations. Input variables allow the MPU to control the behavior of the CE code. Output
variables are outputs of the CE calculations. The corresponding MPU address for the most significant
byte is given by 0x0000 + 4 x CE_address and by 0x0003 + 4 x CE_address for the least significant byte.
5.3.3
Constants
Constants used in the CE Data Memory tables are:
•
•
•
•
•
•
•
•
Sampling Frequency: FS = 32768 Hz/13 = 2520.62 Hz.
F0 is the fundamental frequency of the mains phases.
IMAX is the external rms current corresponding to 250 mV pk (176.8 mV rms) at the inputs IA and IB.
IMAX needs to be adjusted if the pre-amplifier is activated for the IAP-IAN inputs. For a 250 µΩ shunt
resistor, IMAX becomes 707 A (176.8 mV rms / 250 µΩ = 707.2 A rms).
VMAX is the external rms voltage corresponding to 250 mV pk at the VA and VB inputs.
NACC, the accumulation count for energy measurements is SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0],
0x2108[7:0]).
The duration of the accumulation interval for energy measurements is SUM_SAMPS[12:0] / FS.
X is a gain constant of the pulse generators. Its value is determined by PULSE_FAST and PULSE_SLOW
(see Table 83).
Voltage LSB (for sag threshold) = VMAX * 7.879810-9 V.
The system constants IMAX and VMAX are used by the MPU to convert internal digital quantities (as
used by the CE) to external, i.e., metering quantities. Their values are determined by the scaling of the
voltage and current sensors used in an actual meter. The LSB values used in this document relate digital
quantities at the CE or MPU interface to external meter input quantities. For example, if a SAG threshold
of 80 V rms is desired at the meter input, the digital value that should be programmed into SAG_THR (CE
RAM 0x24) would be 80 Vrms * SQRT(2)/SAG_THRLSB, where SAG_THRLSB is the LSB value in the
description of SAG_THR (see Table 84).
Rev 2
125
71M6541D/F/G and 71M6542F/G Data Sheet
The parameters EQU[2:0] (I/O RAM 0x2106[7:5]), CE_E (I/O RAM 0x2106[0]), and SUM_SAMPS[12:0] are
essential to the function of the CE are stored in I/O RAM (see 5.2 I/O RAM Map – Alphabetical Order for
details).
5.3.4
Environment
Before starting the CE using the CE_E bit (I/O RAM 0x2106[0]), the MPU has to establish the proper
environment for the CE by implementing the following steps:
•
•
•
•
Locate the CE code in Flash memory using CE_LCTN[5:0] (I/O RAM 0x2109[5:0])
Load the CE data into RAM
Establish the equation to be applied in EQU[2:0] (I/O RAM 0x2106[7:5])
Establish the number of samples per accumulation period in SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0],
0x2108[7:0])
Establish the number of cycles per ADC multiplexer frame (MUX_DIV[3:0] (I/O RAM 0x2100[7:4]))
Apply proper values to MUXn_SEL, as well as proper selections for DIFFn_E (I/O RAM 0x210C[5:4])
and RMT_E (I/O RAM 0x2709[3]) in order to configure the analog inputs
Initialize any MPU interrupts, such as CE_BUSY, XFER_BUSY, or the power failure detection interrupt
VMAX = 600 V, IMAX = 707 A, and kH = 1 Wh/pulse are assumed as default settings
•
•
•
•
When different CE codes are used, a different set of environment parameters need to be established.
The exact values for these parameters are listed in the Application Notes and other documentation which
accompanies the CE code.
Operating CE codes with environment parameters deviating from the values specified by Teridian
leads to unpredictable results. See Table 1 and Table 2.
Typically, there are thirteen 32768 Hz cycles per ADC multiplexer frame (see 2.2.2 Input Multiplexer).
This means that the product of the number of cycles per slot and the number of conversions per frame
must be 12 (plus one settling cycle per frame, see Figure 6 and Figure 7). The default configuration is
FIR_LEN[1:0] = 01, I/O RAM 0x210C[2:1], (three cycles per conversion) and MUX_DIV[3:0] = 3 (3
conversions per multiplexer cycle).
Sample configurations can be copied from Demo Code provided by Teridian with the Demo Kits.
5.3.5
CE Calculations
Referring to Table 78, The MPU selects the desired equation by writing the EQU[2:0] (I/O RAM
0x2106[7:5]).
Table 78: CE EQU Equations and Element Input Mapping
EQU
Watt & VAR Formula
(WSUM/VARSUM)
0
VA IA – 1 element, 2W 1φ
VA*(IA-IB)/2 – 1 element, 3W 1φ
1
†
2
VA*IA + VB*IB – 2 element, 3W 3φ Delta
Note:
†
71M6542F/G only.
126
Inputs Used for Energy/Current Calculation
W0SUM/
VAR0SUM
W1SUM/
VAR1SUM
I0SQ
SUM
I1SQ
SUM
VA*IA
VA*(IA-IB)/2
VA*IA
VA*IB
–
VB*IB
IA
IA-IB
IA
IB
IB
–
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5.3.6
CE Front End Data (Raw Data)
Access to the raw data provided by the AFE is possible by reading addresses 0-3, 9 and 10 (decimal) shown
in Table 79.
The MUX_SEL column in Table 79 shows the MUX_SEL handles for the various sensor input pins. For
example, if differential mode is enable via control bit DIFFA_E = 1 (I/O RAM 0x210C[4]), then the inputs IAP
and IAN are combined together to form a single differential input and the corresponding MUX_SEL handle is
0. Similarly, the CE RAM location column provides the CE RAM address where the sample data is stored.
Continuing with the same example, if DIFFA_E = 1, the corresponding CE RAM location where the
samples for the IAP-IAN differential input are stored is 0 and CE RAM location is not disturbed.
The IB input can be configured as a direct-connected sensor (i.e., directly connected to the 71M654x) or as a
remote sensor (i.e., using a 71M6x01 Isolated Sensor). If the remote sensor is disabled by RMT_E = 0 and
differential mode is enabled by DIFFB_E = 1 (I/O RAM 0x210C[5]), then IBP and IBN form a differential
input with a MUX_SEL handle of 2, and the corresponding samples are stored in CE RAM location 2 (CE
RAM location 3 is not disturbed). If the remote sensor enable bit RMT_E = 1 and DIFFB_E = 0 or 1, then the
MUX_SEL handle is undefined (i.e., the sensor is not connected to the 71M654x, so MUX_SEL does not
apply, see 2.2 Analog Front End (AFE) on page 12), and the samples corresponding to this remote
differential IBP-IBN input are stored in CE RAM location 2 (CE RAM location 3 is not disturbed).
The voltage sensor inputs (VA and VB) do not have any associated configuration bits. VA has a MUX_SEL
handle value of 10, and its samples are stored in CE RAM location 10. VB has a MUX_SEL handle value of 9
and its samples are stored in CE RAM location 9.
Table 79: CE Raw Data Access Locations
ADC
Location
MUX_SEL Handle
Pin
ADC0
ADC1
IAP
IAP
ADC2
ADC3
IBP
IBN
CE RAM Location
DIFFA_E
DIFFA_E
0
1
0
1
0
0
0
0
1
1
RMT_E, DIFFB_E
RMT_E, DIFFB_E
0,0
0,1
1,0
1,1
0,0
0,1
1,0
1,1
2
2
2
–
–
2
2*
2*
3
3
There are no configuration bits for ADC9, 10
9
9
10
10
ADC9
VB†
ADC10
VA
Notes:
* Remote interface data.
†
71M6542F/G only.
5.3.7
FCE Status and Control
The CE Status Word, CESTATUS, is useful for generating early warnings to the MPU (Table 80). It contains
sag warnings for phase A and B, as well as F0, the derived clock operating at the fundamental input frequency. The MPU can read the CE status word at every CE_BUSY interrupt. Since the CE_BUSY interrupt occurs at 2520.6 Hz, it is desirable to minimize the computation required in the interrupt handler of
the MPU.
Table 80: CESTATUS Register
CE Address
0x80
Name
CESTATUS
Description
See description of CESTATUS bits in Table 81.
CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful
for generating an early power fail warning to initiate necessary data storage. CESTATUS represents the
Rev 2
127
71M6541D/F/G and 71M6542F/G Data Sheet
status flags for the preceding CE code pass (CE_BUSY interrupt). The significance of the bits in
CESTATUS is shown in Table 81.
Table 81: CESTATUS (CE RAM 0x80) Bit Definitions
CESTATUS
bit
31:4
3
2
Not Used
F0
Not Used
1
SAG_B
0
SAG_A
Name
Description
These unused bits are always zero.
F0 is a square wave at the exact fundamental input frequency.
This unused bit is always zero.
Normally zero. Becomes one when VB remains below SAG_THR for
SAG_CNT samples. Does not return to zero until VB rises above
SAG_THR.
Normally zero. Becomes one when VA remains below SAG_THR for
SAG_CNT samples. Does not return to zero until VA rises above
SAG_THR.
The CE is initialized by the MPU using CECONFIG (Table 82). This register contains in packed form
SAG_CNT, FREQSEL[1:0], EXT_PULSE, PULSE_SLOW and PULSE_FAST. The CECONFIG bit definitions are
given in Table 83.
Table 82: CECONFIG Register
CE
Address
Name
Data
Description
1
0x0030DB00
See description of the CECONFIG bits in
0x00B0DB002 Table 83.
1. Default for CE41A01 (71M6541D/F/G or CE41A04 (71M6542F/G) CE code for use with local
sensors.
2. Default for CE41B016201 and CE41B016601 codes that support the 71M6x01 remote
sensors.
0x20
CECONFIG
Table 83: CECONFIG (CE RAM 0x20) Bit Definitions
CECONFIG
bit
Name
23
Reserved
0
22
EXT_TEMP
0
21
EDGE_INT
1
20
SAG_INT
1
19:8
SAG_CNT
252
(0xFC)
7:6
FREQSEL[1:0]
0
Default Description
When this bit is set, control of temperature compensation is
enabled for the 71M6x01 Isolated Sensor Interface.
When 1, the MPU controls temperature compensation via the
GAIN_ADJn registers (CE RAM 0x40-0x42), when 0, the CE is in
control.
When 1, XPULSE produces a pulse for each zero-crossing of
the mains phase selected by FREQSEL[1:0] , which can be used
to interrupt the MPU.
When 1, activates YPULSE output when a sag condition is
detected.
The number of consecutive voltage samples below SAG_THR
(CE RAM 0x24) before a sag alarm is declared. The default value
is equivalent to 100 ms.
FREQSEL[1:0] selects the phase to be used for the frequency
monitor, sag detection, and for the zero crossing counter
(MAINEDGE_X, CE RAM 0x83).
FREQ SEL[1:0]
0
0
1
*71M6542F/G only
128
0
1
X
Phase Selected
A
B*
Not allowed
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5
EXT_PULSE
1
4:2
Reserved
0
1
PULSE_FAST
0
0
PULSE_SLOW
0
When zero, causes the pulse generators to respond to internal
data (WPULSE = WSUM_X (CE RAM 0x84), VPULSE = VARSUM_X
(CE RAM 0x88)). Otherwise, the generators respond to values the
MPU places in APULSEW and APULSER (CE RAM 0x45 and 0x49).
Reserved.
When PULSE_FAST = 1, the pulse generator input is increased
16x. When PULSE_SLOW = 1, the pulse generator input is
reduced by a factor of 64. These two parameters control the
pulse gain factor X (see table below). Allowed values are either
1 or 0. Default is 0 for both (X = 6).
PULSE_FAST PULSE_SLOW
X
0
0
1.5 * 22 = 6
6
1
0
1.5 * 2 = 96
-4
0
1
1.5 * 2 = 0.09375
1
1
Do not use
The FREQSEL[1:0] field in CECONFIG (CE RAM 0x20[7:6]) selects the phase that is utilized to generate a sag
interrupt. Thus, a SAG_INT event occurs when the selected phase has satisfied the sag event criteria as
set by the SAG_THR (CE RAM 0x24) register and the SAG_CNT field in CECONFIG (CE RAM 0x20[19:8]).
When the SAG_INT bit (CE RAM 0x20[20]) is set to 1, a sag event generates a transition on the YPULSE
output. In a two-phase system (71M6542F/G), and after a sag interrupt, the MPU should change the
FREQSEL[1:0] setting to select the other phase, if it is powered. Even though a sag interrupt is only
generated on the selected phase, both phases are simultaneously checked for sag. The presence of
power on a given phase can be sensed by directly checking the SAG_A and SAG_B bits in CESTATUS (CE
RAM 0x80[0:1]).
The EXT_TEMP bit enables temperature compensation by the MPU, when set to 1. When 0, internal (CE)
temperature compensation is enabled.
The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by
the MPU if the EXT_PULSE bit = 1 (CE RAM 0x20[5]). In this case, the MPU controls the pulse rate (external
pulse generation) by placing values into APULSEW and APULSER (CE RAM 0x45 and 0x49). By setting
EXT_PULSE = 0, the CE controls the pulse rate based on WSUM_X (CE RAM 0x84) and VARSUM_X (CE
RAM 0x88).
The 71M6541D/F/G and 71M6542F/G Demo Code creep function halts both internal and external
pulse generation.
Table 84: Sag Threshold and Gain Adjust Control
CE
Address
Name
Default
7
0x24
SAG_THR
2.39*10
0x40
GAIN_ADJ0
16384
0x41
GAIN_ADJ1
16384
0x42
GAIN_ADJ2
16384
5.3.8
Rev 2
Description
The voltage threshold for sag warnings. The default value is
equivalent to 113Vpk or 80 Vrms if VMAX = 600 Vrms.
 ∙ √2
_ =
 ∙ 7.8798 ∙ 10−9
This register scales the voltage measurement channels VA and
VB*. The default value of 16384 is equivalent to unity gain (1.000).
*71M6542F/G only
This register scales the IA current channel for Phase A. The
default value of 16384 is equivalent to unity gain (1.000).
This register scales the IB current channel for Phase B. The
default value of 16384 is equivalent to unity gain (1.000).
CE Transfer Variables
129
71M6541D/F/G and 71M6542F/G Data Sheet
When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer
variables. CE transfer variables are modified during the CE code pass that ends with an XFER_BUSY
interrupt. They remain constant throughout each accumulation interval. In this data sheet, the names of
CE transfer variables always end with “_X”. The transfer variables can be categorized as:
•
•
•
Fundamental energy measurement variables
Instantaneous (RMS) values
Other measurement parameters
5.3.8.1 Fundamental Energy Measurement Variables
Table 85 and Table 86 describe each transfer variable for fundamental energy measurement. All
variables are signed 32-bit integers. Accumulated variables such as WSUM are internally scaled so they
have at least 2x margin before overflow when the integration time is one second. Additionally, the hardware
does not permit output values to fold back upon overflow.
Table 85: CE Transfer Variables (with Local Sensors)
CE
Address
Name
0x84†
WSUM_X
0x85
0x86
W0SUM_X
W1SUM_X
0x88†
VARSUM_X
0x89
0x8A
VAR0SUM_X
VAR1SUM_X
Description
Configuration
The signed sum: W0SUM_X+W1SUM_X. Not used
for EQU[2:0] = 0 (I/O RAM 0x2106[7:5]) and
EQU[2:0] = 1.
The sum of Wh samples from each wattmeter
element.
LSBW = 9.4045*10-13 * VMAX * IMAX Wh.
The signed sum: VAR0SUM_X+VAR1SUM_X. Not
used for EQU[2:0] = 0 and EQU[2:0] = 1.
The sum of VARh samples from each wattmeter
element.
-13
LSBW = 9.4045*10 * VMAX * IMAX VARh.
Figure 35 (page 93)
Figure 37 (page 95)
Note:
†
71M6542 only.
Table 86: CE Transfer Variables (with Remote Sensor)
CE
Address
Name
0x84†
WSUM_X
0x85
0x86
W0SUM_X
W1SUM_X
0x88†
VARSUM_X
0x89
0x8A
VAR0SUM_X
VAR1SUM_X
Description
Configuration
The signed sum: W0SUM_X+W1SUM_X. Not used
for EQU[2:0] = 0 (I/O RAM 0x2106[7:5]) and
EQU[2:0] = 1.
The sum of Wh samples from each wattmeter
element.
LSB = 1.55124*10-12 * VMAX* IMAX Wh.
The signed sum: VAR0SUM_X+VAR1SUM_X. Not
used for EQU[2:0] = 0 and EQU[2:0] = 1.
The sum of VARh samples from each wattmeter
element.
-12
LSB = 1.55124*10 *VMAX* IMAX VARh.
Figure 36 (page 94)
Figure 38 (page 96)
Note:
†
71M6542 only.
WSUM_X (CE RAM 0x84) and VARSUM_X (CE RAM 0x88) are the signed sum of Phase-A and Phase-B Wh
or VARh values according to the metering equation specified in the I/O RAM control field EQU[2:0] (I/O
RAM 0x2106[7:5]). WxSUM_X (x = 0 or 1, CE RAM 0x85 and 0x86) is the Wh value accumulated for phase x
in the last accumulation interval and can be computed based on the specified LSB value.
130
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5.3.8.2 Instantaneous Energy Measurement Variables
IxSQSUM_X and VxSQSUM (see Table 87) are the sum of the squared current and voltage samples
acquired during the last accumulation interval.
Table 87: CE Energy Measurement Variables (with Local Sensors)
CE
Address
Name
0x8C
I0SQSUM_X
0x8D
I1SQSUM_X
†
0x90
V0SQSUM_X
0x91†
V1SQSUM_X
Configuration
Description
The sum of squared current samples from each
element.
-13
2 2
LSBI = 9.4045*10 IMAX A h
When EQU = 1, I0SQSUM_X is based on IA and
IB.
The sum of squared voltage samples from each
element.
-13
2 2
LSBV= 9.4045*10 VMAX V h
Figure 35 (page 93)
Figure 37 (page 95)
71M6542 only.
Table 88: CE Energy Measurement Variables (with Remote Sensor)
CE
Address
0x8C
I0SQSUM_X
0x8D
I1SQSUM_X
†
Name
0x90
V0SQSUM_X
0x91†
V1SQSUM_X
Description
Configuration
The sum of squared current samples from each
element.
-12
2 2
LSBI = 2.55872*10 * IMAX A h
When EQU = 1, I0SQSUM_X is based on IA and
IB.
The sum of squared voltage samples from each
element.
LSBV= 9.40448*10-13 * VMAX2 V2h
Figure 36 (page 94)
Figure 38 (page 96)
71M6542 only.
The RMS values can be computed by the MPU from the squared current and voltage samples as follows:
Ix RMS =
IxSQSUM ⋅ LSBI ⋅ 3600 ⋅ FS
N ACC
VxRMS =
VxSQSUM ⋅ LSBV ⋅ 3600 ⋅ FS
N ACC
Note: NACC = SUM_SAMPS[12:0] (CE RAM 0x23).
Other Transfer variables include those available for frequency and phase measurement, and those
reflecting the count of the zero-crossings of the mains voltage and the battery voltage. These transfer
variables are listed in Table 89.
MAINEDGE_X (CE RAM 0x83) reflects the number of half-cycles accounted for in the last accumulated
interval for the AC signal of the phase specified in the FREQSEL[1:0] field in CECONFIG (CE RAM 0x20[7:6]).
MAINEDGE_X is useful for implementing a real-time clock based on the input AC signal.
Rev 2
131
71M6541D/F/G and 71M6542F/G Data Sheet
Table 89: Other Transfer Variables
CE
Address
Name
Description
2520.6 Hz
≈ 0.509 ⋅ 10− 6 Hz(for Local)
32
2
2520.6 Hz
LSB ≡
≈ 0.587 ⋅ 10− 6 Hz(for Remote)
232
The number of edge crossings of the selected voltage in the previous
accumulation interval. Edge crossings are either direction and are
de-bounced.
Fundamental frequency: LSB ≡
0x82
FREQ_X
0x83
MAINEDGE_X
5.3.9
Pulse Generation
Table 90 describes the CE pulse generation parameters.
The combination of the CECONFIG PULSE_SLOW and PULSE_FAST bits (CE RAM 0x20[0:1]) controls the
speed of the pulse rate. The default values of 0 and 0 maintain the original pulse rate given by the Kh
equation.
WRATE (CE RAM 0x21) controls the number of pulses that are generated per measured Wh and VARh
quantities. The lower WRATE is, the slower the pulse rate for the measured energy quantity. The metering
constant Kh is derived from WRATE as the amount of energy measured for each pulse. That is, if Kh =
1Wh/pulse, a power applied to the meter of 120 V and 30 A results in one pulse per second. If the load
is 240 V at 150 A, ten pulses per second are generated.
Control is transferred to the MPU for pulse generation if EXT_PULSE = 1 (CE RAM 0x20[5]). In this case,
the pulse rate is determined by APULSEW and APULSER (CE RAM 0x45 and 0x49). The MPU has to
load the source for pulse generation in APULSEW and APULSER to generate pulses. Irrespective of the
EXT_PULSE status, the output pulse rate controlled by APULSEW and APULSER is implemented by the CE
only. By setting EXT_PULSE = 1, the MPU is providing the source for pulse generation. If EXT_PULSE is
0, W0SUM_X (CE RAM 0x85) and VAR0SUM_X (CE RAM 0x89) are the default pulse generation sources. In
this case, creep cannot be controlled since it is an MPU function.
The maximum pulse rate is 3*FS = 7.56 kHz.
See 2.3.6.2 VPULSE and WPULSE for details on how to adjust the timing of the output pulses.
The maximum time jitter is 1/6 of the multiplexer cycle period (nominally 67 µs) and is independent of the
number of pulses measured. Thus, if the pulse generator is monitored for one second, the peak jitter is
67 ppm. After 10 seconds, the peak jitter is 6.7 ppm. The average jitter is always zero. If it is attempted
to drive either pulse generator faster than its maximum rate, it simply outputs at its maximum rate without
exhibiting any rollover characteristics. The actual pulse rate, using WSUM as an example, is:
RATE =
WRATE ⋅ WSUM ⋅ FS ⋅ X
Hz ,
2 46
where FS = sampling frequency (2520.6 Hz), X = Pulse speed factor derived from the CE variables
PULSE_SLOW (CE RAM 0x20[0]) and PULSE_FAST (CE RAM 0x20[1]).
132
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 90: CE Pulse Generation Parameters
CE
Address
Name
Default
Description
Kh =
0x21
WRATE
547
0x22
0x23
KVAR
SUM_SAMPS
6444
2520
0x45
APULSEW
0
0x46
WPULSE_CTR
0
0x47
WPULSE_FRAC
0
0x48
0x49
0x4A
WSUM_ACCUM
APULSER
VPULSE_CTR
0
0
0
0x4B
VPULSE_FRAC
0
0x4C
VSUM_ACCUM
0
Rev 2
VMAX ⋅ IMAX ⋅ K
⋅ Wh / pulse
WRATE ⋅ N ACC ⋅ X
where:
K = 66.1782 (Local Sensors)
K = 109.1587 (Remote Sensor)
NACC = SUM_SAMPS[12:0] (CE RAM 0x23)
See Table 83 for the definition of X.
The default value yields 1.0 Wh/pulse for VMAX = 600 V and
IMAX = 208 A. The maximum value for WRATE is 32,768 (215).
Scale factor for VAR measurement.
SUM_SAMPS (NACC).
Wh pulse (WPULSE) generator input to be updated by the MPU
when using external pulse generation. The output pulse rate is:
APULSEW * FS * 2-32 * WRATE * X * 2-14.
This input is buffered and can be updated by the MPU during a
conversion interval. The change takes effect at the beginning of
the next interval.
WPULSE counter.
Unsigned numerator, containing a fraction of a pulse. The value
in this register always counts up towards the next pulse.
Roll-over accumulator for WPULSE.
VARh (VPULSE) pulse generator input.
VPULSE counter.
Unsigned numerator, containing a fraction of a pulse. The value
in this register always counts up towards the next pulse.
Roll-over accumulator for VPULSE.
133
71M6541D/F/G and 71M6542F/G Data Sheet
5.3.10 Other CE Parameters
Table 91 shows the CE parameters used for suppression of noise due to scaling and truncation effects.
Table 91: CE Parameters for Noise Suppression and Code Version
CE
Address
Name
Default
Description
QUANT_VA
0x25
0
QUANT_IA
0x26
0
Compensation factors for truncation and noise in voltage, current,
real energy and reactive energy for phase A.
QUANT_A
0x27
0
QUANT_VARA
0x28
0
QUANT_VB
0x29 †
0
Compensation factors for truncation and noise in voltage, current,
QUANT_IB
0x2A
0
real energy and reactive energy for phase B.
QUANT_B
0x2B
0
†
71M6542 only.
QUANT_VARB
0x2C
0
0x38
0x43453431
CE file name identifier in ASCII format (CE41a01f). These values
0x39
0x6130316B
are overwritten as soon as the CE starts
0x3A
0x00000000
LSB weights for use with Local Sensors:
QUANT _ Ix _ LSB = 5.08656 ⋅ 10 −13 ⋅ IMAX 2 ( Amps 2 )
QUANT _ Wx _ LSB = 1.04173 ⋅ 10 −9 ⋅ VMAX ⋅ IMAX (Watts)
QUANT _ VARx _ LSB = 1.04173 ⋅ 10 −9 ⋅ VMAX ⋅ IMAX (Vars)
LSB weights for use with the 71M6x01 isolated sensors:
QUANT _ Ix _ LSB = 1.38392 ⋅ 10−12 ⋅ IMAX 2 ( Amps 2 )
QUANT _ Wx _ LSB = 1.71829 ⋅ 10−9 ⋅ VMAX ⋅ IMAX (Watts)
QUANT _ VARx _ LSB = 1.71829 ⋅ 10−9 ⋅ VMAX ⋅ IMAX (Vars)
134
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5.3.11 CE Calibration Parameters
Table 92 lists the parameters that are typically entered to effect calibration of meter accuracy.
Table 92: CE Calibration Parameters
CE
Address
Name
Default
0x10
0x11
0x13
†
0x14
CAL_IA
CAL_VA
CAL_IB
CAL_VB
16384
16384
16384
16384
0x12
PHADJ_A
0
Description
These constants control the gain of their respective channels. The
nominal value for each parameter is 214 = 16384. The gain of each
channel is directly proportional to its CAL parameter. Thus, if the
gain of a channel is 1% slow, CAL should be increased by 1%.
Refer to the 71M6541 Demo Board User’s Manual for the equations
to calculate these calibration parameters.
†
71M6542 only.
These constants control the CT phase compensation. Compensation
does not occur when PHADJ_X = 0. As PHADJ_X is increased,
more compensation (lag) is introduced. The range is ± 215 – 1. If
it is desired to delay the current by the angle Φ, the equations are:
PHADJ _ X = 2 20
0x15
PHADJ_B
0
0.02229 ⋅ TANΦ
at 60Hz
0.1487 − 0.0131 ⋅ TANΦ
0.0155 ⋅ TANΦ
at 50Hz
0.1241 − 0.009695 ⋅ TANΦ
The shunt delay compensation is obtained using the equation
provided below:
 2πf 
 2πf
 + 2ab cos
a 2 cos 2 
2π
 fs 
 fs
DLYADJ _ X = ∆ deg rees (1 + 0.1∆ deg rees )214
360
 2πf 

c sin 
 fs 
PHADJ _ X = 2 20
0x12
DLYADJ_A
0

 + b

where:
a = 2A
b = A2 + 1
0x15
DLYADJ_B
0
 = 22 + 4 �
2
�+2

Where, f is the mains frequency and fs is the sampling frequency.
The table below provides the value of A for each current channel:
Value of A
(decimal)
Channel
Eq. 0 or 2
Eq. 1
DLYADJ_A
15811 / 214
6811 / 214
DLYADJ_B
-1384 / 214
-1384 / 214
Rev 2
135
71M6541D/F/G and 71M6542F/G Data Sheet
5.3.12 CE Flow Diagrams
Figure 44 through Figure 46 show the data flow through the CE in simplified form. Functions not shown
include delay compensation, sag detection, scaling and the processing of meter equations.
Figure 44: CE Data Flow: Multiplexer and ADC
Figure 45: CE Data Flow: Scaling, Gain Control, Intermediate Variables
136
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
SUM
Σ
W0
W1
Σ
VAR0
Σ
VAR1
Σ
W0SUM_X
MPU
W1SUM_X
VAR0SUM_X
VAR1SUM_X
SUM_SAMPS=2520
SQUARE
I0
SUM
I0SQ
I2
V0SQ
V0
V2
I1
I2
I1SQ
Σ
I0SQSUM_X
Σ
V0SQSUM_X
Σ
I1SQSUM_X
F0
Figure 46: CE Data Flow: Squaring and Summation Stages
Rev 2
137
71M6541D/F/G and 71M6542F/G Data Sheet
6
Electrical Specifications
This section provides the electrical specifications for the 71M654x. Please refer to the 71M6xxx Data
Sheet for the 71M6x01 electrical specifications, pin-out, and package mechanical data.
The devices are 100% production tested at room temperature, and performance over the full temperature
range is guaranteed by design.
6.1
Absolute Maximum Ratings
Table 93 shows the absolute maximum ratings for the device. Stresses beyond Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings only and functional operation at
these or any other conditions beyond those indicated under recommended operating conditions (see 6.3
Recommended Operating Conditions) is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability. All voltages are with respect to GNDA.
Table 93: Absolute Maximum Ratings
Voltage and Current
Supplies and Ground Pins
V3P3SYS, V3P3A
VBAT, VBAT_RTC
GNDD
Analog Output Pins
VREF
VDD
V3P3D
VLCD
Analog Input Pins
IAP-IAN, VA, IBP-IBN, VB† († 71M6542F/G
only)
XIN, XOUT
−0.5 V to 4.6 V
-0.5 V to 4.6 V
-0.1 V to +0.1 V
-10 mA to +10 mA,
-0.5 V to V3P3A+0.5 V
-10 mA to 10 mA,
-0.5 to 3.0 V
-10 mA to 10 mA,
-0.5 V to 4.6 V
-10 mA to 10 mA,
-0.5 V to 6 V
-10 mA to +10 mA
-0.5 V to V3P3A+0.5 V
-10 mA to +10 mA
-0.5 V to 3.0 V
SEG and SEGDIO Pins
Configured as SEG or COM drivers
Configured as Digital Inputs
Configured as Digital Outputs
-1 mA to 1 mA,
-0.5 V to VLCD+0.5 V
-10 mA to 10 mA,
-0.5 V to 6 V
-10 mA to 10 mA,
-0.5 V to V3P3D+0.5 V
Digital Pins
Inputs (PB, RESET, RX, ICE_E, TEST)
Outputs (TX)
Temperature and ESD Stress
Operating junction temperature (peak, 100ms)
Operating junction temperature (continuous)
Storage temperature
138
-10 mA to 10 mA,
-0.5 to 6 V
-10 mA to 10 mA,
-0.5 V to V3P3D+0.5 V
140 °C
125 °C
−45 °C to +165 °C
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Solder temperature – 10 second duration
ESD stress on all pins
6.2
+250 °C
±4 kV
Recommended External Components
Table 94: Recommended External Components
Name
C1
C2
CSYS
CVDD
From
V3P3A
V3P3D
V3P3SYS
VDD
To
GNDA
GNDD
GNDD
GNDD
CVLCD
VLCD
GNDD
XTAL
XIN
XOUT
CXS
XIN
GNDA
CXL
XOUT
GNDA
6.3
Function
Bypass capacitor for 3.3 V supply
Bypass capacitor for 3.3 V output
Bypass capacitor for V3P3SYS
Bypass capacitor for VDD
Bypass capacitor for VLCD pin (when
charge pump is used)
32.768 kHz crystal – electrically similar to
ECS .327-12.5-17X, Vishay XT26T or
Suntsu SCP6–32.768kHz TR (load
capacitance 12.5 pF).
Load capacitor values for crystal depend on
crystal specifications and board parasitics.
Nominal values are based on 4 pF board
capacitance and include an allowance for
chip capacitance.
Value
Unit
≥0.1 ±20%
0.1 ±20%
≥1.0 ±30%
0.1 ±20%
µF
µF
µF
µF
≥0.1 ±20%
µF
32.768
kHz
15 ±10%
pF
10 ±10%
pF
Recommended Operating Conditions
Unless otherwise specified, all parameters listed in 6.4 Performance Specifications and 6.5 Timing
Specifications are valid over the Recommended Operating Conditions provided in Table 95 below.
Table 95: Recommended Operating Conditions
Parameter
Condition
V3P3SYS and V3P3A Supply Voltage for
VBAT=0 V to 3.8 V
precision metering operation (MSN mode).
VBAT_RTC =0 V to
Voltages at VBAT and VBAT_RTC need
3.8 V
not be present.
VBAT Voltage (BRN mode). V3P3SYS is V3P3SYS < 2.8 V
below the 2.8 V comparator threshold.
and
Either V3P3SYS or VBAT_RTC must be
Max (VBAT_RTC,
high enough to power the RTC module.
V3P3SYS) > 2.0 V
VBAT_RTC Voltage. VBAT_RTC is not
needed to support the RTC and nonV3P3SYS<2.0 V
volatile memory unless V3P3SYS < 2.0 V
Operating Temperature
Notes:
1. GNDA and GNDD must be connected together.
2. V3P3SYS and V3P3A must be connected together.
Rev 2
Min
Typ
Max
Unit
3.0
3.6
V
2.5
3.8
V
2.0
3.8
V
-40
+85
ºC
139
71M6541D/F/G and 71M6542F/G Data Sheet
6.4
Performance Specifications
6.4.1
Input Logic Levels
Table 96: Input Logic Levels
Parameter
Condition
Min
Typ
Max
Unit
1
Digital high-level input voltage , VIH
2
1
Digital low-level input voltage , VIL
0.8
Input pullup current, IIL
E_RXTX, E_RST, E_TCLK
VIN=0 V,
10
100
OPT_RX, OPT_TX
ICE_E=3.3 V
10
100
SPI_CSZ (SEGDIO36)
10
10
Other digital inputs
-1
0
1
Input pull down current, IIH
VIN=V3P3D
ICE_E, RESET, TEST
10
100
Other digital inputs
-1
0
1
Note:
1. In battery powered modes, digital inputs should be below 0.1 V or above VBAT – 0.1 V to
minimize battery current.
6.4.2
V
V
µA
µA
µΩ
µA
µA
µA
Output Logic Levels
Table 97: Output Logic Levels
Parameter
Digital high-level output voltage
VOH
Digital low-level output voltage
VOL
Condition
ILOAD = 1 mA
ILOAD = 15 mA
(see notes 1, 2)
ILOAD = 1 mA
ILOAD = 15 mA
(see note 1)
Min
V3P3D–0.4
V3P3D-0.6
0
0
Typ
Max
Unit
V
V
0.4
0.8
V
V
Note:
1. Guaranteed by design, not production tested.
2. Caution: The sum of all pull up currents must be compatible with the on-resistance of the
internal V3P3D switch. See 6.4.6 V3P3D Switch on page 143.
140
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.3
Battery Monitor
Table 98: Battery Monitor Performance Specifications (TEMP_BAT= 1)
Parameter
BV: Battery Voltage
(definition)
Measurement Error
 BV

100 ⋅ 
− 1
 VBAT 
Input impedance in
continuous measurement,
MSN mode.
V(VBAT_RTC)/I(VBAT_RTC)
Load applied with BCURR
IBAT(BCURR=1) - IBAT(BCURR=0)
6.4.4
Condition
Min
Typ
Max
Unit
 = 3.3 + ( − 142) ∙ 0.0246 +  ∙ 297
MSN mode, TEMP_PWR = 1
V
 = 3.291 + ( − 142) ∙ 0.0255 +  ∙ 328
BRN mode,
TEMP_PWR=TEMP_BSEL
VBAT =
2.0 V
2.5 V
3.0 V
4.0 V
-7.5
-5
-3
-3
V3P3 = 3.3 V,
TEMP_BSEL = 0,
TEMP_PER = 111,
VBAT_RTC = 3.6 V,
7.5
5
3
5
1
MΩ
50
V3P3 = 3.3 V
%
100
140
µA
Temperature Monitor
Table 99. Temperature Monitor
Parameter
Condition
Min
Typ
Max
Unit
In MSN, TEMP_PWR=1:
Temperature Measurement
Equation
Temperature Error
VBAT_RTC charge per
measurement
 = 0.325 ∙  + 22
 = 0.325 ∙  + 0.00218 ∙  2 − 0.609 ∙  + 64.4
TA=+22°C
TEMP_BSEL = 0,
TEMP_PWR=0,
SLP Mode,
VBAT_RTC = 3.6 V
TEMP_PWR = 0,
Duration of temperature
TEMP_PER = 7,
measurement after setting
SLP Mode,
TEMP_START
VBAT_RTC = 3.6 V
Force V3P3D = 1.0 V
(see note 1)
Notes:
1. Guaranteed by design; not production tested.
Rev 2
°C
In BRN, TEMP_PWR = TEMP_BSEL:
-2
+2
16
15
°C
µC
60
ms
141
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.5
Supply Current
The supply currents provided in Table 100 below include only the current consumed by the 71M654x.
Refer to the 71M6xxx Data Sheet for additional current required when using a 71M6x01 remote sensor.
Table 100: Supply Current Performance Specifications
Parameter
Condition
I1:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
Single-phase: 2 Currents, 1 Voltage
V3P3A = V3P3SYS = 3.3 V,
MPU_DIV [2:0]= 3 (614 kHz MPU clock),
No Flash memory write,
RTM_E=0, PRE_E=0, CE_E=1, ADC_E=1,
ADC_DIV=1, MUX_DIV[3:0]=3,
FIR_LEN[1:0]=1, PLL_FAST=1
I1a:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
I1b:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
I1c:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
I2:
V3P3A + V3P3SYS dynamic
current
Min
Typ
Max
Unit
5.5
6.7
mA
2.6
3.5
mA
Same as I1, except PRE_E = 1
5.7
6.9
mA
Same as I1, except PLL_FAST = 0 and
PRE_E = 1
2.6
3.6
mA
0.4
0.6
mA/
MHz
0
2.4
0.4
24
3.0
1.1
0
300
3.2
108
36
11
3.4
+300
nA
mA
nA
µA
µA
µA
nA
0
240
1.8
0.7
1.5
300
320
4.1
1.7
3.2
nA
nA
µA
µA
µA
7.1
8.7
mA
Same as I1, except PLL_FAST=0
Same as I1, except with variation of
MPU_DIV[2:0].
I MPU_DIV = 0 - I MPU_DIV = 3
4.3
VBAT current
I3: MSN Mode
I4: BRN Mode
I5: LCD Mode (ext. VLCD)
Note 1
I6: LCD Mode (boost, DAC)
Note 1
I7: LCD Mode (DAC)
I8: LCD Mode (VBAT)Note 1
I9: SLP Mode
-300
CE_E=0
LCD_VMODE[1:0]=3, also see note 2
LCD_VMODE[1:0]=2, also see note 3
LCD_VMODE[1:0]=1, also see note 3
LCD_VMODE[1:0]=0, also see note 3
SLP Mode
-300
VBAT_RTC current
I10: MSN
I11: BRN
I12: LCD Mode
I13: SLP Mode
I14: SLP Mode (see note 1)
I15:
V3P3A + V3P3SYS current,
Write Flash with ICE
-300
LCD_VMODE[1:0]=2, also see note 2
TA ≤ 25 °C
TA = 85 °C
Same as I1, except write Flash at maximum rate,
CE_E=0, ADC_E=0.
Notes:
1.
2.
3.
142
Guaranteed by design; not production tested.
LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, all LCD_MAPn bits = 1, LCD_BLANK=0,
LCD_ON=1.
LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, all LCD_MAPn bits = 0.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.6
V3P3D Switch
Table 101: V3P3D Switch Performance Specifications
Parameter
On resistance – V3P3SYS to V3P3D
On resistance – VBAT to V3P3D
V3P3D IOH, MSN
V3P3D IOH, BRN
6.4.7
Condition
| IV3P3D | ≤ 1 mA
| IV3P3D | ≤ 1 mA,
VBAT>2.5V
V3P3SYS = 3V
V3P3D = 2.9V
VBAT = 2.6V
V3P3D = 2.5V
Min
Typ
Max
10
Unit
Ω
10
Ω
10
mA
10
mA
Internal Power Fault Comparators
Table 102. Internal Power Fault Comparator Specifications
Parameter
Condition
Overall response time
100mV overdrive, falling
100mV overdrive, rising
Falling Threshold
3.0 V Comparator
2.8 V Comparator
Difference 3.0V and 2.8V Comparators
Falling Threshold
2.25 V Comparator
2.0 V Comparator
VDD (@VBAT=3.0V) – 2.25V Comparator
Difference 2.25V and 2.0V Comparators
Hysteresis,
(Rising Threshold - Falling Threshold)
3.0 V Comparator
2.8 V Comparator
2.25 V Comparator
2.0 V Comparator
6.4.8
Min
Typ
20
Max
Unit
200
200
µs
µs
V3P3 falling
2.83
2.75
50
2.93
2.81
136
3.03
2.87
220
V
V
mV
2.2
1.90
0.25
0.15
2.25
2.00
0.35
0.25
2.5
2.20
0.45
0.35
V
V
V
V
22
25
10
10
45
42
33
28
65
60
60
60
mV
mV
mV
mV
VDD falling
TA = 22 °C
2.5 V Voltage Regulator – System Power
Table 103: 2.5 V Voltage Regulator Performance Specifications
Parameter
V2P5
V2P5 load regulation
Voltage overhead V3P3SYS-V2P5
Rev 2
Condition
V3P3 = 3.0 V - 3.8 V
ILOAD = 0 mA
VBAT = 3.3 V , V3P3 = 0 V
ILOAD = 0 mA to 1 mA
ILOAD = 5 mA,
Reduce V3P3D until V2P5
drops 200 mV
Min
Typ
Max
Unit
2.55
2.65
2.75
V
40
mV
440
mV
143
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.9
2.5 V Voltage Regulator – Battery Power
Unless otherwise specified, V3P3SYS = V3P3A = 0, PB=GND (BRN).
Table 104: Low-Power Voltage Regulator Performance Specifications
Parameter
Condition
VBAT = 3.0 V - 3.8 V,
V3P3 = 0 V, ILOAD = 0 mA
VBAT = 3.3 V, V3P3 = 0 V,
ILOAD = 0 mA to 1 mA
ILOAD = 0ma, VBAT = 2.0 V,
V3P3 = 0 V.
V2P5
V2P5 load regulation
Voltage Overhead 2V − VBAT-VDD
Min
Typ
Max
Unit
2.55
2.65
2.75
V
40
mV
200
mV
6.4.10 Crystal Oscillator
Measurement conditions: Crystal disconnected, test load of 200 pF/100 kΩ between XOUT and GNDD.
Table 105: Crystal Oscillator Performance Specifications
Parameter
Condition
Maximum Output Power to Crystal
XIN to XOUT Capacitance
(see note 1)
Crystal connected, see note 1
Capacitance change on XOUT
Min
RTC_ADJ = 7F to 0,
Bias voltage = unbiased
Vpp = 0.1 V
Typ
Max
Unit
1
μW
3
pF
15
pF
Notes:
1. Guaranteed by design; not production tested.
6.4.11 Phase-Locked Loop (PLL)
Table 106: PLL Performance Specifications
Parameter
PLL Power up Settling Time
(see note 1)
PLL_FAST settling time
PLL_FAST rise (see note 1)
PLL_FAST fall (see note 1)
PLL SLP to MSN Settling Time
(see note 2)
PLL power up overshoot
(see note 1)
Condition
PLL_FAST = 0, V3P3 = 0 V to 3.3 V
step, measured from first edge of
MCK
V3P3 = 0 V, VBAT = 3.8 V to 2.0 V
Min
Typ
Max
Unit
5
ms
5
5
ms
ms
PLL_FAST = 0
5
ms
PLL_FAST = 0
2.5
MHz
Notes:
1. Guaranteed by design; not production tested.
144
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.12 LCD Drivers
Table 107: LCD Driver Performance Specifications
PARAMETER
VLCD Current
(see Notes 1 to 4)
Notes:
1.
2.
3.
4.
Rev 2
CONDITION
MIN
TYP
VLCD=3.3, all LCD map bits=0
VLCD=5.0, all LCD map bits=0
MAX
2
3
UNIT
uA
uA
These specifications apply to all COM and SEG pins.
VLCD = 2.5 V to 5 V.
LCD_VMODE=3, LCD_ON=1, LCD_BLANK=0, LCD_MODE=6, LCD_CLK=2.
Output load is 74 pF per SEG and COM pin.
145
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.13 VLCD Generator
1
Table 108: LCD Driver Performance Specifications
Parameter
VSYS to VLCD switch impedance
VBAT to VLCD switch impedance
LCD Boost Frequency
VLCD IOH current
(VLCD(0)-VLCD(IOH)<0.25)
Condition
V3P3 = 3.3 V,
RVLCD=removed, LCD_BAT=0,
LCD_VMODE[1:0]=0,
∆ILCD=10 µA
V3P3 = 0 V, VBAT = 2.5 V,
RVLCD =removed, LCD_BAT =1,
LCD_VMODE[1:0]=0,
∆ILCD=10 µA
LCD_VMODE[1:0] = 2,
RVLCD = removed,
CVLCD = removed
PLL_FAST=1
PLL_FAST=0
LCD_VMODE[1:0] = 2,
LCD_CLK[1:0] = 2,
RVLCD = removed,
V3P3 = 3.3V,
LCD_DAC[4:0] = 1F
Min
Typ
Max
Unit
750
Ω
700
Ω
820
786
kHz
kHz
10
µA
From LCDADJ0 and LCDADJ12 fuses:
12 − 0
(_) = 5 �0 +
_�
12
_
 (_) = 2.65 + 2.65
+ (_)
31
The above equations describe the nominal value of VLCD for a specific LCD_DAC value. The
specifications below list the maximum deviation between actual VLCD and VLCDnom. Note that when
VCC and boost are insufficient, the LCD DAC will not reach its target value and a large negative error
will occur.
LCD_DAC Error. VLCD-VLCDnom
(see note 2)
Full Scale, with Boost
V3P3 =3.6 V
V3P3 =3.0 V
VBAT=4.0 V, V3P3=0, BRN Mode
VBAT=2.5 V, V3P3=0, BRN Mode
LCD_DAC Error. VLCD-VLCDnom
DAC=12, with Boost
V3P3 = 3.6 V
V3P3 = 3.0 V
VBAT = 2.5 V, V3P3 = 0 V, BRN Mode
LCD_DAC Error. VLCD-VLCDnom
Zero Scale, with Boost
V3P3 = 3.6 V
V3P3 = 3.0 V
VBAT = 4.0 V, V3P3 = 0 V, BRN Mode
(see note 2)
VBAT = 2.5 V, V3P3 = 0 V, BRN Mode
LCD_DAC Error. VLCD-VLCDnom
Full Scale, no Boost
V3P3 = 3.6 V (see note 2)
V3P3 = 3.0 V (see note 2)
VBAT = 4.0 V, V3P3 = 0 V, BRN Mode
VBAT = 2.5 V, V3P3 = 0 V, BRN Mode
146
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] = 1F,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] = C,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] =0,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
LCD_VMODE[1:0] = 1,
LCD_DAC[4:0] = 1F,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.15
-0.4
-0.15
-1.3
0.15
0.15
0.15
V
V
V
V
-0.15
-0.15
-0.15
0.15
0.15
0.15
V
V
V
-0.15
-0.15
-0.15
0.15
0.15
0.15
V
V
V
-0.15
0.15
V
-2.1
-2.8
-1.8
-3.2
V
V
V
V
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Parameter
Condition
Min
Typ
Max
Unit
LCD_DAC Error. VLCD-VLCDnom
LCD_VMODE[1:0] = 1,
LCD_DAC[4:0] = C,
DAC=12, no Boost
-0.5
V
LCD_CLK[1:0]=2,
V3P3 = 3.6 V
-1.1
LCD_MODE[2:0]=6
V
V3P3 = 3.0 V
2
2
-0.15
0.15
V
VBAT = 4.0 V, V3P3 = 0 V, BRN Mode
2
-1.5
V
VBAT = 2.5 V, V3P3 = 0 V, BRN Mode
LCD_DAC Error. VLCD-VLCDnom
LCD_VMODE[1:0] = 1,
LCD_DAC[4:0] = 0,
Zero Scale, no Boost
LCD_CLK[1:0]=2,
-0.15
0.15
V
V3P3 = 3.6 V
LCD_MODE[2:0]=6
-0.15
0.15
V
V3P3 = 3.0 V
-0.15
0.15
V
VBAT = 4.0 V, V3P3 = 0 V, BRN Mode
-0.45
0.15
V
VBAT = 2.5 V, V3P3 = 0 V, BRN Mode
LCD_DAC Error. VLCD-VLCDnom
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] = 1F,
Full Scale, with Boost, LCD mode
-0.15
0.15
V
LCD_CLK[1:0]=2,
VBAT = 4.0 V, V3P3 = 0 V
-1.3
LCD_MODE[2:0]=6
V
VBAT = 2.5 V, V3P3 = 0 V
Notes:
1. The following test conditions also apply to all parameters provided in this table: bypass capacitor CVLCD ≥
0.1 µF, test load RVLCD = 500 kΩ, no display, all SEGDIO pins configured as DIO.
2. Guaranteed by design; not production tested.
Rev 2
147
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.14 VREF
Table 109 shows the performance specifications for the ADC reference voltage (VREF).
Table 109: VREF Performance Specifications
Parameter
VREF output voltage,
VREF(22)
VREF output voltage,
VREF(22)
Condition
TA = 22 ºC
VREF power supply sensitivity
ΔVREF / ΔV3P3A
V3P3A = 3.0 to 3.6 V
VNOM definition (see note 2)
VNOM temperature
coefficients:
TC1 =
TC2 =
Max
Unit
1.193
1.195
1.197
V
1.195
VREF_CAL = 1,
ILOAD = 10 µA, -10 µA
VREF chop step, trimmed
Typ
PLL_FAST=0
VREF output impedance
VREF input impedance
Min
VREF_DIS = 1,
VREF = 1.3 V to 1.7 V
VREF(CHOP=01) −
VREF(CHOP=10)
-1.5
V
3.2
kΩ
1.5
mV/V
kΩ
100
-10
0
10
VNOM (T ) = VREF (22) + (T − 22)TC1 + (T − 22) 2 TC 2
275 − 4.95 ⋅ TRIMT
mV
V
µV/°C
µV/°C2
−0.557 + 0.00028 ⋅ TRIMT
VREF(T) deviation from
VNOM(T) (see note 1):
VREF (T ) − VNOM (T ) 106
VNOM (T )
62
VREF aging
-40
+40
±25
ppm/°C
ppm/
year
Notes:
1.
2.
3.
148
Guaranteed by design; not production tested.
This relationship describes the nominal behavior of VREF at different temperatures, as governed by a
st
nd
second order polynomial of 1 and 2 order coefficients TC1 and TC2.
For the parameters in this table, unless otherwise specified, VREF_DIS = 0, PLL_FAST=1.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.15 ADC Converter
Table 110. ADC Converter Performance Specifications
Parameter
Condition
Recommended Input Range
(Vin - V3P3A)
Voltage to Current Crosstalk
6
10 *Vcrosstalk
cos(∠Vin − ∠Vcrosstalk )
Vin
(see note 1)
Input Impedance, no pre-amp
ADC Gain Error vs %Power Supply
Variation
10 6 ∆Nout PK 357 nV / VIN
100 ∆V 3P3 A / 3.3
Input Offset
IADC0=IADC1=V3P3A
IADC0=V3P3A
THD @ 250mVpk
Name
FIR_LEN
A
B
C
D
E
F
G
H
J
ADC_DIV
0
1
0
1
2
0
0
1
2
0
0
0
0
0
1
1
1
1
PLL_FAST
0
0
1
1
1
0
1
1
1
MUX_DIV
3
2
11
6
4
2
6
3
2
FIR_LEN
A
B
C
D
E
F
G
H
J
ADC_DIV
0
1
0
1
2
0
0
1
2
0
0
0
0
0
1
1
1
1
PLL_FAST
0
0
1
1
1
0
1
1
1
MUX_DIV
3
2
11
6
4
2
6
3
2
Typ
Max
Unit
-250
250
mV
peak
-10
10
μV/V
40
90
kΩ
50
ppm / %
10
10
mV
mV
Vin=200 mV pk, 65 Hz
V3P3A=3.0 V, 3.6 V
DIFF0_E=1, PRE_E=0
DIFF0_E=0, PRE_E=0
THD @ 20mVpk
Name
Vin = 200 mV peak,
65 Hz, on VADC10 (VA)
or VADC9 (VB)†
†71M6542F/G only.
Vcrosstalk = largest
measurement on IAP-IAN
or IBP-IBN
Vin=65 Hz
Min
VIN = 65Hz, 250mVpk,
64kpts FFT, Blackman Harris
Window.
VIN = 65Hz, 20mVpk,
64kpts FFT, Blackman Harris
Window.
-10
-10
A
B
C
D
E
F
G
H
J
-82
-84
-83
-86
A
B
C
D
E
F
G
H
J
-75
-75
-75
-75
-75
-75
-75
-75
-75
dB
A
B
C
D
E
F
G
H
J
-85
-91
-85
-91
-93
-85
-85
-91
-93
dB
A
B
C
D
E
F
G
H
J
3470
406
3040
357
151
3470
3040
357
151
nV
LSB Size:
Name
A
B
C
D
E
F
G
H
J
FIR_LEN
ADC_DIV
0
1
0
1
2
0
0
1
2
0
0
0
0
0
1
1
1
1
PLL_FAST
0
0
1
1
1
0
1
1
1
MUX_DIV
3
2
11
6
4
2
6
3
2
Digital Full-Scale:
Name
A
B
C
D
E
F
G
H
J
Rev 2
FIR_LEN
0
1
0
1
2
0
0
1
2
ADC_DIV
0
0
0
0
0
1
1
1
1
PLL_FAST
0
0
1
1
1
0
1
1
1
MUX_DIV
3
2
11
6
4
2
6
3
2
Vin=65Hz, 20mVpk,
64kpts FFT, BlackmanHarris window
A: ±91125
B: ±778688
C: ±103823
D: ±884736
E: ±2097152
F: ±91125
G: ±103823
H: ±884736
J: ±2097152
LSB
149
71M6541D/F/G and 71M6542F/G Data Sheet
Notes:
1. Guaranteed by design; not production tested.
2. Unless stated otherwise, the following test conditions apply to all the parameters provided in
this table: FIR_LEN[1:0]=1, VREF_DIS=0, PLL_FAST=1, ADC_DIV=0, MUX_DIV=6, LSB values
do not include the 9-bit left shift at CE input.
6.4.16 Pre-Amplifier for IAP-IAN
Table 111: Pre-Amplifier Performance Specifications
PARAMETER
Differential Gain
Vin=30mV differential
Vin=15mV differential (see note 1)
Gain Variation vs V3P3
Vin=30mV differential (see note 1)
Gain Variation vs Temp
Vin=30mV differential (see note 1)
Phase Shift,
Vin=30mV differential (see note 1)
Preamp input current
IADC0
IADC1
Preamp+ADC THD
Vin=30mV differential
Vin=15mV differential
CONDITION
TA= +25⁰C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1,
2520Hz sample rate
V3P3 =
2.97 V, 3.63 V
TA = -40⁰C, 85⁰C
TA=25⁰C,
V3P3=3.3 V
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1
2520Hz sample rate,
IADC0=IADC1=V3P3
TA=25⁰C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1,
2520Hz sample rate.
TA=25⁰C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1,
2520Hz sample rate
Preamp Offset
IADC0=IADC1=V3P3+30mV
IADC0=IADC1= V3P3+15mV
IADC0=IADC1= V3P3
IADC0=IADC1= V3P3-15mV
IADC0=IADC1= V3P3-30mV
Notes:
1. Guaranteed by design; not production tested.
150
MIN
TYP
MAX
UNIT
7.8
7.8
7.92
7.92
8.0
8.0
V/V
V/V
100
ppm/%
-80
ppm/C
6
mº
16
16
uA
uA
-100
10
-25
-6
4
4
9
9
-82
-86
dB
dB
-0.63
-0.57
-0.56
-0.56
-0.55
mV
mV
mV
mV
mV
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
6.5
Timing Specifications
6.5.1
Flash Memory
Table 112: Flash Memory Timing Specifications
Parameter
Condition
Flash write cycles
Flash data retention
-40 °C to +85 °C
25 °C
85 °C
Min
Typ
Max
20,000
100
10
Cycles
Years
Flash byte writes between page or
mass erase operations
Write Time per Byte
Page Erase (1024 bytes)
Mass Erase
6.5.2
Unit
2
Cycles
21
21
21
µs
ms
Ms
SPI Slave
Table 113. SPI Slave Timing Specifications
Parameter
SPI Setup Time
SPI Hold Time
SPI Output Delay
SPI Recovery Time
SPI Removal Time
SPI Clock High
SPI Clock Low
SPI Clock Freq
SPI Transaction Space
6.5.3
Condition
SPI_DI to SPI_CK rise
SPI_CK rise to SPI_DI
SPI_CK fall to SPI_D0
SPI_CSZ fall to SPI_CK
SPI_CK to SPI_CSZ rise
SPI Freq/MPU Freq
SPI_CSZ rise to SPI_CSZ fall
Min
10
10
Typ
Max
40
10
15
40
40
2.0
4.5
Unit
ns
ns
ns
ns
ns
ns
ns
MHz/MHz
MPU Cycles
EEPROM Interface
Table 114: EEPROM Interface Timing
Parameter
Condition
2
Write Clock frequency (I C)
Write Clock frequency (3-wire)
Rev 2
CKMPU = 4.9 MHz,
Using interrupts
CKMPU = 4.9 MHz,
bit-banging DIO2/3
PLL_FAST = 0
CKMPU = 4.9 MHz
PLL_FAST = 0
PLL_FAST = 1
Min
Typ
Max
Unit
310
kHz
100
kHz
160
500
kHz
151
71M6541D/F/G and 71M6542F/G Data Sheet
6.5.4
RESET Pin
Table 115: RESET Pin Timing
Parameter
Condition
Reset pulse width
Reset pulse fall time (see note 1)
Notes:
1. Guaranteed by design; not production tested.
6.5.5
Min
Typ
Max
Unit
1
µs
µs
5
RTC
Table 116: RTC Range for Date
Parameter
Range for date
152
Condition
Min
Typ
Max
Unit
2000
-
2255
Year
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
6.6
Package Outline Drawings
6.6.1
64-Pin LQFP Outline Package Drawing
11.7
12.3
11.7
+
12.3
PIN No. 1 Indicator
9.8
10.2
0.50 Typ.
0.60 Typ.
0.00
0.20
0.14
0.28
1.40
1.60
Figure 47: 64-pin LQFP Package Outline
Rev 2
153
71M6541D/F/G and 71M6542F/G Data Sheet
6.6.2
100-Pin LQFP Package Outline Drawing
Controlling dimensions are in mm.
15.7(0.618)
16.3(0.641)
1
15.7(0.618)
16.3(0.641)
Top View
14.000 +/- 0.200
MAX. 1.600
1.50 +/- 0.10
0.225 +/- 0.045
0.50 TYP.
0.10 +/- 0.10
0.60 TYP>
Side View
Figure 48: 100-pin LQFP Package Outline
154
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Package Markings
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
71M6541DIGT.428AB
104224TH
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
71M6542G-IGT
110124TK
445AP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
6.7
Figure 49. Package Markings (Examples)
Figure 49 provides an example of the package markings for the 64-pin and 100-pin packages. Package
markings comprise three lines of text and are as described in Table 117 and Table 118 below.
Line No.
Table 117. 71M6541 Package Markings
Markings
Description
1
71M6541D-
2
IGT.428AB
3
104224TH
Part number (‘IGT’ wraps to the next line)
Refer to Table 122.
The five characters to the right of the dot
(i.e., 428AB) are the lot code.
The first four digits to the left are the year
and week of manufacture as YYWW. In
this example, the date code is 1042 which
represents year 2010, week 42.
The last four characters (i.e., 24TH) are
reserved for Maxim internal use only.
Line No.
1
2
Table 118. 71M6542 Package Markings
Markings
Description
71M6542G-IGT
110124TK
Part number. Refer to Table 122.
The first four digits to the left are the year
and week of manufacture as YYWW. In
this example, the date code is 1101 which
represents year 2011, week 1.
The last four characters (i.e., 24TK) are
reserved for Maxim internal use only.
3
Rev 2
445AP
A five character lot code.
155
71M6541D/F/G and 71M6542F/G Data Sheet
Pinout Diagrams
6.8.1
71M6541D/F/G LQFP-64 Package Pinout
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SPI_CKI/SEGDIO39
SEGDIO44
SEGDIO45
TMUX2OUT/SEG46
TMUXOUT/SEG47
RESET
PB
VLCD
VREF
IAP
IAN
V3P3A
VA
TEST
GNDA
XOUT
6.8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Teridian
71M6541D
71M6541F
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
XIN
VBAT_RTC
VBAT
V3P3SYS
IBP
IBN
GNDD
V3P3D
VDD
ICE_E
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
RX
TX
OPT_TX/SEGDIO51
SEGDIO14
SEGDIO13
SEGDIO12
SEGDIO11
SEGDIO10
SEGDIO9
SEGDIO8/DI
SEGDIO7/YPULSE
SEGDIO6/XPULSE
SEGDIO5
SEGDIO4
SEGDIO3/SDATA
SEGDIO2/SDCK
SEGDIO1/VPULSE
SEGDIO0/WPULSE
OPT_RX/SEGDIO55
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SPI_DI/SEGDIO38
SPI_DO/SEGDIO37
SPI_CSZ/SEGDIO36
COM0
COM1
COM2
COM3
SEGDIO27/COM4
SEGDIO26/COM5
SEGDIO25
SEGDIO24
SEGDIO23
SEGDIO22
SEGDIO21
SEGDIO20
SEGDIO19
Figure 50: Pinout for the 71M6541D/F/G (LQFP-64 Package)
156
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
71M6542F/G LQFP-100 Package Pinout
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
SPI_CKI/SEGDIO39
SEGDIO40
SEGDIO41
SEGDIO42
SEGDIO43
SEGDIO44
SEGDIO45
TMUX2OUT/SEG46
TMUXOUT/SEG47
RESET
PB
VLCD
VREF
IAP
IAN
V3P3A
NC
VB
VA
TEST
GNDA
NC
NC
NC
XOUT
6.8.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Teridian
71M6542F
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
XIN
NC
NC
GNDA
VBAT_RTC
VBAT
V3P3SYS
IBP
IBN
NC
NC
NC
NC
GNDD
V3P3D
VDD
ICE_E
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
RX
TX
OPT_TX/SEGDIO51
SEGDIO52
SEGDIO53
NC
SEGDIO17
SEGDIO16
SEGDIO15
SEGDIO14
SEGDIO13
SEGDIO12
SEGDIO11
SEGDIO10
SEGDIO9
SEGDIO8/DI
SEGDIO7/YPULSE
SEGDIO6/XPULSE
SEGDIO5
NC
SEGDIO4
SEGDIO3/SDATA
SEGDIO2/SDCK
SEGDIO1/VPULSE
SEGDIO0/WPULSE
OPT_RX/SEGDIO55
SEGDIO54
NC
NC
NC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SPI_DI/SEGDIO38
SPI_DO/SEGDIO37
SPI_CSZ/SEGDIO36
SEGDIO35
SEGDIO34
SEGDIO33
SEGDIO32
SEGDIO31
SEGDIO30
SEGDIO29
SEGDIO28
COM0
COM1
COM2
COM3
SEGDIO27/COM4
SEGDIO26/COM5
SEGDIO25
SEGDIO24
SEGDIO23
SEGDIO22
SEGDIO21
SEGDIO20
SEGDIO19
SEGDIO18
Figure 51: Pinout for the 71M6542F/G (LQFP-100 Package)
Rev 2
157
71M6541D/F/G and 71M6542F/G Data Sheet
6.9
Pin Descriptions
6.9.1
Power and Ground Pins
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output.
The circuit number denotes the equivalent circuit, as specified under 6.9.4 I/O Equivalent Circuits.
.
Table 119: Power and Ground Pins
Pin
Pin
(64 pin)
(100-pin)
50
Name
Type
Circuit
72, 80
GNDA
P
–
42
62
GNDD
P
–
53
85
V3P3A
P
–
45
69
V3P3SYS
P
–
41
61
V3P3D
O
13
40
60
VDD
O
–
57
89
VLCD
O
–
46
70
VBAT
P
12
47
71
VBAT_RTC
P
12
158
Description
Analog ground: This pin should be connected directly to
the ground plane.
Digital ground: This pin should be connected directly to
the ground plane.
Analog power supply: A 3.3 V power supply should be
connected to this pin. V3P3A must be the same
voltage as V3P3SYS.
System 3.3 V supply. This pin should be connected to a
3.3 V power supply.
Auxiliary voltage output of the chip. In mission mode,
this pin is connected to V3P3SYS by the internal
selection switch. In BRN mode, it is internally
connected to VBAT. V3P3D is floating in LCD and
sleep mode. A 0.1 µF bypass capacitor to ground
must be connected to this pin.
The output of the 2.5V regulator. This pin is powered
in MSN and BRN modes. A 0.1 µF bypass capacitor to
ground should be connected to this pin.
The output of the LCD DAC. A 0.1 µF bypass
capacitor to ground should be connected to this pin.
Battery backup pin to support the battery modes (BRN,
LCD). A battery or super-capacitor is to be connected
between VBAT and GNDD. If no battery is used,
connect VBAT to V3P3SYS.
RTC and oscillator power supply. A battery or supercapacitor is to be connected between VBAT and
GNDD. If no battery is used, connect VBAT_RTC to
V3P3SYS.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
6.9.2
Analog Pins
Table 120: Analog Pins
†
Pin
Pin
(64 pin)
(100-pin)
Name
55
54
87
86
IAPIAN
44
43
68
67
IBPIBN
52
--
82
83
56
48
49
Type
Circuit
I
6
VA
†
VB
I
6
88
VREF
O
9
75
76
XIN
XOUT
I
O
8
Description
Differential or single-ended Line Current Sense Inputs:
These pins are voltage inputs to the internal A/D
converter. Typically, they are connected to the outputs
of current sensors. Unused pins must be tied to
V3P3A.
Pins IBP-IBN may be configured for communication with
the remote sensor interface (71M6x01). When RMT_E =
1 (I/O RAM 0x2709[3]), the IBP-IBN pins become
balanced differential pair. If unused, RMT_E must be
zero and IBP-IBN must tied to V3P3A.
Line Voltage Sense Inputs: These pins are voltage
inputs to the internal A/D converter. Typically, they are
connected to the outputs of resistor dividers. Unused
pins must be tied to V3P3A.
Voltage Reference for the ADC. This pin should be left
unconnected (floating).
Crystal Inputs: A 32 kHz crystal should be connected
across these pins. Typically, a 15 pF capacitor is also
connected from XIN to GNDA and a
10 pF capacitor is connected from XOUT to GNDA. It
is important to minimize the capacitance between these
pins. See the crystal manufacturer datasheet for details.
If an external clock is used, a 150 mV (p-p) clock signal
should be applied to XIN, and XOUT should be left
unconnected.
Pin VB only available on 71M6542F/G.
Rev 2
159
71M6541D/F/G and 71M6542F/G Data Sheet
6.9.3
Digital Pins
Table 121 lists the digital pins. Pin types: P = Power, O = Output, I = Input, I/O = Input/Output, N/C = no
connect. The circuit number denotes the equivalent circuit, as specified in 6.9.4 I/O Equivalent Circuits.
Table 121: Digital Pins
Pin
(64-pin)
Pin
(100-pin)
Name
Type
Circuit
4-7
12–15
COM0–COM3
O
5
31
45
SEGDIO0/WPULSE
30
44
SEGDIO1/VPULSE
29
43
SEGDIO2/SDCK
28
42
SEGDIO3/SDATA
27
41
SEGDIO4
26
39
SEGDIO5
25
38
SEGDIO6/XPULSE
24
37
SEGDIO7/YPULSE
23
36
SEGDIO8/DI
22-17
35–30
SEGDIO[9:14]
--
29-27
SEGDIO[15:17]
--
25
SEGDIO[18]
16-10
24–18
SEGDIO[19:25]
--
11–4
SEGDIO[28:35]
63-62
95-94
SEGDIO[44:45]
--
99–96
SEGDIO[40:43]
--
52
SEGDIO52
--
51
SEGDIO53
--
47
SEGDIO54
9
17
SEGDIO26/COM5
8
16
SEGDIO27/COM4
3
3
SPI_CSZ/SEGDIO36
2
2
SPI_DO/SEGDIO37
1
1
SPI_DI/SEGDIO38
64
100
SPI_CKI/SEGDIO39
33
53
OPT_TX/SEGDIO51
32
46
38
36
37
58
56
57
OPT_RX/SEGDIO55
E_RXTX/SEG48
E_RST/SEG50
E_TCLK/SEG49
160
I/O
3, 4, 5
Function
LCD Common Outputs. These four pins provide the select
signals for the LCD display.
Multiple-Use Pins. Configurable as either LCD segment
driver or DIO. Alternative functions with proper selection of
associated I/O RAM registers are:
SEGDIO0 = WPULSE
SEGDIO1 = VPULSE
SEGDIO2 = SDCK
SEGDIO3 = SDATA
SEGDIO6 = XPULSE
SEGDIO7 = YPULSE
SEGDIO8 = DI
Unused pins must be configured as outputs or
terminated to V3P3/GNDD.
I/O
3, 4, 5
Multiple-Use Pins. Configurable as either LCD segment
driver or DIO with alternative function (LCD common
drivers).
I/O
3, 4, 5
Multiple-Use Pins. Configurable as either LCD segment
driver or DIO with alternative function (SPI interface).
I/O
3, 4, 5
Multiple-Use Pins, configurable as either LCD segment
driver or DIO with alternative function (optical port/UART1)
I/O
1, 4, 5
O
4, 5
Multiuse Pins. Configurable as either emulator port pins
(when ICE_E pulled high) or LCD segment drivers (when
ICE_E tied to GND).
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Pin
(64-pin)
Pin
(100-pin)
Name
39
59
ICE_E
60
92
TMUXOUT/SEG47
61
93
TMUX2OUT/SEG46
Type
Circuit
I
2
ICE Enable. When zero, E_RST, E_TCLK, and E_RXTX
become SEG50, SEG49, and SEG48 respectively. For
production units, this pin should be pulled to GND to disable
the emulator port.
O
4, 5
Multiple-Use Pins. Configurable as either multiplexer/clock
output or LCD segment driver using the I/O RAM registers.
59
91
RESET
I
2
35
55
RX
I
3
34
54
TX
O
4
51
81
TEST
I
7
58
90
PB
I
3
--
26, 40,
48, 49,
50, 63,
64, 65,
66, 73,
74, 77,
78, 79,
84
NC
N/C
—
Rev 2
Function
Chip Reset. This input pin is used to reset the chip into a
known state. For normal operation, this pin is pulled low. To
reset the chip, this pin should be pulled high. This pin has
an internal 30 μA (nominal) current source pulldown. No
external reset circuitry is necessary.
UART0 Input. If this pin is unused it must be terminated
to V3P3D or GNDD.
UART0 Output
Enables Production Test. This pin must be grounded in
normal operation.
Pushbutton Input. This pin must be at GNDD when not active
or unused. A rising edge sets the WF_PB flag. It also
causes the part to wake up if it is in SLP or LCD mode. PB
does not have an internal pullup or pulldown resistor.
No Connection. Do not connect this pin.
161
71M6541D/F/G and 71M6542F/G Data Sheet
6.9.4
I/O Equivalent Circuits
V3P3D
V3P3A
V3P3D
110K
Digital
Input
Pin
CMOS
Input
from
internal
reference
LCD SEG
Output
Pin
LCD
Driver
VREF
Pin
GNDD
GNDA
GNDD
LCD Output Equivalent Circuit
Type 5:
LCD SEG or
pin configured as LCD SEG
Digital Input Equivalent Circuit
Type 1:
Standard Digital Input or
pin configured as DIO Input
with Internal Pull-Up
VREF Equivalent Circuit
Type 9:
VREF
V3P3A
V3P3D
V3P3D
Digital
Input
Pin
CMOS
Input
Analog
Input
Pin
GNDD
GNDD
Analog Input Equivalent Circuit
Type 6:
ADC Input
Digital Input
Type 2:
Pin configured as DIO Input
with Internal Pull-Down
V2P5 Equivalent Circuit
Type 10:
V2P5
V3P3A
V3P3D
Comparator
Input
Pin
To
Comparator
VLCD
Pin
LCD
Drivers
GNDA
Digital
Input
Pin
V2P5
Pin
GNDA
110K
GNDD
from
internal
reference
To
MUX
CMOS
Input
GNDD
Comparator Input Equivalent
Circuit Type 7:
Comparator Input
VLCD Equivalent Circuit
Type 11:
VLCD Power
GNDD
Oscillator
Pin
Digital Input Type 3:
Standard Digital Input or
pin configured as DIO Input
To
Oscillator
Power
Down
Circuits
VBAT
Pin
GNDD
GNDD
V3P3D
Oscillator Equivalent Circuit
Type 8:
Oscillator I/O
V3P3D
10
Digital
Output
Pin
CMOS
Output
from
V3P3SYS
V3P3D
Pin
GNDD
GNDD
Digital Output Equivalent Circuit
Type 4:
Standard Digital Output or
pin configured as DIO Output
VBAT Equivalent Circuit
Type 12:
VBAT Power
40
from
VBAT
V3P3D Equivalent Circuit
Type 13:
V3P3D
Figure 52: I/O Equivalent Circuits
162
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
7
Ordering Information
7.1
71M6541D/F/G and 71M6542F/G
Table 122. Ordering Information
Part
Part Description
(Package, Accuracy)
71M6541D
64-pin LQFP Lead-Free, 0.5%
71M6541D
64-pin LQFP Lead-Free, 0.5%
71M6541F
64-pin LQFP Lead-Free, 0.5%
71M6541F
64-pin LQFP Lead-Free, 0.5%
71M6541G* 64-pin LQFP Lead-Free, 0.5%
71M6541G* 64-pin LQFP Lead-Free, 0.5%
71M6542F
100-pin LQFP Lead-Free, 0.5%
71M6542F
100-pin LQFP Lead-Free, 0.5%
71M6542G
100-pin LQFP Lead-Free, 0.5%
71M6542G
100-pin LQFP Lead-Free, 0.5%
Flash
Size
Packaging
32 KB bulk
tape and
32 KB
reel
64 KB bulk
tape and
64 KB
reel
128 KB bulk
tape and
128 KB
reel
64 KB bulk
tape and
64 KB
reel
128 KB bulk
tape and
128 KB
reel
Order Number
Package
Marking
71M6541D-IGT/F
71M6541D-IGT
71M6541D-IGTR/F 71M6541D-IGT
71M6541F-IGT/F
71M6541F-IGT
71M6541F-IGTR/F 71M6541F-IGT
71M6541G-IGT/F
71M6541G-IGT
71M6541G-IGTR/F 71M6541G-IGT
71M6542F-IGT/F
71M6542F-IGT
71M6542F-IGTR/F 71M6542F-IGT
71M6542G-IGT/F
71M6542G-IGT
71M6542G-IGTR/F 71M6542G-IGT
*Future product—contact factory for availability.
8
Related Information
Users need these additional documents related to the 71M6541D/F/G and 71M6542F/G:
•
•
•
•
71M6541D/F/G and 71M6542F/G Data Sheet (this document)
71M6xxx Data Sheet
71M6541 Demo Board User’s Manual
71M654x Software User’s Guide
9
Contact Information
For more information about Maxim products or to check the availability of the 71M6541D/F/G and
71M6542F/G, contact technical support at www.maxim-ic.com/support.
Rev 2
163
71M6541D/F/G and 71M6542F/G Data Sheet
Appendix A: Acronyms
AFE
AMR
ANSI
CE
DIO
DSP
FIR
I2C
ICE
IEC
MPU
PLL
RMS
SFR
SOC
SPI
TOU
UART
164
Analog Front End
Automatic Meter Reading
American National Standards Institute
Compute Engine
Digital I /O
Digital Signal Processor
Finite Impulse Response
Inter-IC Bus
In-Circuit Emulator
International Electrotechnical Commission
Microprocessor Unit (CPU)
Phase-locked loop
Root Mean Square
Special Function Register
System on Chip
Serial Peripheral Interface
Time of Use
Universal Asynchronous Receiver/Transmitter
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Appendix B: Revision History
REVISION
NUMBER
1.0
REVISION
DATE
3/11
1.1
4/11
2
Rev 2
11/11
DESCRIPTION
Initial release
Removed the information about 18mW typ consumption at 3.3V
in sleep mode from the Features section
Updated the Temperature Measurement Equation and
Temperature Error parameters in Table 99
Promoted 71M6542G to production level (Table 122)
Added references to 71M6541G/2G throughout the document,
as appropriate.
Added missing data sheet title header to odd and even pages.
Corrected errata detected since the previous v1.1 (see
indicated pages changed).
Added section 6.7 on page 155.
PAGES
CHANGED
—
1
141
1, 9, 10, 27,
49, 54, 56,
62, 97, 120
165
71M6541D/F/G and 71M6542F/G Data Sheet
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit
patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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