WED3EG6418S-D4 FINAL 128MB- 16Mx64 DDR SDRAM UNBUFFERED W/PLL FEATURES DESCRIPTION Double-data-rate architecture Speed of 100MHz, 133MHz and 166MHz Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) The WED3DG6418S is a 16Mx64 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM component. The module consists of eight 16Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 200 Pin FR4 substrate. Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect JEDEC standard 200 pin SO-DIMM package Power Supply: 2.5V ± 0.25V Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct. 2002 Rev. # 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG6418S-D4 FINAL PIN CONFIGURATIONS PIN NAMES Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VREF 51 VSS 101 A9 151 DQ42 2 VREF 52 VSS 102 A8 152 DQ46 3 VSS 53 DQ19 103 VSS 153 DQ43 4 VSS 54 DQ23 104 VSS 154 DQ47 5 DQ0 55 DQ24 105 A7 155 VCC 6 DQ4 56 DQ28 106 A6 156 VCC 7 DQ1 57 VCC 107 A5 157 VCC 8 DQ5 58 VCC 108 A4 158 NC 9 VCC 59 DQ25 109 A3 159 VSS 10 VCC 60 DQ29 110 A2 160 NC 11 DQS0 61 DQS3 111 A1 161 VSS 12 DM0 62 DM3 112 A0 162 VSS 13 DQ2 63 VSS 113 VCC 163 DQ48 14 DQ6 64 VSS 114 VCC 164 DQ52 15 VSS 65 DQ26 115 A10/AP 165 DQ49 DQ53 16 VSS 66 DQ30 116 BA1 166 17 DQ3 67 DQ27 117 BA0 167 VCC 18 DQ7 68 DQ31 118 RAS# 168 VCC DQS6 19 DQ8 69 VCC 119 WE# 169 20 DQ12 70 VCC 120 CAS# 170 DM6 21 VCC 71 NC 121 CSO 171 DQ50 22 VCC 72 NC 122 NC 172 DQ54 23 DQ9 73 NC 123 NC 173 VSS 24 DQ13 74 NC 124 NC 174 VSS 25 DQS1 75 VSS 125 VSS 175 DQ51 26 DM1 76 VSS 126 VSS 176 DQ55 27 VSS 77 DQS8 127 DQ32 177 DQ56 28 VSS 78 DM8 128 DQ36 178 DQ60 29 DQ10 79 NC 129 DQ33 179 VCC 30 DQ14 80 NC 130 DQ37 180 VCC 31 DQ11 81 VCC 131 VCC 181 DQ57 32 DQ15 82 VCC 132 VCC 182 DQ61 33 VCC 83 NC 133 DQS4 183 DQS7 34 VCC 84 NC 134 DM4 184 DM7 35 CK0 85 NC 135 DQ34 185 VSS 36 VCC 86 NC 136 DQ38 186 VSS 37 CK0# 87 VSS 137 VSS 187 DQ58 38 VSS 88 VSS 138 VSS 188 DQ62 39 VSS 89 NC 139 DQ35 189 DQ59 40 VSS 90 VSS 140 DQ39 190 DQ63 41 DQ16 91 NC 141 DQ40 191 VCC 42 DQ20 92 VCC 142 DQ44 192 VCC 43 DQ17 93 VCC 143 VCC 193 SDA 44 DQ21 94 VCC 144 VCC 194 SA0 45 VCC 95 NC 145 DQ41 195 SCL 46 VCC 96 CKE0 146 DQ45 196 SA1 47 DQS2 97 NC 147 DQS5 197 VCCSPD 48 DM2 98 NC 148 DM5 198 SA2 49 DQ18 99 NC 149 VSS 199 VCCID 50 DQ22 100 A11 150 VSS 200 NC A0 – A11 BA0-BA1 DQ0-DQ63 DQS0-DQS8 CK0 CK0# CKE0 CS0# RAS# CAS# WE# DQM0-DQM8 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock input Clock input Clock Enable Input Chip select Input Row Address Strobe Column Address Strobe Write Enable Data-In Mask Power Supply (2.5V) Power Supply for DQS (2.5V) Ground Power Supply for Reference Serial EEPROM Power Supply (2.3V to 3.6V) Serial data I/O Serial clock Address in EEPROM VCC Identification Flag No Connect White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct. 2002 Rev. # 0 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG6418S-D4 FINAL FUNCTIONAL BLOCK DIAGRAM WE#,RAS#CAS# CKE0 SO# BA0,BA1,A0-A11 DQ0-7 DQ0-7 DQ0-7 DM DQM0 DM DQ32-39 DQM4 U3 U1 SERIAL PD SCL SDA WP A0 A1 A2 DQ0-7 DQ8-15 SA0 SA1 SA2 DM DQM1 CK0 120 Ω CK0# PLL DQ0-7 DM DQ16-23 DM U6 DQ0-7 DQM2 DQM5 DM DQ48-55 DQM6 U7 U5 DQ0-7 DM DQ40-479 U4 U2 DDR SDRAM U1 DDR SDRAM U2 DDR SDRAM U3 DDR SDRAM U4 DDR SDRAM U4 DDR SDRAM U6 DDR SDRAM U7 DDR SDRAM U8 DQ0-7 DQ24-31 DQ0-7 DQM3 DM DQ56-63 DQM7 U8 White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct. 2002 Rev. # 0 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG6418S-D4 FINAL Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 8 50 Units V V °C W mA Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC CHARACTERISTICS (tA = 0 to 70°C, VCC = 2.5V ± 0.2V) Parameter Supply Voltage Supply Voltage Reference Voltage Termination Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Symbol VCC VCCQ VREF VTT VIH VIL VOH VOL Min 2.3 2.3 VCCQ/2-50mV VREF-0.04 VREF+0.15 -0.3 VTT+0.76 — Max 2.7 2.7 VCCQ/2+50mV VREF+0.04 VCCQ+0.3 VREF+0.15 — VTT-0.76 Unit V V V V V V V V CAPACITANCE (tA = 23°C, f = 1MHz, VCC = 3.3V, VREF=1.4V ± 200mV) Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0) Input Capacitance (CK0, CK0#) Input Capacitance (CS0#) Input Capacitance (DQM0-DQM8) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63)(DQS) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT Min - Max 34 34 34 30 30 10 45 10 Unit pF pF pF pF pF pF pF pF White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct. 2002 Rev. # 0 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG6418S-D4 FINAL IDD SPECIFICATIONS AND TEST CONDITIONS (Recommended operating conditions, tA = 0 to 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V) Parameter Symbol Operating Current IDD0 Operating Current IDD1 Precharge PowerDown Standby Current IDD2P Idle Standby Current IDD2F Active Power-Down Standby Current IDD3P Active Standby Current IDD3N Operating Current IDD4R Operating Current IDD4W Auto Refresh Current Self Refresh Current IDD5 IDD6 Operating Current IDD7A Conditions One device bank; Active = Precharge; tRC=tRC(MIN); tCK=tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device banks; Active-Read-Precharge; Burst = 2; tRC=tRC(MIN); tCK=tCK (MIN); lOUT=0mA; Address and control inputs changing once per clock cycle. All device bank idle; Power-down mode; tCK=tCK(MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; Power-down mode; tCK(MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Burst = 2; Reads; Continous burst; Once device bank active; Address and control inputs changing once per clock cycle; tCK=tCK(MIN); IOUT=0mA Burst=2; Writes; Continous burst; Once device bank active; Address and control inputs changing once per clock cycle; tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. tRC=tRC(MIN) CKE £ 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC(MIN); tCK=tCK(MIN); Address and control input change only during Active Read or Write commands. DDR333@CL=2.5 Max DDR266@CL=2, 2.5 Max DDR200@CL=2 Max Units 840 760 680 mA 1040 960 880 mA 24 24 24 mA 200 180 160 mA 280 280 225 mA 495 440 360 mA 1280 1140 960 mA 1216 1040 815 mA 1520 16 1440 16 1315 16 mA mA 2640 2400 1920 mA * Module IDD was calculated on the basis of component IDD and can be different measured according to DQ loading cap. White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct. 2002 Rev. # 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG6418S-D4 FINAL DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT: ONE BANK IDD7A : OPERATING CURRENT : FOUR BANK OPERATION 1. Typical Case : VCC = 2.5V, T = 25°C 2. Worst Case : VCC = 2.7V, T = 10°C 3. Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA 4. Timing patterns -DDR200 (100Mhz, CL = 2) : tCK = 10ns, CL2, BL = 4, tRCD = 2*tCK, tRAS = 5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst 1. Typical Case : Vcc = 2.5V, T = 25°C 2. Worst Case : Vcc = 2.7V, T = 10°C 3. Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. IOUT = 0mA 4. Timing patterns - DDR200 (100Mhz, CL = 2) : tCK = 10ns, CL2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 repeat the same timing with random address changing; 100% of data changing at every burst -DDR266B (133Mhz, CL = 2.5): tCK = 7.5ns, CL = 2.5, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst -DDR266B (133Mhz, CL = 2.5) : tCK = 7.5ns, CL = 2.5, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst -DDR266A (133Mhz, CL = 2) : tCK = 7.5ns, CL = 2, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst -DDR266A (133Mhz, CL = 2) : tCK = 7.5ns, CL2 = 2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst -DDR333 (166MHz, CL = 2.5) : tCK = 6ns, CL = 2.5, BL = 4, tRCD = 10*tCK, tRAS = 7*tCK Read " A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst. -DDR333 (166MHz, CL = 2.5) : tCK = 6ns, CL = 2.5, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct. 2002 Rev. # 0 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG6418S-D4 FINAL ORDER INFORMATION Part Number WED3EG6418S335D4 WED3EG6418S262D4 WED3EG6418S265D4 WED3EG6418S202D4 Speed 166MHz/333Mbps 133MHz/266Mbps 133MHz/266Mbps 100MHz/200Mbps CAS Latency CL=2.5 CL=2 CL=2.5 CL=2 PACKAGE DIMENSIONS ALL DIMENSIONS ARE IN INCHES 2.666 MAX. .150 MAX .079 .157+/-.004 .787 PI .157 MIN. .091 REF. .165 1.866 .071 .449 .039±.004 White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct. 2002 Rev. # 0 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com