White Electronic Designs WED3EG7218S-JD3 PRELIMINARY* 128MB – 16Mx72 DDR SDRAM UNBUFFERED FEATURES DESCRIPTION Double-data-rate architecture The WED3EG7218S is a 16Mx72 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM component. The module consists of nine 16Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. DDR200, DDR266, DDR333 and DDR400 • JEDEC design specified BI-directional data strobes (DQS) Differential clock inputs (CK & CK#) Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. * This product is under development, is not qualified or characterized and is subject to change without notice. Auto and self refresh Serial presence detect Power supply: • VCC = VCCQ = 2.5V±0.2V (100, 133 and 166MHz) • VCC = VCCQ = 2.6V±0.1V (200MHz) JEDEC 184 pin DIMM package • JD3 PCB height: 30.48 (1.20") Max NOTE: Consult factory for availability of: • RoHS Products • Vendor source control options • Industrial temperature option OPERATING FREQUENCIES DDR400 @CL=3 DDR333 @CL=2.5 DDR266 @CL=2 DDR266 @CL=2.5 DDR200 @CL=2 Clock Speed 200MHz 166MHz 133MHz 133MHz 100MHz CL-tRCD-tRP 3-3-3 2.5-3-3 2-2-2 2.5-3-3 2-2-2 June 2006 Rev. 2 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7218S-JD3 PRELIMINARY PIN CONFIGURATION PIN NAMES Pin Front Pin Front Pin Front Pin Front A0 – A12 1 VREF 47 DQS8 93 VSS 139 VSS BA0-BA1 Address input (Multiplexed) Select Bank Address 2 DQ0 48 A0 94 DQ4 140 DQM8 DQ0-DQ63 Data Input/Output 3 VSS 49 CB2 95 DQ5 141 A10 CB0-CB7 Check bits 4 DQ1 50 VSS 96 VCCQ 142 CB6 DQS0-DQS8 Data Strobe Input/Output 5 DQS0 51 CB3 97 DQM0 143 VCCQ CK0, CK1, CK2 Clock input 6 DQ2 52 BA1 98 DQ6 144 CB7 CK0#, CK1#, CK2# Clock input 7 VCC 53 DQ32 99 DQ7 145 VSS CKE0 Clock Enable input 8 DQ3 54 VCCQ 100 VSS 146 DQ36 CS0# Chip select Input Row Address Strobe 9 NC 55 DQ33 101 NC 147 DQ37 RAS# 10 NC 56 DQS4 102 NC 148 VCC CAS# Column Address Strobe 11 VSS 57 DQ34 103 *A13 149 DQM4 WE# Write Enable 12 DQ8 58 VSS 104 VCCQ 150 DQ38 DQM0-DQM8 Data-in Mask 13 DQ9 59 BA0 105 DQ12 151 DQ39 VCC Power Supply (2.5V) 14 DQS1 60 DQ35 106 DQ13 152 VSS VCCQ Power Supply for DQS (2.5V) 15 VCCQ 61 DQ40 107 DQM1 153 DQ44 VSS Ground 16 CK1 62 VCCQ 108 VCC 154 RAS# VREF Power Supply for Reference 17 CK1# 63 WE# 109 DQ14 155 DQ45 VCCSPD Serial EEPROM Power Supply (2.3V to 3.6V) 18 VSS 64 DQ41 110 DQ15 156 VCCQ SDA Serial data I/O 19 DQ10 65 CAS# 111 *CKE1 157 CS0# SCL Serial clock 20 DQ11 66 VSS 112 VCCQ 158 *CS1# SA0-SA2 Address in EEPROM 21 CKE0 67 DQS5 113 *BA2 159 DQM5 VDDID VDD Identification Flag NC No Connect 22 VCCQ 68 DQ42 114 DQ20 160 VSS 23 DQ16 69 DQ43 115 A12 161 DQ46 24 DQ17 70 VCC 116 VSS 162 DQ47 25 DQS2 71 CS2# 117 DQ21 163 *CS3# 26 VSS 72 DQ48 118 A11 164 VCCQ 27 A9 73 DQ49 119 DQM2 165 DQ52 28 DQ18 74 VSS 120 VCC 166 DQ53 29 A7 75 CK2# 121 DQ22 167 NC 30 VCCQ 76 CK2 122 A8 168 VCC 31 DQ19 77 VCCQ 123 DQ23 169 DQM6 32 A5 78 DQS6 124 VSS 170 DQ54 33 DQ24 79 DQ50 125 A6 171 DQ55 VCCQ 34 VSS 80 DQ51 126 DQ28 172 35 DQ25 81 VSS 127 DQ29 173 NC 36 DQS3 82 VDDID 128 VCCQ 174 DQ60 37 A4 83 DQ56 129 DQM3 175 DQ60 38 VCC 84 DQ57 130 A3 176 VSS 39 DQ26 85 VCC 131 DQ30 177 DQM7 40 DQ27 86 DQS7 132 VSS 178 DQ62 41 A2 87 DQ58 133 DQ31 179 DQ63 VCCQ 42 VSS 88 DQ59 134 CB4 180 43 A1 89 VSS 135 CB5 181 SA0 44 CB0 90 NC 136 VCCQ 182 SA1 45 CB1 91 SDA 137 CK0 183 SA2 46 VCC 92 SCL 138 CK0# 184 VCCSPD June 2006 Rev. 2 * Not Used 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7218S-JD3 PRELIMINARY FUNCTIONAL BLOCK DIAGRAM CS0# DQS0 DQM0 DQS4 DQM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS1 DQS5 DQM1 DQM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS2 DQS6 DQM2 DQM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS3 DQS7 DQM3 DQM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQS8 DQM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQS SERIAL PD SCL WP SDA A0 A1 A2 SA0 SA1 SA2 VCCSPD SPD RAS# RAS#: DDR SDRAMs VCCQ CAS# CAS#: DDR SDRAMs VCC BA0-BA1: DDR SDRAMs VREF DDR SDRAMs VSS DDR SDRAMs BA0-BA1 WE# A0-A12 CKE0 WE#: DDR SDRAMs DDR SDRAMs DDR SDRAMs A0-A12: DDR SDRAMs CKE0: DDR SDRAMs CLOCK INPUT CK0, CK0# 3 SDRAMS CK1, CK1# 3 SDRAMS CK2, CK2# 3 SDRAMS NOTE: All resistor values are 22 ohms unless otherwise specified June 2006 Rev. 2 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7218S-JD3 PRELIMINARY ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Units Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 ~ 3.6 V TSTG -55 ~ +150 °C Power Dissipation PD 9 W Short Circuit Current I0S 50 mA Storage Temperature Notes: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC CHARACTERISTICS (0°C ≤ TA ≤ 70°C, VCC = 2.5V ± O.2V) Parameter Symbol Min Max Unit Supply Voltage VCC 2.3 2.7 V Supply Voltage VCCQ 2.3 2.7 V Reference Voltage VREF 1.15 1.35 V Termination Voltage VTT 1.15 1.35 V Input High Voltage VIH VREF+0.15 VCCQ+0.3 V Input Low Voltage VIL -0.3 VREF+0.15 V Output High Voltage VOH VTT+0.76 — V Output Low Voltage VOL — VTT-0.76 V Symbol Max Unit CIN1 45 pF Input Capacitance (RAS#,CAS#,WE#) CIN2 45 pF Input Capacitance (CKE0, CKE1) CIN3 45 pF Input Capacitance (CK0,CK0#) CIN4 40 pF Input Capacitance (CS0#, CS1#) CIN5 44 pF Input Capacitance (DQM0-DQM8) CIN6 15 pF Input Capacitance (BA0-BA1) CIN7 45 pF Data Input/Output capacitance (DQ0-DQ63)(DQS) COUT 15 pF Data Input/Output Capacitance (CB0-CB7) COUT 15 pF CAPACITANCE (TA = 25°C. f = 1MHz, VCC = 2.5V) Parameter Input Capacitance (A0-A12) June 2006 Rev. 2 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7218S-JD3 PRELIMINARY ICC SPECIFICATIONS AND TEST CONDITIONS DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V includes DDR SDRAM component only DDR266@ CL=2 Max DDR266@ CL=2.5 Max DDR200@ CL=2 Max Units ICC0 One device bank; Active = Precharge; TRC=TRC(MIN); TCK=TCK(MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles 990 990 810 mA Operating Current ICC1 One device bank; Active-readPrecharge; Burst = 2; TRC=TRC(MIN); TCK=TCK(MIN); lout=0mA; Address and control inputs changing once per clock cycle 1260 1260 1035 mA Precharge Power-Down Standby Current ICC2P All device banks idle; Power-down mode; TCK=TCK(MIN); CKE=(low) 270 270 255 mA Idle Standby Current ICC2F CS# = High; All device banks idle; TCK=TCK(MIN); CKE=high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. 495 495 405 mA Active PowerDown Standby Current ICC3P One device bank active; Power-down mode; TCK(MIN); CKE=(low) 315 315 270 mA ICC3N CS# = High; CKE = High; One device bank; Active-Precharge; TRC = TRAS(MAX); TCK = TCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 540 540 450 mA ICC4R Burst = 2; Reads; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK = TCK(MIN); lout = 0mA 1800 1800 1485 mA Operating Current ICC4W Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK = TCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle. 1935 1935 1530 mA Auto Refresh Current ICC5 TRC = TRC(MIN) 1935 1935 1530 mA Self Refresh Current ICC6 CKE ≤ 0.2V Standard 18 18 18 Low Power 9 9 9 Parameter Operating Current Active Standby Current Operating Current June 2006 Rev. 2 Symbol DDR400@ CL=3 Max Conditions 5 DDR333@ CL=2.5 Max mA White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7218S-JD3 PRELIMINARY DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT : ONE BANK IDD7A : OPERATING CURRENT : FOUR BANKS 1. Typical Case : VCC=2.5V, T=25°C 1. Typical Case : VCC=2.5V, T=25°C 2. Worst Case : VCC=2.7V, T=10°C 2. Worst Case : VCC=2.7V, T=10°C 3. Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA 3. Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA 4. Timing Patterns : 4. Timing Patterns : • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR400 (200MHz, CL=3) : tCK=5ns, BL=4, tRCD=15*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR400 (200MHz, CL=3) : tCK=5ns, BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst R (0-3) = Read Bank 0-3 June 2006 Rev. 2 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7218S-JD3 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V AC Characteristics 403 Parameter 335 262/265 202 Symbol Min Max Min Max Min Max Min Max Units Access window of DQs from CK, CK# tAC -0.70 +0.70 -0.70 +0.70 -0.75 +0.75 -0.75 +0.75 ns Notes CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 16 CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 16 ns 22 6 13 7.5 13 7.5 13 ns 22 7.5 13 7.5 13 10 13 ns 22 ns 14,17 CL=3 tCK (3) 5 7.5 CL=2.5 tCK (2.5) 6 13 CL=2 tCK (2) 7.5 13 tDH 0.40 0.45 DQ and DM input setup time relative to DQS tDS 0.40 0.45 0.5 0.5 ns 14,17 DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 1.75 1.75 ns 17 Access window of DQS from CK, CK# tDQSCK -0.60 DQS input high pulse width tDQSH 0.35 0.35 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 0.35 0.35 tCK DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ Write command to first DQS latching transition tDQSS 0.72 DQS falling edge to CK rising - setup time tDSS 0.2 DQS falling edge from CK rising - hold time tDSH 0.2 0.2 Half clock period tHP tCH, tCL tCH, tCL Data-out high-impedance window from CK, CK# tHZ Data-out low-impedance window from CK, CK# tLZ -0.70 -0.70 -0.75 -0.75 Clock cycle time DQ and DM input hold time relative to DQS +0.60 0.5 -0.60 +0.60 0.40 1.28 -0.75 0.45 0.75 1.25 0.2 0.5 +0.75 0.5 0.75 1.25 0.2 +0.70 -0.75 0.75 +0.75 ns 0.5 ns 1.25 tCK 13,14 0.2 tCK 0.2 0.2 tCK tCH, tCL tCH, tCL ns 18 ns 8,19 ns 8,20 +0.70 +0.75 +0.75 Address and control input hold time (fast slew rate) tIHf 0.60 0.75 0.90 0.90 ns 6 Address and control input set-up time (fast slew rate) tISf 0.60 0.75 0.90 0.90 ns 6 Address and control input hold time (slow slew rate) tIHs 0.60 0.80 1 1 ns 6 Address and control input setup time (slow slew rate) tISs 0.60 0.80 1 1 ns 6 Address and control input pulse width (for each input) tIPW 2.2 2.2 2.2 2.2 ns LOAD MODE REGISTER command cycle time tMRD 10 12 15 15 ns DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP-tQHS tHP-tQHS tHP-tQHS tHP-tQHS ns Data hold skew factor tQHS ACTIVE to PRECHARGE command tRAS 40 ACTIVE to READ with Auto precharge command tRAP 15 15 15 20 ns ACTIVE to ACTIVE/AUTO REFRESH command period tRC 55 60 60 65 ns AUTO REFRESH command period tRFC 70 72 75 75 ns June 2006 Rev. 2 0.50 70,000 7 0.55 42 70,000 0.75 40 120,000 45 0.75 ns 120,000 ns 13,14 15 21 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7218S-JD3 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued) DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V AC Characteristics Parameter ACTIVE to READ or WRITE delay PRECHARGE command period 403 Symbol Min tRCD 15 335 Max Min 262/265 Max 15 Min Max 15 15 202 Min Max 20 15 Units Notes ns tRP 15 DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 20 1.1 tCK ns DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK ACTIVE bank a to ACTIVE bank b command tRRD 10 12 15 15 ns DQS write preamble tWPRE 0.25 0.25 0.25 0.25 tCK DQS write preamble setup time tWPRES 0 0 0 0 ns 10,11 DQS write postamble tCK 9 tWPST 0.4 Write recovery time tWR 15 15 15 15 ns Internal WRITE to READ command delay tWTR 2 1 1 1 tCK Data valid output window NA tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ REFRESH to REFRESH command interval tREFC 0.6 0.4 70.3 0.6 0.4 70.3 0.4 70.3 70.3 12 μs 12 tVTD Exit SELF REFRESH to non-READ command tXSNR 70 75 75 75 ns Exit SELF REFRESH to READ command tXSRD 200 200 200 200 tCK 8 0 7.8 13 tREFI 0 7.8 ns μs Average periodic refresh interval 0 7.8 0.6 Terminating voltage delay to VCC June 2006 Rev. 2 7.8 0.6 0 ns White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7218S-JD3 PRELIMINARY Notes 1. All voltages referenced to VSS 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at normal reference / supply voltage levels, but the related specifications and device operations are guaranteed for the full voltage range specified. 3. Outputs are measured with equivalent load: 11. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be high during this time, depending on tDQSS. 12. The refresh period is 64ms. This equates to an average refresh rate of 7.8125µs. However, an AUTO REFRESH command must be asserted at least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 13. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycled variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. VTT Output (VOUT) 4. 5. 6. 50Ω Reference Point 30pF AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). The AC and DC input level specifications are defined in the SSTL_ 2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [high] level). For slew rates less than 1V/ns and greater than or equal to 0.5V/ ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. For 403 and 335, slew rates must be greater than or equal to 0.5V/ns. 14. Referenced to each output group: x8 = DQS with DQ0-DQ7. 15. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. 16. JEDEC specifies CK and CK# input slew rate must be > 1V/ns (2V/ns differentially). 17. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns, functionality is uncertain. 18. tHP min is the lesser of tCL min and tCH min actually applied to the device CK and CK# inputs, collectively during bank active. 7. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW. 19. tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX) condition. 8. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) and begins driving (LZ). 20. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. 21. CKE must be active (High) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfied. 22. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). 9. 10. The intent of the “Don’t Care” state after completion of the postamble is the DQS-driven signal should either be HIGH, LOW, or high-Z, and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions HIGH (above VIHDC (MIN) then it must not transition LOW (below VIHDC) prior to tDQSH (MIN). This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. June 2006 Rev. 2 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7218S-JD3 PRELIMINARY ORDERING INFORMATION FOR JD3 Part Number Speed/Data Rate Frequency CAS Latency tRCD tRP Height* WED3EG7218S403JD3xxx 200MHz/400Mb/s 3 3 3 30.48mm (1.20") WED3EG7218S335JD3xxx 166MHz/333Mb/s 2.5 3 3 30.48mm (1.20") WED3EG7218S262JD3xxx 133MHz/266Mb/s 2 2 2 30.48mm (1.20") WED3EG7218S265JD3xxx 133MHz/266Mb/s 2.5 3 3 30.48mm (1.20") WED3EG7218S202JD3xxx 100MHz/200Mb/s 2 2 2 30.48mm (1.20") NOTES: • Consult Factory for availability of RoHS products. (G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR JD3 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 3.99 (0.157 (2x)) 2.54 (0.100) 30.48 (1.20) MAX 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 6.35 (0.250) 49.53 (1.950) 1.27 (0.050 TYP.) 1.78 (0.070) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 3.99 (0.157) (MIN) 1.27 ± 0.10 (0.050 ± 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) June 2006 Rev. 2 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7218S-JD3 PRELIMINARY PART NUMBERING GUIDE WED 3 E G 72M 18 S xxx JD3 x x G WEDC MEMORY (SDRAM) DDR GOLD DEPTH BUS WIDTH 2.5V SPEED (Mb/s) PACKAGE 184 PIN INDUSTRIAL TEMP OPTION (For commercial leave "blank" for industrial add "I") COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT June 2006 Rev. 2 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7218S-JD3 PRELIMINARY Document Title 128MB – 16Mx72 DDR SDRAM UNBUFFERED DRAM DIE OPTIONS: • SAMSUNG: H-Die • MICRON: T26Z: G-Die Revision History Rev # History Release Date Status Rev A Created Datasheet 3-6-02 Advanced Rev 0 0.1 Updated IDD and CAP specs 11-04 Preliminary 11-05 Preliminary 6-06 Preliminary 0.2 Updated AC specs 0.3 Moved from Advanced to Preliminary 0.4 Added Lead-Free and RoHS note Rev 1 1.0 Added JEDEC PCB option (JD3) 1.1 D3 PCB option "NOT RECOMMENDED FOR NEW DESIGNS" Rev 2 2.1 Removed "D3" package option 2.2 Added "Part Numbering Guide" 2.3 Added DRAM die options 2.4 Added DDR400 and DDR333 ICC & AC specifications June 2006 Rev. 2 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com