74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs tm Features General Description ■ ICC and IOZ reduced by 50% ■ Guaranteed simultaneous switching noise level and The ACQ/ACTQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The ACQ/ACTQ573 is functionally identical to the ACQ/ACTQ373 but with inputs and outputs on opposite sides of the package. The ACQ/ ACTQ utilizes Fairchild's Quiet Series™ technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance. dynamic threshold performance ■ Guaranteed pin-to-pin skew AC performance ■ Improved latch-up immunity ■ Inputs and outputs on opposite sides of package allow easy interface with microprocessors ■ Outputs source/sink 24mA Ordering Information Order Number Package Number Package Description 74ACQ573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACQ573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACQ573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACTQ573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACTQ573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACTQ573QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide 74ACTQ573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram Pin Descriptions Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE 3-STATE Output Enable Input O0–O7 3-STATE Latch Outputs FACT™, Quiet Series™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation. ©1990 Fairchild Semiconductor Corporation 74ACQ573, 74ACTQ573 Rev. 1.5 www.fairchildsemi.com 74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs April 2007 Functional Description The ACQ/ACTQ573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the information that was present on the D-type inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. IEEE/IEC Truth Table Inputs Outputs OE LE D On L H H H L H L L L L X O0 H X X Z H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1990 Fairchild Semiconductor Corporation 74ACQ573, 74ACTQ573 Rev. 1.5 www.fairchildsemi.com 2 74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs Logic Symbol Symbol VCC IIK Parameter Rating Supply Voltage –0.5V to +7.0V DC Input Diode Current VI = –0.5V –20mA VI = VCC + 0.5V +20mA VI DC Input Voltage IOK DC Output Diode Current –0.5V to VCC + 0.5V VO = –0.5V –20mA VO = VCC + 0.5V +20mA VO DC Output Voltage –0.5V to VCC + 0.5V IO DC Output Source or Sink Current ±50mA ICC or IGND DC VCC or Ground Current per Output Pin TSTG ±50mA Storage Temperature –65°C to +150°C DC Latch-Up Source or Sink Current TJ ±300mA Junction Temperature 140°C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Parameter Rating Supply Voltage ACQ 2.0V to 6.0V ACTQ 4.5V to 5.5V VI Input Voltage 0V to VCC VO Output Voltage 0V to VCC TA Operating Temperature ∆V / ∆t –40°C to +85°C 125mV/ns Minimum Input Edge Rate, ACQ Devices: VIN from 30% to 70% of VCC, VCC @ 3.0V, 4.5V, 5.5V ∆V / ∆t 125mV/ns Minimum Input Edge Rate, ACTQ Devices: VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V ©1990 Fairchild Semiconductor Corporation 74ACQ573, 74ACTQ573 Rev. 1.5 www.fairchildsemi.com 3 74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = +25°C Symbol VIH Parameter Minimum HIGH Level Input Voltage VCC (V) 3.0 Conditions VOUT = 0.1V or VCC – 0.1V Maximum LOW Level Input Voltage 2.1 2.1 2.25 3.15 3.15 2.75 3.85 3.85 1.5 0.9 0.9 2.25 1.35 1.35 2.75 1.65 1.65 2.99 2.9 2.9 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 4.5 3.0 4.5 VOUT = 0.1V or VCC – 0.1V 5.5 VOH Minimum HIGH Level Output Voltage Guaranteed Limits 1.5 5.5 VIL Typ. TA = –40°C to +85°C 3.0 IOUT = –50µA Units V V V VIN = VIL or VIH: 3.0 IOH = –12mA 2.56 2.46 4.5 IOH = –24mA 3.86 3.76 4.86 4.76 0.1 0.1 5.5 VOL Maximum LOW Level Output Voltage IOH = –24mA(1) 3.0 4.5 0.002 IOUT = 50µA 5.5 0.001 0.1 0.1 0.001 0.1 0.1 V VIN = VIL or VIH: 3.0 IOL = 12mA 0.36 0.44 4.5 IOL = 24mA 0.36 0.44 0.36 0.44 ± 0.1 ± 1.0 µA 24mA(1) 5.5 IOL = Maximum Input Leakage Current 5.5 VI = VCC, GND Minimum Dynamic Output Current(2) 5.5 VOLD = 1.65 VMax 75 mA 5.5 VOHD = 3.85 VMin –75 mA Maximum Quiescent Supply Current 5.5 VIN = VCC or GND 4.0 40.0 µA Maximum 3-STATE Leakage Current 5.5 VI (OE) = VIL, VIH; VI = VCC, GND; VO = VCC, GND ±0.25 ±2.5 µA VOLP Quiet Output Maximum Dynamic VOL 5.0 Figures 1 & 2(4) 1.1 1.5 V VOLV Quiet Output Minimum Dynamic VOL 5.0 Figures 1 & 2(4) –0.6 –1.2 V VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 (5) 3.1 3.5 V VILD Maximum LOW Level Dynamic Input Voltage 5.0 (5) 1.9 1.5 V IIN (3) IOLD IOHD ICC (3) IOZ Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. 3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 4. Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND. 5. Max number of Data Inputs (n) switching. (n – 1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f = 1MHz. ©1990 Fairchild Semiconductor Corporation 74ACQ573, 74ACTQ573 Rev. 1.5 www.fairchildsemi.com 4 74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs DC Electrical Characteristics for ACQ TA = +25°C Symbol VIH VIL VOH Parameter VCC (V) Conditions Typ. TA = –40°C to +85°C Guaranteed Limits VOUT = 0.1V or VCC – 0.1V 1.5 2.0 2.0 1.5 2.0 2.0 VOUT = 0.1V or VCC – 0.1V 1.5 0.8 0.8 5.5 1.5 0.8 0.8 4.5 IOUT = –50µA 4.49 4.4 4.4 5.49 5.4 5.4 3.86 3.76 4.86 4.76 0.001 0.1 0.1 0.001 0.1 0.1 0.36 0.44 0.36 0.44 Minimum HIGH Level Input Voltage 4.5 Maximum LOW Level Input Voltage 4.5 Minimum HIGH Level Output Voltage 5.5 5.5 Units V V V VIN = VIL or VIH: 4.5 VOL Maximum LOW Level Output Voltage IOH = –24mA –24mA(6) 5.5 IOH = 4.5 IOUT = 50µA 5.5 V VIN = VIL or VIH: 4.5 IOL = 24mA 5.5 IOL = 24mA(6) IIN Maximum Input Leakage Current 5.5 VI = VCC, GND ±0.1 ±1.0 µA IOZ Maximum 3-STATE Leakage Current 5.5 VI = VIL, VIH; VO = VCC, GND ±0.25 ±2.5 µA ICCT Maximum ICC/Input 5.5 VI = VCC – 2.1V 1.5 mA IOLD Minimum Dynamic Output Current(7) 5.5 VOLD = 1.65V Max. 75 mA 5.5 VOHD = 3.85V Min. –75 mA Maximum Quiescent Supply Current 5.5 VIN = VCC or GND 40.0 µA VOLP Quiet Output Maximum Dynamic VOL 5.0 Figures 1 & 2(8) 1.1 1.5 V VOLV Quiet Output Minimum Dynamic VOL 5.0 Figures 1 & 2(8) –0.6 –1.2 V VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 (9) 1.9 2.2 V VILD Maximum LOW Level Dynamic Input Voltage 5.0 (9) 1.2 0.8 V IOHD ICC 0.6 4.0 Notes: 6. All outputs loaded; thresholds on input associated with output under test. 7. Maximum test duration 2.0ms, one output loaded at a time. 8. Max number of outputs defined as (n). Data Inputs are driven 0V to 3V. One output @ GND. 9. Max number of data inputs (n) switching. (n – 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1MHz. ©1990 Fairchild Semiconductor Corporation 74ACQ573, 74ACTQ573 Rev. 1.5 www.fairchildsemi.com 5 74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs DC Electrical Characteristics for ACTQ TA = +25°C, CL = 50pF VCC (V)(10) Min. Typ. Max. Min. Max. Units Propagation Delay, Dn to On 3.3 2.5 8.5 10.5 2.5 11.0 ns 5.0 1.5 5.5 7.0 1.5 7.5 Propagation Delay, LE to On 3.3 2.5 8.5 12.0 2.5 12.5 5.0 2.0 6.0 8.0 2.0 8.5 Output Enable Time 3.3 2.5 8.5 13.0 2.5 13.5 5.0 1.5 6.0 8.5 1.5 9.0 Symbol Parameter tPHL, tPLH tPLH, tPHL tPZL, tPZH tPHZ, tPLZ TA = –40°C to +85°C, CL = 50pF Output Disable Time tOSHL, tOSLH Output to Output Skew, Dn to On(11) 3.3 1.0 9.0 14.5 1.0 15.0 5.0 1.0 6.0 9.5 1.0 10.0 3.3 1.0 1.5 1.5 5.0 0.5 1.0 1.0 ns ns ns ns Notes: 10. Voltage range 5.0 is 5.0V ± 0.5V. Voltage range 3.3 is 3.3V ± 0.3V. 11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. AC Operating Requirements for ACQ TA = +25°C, CL = 50pF Symbol Parameter VCC (V)(12) Typ. TA = –40°C to +85°C, CL = 50pF Guaranteed Minimum tS Setup Time, HIGH or LOW, Dn to LE 3.3 0 3.0 3.0 5.0 0 3.0 3.0 tH Hold Time, HIGH or LOW, Dn to LE 3.3 0 1.5 1.5 5.0 0 1.5 1.5 LE Pulse Width, HIGH 3.3 2.0 4.0 4.0 5.0 2.0 4.0 4.0 tW Units ns ns ns Note: 12. Voltage range 5.0 is 5.0V ± 0.5V. Voltage range 3.3 is 3.3V ± 0.3V. ©1990 Fairchild Semiconductor Corporation 74ACQ573, 74ACTQ573 Rev. 1.5 www.fairchildsemi.com 6 74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs AC Electrical Characteristics for ACQ TA = +25°C, CL = 50pF TA = –40°C to +85°C, CL = 50pF VCC (V)(13) Min. Typ. Max. Min. Max. Units Propagation Delay, Dn to On 5.0 2.0 6.5 7.5 2.0 8.0 ns tPLH, tPHL Propagation Delay, LE to On 5.0 2.5 7.0 8.5 2.5 9.0 ns tPZL, tPZH Output Enable Time 5.0 2.0 7.0 9.0 2.0 9.5 ns tPHZ, tPLZ Output Disable Time 5.0 1.0 8.0 10.0 1.0 10.5 ns 0.5 1.0 1.0 ns Symbol Parameter tPHL, tPLH tOSHL, tOSLH Output to Output Skew, Dn to On(14) 5.0 Note: 13. Voltage range 5.0 is 5.0V ± 0.5V. 14. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. AC Operating Requirements for ACTQ TA = +25°C, CL = 50pF Symbol Parameter VCC (V)(15) Typ. TA = –40°C to +85°C, CL = 50pF Guaranteed Minimum Units tS Setup Time, HIGH or LOW, Dn to LE 5.0 0 3.0 3.0 ns tH Hold Time, HIGH or LOW, Dn to LE 5.0 0 1.5 1.5 ns tW LE Pulse Width, HIGH 5.0 2.0 4.0 4.0 ns Notes: 15. Voltage range 5.0 is 5.0V ± 0.5V. Capacitance Symbol Parameter Conditions Typ. Units CIN Input Capacitance VCC = OPEN 4.5 pF CPD Power Dissipation Capacitance VCC = 5.0V 42.0 pF ©1990 Fairchild Semiconductor Corporation 74ACQ573, 74ACTQ573 Rev. 1.5 www.fairchildsemi.com 7 74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs AC Electrical Characteristics for ACTQ VOLP/VOLV and VOHP/VOHV: The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. ■ Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. ■ Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. ■ Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50pF, 500Ω. 2. Deskew the HFS generator so that no two channels have greater than 150ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. VILD and VIHD: ■ Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. ■ First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. ■ Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. ■ Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1MHz. Greater frequencies will increase DUT heating and affect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. Notes: 16. VOHV and VOLP are measured with respect to ground reference. 17. Input pulses have the following characteristics: f = 1MHz, tr = 3ns, tf = 3ns, skew < 150ps. Figure 1. Quiet Output Noise Voltage Waveforms ©1990 Fairchild Semiconductor Corporation 74ACQ573, 74ACTQ573 Rev. 1.5 Figure 2. Simultaneous Switching Test Circuit www.fairchildsemi.com 8 74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs FACT Noise Characteristics Dimensions are in inches (millimeters) unless otherwise noted. Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1990 Fairchild Semiconductor Corporation 74ACQ573, 74ACTQ573 Rev. 1.5 www.fairchildsemi.com 9 74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs Physical Dimensions 74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1990 Fairchild Semiconductor Corporation 74ACQ573, 74ACTQ573 Rev. 1.5 www.fairchildsemi.com 10 74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 5. 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA20 ©1990 Fairchild Semiconductor Corporation 74ACQ573, 74ACTQ573 Rev. 1.5 www.fairchildsemi.com 11 74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 6. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 ©1990 Fairchild Semiconductor Corporation 74ACQ573, 74ACTQ573 Rev. 1.5 www.fairchildsemi.com 12 ® ACEx Across the board. Around the world.¥ ActiveArray¥ Bottomless¥ Build it Now¥ CoolFET¥ CROSSVOLT¥ CTL™ Current Transfer Logic™ DOME¥ 2 E CMOS¥ ® EcoSPARK EnSigna¥ FACT Quiet Series™ ® FACT ® FAST FASTr¥ FPS¥ ® FRFET GlobalOptoisolator¥ GTO¥ HiSeC¥ i-Lo¥ ImpliedDisconnect¥ IntelliMAX¥ ISOPLANAR¥ MICROCOUPLER¥ MicroPak¥ MICROWIRE¥ MSX¥ MSXPro¥ OCX¥ OCXPro¥ ® OPTOLOGIC ® OPTOPLANAR PACMAN¥ POP¥ ® Power220 ® Power247 PowerEdge¥ PowerSaver¥ ® PowerTrench Programmable Active Droop¥ ® QFET QS¥ QT Optoelectronics¥ Quiet Series¥ RapidConfigure¥ RapidConnect¥ ScalarPump¥ SMART START¥ ® SPM STEALTH™ SuperFET¥ SuperSOT¥-3 SuperSOT¥-6 SuperSOT¥-8 SyncFET™ TCM¥ ® The Power Franchise ® TinyLogic TINYOPTO¥ TinyPower¥ TinyWire¥ TruTranslation¥ PSerDes¥ ® UHC UniFET¥ VCX¥ Wire¥ ™ TinyBoost¥ TinyBuck¥ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Definition Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I24 ©1990 Fairchild Semiconductor Corporation 74ACQ573, 74ACTQ573 Rev. 1.5 www.fairchildsemi.com 13 74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.