LTC3567 High Efficiency USB Power Manager Plus 1A Buck-Boost Converter with I2C Control DESCRIPTION FEATURES Power Manager n High Efficiency Switching PowerPath™ Controller with Bat-Track™ Adaptive Output Control n Programmable USB or Wall Current Limit (100mA/500mA/1A) n Full Featured Li-Ion/Polymer Battery Charger n “Instant-On” Operation with a Discharged Battery n 1.5A Maximum Charge Current n Internal 180mΩ Ideal Diode Plus External Ideal Diode Controller Powers Load in Battery Mode n Low No-Load I When Powered from BAT (<30μA) Q 1A Buck-Boost DC/DC n High Efficiency (1A I OUT) n 2.25MHz Constant Frequency Operation n Low No-Load Quiescent Current (~13μA) n Zero Shutdown Current n I2C Control of All Functions n The LTC3567’s switching input stage transmits nearly all of the 2.5W available from the USB port to the system load with minimal power wasted as heat. This feature allows the LTC3567 to provide more power to the application and eases thermal budgeting constraints in small spaces. The synchronous buck-boost DC/DC can provide up to 1A output current. The LTC3567 is available in a low profile 24-pin (4mm × 4mm × 0.75mm) QFN surface mount package. APPLICATIONS n The LTC®3567 is a highly integrated power management and battery charger IC for Li-Ion/Polymer battery applications. It includes a high efficiency current limited switching PowerPath manager with automatic load prioritization, a battery charger, an ideal diode, and a high efficiency synchronous buck-boost switching regulator. Designed specifically for USB applications, the LTC3567’s switching power manager automatically limits input current to a maximum of either 100mA or 500mA for USB or 1A for adapter-powered applications. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. PowerPath and Bat-Track are a trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6522118 and 6404251. HDD Based MP3 Players, PDA, GPS, PMP Products Other USB Based Handheld Products TYPICAL APPLICATION LTC3567 USB Power Manager with a 3.3V/1A Buck-Boost FROM AC ADAPTER Switching Regulator Efficiency to System Load (POUT/PBUS) 3.3μH VBUS SW 10μF CLPROG 3.01k 100k 0.1μF DIGITAL CONTROL PROG 90 80 OPTIONAL 2k BAT CHRG LTC3567 EN1 SDA DVCC + LDO3V3 VIN1 SWAB1 CHRGEN SCL I2C SERIAL INTERFACE 100 GATE NTC T 100k VOUT = BAT + 300mV OTHER DC/DCs VOUT 4.7μF Li-Ion 3.3V/20mA ALWAYS ON LDO 1μF 70 BAT = 4.2V 60 BAT = 3.3V 50 40 30 2.2μH 1μF SWCD1 VOUT1 3.3V/1A HDD 324k 10μF FB1 1.5nF VC1 EFFICIENCY (%) FROM USB 105k 20 10 0 0.01 VBUS = 5V IBAT = 0mA 10x MODE 0.1 IOUT (A) 1 3567 TA01b 3567 TA01 3567f 1 LTC3567 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) VBUS (Transient) t<1ms, Duty Cycle<1% ...... –0.3V to 7V VBUS (Static), VIN1, BAT, NTC, CHRG, DVCC, SCL, SDA, EN1, CHRGEN ................................. –0.3V to 6V FB1, VC1 .................–0.3V to Lesser of 6V or VIN1 + 0.3V ICLPROG ....................................................................3mA ICHRG ......................................................................50mA IPROG ........................................................................2mA ILDO3V3 ...................................................................30mA ISW, IBAT, IVOUT ............................................................2A IVOUT1, ISWAB1, ISWCD1, ............................................2.5A Operating Temperature Range (Note 2).... –40°C to 85°C Junction Temperature (Note 3) ............................. 125°C Storage Temperature Range................... –65°C to 125°C BAT VOUT VBUS SW CHRGEN EN1 TOP VIEW 24 23 22 21 20 19 LDO3V3 1 18 GATE CLPROG 2 17 GND NTC 3 16 CHRG 25 FB1 4 15 PROG GND 9 10 11 12 SWCD1 8 VOUT1 7 VIN1 13 SCL DVCC 14 SDA GND 6 SWAB1 VC1 5 UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3567EUF#PBF LTC3567EUF#TRPBF 3567 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VIN1 = VOUT1 = 3.8V, VBAT = 3.8V, DVCC = 3.3V, RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX 95 460 860 0.38 100 500 1000 0.50 UNITS PowerPath Switching Regulator VBUS Input Supply Voltage IBUSLIM Total Input Current 1x Mode, VOUT = BAT 5x Mode, VOUT = BAT 10x Mode, VOUT = BAT Suspend Mode, VOUT = BAT 4.35 IBUSQ VBUS Quiescent Current 1x Mode, IOUT = 0mA 5x Mode, IOUT = 0mA 10x Mode, IOUT = 0mA Suspend Mode, IOUT = 0mA 7 15 15 0.044 mA mA mA mA hCLPROG (Note 4) Ratio of Measured VBUS current to CLPROG Program Current 1x Mode 5x Mode 10x Mode Suspend Mode 224 1133 2140 11.3 mA/mA mA/mA mA/mA mA/mA l l l l 87 436 800 0.31 5.5 V mA mA mA mA 3567f 2 LTC3567 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VIN1 = VOUT1 = 3.8V, VBAT = 3.8V, DVCC = 3.3V, RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS IOUT (POWERPATH) VOUT Current Available Before Loading BAT 1x Mode, BAT = 3.3V 5x Mode, BAT = 3.3V 10x Mode, BAT = 3.3V Suspend Mode MIN 135 672 1251 0.32 mA mA mA mA VCLPROG CLPROG Servo Voltage in Current Limit 1x, 5x, 10x Modes Suspend Mode 1.188 100 V mV VUVLO_VBUS VBUS Undervoltage Lockout Rising Threshold Falling Threshold 3.95 TYP 4.30 4.00 MAX 4.35 V V VUVLO_VBUS-VBAT VBUS to BAT Differential Undervoltage Lockout Rising Threshold Falling Threshold VOUT VOUT Voltage 1x, 5x, 10x Modes, 0V < BAT < 4.2V, IOUT = 0mA, Battery Charger Off 3.4 BAT+0.3 4.7 V USB Suspend Mode, IOUT = 250μA 4.5 4.6 4.7 V 1.8 2.25 2.7 MHz fOSC Switching Frequency 200 50 UNITS l mV mV RPMOS_POWERPATH PMOS On-Resistance 0.18 Ω RNMOS_POWERPATH NMOS On-Resistance 0.30 Ω IPEAK_POWERPATH Peak Switch Current Limit 2 3 A A 1x, 5x Modes 10x Mode Battery Charger VFLOAT BAT Regulated Output Voltage ICHG Constant Current Mode Charge Current IBAT l Battery Drain Current VPROG PROG Pin Servo Voltage VPROG_TRIKL PROG Pin Servo Voltage in Trickle Charge RPROG = 5k VBUS > VUVLO, Battery Charger Off, IOUT = 0μA VBUS = 0V, IOUT = 0μA (Ideal Diode Mode) 4.179 4.165 4.200 4.200 4.221 4.235 V V 980 185 1022 204 1065 223 mA mA 2 3.5 5 μA 27 38 μA VBAT < VTRIKL 1.000 V 0.100 V VC/10 C/10 Threshold Voltage at PROG 100 mV hPROG Ratio of IBAT to PROG Pin Current 1022 mA/mA ITRKL Trickle Charge Current BAT < VTRKL VTRKL Trickle Charge Threshold Voltage BAT Rising ΔVTRKL Trickle Charge Hysteresis Voltage VRECHRG Recharge Battery Threshold Voltage Threshold Voltage Relative to VFLOAT tTERM Safety Timer Termination Timer Starts When BAT = VFLOAT 3.3 tBADBAT Bad Battery Termination Time BAT < VTRKL 0.42 hC/10 End of Charge Indication Current Ratio (Note 5) 0.088 VCHRG CHRG Pin Output Low Voltage ICHRG = 5mA ICHRG CHRG Pin Leakage Current VCHRG = 5V 100 2.7 2.85 mA 3.0 135 –75 –100 V mV –125 mV 4 5 Hour 0.5 0.63 Hour 0.1 0.112 mA/mA 65 100 mV 1 μA 3567f 3 LTC3567 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VIN1 = VOUT1 = 3.8V, VBAT = 3.8V, DVCC = 3.3V, RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RON_CHG Battery Charger Power FET On Resistance (Between VOUT and BAT) 0.18 Ω TLIM Junction Temperature in Constant Temperature Mode 110 °C NTC VCOLD Cold Temperature Fault Threshold Voltage Rising Threshold Hysteresis 75.0 76.5 1.5 78.0 %VBUS %VBUS VHOT Hot Temperature Fault Threshold Voltage Falling Threshold Hysteresis 33.4 34.9 1.5 36.4 %VBUS %VBUS VDIS NTC Disable Threshold Voltage Falling Threshold Hysteresis 0.7 1.7 50 2.7 %VBUS mV INTC NTC Leakage Current VNTC = VBUS = 5V –50 50 nA VFWD Forward Voltage VBUS = 0V, IOUT = 10mA IOUT = 10mA RDROPOUT Internal Diode On-Resistance, Dropout VBUS = 0V IMAX_DIODE Internal Diode Current Limit Ideal Diode 2 15 mV mV 0.18 Ω 1.6 A Always On 3.3V Supply VLDO3V3 Regulated Output Voltage 0mA < ILDO3V3 < 25mA 3.1 3.3 3.5 V RCL_LDO3V3 Closed-Loop Output Resistance 4 Ω ROL_LDO3V3 Dropout Output Resistance 23 Ω Logic (CHRGEN, EN1) VIL Logic Low Input Voltage 0.4 VIH Logic High Input Voltage IPD_EN1 EN1 Pull-Down Current 1.6 IPD_CHRGEN CHRGEN Pull-Down Current 1.6 1.2 V V μA 10 μA 5.5 V 1 μA I2C Port (Note 6) DVCC Input Supply Voltage IDVCC DVCC Current VDVCC_UVLO DVCC UVLO ADDRESS I2C Address VIH, SDA, SCL Input High Voltage VIL, SDA, SCL Input Low Voltage 1.6 SCL/SDA = 0kHz 0.3 1.0 V 0001001[0] 70 –1 %DVCC %DVCC IIH, IIL SDA, SCL Input High/Low Current VOLSDA SDA Output Low Voltage fSCL Clock Operating Frequency tBUF Bus Free Time Between Stop and Start Condition 1.3 μs tHD_STA Hold Time After (Repeated) Start Condition 0.6 μs tSU_STA Repeated Start Condition Setup Time 0.6 μs ISDA = 3mA 0 30 1 μA 0.4 V 400 kHz 3567f 4 LTC3567 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VIN1 = VOUT1 = 3.8V, VBAT = 3.8V, DVCC = 3.3V, RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX tSU_STO Stop Condition Setup Time tHD_DAT (O) Data Hold Time Output 0 tHD_DAT (I) Data Hold Time Input 0 ns tSU_DAT Data Setup Time 100 ns tLOW SCL Clock Low Period 1.3 μs tHIGH SCL Clock High Period 0.6 μs tf Clock/Data Fall Time CB = Capacitance of One BUS Line (pF) 20+0.1•CB 300 ns tr Clock/Data Rise Time CB = Capacitance of One BUS Line (pF) 20+0.1•CB 300 ns tSP Input Spike Suppression Pulse Width 50 ns 0.6 UNITS μs 900 ns Buck-Boost Regulator VIN1 Input Supply Voltage VOUTUVLO VOUT UVLO – VOUT Falling VOUT UVLO – VOUT Rising 2.7 VIN1 Connected to VOUT Through Low Impedance. Switching Regulator is Disabled in UVLO 2.5 l 1.8 5.5 V 2.6 2.8 2.9 V V 2.25 2.7 MHz fOSC Oscillator Frequency IVIN1 Input Current PWM Mode, IOUT1 = 0μA Burst Mode® Operation, IOUT1 = 0μA Shutdown 220 13 0 400 20 1 μA μA μA VOUT1(LOW) Minimum Regulated Output Voltage For Burst Mode Operation or Synchronous PWM Operation 2.65 2.75 V VOUT1(HIGH) Maximum Regulated Output Voltage ILIMF1 Forward Current Limit (Switch A) PWM Mode IPEAK1(BURST) Forward Burst Current Limit (Switch A) IZERO1(BURST) 5.50 5.60 V l 2 2.5 3 Burst Mode Operation l 200 275 350 mA Reverse Burst Current Limit (Switch D) Burst Mode Operation l –30 0 30 mA IMAX1(BURST) Maximum Deliverable Output Current in Burst Mode Operation 2.7V ≤ VIN1 ≤ 5.5V, 2.75V ≤ VOUT1 ≤ 5.5V (Note 6) VFBHIGH1 Maximum Servo Voltage Full Scale (1,1,1,1) l 0.780 0.800 0.820 Zero Scale (0,0,0,0) l 0.405 0.425 0.445 50 A mA V VFBLOW1 Minimum Servo Voltage VLSB1 VFB1 Servo Voltage Step Size IFB1 FB1 Input Current VFB1 = 0.8V RDS(ON)P PMOS RDS(ON) Switches A, D 0.22 Ω RDS(ON)N NMOS RDS(ON) Switches B, C 0.17 Ω 25 -50 V mV 50 nA ILEAK(P) PMOS Switch Leakage Switches A, D –1 1 μA ILEAK(N) NMOS Switch Leakage Switches B, C –1 1 μA RVOUT1 VOUT1 Pull-Down in Shutdown DBUCK(MAX) Maximum Buck Duty Cycle PWM Mode DBOOST(MAX) Maximum Boost Duty Cycle PWM Mode tSS1 Soft-Start Time 10 l 100 kΩ % 75 % 0.5 ms Burst Mode is a registered trademark of Linear Technology Corporation. 3567f 5 LTC3567 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3567E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: The LTC3567 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperatures will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 4: Total Input current is the sum of quiescent current, IVBUSQ, and measured current given by: VCLPROG/RCLPROG • (hCLPROG + 1) Note 5: hC/10 is expressed as a fraction of measured full charge current with indicated PROG resistor. Note 6: Guaranteed by design. TYPICAL PERFORMANCE CHARACTERISTICS Ideal Diode Resistance vs Battery Voltage Ideal Diode V-I Characteristics 1.0 0.20 INTERNAL IDEAL DIODE ONLY 0.4 0.2 INTERNAL IDEAL DIODE 0.15 0.10 INTERNAL IDEAL DIODE WITH SUPPLEMENTAL EXTERNAL VISHAY Si2333 PMOS 0.05 VBUS = 0V VBUS = 5V 0.04 0.12 0.16 0.08 FORWARD VOLTAGE (V) 0 2.7 0.20 3.0 3.6 3.9 3.3 BATTERY VOLTAGE (V) 3567 G01 3.25 4.2 700 150 600 125 VBUS = 5V RPROG = 1k RCLPROG = 2.94k 400 300 200 4.2 3567 G04 600 800 400 OUTPUT CURRENT (mA) 25 IVOUT = 0μA VBUS = 0V 20 VBUS = 5V RPROG = 1k RCLPROG = 2.94k 100 75 50 0 1000 Battery Drain Current vs Battery Voltage 15 10 VBUS = 5V (SUSPEND MODE) 5 25 100 200 0 3567 G03 USB Limited Battery Charge Current vs Battery Voltage CHARGE CURRENT (mA) CHARGE CURRENT (mA) BAT = 3.4V 3.75 3567 G02 USB Limited Battery Charge Current vs Battery Voltage 5x USB SETTING, BATTERY CHARGER SET FOR 1A 0 3.0 3.3 3.6 2.7 3.9 BATTERY VOLTAGE (V) 4.00 3.50 BATTERY CURRENT (μA) 0 VBUS = 5V 5x MODE 4.25 OUTPUT VOLTAGE (V) RESISTANCE (Ω) CURRENT (A) 4.50 BAT = 4V 0.6 500 Output Voltage vs Output Current (Battery Charger Disabled) 0.25 INTERNAL IDEAL DIODE WITH SUPPLEMENTAL EXTERNAL VISHAY Si2333 PMOS 0.8 0 TA = 25°C unless otherwise noted. 1x USB SETTING, BATTERY CHARGER SET FOR 1A 2.7 3.0 3.3 3.6 3.9 BATTERY VOLTAGE (V) 4.2 3567 G05 0 2.7 3.0 3.6 3.9 3.3 BATTERY VOLTAGE (V) 4.2 3567 G06 3567f 6 LTC3567 TYPICAL PERFORMANCE CHARACTERISTICS Battery Charging Efficiency vs Battery Voltage with No External Load (PBAT/PBUS) 100 BAT = 3.8V 1x MODE 90 RCLPROG = 3.01k RPROG = 1k IVOUT = 0mA 5x, 10x MODE VBUS Current vs VBUS Voltage (Suspend) 50 BAT = 3.8V IVOUT = 0mA 5x CHARGING EFFICIENCY QUIESCENT CURRENT (μA) PowerPath Switching Regulator Efficiency vs Output Current 100 TA = 25°C unless otherwise noted. 80 EFFICIENCY (%) EFFICIENCY (%) 90 70 60 1x CHARGING EFFICIENCY 80 70 50 40 0.01 0.1 OUTPUT CURRENT (A) 60 2.7 1 3.0 3.6 3.9 3.3 BATTERY VOLTAGE (V) 3567 G07 0.1 0.3 0.4 0.2 LOAD CURRENT (mA) 0.1 0.3 0.4 0.2 LOAD CURRENT (mA) BAT = 3.6V BAT = 3V BAT = 3.1V BAT = 3.2V BAT = 3.3V 2.8 0.5 5 0 15 20 10 LOAD CURRENT (mA) Low-Battery (Instant-On) Output Voltage vs Temperature 4.21 3.68 4.20 3.66 BAT = 2.7V IVOUT = 100mA 5x MODE OUTPUT VOLTAGE (V) 500 FLOAT VOLTAGE (V) 25 3567 G12 3567 G11 600 200 BAT = 3.5V 3.0 Battery Charger Float Voltage vs Temperature THERMAL REGULATION BAT = 3.4V 3.2 2.6 0 5 3567 G09 OUTPUT VOLTAGE (V) 0.2 Battery Charge Current vs Temperature 300 4 3.3V LDO Output Voltage vs Load Current, VBUS = 0V 0.3 0 0.5 400 3 2 BUS VOLTAGE (V) BAT = 3.9V, 4.2V 3567 G10 CHARGE CURRENT (mA) 1 0 0.1 VBUS = 5V BAT = 3.3V RCLPROG = 2.94k 0 0 4.2 VBUS = 5V BAT = 3.3V RCLPROG = 2.94k 0.4 VBUS CURRENT (mA) OUTPUT VOLTAGE (V) 4.5 2.5 10 3.4 0.5 3.0 20 VBUS Current vs Load Current in Suspend 5.0 3.5 30 3567 G08 Output Voltage vs Load Current in Suspend 4.0 40 4.19 4.18 3.64 3.62 100 RPROG = 2k 10x MODE 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 3567 G13 4.17 –40 –15 35 10 TEMPERATURE (°C) 60 85 3567 G14 3.60 –40 –15 35 10 TEMPERATURE (°C) 60 85 3567 G15 3567f 7 LTC3567 TYPICAL PERFORMANCE CHARACTERISTICS VBUS Quiescent Current vs Temperature 15 2.4 FREQUENCY (MHz) VBUS = 5V QUIESCENT CURRENT (mA) 2.6 BAT = 3.6V VBUS = 0V 2.2 BAT = 3V VBUS = 0V 2.0 VBUS Quiescent Current in Suspend vs Temperature 70 VBUS = 5V IVOUT = 0μA 5x MODE 12 QUIESCENT CURRENT (μA) Oscillator Frequency vs Temperature TA = 25°C unless otherwise noted. 9 1x MODE 6 IVOUT = 0μA 60 50 40 BAT = 2.7V VBUS = 0V 1.8 –40 –15 35 10 TEMPERATURE (°C) 60 3 –40 85 –15 35 10 TEMPERATURE (°C) 60 CHRG Pin Current vs Voltage (Pull-Down State) 60 0mA 40 VLDO3V3 20mV/DIV AC COUPLED 40 BATTERY CURRENT (μA) CHRG PIN CURRENT (mA) 50 ILDO3V3 5mA/DIV 20 VBAT = 3.8V 1 3 4 2 CHRG PIN VOLTAGE (V) 20μs/DIV BAT = 3.8V VBUS = 0V BUCK REGULATORS OFF 30 20 0 –40 –15 35 10 TEMPERATURE (°C) 3567 G19 0.40 0.35 0.20 0.30 2600 85 Buck-Boost Regulator Burst Mode Operation Quiescent Current 14.0 VIN1 = 3V VOUT1 = 3.3V 13.5 2550 VIN1 = 4.5V VIN1 = 3.6V 0.10 0.20 0.05 0.15 0.10 5 25 45 65 85 105 125 TEMPERATURE (°C) 3567 G22 VIN1 = 3V VIN1 = 4.5V IQ (μA) 0.25 13.0 2500 ILIMF (mA) NMOS VIN1 = 3V NMOS VIN1 = 3.6V NMOS VIN1 = 4.5V NMOS RDS(ON) (Ω) PMOS RDS(ON) (Ω) Buck-Boost Regulator Current Limit vs Temperature PMOS VIN1 = 3V PMOS VIN1 = 3.6V 0.25 PMOS VIN1 = 4.5V 0 –55 –35 –15 60 3567 G21 RDS(ON) for Buck-Boost Regulator Power Switches vs Temperature 0.15 85 10 3567 G20 5 0.30 60 Battery Drain Current vs Temperature VBUS = 5V BAT = 3.8V 0 35 10 TEMPERATURE (°C) 3567 G18 3.3V LDO Step Response (5mA to 15mA) 80 0 –15 3567 G17 3567 G16 100 30 –40 85 2450 12.5 2400 12.0 2350 11.5 2300 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 3567 G23 11.0 –55 –35 –15 VIN1 = 3.6V 5 25 45 65 85 105 125 TEMPERATURE (°C) 3567 G24 3567f 8 LTC3567 TYPICAL PERFORMANCE CHARACTERISTICS Buck-Boost Regulator PWM Mode Efficiency Buck-Boost Regulator vs ILOAD 90 90 BURST MODE OPERATION 90 CURVES 80 80 BURST MODE OPERATION CURVES VIN1 = 3V VIN1 = 3.6V VIN1 = 4.5V 70 60 50 PWM MODE CURVES VIN1 = 3V VIN1 = 3.6V VIN1 = 4.5V 40 30 20 VOUT1 = 3.3V TYPE 3 COMPENSATION 10 0 0.1 1 10 ILOAD (mA) 100 1000 100 70 ILOAD = 50mA ILOAD = 200mA ILOAD = 1000mA 60 50 40 20 10 3.300 3.289 3.278 1 10 100 1A 1 10 ILOAD (mA) 300 STEADY STATE ILOAD START-UP WITH A RESISTIVE LOAD START-UP WITH A CURRENT SOURCE LOAD 250 100 1000 3567 G27 Buck-Boost Regulator Load Step, 0mA to 300mA CH1 VOUT1 AC 100mV/DIV 200 150 CH2 ILOAD DC 200mA/DIV 100 50 VOUT1 = 3.3V TYPE 3 COMPENSATION VOUT1 = 5V TYPE 3 COMPENSATION 3567 G26 REDUCTION BELOW 1A (mA) 3.311 3.267 0 0.1 Reduction in Current Deliverability at Low VIN1 VIN1 = 3V VIN1 = 3.6V VIN1 = 4.5V VIN1 = 3V VIN1 = 3.6V VIN1 = 4.5V 40 10 VOUT1 = 3.3V TYPE 3 COMPENSATION 0 3.1 3.9 2.7 3.5 VIN1 (V) 4.7 VIN1 = 3V VIN1 = 3.6V VIN1 = 4.5V 50 20 4.3 PWM MODE CURVES 60 30 Buck-Boost Regulator Load Regulation 3.322 70 30 3567 G25 3.333 EFFICIENCY (%) 100 EFFICIENCY (%) EFFICIENCY (%) Buck-Boost Regulator PWM Efficiency vs VIN1 100 80 VOUT1 (V) TA = 25°C unless otherwise noted. VOUT1 = 3.3V TYPE 3 COMPENSATION 0 2.7 3.1 3.5 ILOAD (mA) 3567 G28 3.9 VIN1 (V) 4.3 4.7 VIN1 = 4.2V VOUT1 = 3.3V L = 2.2μH COUT = 47μF 100μs/DIV 3567 G30 3567 G29 PIN FUNCTIONS LDO3V3 (Pin 1): 3.3V LDO Output Pin. This pin provides a regulated always-on, 3.3V supply voltage. LDO3V3 gets its power from VOUT. It may be used for light loads such as a watchdog microprocessor or real time clock. A 1μF capacitor is required from LDO3V3 to ground. If the LDO3V3 output is not used it should be disabled by connecting it to VOUT. when the synchronous switch of the PowerPath switching regulator is on. The switching regulator delivers power until the CLPROG pin reaches 1.188V. Several VBUS current limit settings are available via user input which will typically correspond to the 500mA and the 100mA USB specifications. A multilayer ceramic averaging capacitor or R-C network is required at CLPROG for filtering. CLPROG (Pin 2): USB Current Limit Program and Monitor Pin. A resistor from CLPROG to ground determines the upper limit of the current drawn from the VBUS pin. A fraction of the VBUS current is sent to the CLPROG pin NTC (Pin 3): Input to the Thermistor Monitoring Circuits. The NTC pin connects to a battery’s thermistor to determine if the battery is too hot or too cold to charge. If the battery’s temperature is out of range, charging is paused 3567f 9 LTC3567 PIN FUNCTIONS until it re-enters the valid range. A low drift bias resistor is required from VBUS to NTC and a thermistor is required from NTC to ground. If the NTC function is not desired, the NTC pin should be grounded. FB1 (Pin 4): Feedback Input for the (Buck-Boost) Switching Regulator. When the regulator’s control loop is complete, this pin servos to 1 of 16 possible set-points based on the commanded value from the I2C serial port. See Table 4. VC1 (Pin 5): Output of the Error Amplifier and Voltage Compensation Node for the (Buck-Boost) Switching Regulator. External Type I or Type III compensation (to FB1) connects to this pin. See Applications Section for selecting buck-boost loop compensation components. GND (Pin 6, 12): Power GND Pins for the buck-boost. SWAB1 (Pin 7): Switch Node for the (Buck-Boost) Switching Regulator. Connected to internal power switches A and B. External inductor connects between this node and SWCD1. DVCC (Pin 8): Logic Supply for the I2C Serial Port. VIN1 (Pin 9): Power Input for the (Buck-Boost) Switching Regulator. This pin will generally be connected to VOUT (Pin 20). A 1μF (min) MLCC capacitor is recommended on this pin. VOUT1 (Pin 10): Regulated Output Voltage for the (BuckBoost) Switching Regulator. SWCD1 (Pin 11): Switch Node for the (Buck-Boost) Switching Regulator. Connected to internal power switches C and D. External inductor connects between this node and SWAB1. SCL (Pin 13): Clock Input Pin for the I2C Serial Port. The I2C logic levels are scaled with respect to DVCC. SDA (Pin 14): Data Input Pin for the I2C Serial Port. The I2C logic levels are scaled with respect to DVCC. PROG (Pin 15): Charge Current Program and Charge Current Monitor Pin. Connecting a resistor from PROG to ground programs the charge current. If sufficient input power is available in constant-current mode, this pin servos to 1V. The voltage on this pin always represents the actual charge current. CHRG (Pin 16): Open-Drain Charge Status Output. The CHRG pin indicates the status of the battery charger. Four possible states are represented by CHRG: charging, not charging, unresponsive battery and battery temperature out of range. CHRG is modulated at 35kHz and switches between a low and high duty cycle for easy recognition by either humans or microprocessors. See Table 1. CHRG requires a pull-up resistor and/or LED to provide indication. GND (Pin 17): GND pin for USB Power Manager. GATE (Pin 18): Analog Output. This pin controls the gate of an optional external P-channel MOSFET transistor used to supplement the ideal diode between VOUT and BAT. The external ideal diode operates in parallel with the internal ideal diode. The source of the P-channel MOSFET should be connected to VOUT and the drain should be connected to BAT. If the external ideal diode FET is not used, GATE should be left floating. BAT (Pin 19): Single Cell Li-Ion Battery Pin. Depending on available VBUS power, a Li-Ion battery on BAT will either deliver power to VOUT through the ideal diode or be charged from VOUT via the battery charger. VOUT (Pin 20): Output Voltage of the Switching PowerPath Controller and Input Voltage of the Battery Charger. The majority of the portable product should be powered from VOUT. The LTC3567 will partition the available power between the external load on VOUT and the internal battery charger. Priority is given to the external load and any extra power is used to charge the battery. An ideal diode from BAT to VOUT ensures that VOUT is powered even if the load exceeds the allotted power from VBUS or if the VBUS power source is removed. VOUT should be bypassed with a low impedance ceramic capacitor. VBUS (Pin 21): Primary Input Power Pin. This pin delivers power to VOUT via the SW pin by drawing controlled current from a DC source such as a USB port or wall adapter. SW (Pin 22): Power Transmission Pin for the USB PowerPath. The SW pin delivers power from VBUS to VOUT via the step-down switching regulator. A 3.3μH inductor should be connected from SW to VOUT. 3567f 10 LTC3567 PIN FUNCTIONS CHRGEN (Pin 23): Logic Input. This logic input pin independently enables the battery charger. Active low. Has a 1.6μA internal pull-down current source. This pin is logically ORed with its corresponding bit in the I2C serial port. pin is logically ORed with its corresponding bit in the I2C serial port. Exposed Pad (Pin 25): Ground. Buck-Boost logic and USB power manager ground connections. The Exposed Pad should be connected to a continuous ground plane on the printed circuit board directly under the LTC3567. EN1 (Pin 24): Logic Input. This logic input pin independently enables the buck-boost switching regulator. Active high. Has a 1.6μA internal pull-down current source. This BLOCK DIAGRAM 21 VBUS SW 2.25MHz PowerPath BUCK REGULATOR 22 LDO3V3 3.3V LDO VOUT SUSPEND LDO 500μA/2.5mA BATTERY TEMPERATURE MONITOR + + CHARGE STATUS 3.6V 18 – CC/CV CHARGER CHRG 1.2V 20 GATE IDEAL +– 0.3V + – 16 NTC + + 3 – CLPROG – 2 1 15mV BAT 19 PROG 15 CHRGEN VIN1 9 ENABLE SWAB1 MODE ILIM DECODE LOGIC 23 24 8 14 13 7 D/A VOUT1 CHRGEN 4 1A, 2.25MHz BUCK-BOOST REGULATOR EN1 10 SWCD1 11 DVCC SDA FB1 I2C PORT 4 VC1 SCL 5 GND 6, 12, 17, 25 3567 BD 3567f 11 LTC3567 TIMING DIAGRAM DATA BYTE A ADDRESS DATA BYTE B WR A7 0 0 0 1 0 0 1 0 SDA 0 0 0 1 0 0 1 0 ACK SCL 1 2 3 4 5 6 7 8 9 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 START STOP ACK 1 2 3 4 5 6 7 8 9 ACK 1 2 3 4 5 6 7 8 9 SDA tSU, STA tSU, DAT tLOW tHD, STA tHD, DAT tBUF tSU, STO 3567 TD SCL tHIGH tHD, STA START CONDITION tr tSP tf REPEATED START CONDITION STOP CONDITION START CONDITION OPERATION Introduction The LTC3567 is a highly integrated power management IC which includes a high efficiency switch mode PowerPath controller, a battery charger, an ideal diode, an always-on LDO and a 1A buck-boost switching regulator. The entire chip is controllable via an I2C serial port. Designed specifically for USB applications, the PowerPath controller incorporates a precision average input current step-down switching regulator to make maximum use of the allowable USB power. Because power is conserved, the LTC3567 allows the load current on VOUT to exceed the current drawn by the USB port without exceeding the USB load specifications. The PowerPath switching regulator and battery charger communicate to ensure that the input current never violates the USB specifications. The ideal diode from BAT to VOUT guarantees that ample power is always available to VOUT even if there is insufficient or absent power at VBUS. An “always-on” LDO provides a regulated 3.3V from available power at VOUT. Drawing very little quiescent current, this LDO will be on at all times and can be used to supply up to 25mA. The LTC3567 also has a general purpose buck-boost switching regulator, which can be independently enabled via direct digital control or the I2C serial port. Along with constant frequency PWM mode, the buck-boost regulator has a low power burst-only mode setting for significantly reduced quiescent current under light load conditions. High Efficiency Switching PowerPath Controller Whenever VBUS is available and the PowerPath switching regulator is enabled, power is delivered from VBUS to VOUT via SW. VOUT drives both the external load (including the buck-boost regulator) and the battery charger. If the combined load does not exceed the PowerPath switching regulator’s programmed input current limit, VOUT will track 0.3V above the battery (Bat-Track). By keeping the voltage across the battery charger low, efficiency is optimized because power lost to the linear battery charger is minimized. Power available to the external load is therefore optimized. If the combined load at VOUT is large enough to cause the switching power supply to reach the programmed input current limit, the battery charger will reduce its charge current by the amount necessary to enable the external load to be satisfied. Even if the battery charge current is 3567f 12 LTC3567 OPERATION If the voltage at BAT is below 3.3V, or the battery is not present and the load requirement does not cause the switching regulator to exceed the USB specification, VOUT will regulate at 3.6V, thereby providing “Instant-On” operation. If the load exceeds the available power, VOUT will drop to a voltage between 3.6V and the battery voltage. If there is no battery present when the load exceeds the available USB power, VOUT can drop toward ground. The power delivered from VBUS to VOUT is controlled by a 2.25MHz constant-frequency step-down switching regulator. To meet the USB maximum load specification, the switching regulator includes a control loop which ensures that the average input current is below the level programmed at CLPROG. 4.5 4.2 3.9 VOUT (V) set to exceed the allowable USB current, the USB specification will not be violated. The switching regulator will limit the average input current so that the USB specification is never violated. Furthermore, load current at VOUT will always be prioritized and only remaining available power will be used to charge the battery. Figure 1 shows the range of possible voltages at VOUT as a function of battery voltage. 300mV 3.3 3.0 2.7 2.4 2.4 2.7 3.0 3.6 3.3 BAT (V) 3.9 4.2 3567 F01 Figure 1. VOUT vs BAT Ideal Diode from BAT to VOUT The LTC3567 has an internal ideal diode as well as a controller for an optional external ideal diode. The ideal diode controller is always on and will respond quickly whenever VOUT drops below BAT. 2200 The current at CLPROG is a fraction (hCLPROG–1) of the VBUS VISHAY Si2333 OPTIONAL EXTERNAL IDEAL DIODE 2000 1800 1600 CURRENT (mA) current. When a programming resistor and an averaging capacitor are connected from CLPROG to GND, the voltage on CLPROG represents the average input current of the switching regulator. When the input current approaches the programmed limit, CLPROG reaches VCLPROG, 1.188V and power out is held constant. The input current is programmed by the B1 and B0 bits of the I2C serial port. It can be configured to limit average input current to one of several possible settings as well as be deactivated (USB suspend). The input current limit will be set by the VCLPROG servo voltage and the resistor on CLPROG according to the following expression: V IVBUS =IBUSQ + CLPROG • (hCLPROG + 1) RCLPROG NO LOAD 3.6 LTC3567 IDEAL DIODE 1400 1200 1000 800 600 ON SEMICONDUCTOR MBRM120LT3 400 200 0 0 60 120 180 240 300 360 420 480 FORWARD VOLTAGE (mV) (BAT – VOUT) 3567 F02 Figure 2. Ideal Diode Operation If the load current increases beyond the power allowed from the switching regulator, additional power will be pulled from the battery via the internal ideal diode. Furthermore, if power to VBUS (USB or wall power) is removed, then all of the application power will be provided by the battery via the ideal diode. The transition from input power to battery power at VOUT will be quick enough to allow only the 10μF capacitor to keep VOUT from drooping. The ideal diode consists of a precision amplifier that enables a large on3567f 13 LTC3567 OPERATION chip P-channel MOSFET transistor whenever the voltage at VOUT is approximately 15mV (VFWD) below the voltage at BAT. The resistance of the internal ideal diode is approximately 180mΩ. If this is sufficient for the application, then no external components are necessary. However, if more conductance is needed, an external P-channel MOSFET transistor can be added from BAT to VOUT. When an external P-channel MOSFET transistor is present, the GATE pin of the LTC3567 drives its gate for automatic ideal diode control. The source of the external P-channel MOSFET should be connected to VOUT and the drain should be connected to BAT. Capable of driving a 1nF load, the GATE pin can control an external P-channel MOSFET transistor having an on-resistance of 40mΩ or lower. Suspend LDO If the LTC3567 is configured for USB suspend mode, the switching regulator is disabled and the suspend LDO provides power to the VOUT pin (presuming there is power available to VBUS). This LDO will prevent the battery from running down when the portable product has access to a suspended USB port. Regulating at 4.6V, this LDO only becomes active when the switching converter is disabled (suspended). To remain compliant with the USB specification, the input to the LDO is current limited so that it will TO USB OR WALL ADAPTER 21 not exceed the 500μA low power suspend specification. If the load on VOUT exceeds the suspend current limit, the additional current will come from the battery via the ideal diode. 3.3V Always-On Supply The LTC3567 includes a low quiescent current low drop-out regulator that is always powered. This LDO can be used to provide power to a system pushbutton controller, standby microcontroller or real time clock. Designed to deliver up to 25mA, the always-on LDO requires at least a 1μF low impedance ceramic bypass capacitor for compensation. The LDO is powered from VOUT, and therefore will enter dropout at loads less than 25mA as VOUT falls near 3.3V. If the LDO3V3 output is not used, it should be disabled by connecting it to VOUT. VBUS Undervoltage Lockout (UVLO) An internal undervoltage lockout circuit monitors VBUS and keeps the PowerPath switching regulator off until VBUS rises above 4.30V and is at least 200mV above the battery voltage. Hysteresis on the UVLO turns off the regulator if VBUS drops below 4.00V or to within 50mV of BAT. When this happens, system power at VOUT will be drawn from the battery via the ideal diode. VBUS SW ISWITCH/N VOUT PWM AND GATE DRIVE CONSTANT CURRENT CONSTANT VOLTAGE BATTERY CHARGER IDEAL DIODE 15mV CLPROG 1.206V – + AVERAGE INPUT CURRENT LIMIT CONTROLLER + + – 2 – + + – GATE 3.5V TO (BAT + 0.3V) TO SYSTEM LOAD 22 20 OPTIONAL EXTERNAL IDEAL DIODE PMOS 18 0.3V 3.6V +– BAT 19 AVERAGE OUTPUT VOLTAGE LIMIT CONTROLLER + SINGLE CELL Li-Ion 3567 F03 Figure 3. PowerPath Block Diagram 3567f 14 LTC3567 OPERATION Battery Charger The LTC3567 includes a constant-current/constant-voltage battery charger with automatic recharge, automatic termination by safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out-oftemperature charge pausing. Battery Preconditioning When a battery charge cycle begins, the battery charger first determines if the battery is deeply discharged. If the battery voltage is below VTRKL, typically 2.85V, an automatic trickle charge feature sets the battery charge current to 10% of the programmed value. If the low voltage persists for more than 1/2 hour, the battery charger automatically terminates and indicates via the CHRG pin that the battery was unresponsive. Once the battery voltage is above 2.85V, the battery charger begins charging in full power constant-current mode. The current delivered to the battery will try to reach 1022V/ RPROG. Depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed rate. The external load will always be prioritized over the battery charge current. The USB current limit programming will always be observed and only additional power will be available to charge the battery. When system loads are light, battery charge current will be maximized. Charge Termination The battery charger has a built-in safety timer. When the voltage on the battery reaches the pre-programmed float voltage of 4.200V, the battery charger will regulate the battery voltage and the charge current will decrease naturally. Once the battery charger detects that the battery has reached 4.200V, the four hour safety timer is started. After the safety timer expires, charging of the battery will discontinue and no more current will be delivered. Automatic Recharge After the battery charger terminates, it will remain off drawing only microamperes of current from the battery. If the portable product remains in this state long enough, the battery will eventually self discharge. To ensure that the battery is always topped off, a charge cycle will automatically begin when the battery voltage falls below 4.1V. In the event that the safety timer is running when the battery voltage falls below 4.1V, it will reset back to zero. To prevent brief excursions below 4.1V from resetting the safety timer, the battery voltage must be below 4.1V for more than 1.3ms. The charge cycle and safety timer will also restart if the VBUS UVLO cycles low and then high (e.g. VBUS, is removed and then replaced), or if the battery charger is cycled on and off by either the I2C port or the CHRGEN digital I/O pin. Charge Current The charge current is programmed using a single resistor from PROG to ground. 1/1022th of the battery charge current is sent to PROG which will attempt to servo to 1.000V. Thus, the battery charge current will try to reach 1022 times the current in the PROG pin. The program resistor and the charge current are calculated using the following equations: RPROG = 1022V 1022V , ICHG = ICHG RPROG In either the constant-current or constant-voltage charging modes, the voltage at the PROG pin will be proportional to the actual charge current delivered to the battery. Therefore, the actual charge current can be determined at any time by monitoring the PROG pin voltage and using the following equation: IBAT = VPROG • 1022 RPROG In many cases, the actual battery charge current, IBAT, will be lower than ICHG due to limited input power available and prioritization with the system load drawn from VOUT. Charge Status Indication The CHRG pin indicates the status of the battery charger. Four possible states are represented by CHRG which include charging, not charging, unresponsive battery, and battery temperature out of range. The signal at the CHRG pin can be easily recognized as one of the above four states by either a human or a 3567f 15 LTC3567 OPERATION microprocessor. An open-drain output, the CHRG pin can drive an indicator LED through a current limiting resistor for human interfacing or simply a pull-up resistor for microprocessor interfacing. To make the CHRG pin easily recognized by both humans and microprocessors, the pin is either low for charging, high for not charging, or it is switched at high frequency (35kHz) to indicate the two possible faults, unresponsive battery and battery temperature out of range. When charging begins, CHRG is pulled low and remains low for the duration of a normal charge cycle. When charging is complete, i.e., the BAT pin reaches 4.200V and the charge current has dropped to one-tenth of the programmed value, the CHRG pin is released (Hi-Z). If a fault occurs, the pin is switched at 35kHz. While switching, its duty cycle is modulated between a high and low value at a very low frequency. The low and high duty cycles are disparate enough to make an LED appear to be on or off thus giving the appearance of “blinking”. Each of the two faults has its own unique “blink” rate for human recognition as well as two unique duty cycles for machine recognition. The CHRG pin does not respond to the C/10 threshold if the LTC3567 is in VBUS current limit. This prevents false end of charge indications due to insufficient power available to the battery charger. Table 1 illustrates the four possible states of the CHRG pin when the battery charger is active. Table 1. CHRG Signal STATUS FREQUENCY MODULATION (BLINK) FREQUENCY DUTY CYCLES Charging 0Hz 0Hz (Lo-Z) 100% Not Charging 0Hz 0Hz (Hi-Z) 0% NTC Fault 35kHz 1.5Hz AT 50% 6.25%, 93.75% Bad Battery 35kHz 6.1Hz AT 50% 12.5%, 87.5% An NTC fault is represented by a 35kHz pulse train whose duty cycle alternates between 6.25% and 93.75% at a 1.5Hz rate. A human will easily recognize the 1.5Hz rate as a “slow” blinking which indicates the out-of-range battery temperature while a microprocessor will be able to decode either the 6.25% or 93.75% duty cycles as an NTC fault. If a battery is found to be unresponsive to charging (i.e., its voltage remains below 2.85V for 1/2 hour), the CHRG pin gives the battery fault indication. For this fault, a human would easily recognize the frantic 6.1Hz “fast” blink of the LED while a microprocessor would be able to decode either the 12.5% or 87.5% duty cycles as a bad battery fault. Note that the LTC3567 is a 3-terminal PowerPath product where system load is always prioritized over battery charging. Due to excessive system load, there may not be sufficient power to charge the battery beyond the trickle charge threshold voltage within the bad battery timeout period. In this case, the battery charger will falsely indicate a bad battery. System software may then reduce the load and reset the battery charger to try again. Although very improbable, it is possible that a duty cycle reading could be taken at the bright-dim transition (low duty cycle to high duty cycle). When this happens the duty cycle reading will be precisely 50%. If the duty cycle reading is 50%, system software should disqualify it and take a new duty cycle reading. NTC Thermistor The battery temperature is measured by placing a negative temperature coefficient (NTC) thermistor close to the battery pack. To use this feature, connect the NTC thermistor, RNTC, between the NTC pin and ground and a resistor, RNOM, from VBUS to the NTC pin. RNOM should be a 1% resistor with a value equal to the value of the chosen NTC thermistor at 25°C (R25). A 100k thermistor is recommended since thermistor current is not measured by the LTC3567 and will have to be budgeted for USB compliance. The LTC3567 will pause charging when the resistance of the NTC thermistor drops to 0.54 times the value of R25 or approximately 54k. For Vishay “Curve 1” thermistor, this corresponds to approximately 40°C. If the battery charger is in constant-voltage (float) mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. As the temperature drops, the resistance of the NTC thermistor rises. The LTC3567 is also designed to pause charging when the value of the NTC thermistor increases to 3.25 times the value of R25. For Vishay “Curve 1” this resistance, 325k, corresponds 3567f 16 LTC3567 OPERATION to approximately 0°C. The hot and cold comparators each have approximately 3°C of hysteresis to prevent oscillation about the trip point. Grounding the NTC pin disables the NTC charge pausing function. Thermal Regulation To optimize charging time, an internal thermal feedback loop may automatically decrease the programmed charge current. This will occur if the die temperature rises to approximately 110°C. Thermal regulation protects the LTC3567 from excessive temperature due to high power operation or high ambient thermal conditions and allows the user to push the limits of the power handling capability with a given circuit board design without risk of damaging the LTC3567 or external components. The benefit of the LTC3567 thermal regulation loop is that charge current can be set according to actual conditions rather than worst-case conditions with the assurance that the battery charger will automatically reduce the current in worst-case conditions. I2C Interface The LTC3567 may receive commands from a host (master) using the standard I2C 2-wire interface. The Timing Diagram shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 I2C accelerator, are required on these lines. The LTC3567 is a receive-only (slave) device. The I2C control signals, SDA and SCL are scaled internally to the DVCC supply. DVCC should be connected to the same power supply as the microcontroller generating the I2C signals. The I2C port has an undervoltage lockout on the DVCC pin. When the DVCC is below approximately 1V, the I2C serial port is cleared and the buck-boost switching regulator is set to full scale. Bus Speed The I2C port is designed to be operated at speeds of up to 400kHz. It has built-in timing delays to ensure correct operation when addressed from an I2C compliant master device. It also contains input filters designed to suppress glitches should the bus become corrupted. Start and Stop Condition A bus master signals the beginning of a communication to a slave device by transmitting a Start condition. A Start condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a Stop condition by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. Byte Format Each byte sent to the LTC3567 must be eight bits long followed by an extra clock cycle for the Acknowledge bit to be returned by the LTC3567. The data should be sent to the LTC3567 most significant bit (MSB) first. Acknowledge The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active low) generated by the slave (LTC3567) lets the master know that the latest byte of information was received. The Acknowledge related clock pulse is generated by the master. The master releases the SDA line (high) during the Acknowledge clock cycle. The slave receiver must pull down the SDA line during the Acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. Slave Address The LTC3567 responds to only one 7-bit address which has been factory programmed to 0001001. The LSB of the address byte is 1 for Read and 0 for Write. This device is write only corresponding to an address byte of 00010010 (0x12). If the correct seven bit address is given but the R/W bit is 1, the LTC3567 will not respond. Bus Write Operation The master initiates communication with the LTC3567 with a Start condition and a 7-bit address followed by the Write Bit R/W = 0. If the address matches that of the LTC3567, the LTC3567 returns an Acknowledge. The master should then deliver the most significant data byte. Again the LTC3567 acknowledges and the cycle is repeated for 3567f 17 LTC3567 OPERATION Table 2. I2C Serial Port Mapping (Defaults 0xFF00 in Reset State or if DVCC = 0V) A7 A6 A5 A4 Reserved for Internal Use A3 A2 A1 A0 Switching Regulator Voltage (See Table 4) B7 B6 Disable Battery Charger Buck-Boost Regulator Mode (See Table 5) Table 3. USB Current Limit Settings B1 B0 USB SETTING 0 0 1x Mode (USB 100mA Limit) 0 1 10x Mode (Wall 1A Limit) 1 0 Suspend 1 1 5x Mode (USB 500mA Limit) Table 4. Buck-Boost Regulator Servo Voltage A3 A2 A1 A0 SWITCHING REGULATOR SERVO VOLTAGE 0 0 0 0 0.425V 0 0 0 1 0.450V 0 0 1 0 0.475V 0 0 1 1 0.500V 0 1 0 0 0.525V 0 1 0 1 0.550V 0 1 1 0 0.575V 0 1 1 1 0.600V 1 0 0 0 0.625V 1 0 0 1 0.650V 1 0 1 0 0.675V 1 0 1 1 0.700V 1 1 0 0 0.725V 1 1 0 1 0.750V 1 1 1 0 0.775V 1 1 1 1 0.800V Table 5. Buck-Boost Switching Regulator Modes B6 SWITCHING REGULATOR MODE 0 PWM Mode 1 Burst Mode Operation the total of one address byte and two data bytes. Each data byte is transferred to an internal holding latch upon the return of an Acknowledge. After both data bytes have been transferred to the LTC3567, the master may terminate B5 B4 B3 Reserved for Internal Use B2 Enable Buck-Boost Regulator B1 B0 Input Current Limit (See Table 3) the communication with a Stop condition. Alternatively, a Repeat-Start condition can be initiated by the master and another chip on the I2C bus can be addressed. This cycle can continue indefinitely and the LTC3567 will remember the last input of valid data that it received. Once all chips on the bus have been addressed and sent valid data, a global Stop condition can be sent and the LTC3567 will update its command latch with the data that it had received. In certain circumstances the data on the I2C bus may become corrupted. In these cases the LTC3567 responds appropriately by preserving only the last set of complete data that it has received. For example, assume the LTC3567 has been successfully addressed and is receiving data when a Stop condition mistakenly occurs. The LTC3567 will ignore this Stop condition and will not respond until a new Start condition, correct address, new set of data and Stop condition are transmitted. Likewise, with only one exception, if the LTC3567 was previously addressed and sent valid data but not updated with a Stop, it will respond to any Stop that appears on the bus, independent of the number of Repeat-Starts that have occurred. If a Repeat-Start is given and the LTC3567 successfully acknowledges its address and first byte, it will not respond to a Stop until both bytes of the new data have been received and acknowledged. Disabling the I2C Port The I2C serial port can be disabled by grounding the DVCC pin. In this mode, control automatically passes to the individual logic input pins EN1 and CHRGEN. However, with the I2C port disabled, the programmable buck-boost switching regulator defaults to a fixed servo voltage of 0.8V in PWM mode, and the USB input current limit defaults to 1x mode (100mA limit). By default the battery charger will be enabled and the buck-boost will be disabled. 3567f 18 LTC3567 OPERATION Buck-Boost DC/DC Switching Regulator Buck-Boost Regulator PWM Operating Mode The LTC3567 contains a 2.25MHz constant-frequency voltage mode buck-boost switching regulator. The regulator provides up to 1A of output load current. The buck-boost can be programmed to a minimum output voltage of 2.75V and can be used to power a microcontroller core, microcontroller I/O, memory, disk drive, or other logic circuitry. When controlled by I2C, the buck-boost has programmable set-points for on-the-fly power savings. To suit a variety of applications, a selectable mode function allows the user to trade off noise for efficiency. Two modes are available to control the operation of the LTC3567’s buck-boost regulator. At moderate to heavy loads, the constant frequency PWM mode provides the least noise switching solution. At lighter loads Burst Mode operation may be selected. The full-scale output voltage is programmed by a user-supplied resistive divider returned to the FB1 pin. An error amplifier compares the divided output voltage with a reference and adjusts the compensation voltage accordingly until the FB1 has stabilized to the selected reference voltage (0.425V to 0.8V). The buck-boost regulator also includes a soft-start to limit inrush current and voltage overshoot when powering on, short circuit current protection, and switch node slew limiting circuitry for reduced radiated EMI. In PWM mode the voltage seen at FB1 is compared to the selected reference voltage (0.425V to 0.8V). From the FB1 voltage an error amplifier generates an error signal seen at VC1. This error signal commands PWM waveforms that modulate switches A, B, C, and D. Switches A and B operate synchronously as do switches C and D. If VIN1 is significantly greater than the programmed VOUT1, then the converter will operate in buck mode. In this mode switches A and B will be modulated, with switch D always on (and switch C always off), to step down the input voltage to the programmed output. If VIN1 is significantly less than the programmed VOUT1, then the converter will operate in boost mode. In this mode switches C and D are modulated, with switch A always on (and switch B always off), to step up the input voltage to the programmed output. If VIN1 is close to the programmed VOUT1, then the converter will operate in 4-switch mode. In this mode the switches sequence through the pattern of AD, AC, BD to either step the input voltage up or down to the programmed output. Input Current Limit The input current limit comparator will shut the input PMOS switch off once current exceeds 2.5A (typical). The 2.5A input current limit also protects against a grounded VOUT1 node. Output Overvoltage Protection If the FB1 node were inadvertently shorted to ground, then the output would increase indefinitely with the maximum current that could be sourced from VIN1. The LTC3567 protects against this by shutting off the input PMOS if the output voltage exceeds a 5.6V (typical). Low Output Voltage Operation When the output voltage is below 2.65V (typical) during start-up, Burst Mode operation is disabled and switch D is turned off (allowing forward current through the well diode and limiting reverse current to 0mA). Buck-Boost Regulator Burst-Mode Operation In Burst Mode operation, the buck-boost regulator uses a hysteretic FB1 voltage algorithm to control the output voltage. By limiting FET switching and using a hysteretic control loop, switching losses are greatly reduced. In this mode output current is limited to 50mA typical. While operating in Burst Mode operation, the output capacitor is charged to a voltage slightly higher than the regulation point. The buck-boost converter then goes into a sleep state, during which the output capacitor provides the load current. The output capacitor is charged by charging the inductor until the input current reaches 275mA typical and then discharging the inductor until the reverse current reaches 0mA typical. This process is repeated until the feedback voltage has charged to 6mV above the regulation point. In the sleep state, most of the regulator’s circuitry is powered down, helping to conserve battery power. When the feedback voltage drops 6mV below the regulation point, the switching regulator circuitry is powered on and another burst cycle begins. The duration for which the regulator sleeps depends on the load current and output capacitor value. The sleep time decreases as the load current increases. The maximum load current in 3567f 19 LTC3567 OPERATION Burst Mode operation is 50mA. The buck-boost regulator will not go to sleep if the current is greater than 50mA, and if the load current increases beyond this point while in Burst Mode operation the output will lose regulation. Burst Mode operation provides a significant improvement in efficiency at light loads at the expense of higher output ripple when compared to PWM mode. For many noisesensitive systems, Burst Mode operation might be undesirable at certain times (i.e., during a transmit or receive cycle of a wireless device), but highly desirable at others (i.e. when the device is in low power standby mode). The B6 bit of the I2C port is used to enable or disable Burst Mode operation at any time, offering both low noise and low power operation when they are needed. Buck-Boost Regulator Soft-Start Operation (typical) period. This limits transient inrush currents during start-up because the output voltage is always “in regulation.” Ramping the reference voltage input also limits the rate of increase in the VC1 voltage which helps minimize output overshoot during start-up. A soft-start cycle occurs whenever the buck-boost is enabled, or after a fault condition has occurred (thermal shutdown or UVLO). A soft-start cycle is not triggered by changing operating modes. This allows seamless operation when transitioning between Burst Mode operation and PWM mode. Low Supply Operation The LTC3567 incorporates an undervoltage lockout circuit on VOUT (connected to VIN1) which shuts down the buck-boost regulator when VOUT drops below 2.6V. This UVLO prevents unstable operation. Soft-start is accomplished by gradually increasing the reference voltage input to the error amplifier over a 0.5ms APPLICATIONS INFORMATION CLPROG Resistor and Capacitor As described in the High Efficiency Switching PowerPath Controller section, the resistor on the CLPROG pin determines the average input current limit when the switching regulator is set to either the 1x mode (USB 100mA), the 5x mode (USB 500mA) or the 10x mode. The input current will be comprised of two components, the current that is used to drive VOUT and the quiescent current of the switching regulator. To ensure that the USB specification is strictly met, both components of input current should be considered. The Electrical Characteristics table gives values for quiescent currents in either setting as well as current limit programming accuracy. To get as close to the 500mA or 100mA specifications as possible, a 1% resistor should be used. Recall that IVBUS = IVBUSQ + VCLPROG/RCLPROG • (hCLPROG + 1). An averaging capacitor or an R-C combination is required in parallel with the CLPROG resistor so that the switching regulator can determine the average input current. This network also provides the dominant pole for the feedback loop when current limit is reached. To ensure stability, the capacitor on CLPROG should be 0.1μF or larger. Choosing the PowerPath Inductor Because the input voltage range and output voltage range of the PowerPath switching regulator are both fairly narrow, the LTC3567 was designed for a specific inductance value of 3.3μH. Some inductors which may be suitable for this application are listed in Table 6. Table 6. Recommended Inductors for PowerPath Controller INDUCTOR L TYPE (μH) MAX IDC (A) MAX DCR (Ω) SIZE IN mm (L × W × H) MANUFACTURER LPS4018 3.3 2.2 0.08 3.9 × 3.9 × 1.7 Coilcraft www.coilcraft.com D53LC DB318C 3.3 3.3 2.26 1.55 0.034 0.070 5.0 × 5.0 × 3.0 Toko 3.8 × 3.8 × 1.8 www.toko.com WE-TPC Type M1 3.3 1.95 0.065 4.8 × 4.8 × 1.8 Würth Elektronik www.we-online.com CDRH6D12 CDRH6D38 3.3 3.3 2.2 3.5 0.0625 6.7 × 6.7 × 1.5 Sumida 0.020 7.0 × 7.0 × 4.0 www.sumida.com 3567f 20 LTC3567 APPLICATIONS INFORMATION VBUS and VOUT Bypass Capacitors Buck-Boost Regulator Inductor Selection The style and value of capacitors used with the LTC3567 determine several important parameters such as regulator control-loop stability and input voltage ripple. Because the LTC3567 uses a step-down switching power supply from VBUS to VOUT, its input current waveform contains high frequency components. It is strongly recommended that a low equivalent series resistance (ESR) multilayer ceramic capacitor be used to bypass VBUS. Tantalum and aluminum capacitors are not recommended because of their high ESR. The value of the capacitor on VBUS directly controls the amount of input ripple for a given load current. Increasing the size of this capacitor will reduce the input ripple. Many different sizes and shapes of inductors are available from numerous manufacturers. Choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection process much simpler. To prevent large VOUT voltage steps during transient load conditions, it is also recommended that a ceramic capacitor be used to bypass VOUT. The output capacitor is used in the compensation of the switching regulator. At least 4μF of actual capacitance with low ESR are required on VOUT. Additional capacitance will improve load transient performance and stability. Multilayer ceramic chip capacitors typically have exceptional ESR performance. MLCCs combined with a tight board layout and an unbroken ground plane will yield very good performance and low EMI emissions. There are several types of ceramic capacitors available, each having considerably different characteristics. For example, X7R ceramic capacitors have the best voltage and temperature stability. X5R ceramic capacitors have apparently higher packing density but poorer performance over their rated voltage and temperature ranges. Y5V ceramic capacitors have the highest packing density, but must be used with caution, because of their extreme nonlinear characteristic of capacitance vs voltage. The actual in-circuit capacitance of a ceramic capacitor should be measured with a small AC signal (ideally less than 200mV) as is expected in-circuit. Many vendors specify the capacitance vs voltage with a 1VRMS AC test signal and as a result overstate the capacitance that the capacitor will present in the application. Using similar operating conditions as the application, the user must measure or request from the vendor the actual capacitance to determine if the selected capacitor meets the minimum capacitance that the application requires. The buck-boost converter is designed to work with inductors in the range of 1μH to 5μH. For most applications a 2.2μH inductor will suffice. Larger value inductors reduce ripple current which improves output ripple voltage. Lower value inductors result in higher ripple current and improved transient response time. To maximize efficiency, choose an inductor with a low DC resistance. For a 3.3V output, efficiency is reduced about 3% for a 100mΩ series resistance at 1A load current, and about 2% for 300mΩ series resistance at 200mA load current. Choose an inductor with a DC current rating at least two times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. If output short circuit is a possible condition, the inductor should be rated to handle the 2.5A maximum peak current specified for the buck-boost converter. Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or Permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. Inductors that are very thin or have a very small volume typically have much higher core and DCR losses, and will not give the best efficiency. The choice of which style inductor to use often depends more on the price vs size, performance and any radiated EMI requirements than on what the LTC3567 requires to operate. The inductor value also has an effect on Burst Mode operation. Lower inductor values will cause the Burst Mode operation switching frequencies to increase. Table 7 shows several inductors that work well with the LTC3567’s buck-boost regulator. These inductors offer a good compromise in current rating, DCR and physical size. Consult each manufacturer for detailed information on their entire selection of inductors. 3567f 21 LTC3567 APPLICATIONS INFORMATION Table 7. Recommended Inductors for Buck-Boost Regulator MAX L IDC (μH) (A) MAX DCR (Ω) LPS4018 3.3 2.2 2.2 2.5 0.08 0.07 3.9 × 3.9 × 1.7 Coilcraft 3.9 × 3.9 × 1.7 www.coilcraft.com D53LC 2.0 3.25 0.02 5.0 × 5.0 × 3.0 Toko www.toko.com 7440430022 2.2 2.5 0.028 4.8 × 4.8 × 2.8 Würth-Elektronik www.we-online.com CDRH4D22/ HP 2.2 2.4 0.044 4.7 × 4.7 × 2.4 Sumida www.sumida.com SD14 2.0 2.56 0.045 5.2 × 5.2 × 1.45 Cooper www.cooper.com INDUCTOR TYPE SIZE IN mm (L × W × H) MANUFACTURER Buck-Boost Regulator Input/Output Capacitor Selection Low ESR MLCC capacitors should also be used at both the buck-boost regulator output (VOUT1) and the buckboost regulator input supply (VIN1). Only X5R or X7R ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. A 22μF output capacitor is sufficient for most applications. The buck-boost regulator input supply should be bypassed with a 2.2μF capacitor. Consult with capacitor manufacturers for detailed information on their selection and specifications of ceramic capacitors. Many manufacturers now offer very thin (<1mm tall) ceramic capacitors ideal for use in height restricted designs. Table 8 shows a list of several ceramic capacitor manufacturers. Table 8. Recommended Ceramic Capacitor Manufacturers MANUFACTURER WEBSITE AVX www.avxcorp.com Murata www.murata.com Taiyo Yuden www.t-yuden.com Vishay Siliconix www.vishay.com TDK www.tdk.com Over-Programming the Battery Charger The USB high power specification allows for up to 2.5W to be drawn from the USB port (5V × 500mA). The PowerPath switching regulator transforms the voltage at VBUS to just above the voltage at BAT with high efficiency, while limiting power to less than the amount programmed at CLPROG. In some cases the battery charger may be programmed (with the PROG pin) to deliver the maximum safe charging current without regard to the USB specifications. If there is insufficient current available to charge the battery at the programmed rate, the PowerPath regulator will reduce charge current until the system load on VOUT is satisfied and the VBUS current limit is satisfied. Programming the battery charger for more current than is available will not cause the average input current limit to be violated. It will merely allow the battery charger to make use of all available power to charge the battery as quickly as possible, and with minimal power dissipation within the battery charger. Alternate NTC Thermistors and Biasing The LTC3567 provides temperature qualified charging if a grounded thermistor and a bias resistor are connected to NTC. By using a bias resistor whose value is equal to the room temperature resistance of the thermistor (R25) the upper and lower temperatures are pre-programmed to approximately 40°C and 0°C, respectively (assuming a Vishay “Curve 1” thermistor). The upper and lower temperature thresholds can be adjusted by either a modification of the bias resistor value or by adding a second adjustment resistor to the circuit. If only the bias resistor is adjusted, then either the upper or the lower threshold can be modified but not both. The other trip point will be determined by the characteristics of the thermistor. Using the bias resistor in addition to an adjustment resistor, both the upper and the lower temperature trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds cannot decrease. Examples of each technique follow. NTC thermistors have temperature characteristics which are indicated on resistance-temperature conversion tables. The Vishay-Dale thermistor NTHS0603N011-N1003F, used in the following examples, has a nominal value of 100k and follows the Vishay “Curve 1” resistance-temperature characteristic. In the explanation below, the following notation is used. R25 = Value of the thermistor at 25°C RNTC|COLD = Value of thermistor at the cold trip point 3567f 22 LTC3567 APPLICATIONS INFORMATION RNTC|HOT = Value of thermistor at the hot trip point rCOLD = Ratio of RNTC|COLD to R25 rHOT= Ratio of RNTC|HOT to R25 RNOM = Primary thermistor bias resistor (see Figure 4a) R1 = Optional temperature range adjustment resistor (see Figure 4b) The trip points for the LTC3567’s temperature qualification are internally programmed at 0.349 • VBUS for the hot threshold and 0.765 • VBUS for the cold threshold. Therefore, the hot trip point is set when: RNTC|HOT • V = 0.349 • VBUS RNOM + RNTC|HOT BUS and the cold trip point is set when: RNTC|COLD • V = 0.765 • VBUS RNOM + RNTC|COLD BUS Solving these equations for RNTC|COLD and RNTC|HOT results in the following: RNTC|HOT = 0.536•RNOM and RNTC|COLD = 3.25•RNOM By setting RNOM equal to R25, the above equations result in rHOT = 0.536 and rCOLD = 3.25. Referencing these ratios to the Vishay Resistance-Temperature Curve 1 chart gives a hot trip point of about 40°C and a cold trip point of about 0°C. The difference between the hot and cold trip points is approximately 40°C. By using a bias resistor, RNOM, different in value from R25, the hot and cold trip points can be moved in either direction. The temperature span will change somewhat due to the nonlinear behavior of the thermistor. The following equations can be used to easily calculate a new value for the bias resistor: rHOT • R25 0.536 r RNOM = COLD • R25 3.25 RNOM = where rHOT and rCOLD are the resistance ratios at the desired hot and cold trip points. Note that these equations are linked. Therefore, only one of the two trip points can be chosen, the other is determined by the default ratios designed in the IC. Consider an example where a 60°C hot trip point is desired. From the Vishay Curve 1 R-T characteristics, rHOT is 0.2488 at 60°C. Using the above equation, RNOM should be set to 46.4k. With this value of RNOM, the cold trip point is about 16°C. Notice that the span is now 44°C rather than the previous 40°C. This is due to the decrease in “temperature gain” of the thermistor as absolute temperature increases. The upper and lower temperature trip points can be independently programmed by using an additional bias resistor as shown in Figure 4b. The following formulas can be used to compute the values of RNOM and R1: rCOLD − rHOT • R25 2.714 R1= 0.536 • RNOM − rHOT • R25 RNOM = For example, to set the trip points to 0°C and 45°C with a Vishay Curve 1 thermistor choose RNOM = 3.266 − 0.4368 • 100k = 104.2k 2.714 The nearest 1% value is 105k R1 = 0.536•105k – 0.4368•100k = 12.6k The nearest 1% value is 12.7k. The final solution is shown in Figure 4b and results in an upper trip point of 45°C and a lower trip point of 0°C. USB Inrush Limiting When a USB cable is plugged into a portable product, the inductance of the cable and the high-Q ceramic input capacitor form an L-C resonant circuit. If the cable does not have adequate mutual coupling or if there is not much impedance in the cable, it is possible for the voltage at the input of the product to reach as high as twice the USB voltage (~10V) before it settles out. To prevent excessive voltage from damaging the LTC3567 during a hot insertion, 3567f 23 LTC3567 APPLICATIONS INFORMATION RNOM 100k NTC VBUS LTC3567 NTC BLOCK VBUS VBUS 0.765 • VBUS VBUS RNOM 105k NTC – TOO_COLD + 3 RNTC 100k 0.765 • VBUS – TOO_COLD + 3 R1 12.7k – – TOO_HOT TOO_HOT 0.349 • VBUS LTC3567 NTC BLOCK 0.349 • VBUS + RNTC 100k + + + NTC_ENABLE NTC_ENABLE 0.017V • VBUS – 0.017 • VBUS – 3567 F04b 3567 F04a (b) (a) Figure 4. NTC Circuits it is best to have a low voltage coefficient capacitor at the VBUS pin to the LTC3567. This is achievable by selecting an MLCC capacitor that has a higher voltage rating than that required for the application. For example, a 16V, X5R, 10μF capacitor in a 1206 case would be a more conservative choice than a 6.3V, X5R, 10μF capacitor in a smaller 0805 case. The size of the input overshoot will be determined by the “Q” of the resonant tank circuit formed by CIN and the input lead inductance. It is recommended to measure the input ringing with the selected components to verify compliance with the Absolute Maximum specifications. Alternatively, the following soft connect circuit (Figure 5) can be employed. In this circuit, capacitor C1 holds MP1 off when the cable is first connected. Eventually C1 begins to charge up to the USB input voltage applying increasing gate support to MP1. The long time constant of R1 and C1 prevent the current from building up in the cable too fast thus dampening out any resonant overshoot. MP1 Si2333 VBUS 5V USB INPUT USB CABLE C1 100nF C2 10μF LTC3567 R1 40k GND 3567 F05 scale output voltage is programmed using a resistor divider from the VOUT1 pin connected to the FB1 pin such that: R1 VOUT1 = VFB1 +1 RFB where VFB1 ranges from 0.425V to 0.8V (see Figure 6). Closing the Feedback Loop The LTC3567 incorporates voltage mode PWM control. The control to output gain varies with operation region (buck, boost, buck-boost), but is usually no greater than 20. The output filter exhibits a double pole response given by: f FILTER _ POLE = Where COUT is the output filter capacitor. The output filter zero is given by: 1 f FILTER _ ZERO = Hz 2 • π • RESR • COUT where RESR is the capacitor equivalent series resistance. A troublesome feature in boost mode is the right-half plane zero (RHP), and is given by: Figure 5. USB Soft Connect Circuit Buck-Boost Regulator Output Voltage Programming The buck-boost regulator can be programmed for output voltages greater than 2.75V and less than 5.5V. The full- 1 Hz 2 • π • L • COUT f RHPZ = VIN12 Hz 2 • π •IOUT • L • VOUT1 The loop gain is typically rolled off before the RHP zero frequency. 3567f 24 LTC3567 APPLICATIONS INFORMATION A simple Type I compensation network (as shown in Figure 6) can be incorporated to stabilize the loop but at the cost of reduced bandwidth and slower transient response. To ensure proper phase margin, the loop must cross unity-gain a decade before the LC double pole. VOUT1 + ERROR AMP 0.8V R1 FB1 – CP1 VC1 RFB 3567 F06 Figure 6. Error Amplifier with Type I Compensation The unity-gain frequency of the error amplifier with the Type I compensation is given by: f UG = 1 Hz 2 • π • R1• CP1 Most applications demand an improved transient response to allow a smaller output filter capacitor. To achieve a higher bandwidth, Type III compensation is required. Two zeros are required to compensate for the double-pole response. Type III compensation also reduces any VOUT1 overshoot seen at start-up. The compensation network depicted in Figure 7 yields the transfer function: VC1 1 (1+ sR2C2) • (1+ s(R1+ R3)C3) = • VOUT1 R1• (C1+ C2) sR2C1C2 s • 1+ • (1+ sR3C3) C1+ C2 + 0.8V R1 FB1 R3 C3 – VC1 R2 C1 C2 The compensator zeros should be placed either before or only slightly after the LC double pole such that their positive phase contributions offset the –180° that occurs at the filter double pole. If they are placed at too low of a frequency, they will introduce too much gain to the system and the crossover frequency will be too high. The two high frequency poles should be placed such that the system crosses unity gain during the phase bump introduced by the zeros and before the boost right-half plane zero and such that the compensator bandwidth is less than the bandwidth of the error amp (typically 900kHz). If the gain of the compensation network is ever greater than the gain of the error amplifier, then the error amplifier no longer acts as an ideal op-amp, and another pole will be introduced at the same point. Recommended Type III compensation components for a 3.3V output: R1: 324kΩ RFB: 105kΩ C1: 10pF R2: 15kΩ C2: 330pF VOUT1 ERROR AMP attempting to cross over after the LC double pole, the system must still cross over before the boost right-half plane zero. If unity gain is not reached sufficiently before the right-half plane zero, then the –180° of phase lag from the LC double pole combined with the –90° of phase lag from the right-half plane zero will result in negating the phase bump of the compensator. RFB 3567 F07 Figure 7. Error Amplifier with Type III Compensation A Type III compensation network attempts to introduce a phase bump at a higher frequency than the LC double pole. This allows the system to cross unity gain after the LC double pole, and achieve a higher bandwidth. While R3: 121kΩ C3: 33pF COUT: 22μF LOUT: 2.2μH Printed Circuit Board Layout Considerations In order to be able to deliver maximum current under all conditions, it is critical that the Exposed Pad on the backside of the LTC3567 package be soldered to the PC board ground. Failure to make thermal contact between 3567f 25 LTC3567 APPLICATIONS INFORMATION the Exposed Pad on the backside of the package and the copper board will result in higher thermal resistances. Furthermore, due to its high frequency switching circuitry, it is imperative that the input capacitors, inductors, and output capacitors be as close to the LTC3567 as possible and that there be an unbroken ground plane under the LTC3567 and all of its external high frequency components. High frequency currents, such as the VBUS, VIN1, and VOUT1 currents on the LTC3567, tend to find their way along the ground plane in a myriad of paths ranging from directly back to a mirror path beneath the incident path on the top of the board. If there are slits or cuts in the ground plane due to other traces on that layer, the current will be forced to go around the slits. If high frequency currents are not allowed to flow back through their natural least-area path, excessive voltage will build up and radiated emissions will occur. There should be a group of vias under the grounded backside of the package leading directly down to an internal ground plane. To minimize parasitic inductance, the ground plane should be on the second layer of the PC board. When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3567. 1. Are the capacitors at VBUS, VIN1, and VOUT1 as close as possible to the LTC3567? These capacitors provide the AC current to the internal power MOSFETs and their drivers. Minimizing inductance from these capacitors to the LTC3567 is a top priority. 2. Are COUT and L1 closely connected? The (-) plate of COUT returns current to the GND plane, and then back to CIN. 3. Keep sensitive components away from the SW pins. Battery Charger Stability Considerations The LTC3567’s battery charger contains both a constantvoltage and a constant-current control loop. The constantvoltage loop is stable without any compensation when a battery is connected with low impedance leads. Excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1μF from BAT to GND. Furthermore, when the battery is disconnected, a 4.7μF capacitor in series with a 0.2Ω to 1Ω resistor from BAT to GND is required to keep ripple voltage low. High value, low ESR multilayer ceramic chip capacitors reduce the constant-voltage loop phase margin, possibly resulting in instability. Ceramic capacitors up to 22μF may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2Ω to 1Ω of series resistance. 3567 F08 Figure 8. Higher Frequency Ground Currents Follow Their Incident Path. Slices in the Ground Plane Cause High Voltage and Increased Emissions. The GATE pin for the external ideal diode controller has extremely limited drive current. Care must be taken to minimize leakage to adjacent PC board traces. 100nA of leakage from this pin will introduce an offset to the 15mV ideal diode of approximately 10mV. To minimize leakage, the trace can be guarded on the PC board by surrounding it with VOUT connected metal, which should generally be less than one volt higher than GATE. In constant-current mode, the PROG pin is in the feedback loop rather than the battery voltage. Because of the additional pole created by any PROG pin capacitance, capacitance on this pin must be kept to a minimum. With no additional capacitance on the PROG pin, the battery charger is stable with program resistor values as high as 25k. However, additional capacitance on this node reduces the maximum allowed program resistor. The pole frequency at the PROG pin should be kept above 100kHz. Therefore, if the PROG pin has a parasitic capacitance, CPROG, the following equation should be used to calculate the maximum resistance value for RPROG: 1 RPROG ≤ 2π • 100kHz • CPROG 3567f 26 LTC3567 TYPICAL APPLICATIONS Direct Pin Controlled LTC3567 USB Power Manager with 3.3V/1A Buck-Boost L1 3.3μH USB 4.5V TO 5.5V SW VBUS C1 10μF 100k C2 22μF VOUT NTC LTC3567 GATE OPTIONAL BAT 100k T + PROG TO OTHER LOADS 1k Li-Ion GND CLPROG 2k 0.1μF CHRG 3.01k VIN1 2.2μF SWAB1 L2 2.2μH PUSH BUTTON MICROCONTROLLER LDO3V3 SWCD1 1μF 121k VOUT1 DVCC 33pF C3 22μF 3.3V/1A DISK DRIVE 324k CHRGEN PARTS LIST C1: MURATA GRM21BR61A/06KE19 C2,C3: TAIYO-YUDEN JMK212BJ226MG L1: COILCRAFT LPS4018-332MLC L2: COILCRAFT LPS4018-222MLC FB1 330pF 15k VC1 EN1 GND I 2C 10pF 105k 2 3567 TA02 PACKAGE DESCRIPTION UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697 Rev B) BOTTOM VIEW—EXPOSED PAD 4.00 ± 0.10 (4 SIDES) 0.70 ±0.05 R = 0.115 TYP 0.75 ± 0.05 PIN 1 TOP MARK (NOTE 6) PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER 23 24 0.40 ± 0.10 1 2 4.50 ± 0.05 2.45 ± 0.05 3.10 ± 0.05 (4 SIDES) 2.45 ± 0.10 (4-SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS (UF24) QFN 0105 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3567f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC3567 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3440 600mA (IOUT), 2MHz Synchronous Buck-Boost DC/DC Converter VIN: 2.5V to 5.5V, VOUT: 2.5V to 5.5V IQ = 25μA, ISD < 1μA, MS, DFN Package LTC3441/ LTC3442 1.2A (IOUT), Synchronous Buck-Boost DC/DC Converters, LTC3441 (1MHz), LTC3443 (600kHz) VIN: 2.5V to 5.5V, VOUT: 2.4V to 5.25V IQ = 25μA, ISD < 1μA, MS, DFN Package LTC3442 1.2A (IOUT), 2MHz Synchronous Buck-Boost DC/DC VIN: 2.4V to 5.5V, VOUT: 2.4V to 5.25V Converter IQ = 28μA, ISD < 1μA, MS Package LTC3455 Dual DC/DC Converter with USB Power Management and Li-Ion Battery Charger Efficiency >96%, Accurate USB Current Limiting (500mA/100mA), 4mm × 4mm QFN-24 Package LTC3538 800mA, 2MHz Synchronous Buck-Boost DC/DC Converter VIN: 2.4V to 5.5V, VOUT: 1.8V to 5.25V IQ = 35μA, 2mm × 3mm DFN-8 Package LTC3550 Dual Input USB/AC Adapter Li-Ion Battery Charger with adjustable output 600mA Buck Converter Synchronous Buck Converter, Efficiency: 93%, Adjustable Output at 600mA; Charge Current: 950mA Programmable, USB Compatible, Automatic Input Power Detection and Selection, 3mm × 5mm DFN-16 Package LTC3550-1 Dual Input USB/AC Adapter Li-Ion Battery Charger with 600mA Buck Converter Synchronous Buck Converter, Efficiency: 93%, Output: 1.875V at 600mA; Charge Current: 950mA Programmable, USB Compatible, Automatic Input Power Detection and Selection, 3mm × 5mm DFN-16 Package LTC3555 Switching USB Power Manager with Li-Ion/Polymer Complete Multi-Function PMIC: Switchmode Power Manager and Three Buck Charger, Triple Synchronous Buck Converter Plus Regulators Plus LDO; Charge Current Programmable Up to 1.5A from Wall LDO Adapter Input, Thermal Regulation Synchronous Buck Converters Efficiency: >95%, ADJ Outputs: 0.8V to 3.6V at 400mA/400mA/1A Bat-Track Adaptive Output Control, 200mΩ Ideal Diode, 4mm × 5mm QFN-28 Package LTC3556 Switching USB Power Manager with Li-Ion/Polymer Complete Multi-Function PMIC: Switching Power Manager, 1A Buck-Boost Plus Charger, 1A Buck-Boost Plus Dual Sync Buck 2 Buck Regulators Plus LDO, ADJ Out Down to 0.8V at 400mA/400mA/1A, Converter Plus LDO Synchronous Buck/Buck-Boost Converter Efficiency: >95%; Charge Current Programmable up to 1.5A from Wall Adapter Input, Thermal Regulation, Bat-Track Adaptive Output Control, 180mΩ Ideal Diode, 4mm × 5mm QFN-28 Package LTC3557/ LTC3557-1 USB Power Manager with Li-Ion/Polymer Charger, Triple Synchronous Buck Converter Plus LDO Complete Multi-Function PMIC: Linear Power Manager and Three Buck Regulators Charge Current Programmable Up to 1.5A from Wall Adapter Input, Thermal Regulation Synchronous Buck Converters Efficiency: >95%, ADJ Output: 0.8V to 3.6V at 400mA/400mA/600mA Bat-Track Adaptive Output Control, 200mΩ Ideal Diode, 4mm × 4mm QFN-28 Package LTC3559 Linear USB Li-Ion/Polymer Battery Charger with Dual Synchronous Buck Converter Adjustable Synchronous Buck Converters, Efficiency: >90%, Outputs: Down to 0.8V at 400mA for Each, Charge Current Programmable Up to 950mA, USB Compatible, 3mm × 3mm QFN-16 Package LTC3566 Switching USB Power Manager with Li-Ion/Polymer Multi-Function PMIC: Switchmode Power Manager and 1A Buck-Boost Regulator Charger, 1A Buck-Boost Converter Plus LDO Plus LDO, Charge Current Programmable up to 1.5A from Wall Adapter Input, Thermal Regulation Synchronous Buck-Boost Converters Efficiency: >95%, ADJ Output: Down to 0.8V at 1A, Bat-Track Adaptive Output Control, 180mΩ Ideal Diode, 4mm × 4mm QFN-24 Package LTC4055 USB Power Controller and Battery Charger Charges Single-Cell Li-Ion Batteries Directly From USB Port, Thermal Regulation, 4mm × 4mm QFN-16 Package LTC4067 Linear USB Power Manager with OVP, Ideal Diode Controller and Li-Ion Charger 13V Overvoltage Transient Protection, Thermal Regulation 200mΩ Ideal Diode with <50mΩ Option, 3mm × 4mm QFN-14 Package LTC4085 Linear USB Power Manager with Ideal Diode Controller and Li-Ion Charger Charges Single Cell Li-Ion Batteries Directly from a USB Port, Thermal Regulation, 200mΩ Ideal Diode with <50mΩ Option, 3mm × 4mm QFN-14 Package LTC4088 High Efficiency USB Power Manager and Battery Charger Maximizes Available Power from USB Port, Bat-Track, “Instant-On” Operation, 1.5A Maximum Charge Current, 180mΩ Ideal Diode with <50mΩ Option, 3.3V/25mA Always-On LDO, 3mm × 4mm DFN-14 Package LTC4088-1/ LTC4088/2 High Efficiency USB Power Manager and Battery Charger with Regulated Output Voltage Maximizes Available Power from USB Port, Bat-Track, “Instant-On” Operation, 1.5A Maximum Charge Current, 180mΩ Ideal Diode with <50mΩ Option, Automatic Charge Current Reduction Maintains 3.6V Minimum VOUT, Battery Charger Disabled when all Logic Inputs are Grounded, 3mm × 4mm DFN-14 Package 3567f 28 Linear Technology Corporation LT 0608 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008