LINER LTC4555

LTC4555
SIM Power Supply
and Level Translator
FEATURES
DESCRIPTION
n
The LTC®4555 provides power conversion and signal
level shifting needed for low voltage 2.5G and 3G cellular
telephones to interface with 1.8V or 3V subscriber identity
modules (SIMs). The part meets all type approval requirements for 1.8V and 3V SIMs and smart cards. The part
contains an LDO linear regulator to supply SIM power at
either 1.8V or 3V from a 3V to 6V input. The output voltage is selected with a single pin and up to 50mA of load
current can be supplied.
n
n
n
n
n
n
n
n
SIM Power Supply: 1.8V/3V at 50mA
Input Voltage Range: 3V to 6V
Controller Voltage Range: 1.2V to 4.4V
14kV ESD On All SIM Contact Pins
Meets All ETSI, IMT-2000 and ISO7816 SIM/Smart
Card Interface Requirements
Level Translators to 1.8V or 3V
20μA Operating Current
Logic-Controlled Shutdown (ISD < 1μA)
Available in a Low Profile, 16-Pin (3mm × 3mm)
QFN Package
Internal level translators allow controllers operating with
supplies as low as 1.2V to interface with 1.8V or 3V smart
cards. Battery life is maximized by 20μA operating current
and <1μA shutdown current. Board area is minimized by
the 3mm × 3mm leadless QFN package.
APPLICATIONS
n
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SIM Interface in 3G Cellular Telephones
Smart Card Readers
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Typical SIM Interface
(1.2V TO 4.4V)
VBAT
(3V TO 6V)
VCC
0.1μF
0.1μF
DVCC
VBAT
SHDN
CONTROLLER
SIM/
SMART CARD
INTERFACE
VCC
VSEL
VCC
1μF
LTC4555
RIN
RST
RST
CIN
CLK
CLK
I/0
I/0
DATA
GND
GND
4555 TA01
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1
LTC4555
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
VBAT, DVCC, VCC to GND ............................ –0.3V to 6.5V
Digital Inputs to GND ................................ –0.3V to 6.5V
CLK, RST, I/O to GND .......................–0.3V to VCC + 0.3V
VCC Short-Circuit Duration ................................... Infinite
Operating Temperature Range (Note 2).... –40°C to 85°C
Junction Temperature ........................................... 125°C
Storage Temperature Range................... –65°C to 125°C
CIN
RIN
DATA
NC
TOP VIEW
16 15 14 13
SHDN 1
12 NC
VSEL 2
11 CLK
17
DVCC 3
10 GND
NC 4
RST
6
7
8
VBAT
NC
VCC
I/O
9
5
UD PACKAGE
16-LEAD (3mm s 3mm) PLASTIC QFN
TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4555EUD#PBF
LTC4555EUD#TRPBF
LAAA
16-Lead (3mm × 3mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
l
VBAT Operating Voltage
VBAT Operating Current
ICC = 0mA
l
VBAT Shutdown Current
SHDN = 0V, VBAT = 4.5V
l
DVCC Operating Voltage
l
DVCC Operating Current
fCLK = 1MHz
l
DVCC Shutdown Current
SHDN = 0V
l
l
DVCC Undervoltage Lockout
TYP
3
MAX
6
20
1.2
5
V
30
μA
1
μA
4.4
V
10
μA
1
μA
1.1
V
2.8
1.7
2.8
3.0
1.8
3.2
1.9
V
V
V
VCC Shorted to GND
60
110
175
mA
Input Voltage Range
SHDN, VSEL, RIN, CIN, DATA
0
DVCC
V
Input Current (IIH/IIL)
SHDN, VSEL, RIN, CIN
l
–100
100
nA
0.7 × DVCC
V
VCC Output Voltage
VCC Short-Circuit Current
VSEL = DVCC, VBAT = 3V, IVCC = 50mA
VSEL = DVCC, VBAT = 3.3V to 6V, IVCC = 0mA to 50mA
VSEL = 0, VBAT = 2.6V to 6V, IVCC = 0mA to 50mA
l
l
0.5
UNITS
Controller Inputs/Outputs
High Input Threshold Voltage (VIH)
RIN, CIN
l
Low Input Threshold Voltage (VIL)
RIN, CIN
l
High Input Threshold Voltage (VIH)
SHDN, VSEL
l
Low Input Threshold Voltage (VIL)
SHDN, VSEL
l
0.2 × DVCC
V
1
0.4
V
V
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LTC4555
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
High Level Input Current (IIH)
DATA
l
MIN
Low Level Input Current (IIL)
DATA
l
High Level Output Voltage (VOH)
DATA IOH = 20μA, I/O = VCC
l
Low Level Output Voltage (VOL)
DATA IOL = –200μA, I/O = 0V
l
DATA Pull-Up Resistance
Between DATA and DVCC
TYP
–20
MAX
UNITS
20
μA
1
mA
0.7 × DVCC
13
V
20
0.4
V
30
kΩ
SIM Inputs/Outputs (VCC = 3V)
High Level Output Voltage (VOH)
I/O, IOH = 20μA, DATA = DVCC
l
Low Level Output Voltage (VOL)
I/O, IOL = –1mA, DATA = 0V
l
High Level Output Voltage (VOH)
RST, CLK, IOH = 20μA
l
Low Level Output Voltage (VOL)
RST, CLK, IOL = –200μA
l
I/O Pull-Up Resistance
Between I/O and VCC
0.8 × VCC
V
0.4
0.9 × VCC
6.5
V
V
10
0.4
V
14
kΩ
SIM Inputs/Outputs (VCC = 1.8V)
High Level Output Voltage (VOH)
I/O, IOH = 20μA, DATA = DVCC
l
Low Level Output Voltage (VOL)
I/O, IOL = –1mA, DATA = 0V
l
High Level Output Voltage (VOH)
RST, CLK, IOH = 20μA
l
Low Level Output Voltage (VOL)
RST, CLK, IOL = –200μA
l
I/O Pull-Up Resistance
Between I/O and VCC
0.8 × VCC
V
0.3
0.9 × VCC
0.2 × VCC
6.5
V
V
10
V
14
kΩ
18
ns
SIM Timing Parameters
CLK Rise/Fall Time
CCLK = 30pF, VCC = 1.8V/3V
l
RST, I/O Rise/Fall Time
RST, I/O Loaded with 30pF, VCC = 1.8V/3V
l
Max CLK Frequency
1
5
μs
MHz
VCC Turn-On Time
SHDN = 1, (Note 3)
0.5
ms
VCC Discharge Time to 1V
SHDN = 0, (Note 3)
0.5
ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC4555E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: Specification is guaranteed by design and not 100% tested in
production.
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LTC4555
TYPICAL PERFORMANCE CHARACTERISTICS
VCC Short-Circuit Current
IBAT vs VBAT
170
22
150
20
TA = –40°C
TA = 25°C
110
TA = –40°C
16
90
14
70
12
50
–40 –20
TA = 85°C
18
130
IBAT (μA)
SHORT-CIRCUIT CURRENT (mA)
VCC = 3V
40
20
60
0
TEMPERATURE (°C)
80
100
4555 G01
10
2.5
TA = 25°C
TA = 85°C
VCC = 1.8V
3.0
3.5
4.0 4.5
VBAT (V)
5.0
5.5
6.0
4555 G02
PIN FUNCTIONS
SHDN (Pin 1): Controller Driven Shutdown Pin. This pin
should be high (DVCC) for normal operation and low to
activate a low current shutdown mode.
VSEL (Pin 2): VCC Voltage Select Pin. A low level selects VCC
= 1.8V while driving this pin to DVCC selects VCC = 3V.
DVCC (Pin 3): Supply Voltage for the Controller Side I/O
Pins (CIN, RIN, DATA). When below 1.1V, the VCC supply
is disabled. This pin should be bypassed with a 0.1μF
ceramic capacitor close to the pin.
NC (Pins 4, 6, 12, 16): No Connect.
VBAT (Pin 5): VCC Supply Input. This pin can be between
3V and 6V for normal operation. VBAT quiescent current
reduces to <1μA in shutdown. This pin should be bypassed
with a 0.1μF ceramic capacitor close to the pin.
VCC (Pin 7): SIM Card VCC Supply. A 1μF low ESR capacitor
needs to be connected close to the VCC pin for stable operation. This pin is discharged to GND during shutdown.
RST (Pin 9): Reset Output Pin for the SIM Card.
GND (Pin 10): Ground for the SIM and Controller. Proper
grounding and bypassing is required to meet 14kV ESD
specifications.
CLK (Pin 11): Clock Output Pin for the SIM Card. This
pin is pulled to ground during shutdown. Fast rising and
falling edges necessitate careful board layout for the CLK
node.
CIN (Pin 13): Clock Input from the Controller.
RIN (Pin 14): Reset Input from the Controller.
DATA (Pin 15): Controller Side Data I/O. This pin is used
for bidirectional data transfer. The controller output must
be an open-drain configuration. The open-drain output
must be capable of sinking greater than 1mA.
Exposed Pad (Pin 17): GND. Must be soldered to PCB.
I/O (Pin 8): SIM-Side Data I/O. The SIM card output must
be on an open-drain driver capable of sourcing >1mA.
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LTC4555
BLOCK DIAGRAM
VBAT
(3V TO 6V)
PROCESSOR
VCC
3
C3
0.1μF
SHUTDOWN
PIN
1
VSIM
VOLTAGE
SELECT
2
RESET
FROM
PROCESSOR
14
CLOCK
FROM
PROCESSOR
13
5
DVCC
VCC
SHDN
CELL PHONE
PROCESSOR
INTERFACE
15
1.8V/3V
AT 50mA
7
50mA LDO
VSEL
C1
1μF
RIN
RST
CIN
CLK
20k
DATA TO/
FROM SIM
C2
0.1μF
VBAT
9
RESET
11
CLOCK
8
BIDIRECTIONAL
I/O
10k
DATA
I/0
LTC4555
10
GND
SIM/
SMART CARD
INTERFACE
4555 BD
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LTC4555
APPLICATIONS INFORMATION
The LTC4555 provides both regulated power and internal
level translators to allow low voltage controllers to interface
with 1.8V or 3V SIMs or smart cards. The part meets all
ETSI, IMT-2000 and ISO7816 requirements for SIM and
smart card interfaces.
VCC Voltage Regulator
provides level translators to allow controllers to communicate with the SIM. The CLK and RST lines to the
SIM are level shifted from the controller supply (GND to
DVCC) to the SIM supply (GND to VCC). The data input to
the SIM requires an open-drain output on the controller.
On-chip pull-up resistors are provided for both the DATA
and I/O lines.
The VCC voltage regulator is a 50mA low dropout (LDO)
regulator with a digitally selected 1.8V or 3V output.
Shutdown Modes
The output voltage is selected via the VSEL pin. The output
is internally current limited and is capable of surviving an
indefinite short to GND.
The LTC4555 enters a low current shutdown mode by
pulling the SHDN pin low. The SHDN pin is an active low
input that the controller can use to directly shut down
the part.
The VCC output should be bypassed with a 1μF capacitor.
The LTC4555 can use either a low ESR ceramic capacitor
or a tantalum electrolytic capacitor on the VCC pin, with
no special ESR requirements.
VBAT should be bypassed with a 0.1μF ceramic capacitor.
Level Translators
All SIMs and smart cards contain a clock input, a reset
input and a bidirectional data input/output. The LTC4555
ESD Protection
All pins that connect to the SIM/smart card will withstand
14kV of human body model ESD. In order to ensure
proper ESD protection, careful board layout is required.
The GND pin should be tied directly to a GND plane. The
VCC capacitor should be located very close to the VCC pin
and tied directly to the GND plane.
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LTC4555
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 p0.05
3.50 p 0.05
1.45 p 0.05
2.10 p 0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 p 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 s 45o CHAMFER
R = 0.115
TYP
0.75 p 0.05
15
16
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
1
1.45 p 0.10
(4-SIDES)
2
(UD16) QFN 0904
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 p 0.05
0.50 BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
7
LTC4555
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ThinSOT is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
LT 0109 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2001