MAXIM MAX15022ATI

19-4107; Rev 0; 5/08
KIT
ATION
EVALU
E
L
B
A
IL
AVA
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
o Output Voltage Adjustable from 0.6V to VAVIN
o Two LDO Controllers
o Lossless, Cycle-by-Cycle Current Sensing
o External Compensation for Maximum Flexibility
o Digital Soft-Start and Soft-Stop for Tracking
Applications
o Digital Soft-Start into a Prebiased Load for
Sequencing Applications
o Sequencing or Coincident/Ratiometric Tracking
o Programmable Switching Frequency from 500kHz
to 4MHz
o Thermal Shutdown and Hiccup-Mode ShortCircuit Protection
o 30µA Shutdown Current
o 100% Maximum Duty Cycle
o Space-Saving (5mm x 5mm) 28-Pin TQFN
Package
RFID Reader Cards
Power-over-Ethernet (PoE) IP Phones
Automotive Multimedia
Multivoltage Supplies
Networking/Telecom
DVDD2
EN3
Applications
PGND2
TOP VIEW
LX2
Pin Configuration
PVIN2
The MAX15022 offers the ability to track (coincident or
ratiometric) or sequence during power-up and powerdown operation. When sequencing, it powers up glitchfree into a prebiased output.
Additional features include an internal undervoltage
lockout with hysteresis and a digital soft-start/soft-stop
for glitch-free power-up and power-down. Protection
features include lossless cycle-by-cycle current limit,
hiccup-mode output short-circuit protection, and thermal shutdown.
The MAX15022 is available in a space-saving, 5mm x
5mm, 28-pin TQFN-EP package and is specified for
operation from -40°C to +125°C temperature range.
o Dual-Output Synchronous Buck Regulators
o Integrated Switches for 4A and 2A Output
Currents
o 180° Out-Of-Phase Operation
EN4
The MAX15022 utilizes a voltage-mode control scheme
with external compensation to provide good noise
immunity and maximum flexibility in selecting inductor
values and capacitor types. The dual switching regulators operate 180° out-of-phase, thereby reducing the
RMS input ripple current and thus the size of the input
bypass capacitor significantly.
o 2.5V to 5.5V Input-Voltage Range
FB4
The MAX15022 is a dual-output, pulse-width-modulated
(PWM), step-down DC-DC regulator with dual LDO controllers. The device operates from 2.5V to 5.5V and
each output can be adjusted from 0.6V to the input
supply (VAVIN). The MAX15022 delivers up to 4A (regulator 1) and 2A (regulator 2) of output current with two
LDO controllers that can be used to drive two external
PNP transistors to provide two additional outputs. This
device offers the ability to adjust the switching frequency from 500kHz to 4MHz and provides the capability of
optimizing the design in terms of size and performance.
Features
21
20
19
18
17
16
15
B4 22
14
FB3
COMP2 23
13
B3
FB2 24
12
COMP1
EN2 25
11
FB1
10
EN1
9
DVDD1
8
PGND1
MAX15022
SGND 26
AVIN 27
4
5
6
7
PGND1
+Denotes a lead-free package.
*EP = Exposed pad.
3
LX1
2
PVIN1
1
PVIN1
PIN-PACKAGE
28 TQFN-EP*
LX1
TEMP RANGE
-40°C to +125°C
PGND1
PART
MAX15022ATI+
*EP
+
RT 28
SEL
Ordering Information
THIN QFN
(5mm x 5mm)
*EP = EXPOSED PAD.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX15022
General Description
MAX15022
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
ABSOLUTE MAXIMUM RATINGS
AVIN, PVIN_, B_, DVDD_, EN_, FB_, RT,
SEL to SGND .........................................................-0.3V to +6V
COMP_ to SGND .....................................-0.3V to (VAVIN + 0.3V)
PGND_ to SGND ...................................................-0.3V to +0.3V
LX Current (Note 1)
Regulator 1...............................................................................6A
Regulator 2...............................................................................3A
Current into Any Pin Other than PVIN_,
LX_ and PGND_.............................................................±50mA
Continuous Power Dissipation (TA = +70°C)
28-Pin TQFN (derate 34.5mW/°C above +70°C) .....2758.6mW
Junction-to-Case Thermal Resistance (θJC)(Note 2) .........2°C/W
Junction-to-Ambient Thermal Resistance (θJA)(Note 2) ..29°C/W
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: LX has internal diodes to PGND_ and PVIN_. Applications that forward bias these diodes should take care not to exceed
the IC’s package power dissipation limits.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations see www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVIN = VPVIN_ = VDVDD_ = 3.3V, VPGND_ = VSGND = 0V, RT = 25kΩ, and TA = TJ = -40°C to +125°C, unless otherwise noted.
Typical values are at TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
2.3
V
SYSTEM SPECIFICATIONS
Input-Voltage Range
VAVIN = VPVIN1 = VPVIN2 = VDVDD1 =
VDVDD2
2.5
Undervoltage Lockout Threshold
AVIN rising
2.1
Undervoltage Lockout Hysteresis
2.2
0.12
V
Operating Supply Current
VEN_= 1.3V, VFB_ = 0.8V
3.5
6
mA
Shutdown Supply Current
VEN_ = 0V
30
65
μA
PWM DIGITAL SOFT-START/SOFT-STOP
Soft-Start/Soft-Stop Duration
Reference Voltage Steps
4096
Clock
Cycles
64
Steps
PWM ERROR AMPLIFIERS
FB1, FB2 Input Bias Current
-1
FB1, FB2 Voltage Set-Point
0.593
COMP1, COMP2 Voltage Range
ICOMP_ = -250μA to +250μA
0.599
0.3
+1
μA
0.605
V
VAVIN - 0.5
V
Error-Amplifier Open-Loop Gain
80
dB
Error-Amplifier Unity-Gain
Bandwidth
12
MHz
2
_______________________________________________________________________________________
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
(VAVIN = VPVIN_ = VDVDD_ = 3.3V, VPGND_ = VSGND = 0V, RT = 25kΩ, and TA = TJ = -40°C to +125°C, unless otherwise noted.
Typical values are at TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LDO CONTROLLERS
FB3, FB4 Input Bias Current
+250
nA
FB3, FB4 Voltage Set-point
5mA sink current, VB_ = 0.5V to 5.5V
0.585
-250
0.600
0.615
V
FB3, FB4 to B3, B4
Transconductance
2.5mA to 10mA sink current,
VB_ = 0.5V to 5.5V
0.56
1.20
2.30
S
B3, B4 Driver Sink Current
VFB3, VFB4 = 0V, VB_ = 0.5V to 5.5V
20
mA
LDO Soft-Start Duration
512
Clock
Cycles
LDO Reference Voltage Steps
64
Steps
POWER MOSFETS
Regulator 1 p-Channel MOSFET
RDSON
Regulator 1 n-Channel MOSFET
RDSON
Regulator 1 Gate Charge
VDVDD1 = 5V
50
90
mΩ
VDVDD1 = 5V
30
50
mΩ
VDVDD1 = 5V
8
nC
4
A
Maximum LX1 RMS Current
Regulator 2 p-Channel MOSFET
RDSON
VDVDD2 = 5V
100
180
mΩ
Regulator 2 n-Channel MOSFET
RDSON
VDVDD2 = 5V
60
100
mΩ
Regulator 2 Gate Charge
VDVDD2 = 5V
4
nC
2
A
Maximum LX2 RMS Current
PWM CURRENT LIMIT AND HICCUP MODE
Regulator 1 Peak Current Limit
Regulator 1 Valley Current Limit
Regulator 2 Peak Current Limit
Regulator 2 Valley Current Limit
Number of Cumulative CurrentLimit Events to Hiccup
Number of Consecutive Noncurrent
Limit Cycles to Clear NCL
Hiccup Timeout
VPVIN = VAVIN = 3.3V
4.5
4.9
5.3
VPVIN = VAVIN = 2.5V
3.40
3.65
3.95
VPVIN = VAVIN = 3.3V
4.0
5.0
5.65
VPVIN = VAVIN = 2.5V
3.0
3.7
4.25
VPVIN = VAVIN = 3.3V
2.25
2.45
2.65
VPVIN = VAVIN = 2.5V
1.70
1.85
1.98
VPVIN = VAVIN = 3.3V
2.0
2.5
2.83
VPVIN = VAVIN = 2.5V
1.5
1.85
2.13
A
A
A
A
NCL
4
Clock
Cycles
NCLR
3
Clock
Cycles
NHT
8192
Clock
Cycles
_______________________________________________________________________________________
3
MAX15022
ELECTRICAL CHARACTERISTICS (continued)
MAX15022
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
ELECTRICAL CHARACTERISTICS (continued)
(VAVIN = VPVIN_ = VDVDD_ = 3.3V, VPGND_ = VSGND = 0V, RT = 25kΩ, and TA = TJ = -40°C to +125°C, unless otherwise noted.
Typical values are at TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
1.207
1.225
1.243
UNITS
ENABLE/SEL
EN_ Threshold
VEN_ rising
EN_ Hysteresis
0.12
EN_ Input Current
-2.5
SEL High Threshold
+2.5
0.85 x VAVIN
SEL Low Threshold
Present only during startup
μA
V
0.2 x VAVIN
SEL Input Bias Current
V
V
-100
V
+100
μA
4000
kHz
OSCILLATOR
Switching Frequency Range
fSW
Oscillator Accuracy
fSW = 4MHz x [VRT(V)/1.067(V)] (Note 4)
fSW ≤ 1500kHz
-6
+6
fSW > 1500kHz
-10
+10
Phase Shift Between Regulators
180
RT Current
RT Voltage Range
0 < VRT < 1.067V
VRT
31.30
32.00
0.130
%
Degrees
32.58
1.067
μA
V
Minimum Controllable On-Time
60
ns
Minimum Controllable Off-Time
60
ns
PWM Ramp Amplitude
PWM Ramp Valley
VAVIN/4
V
0.3
V
THERMAL SHUTDOWN
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Temperature rising
+160
°C
15
°C
Note 3: Specifications are 100% production tested at TA = +25°C and TA = +125°C. Maximum and minimum specifications over
temperature are guaranteed by design.
Note 4: When operating with VAVIN = 2.5V, the maximum operating frequency should be derated to 3MHz.
4
_______________________________________________________________________________________
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
VPVIN1 = 5V
50
40
VOUT1 = 1.8V
50
VOUT1 = 3.3V
40
30
20
20
VOUT1 = 1.8V
fSW = 2MHz
EN2 = 0V
VOUT1 = 1.0V
60
30
10
80
5000
1000
40
VOUT2 = 1.5V
fSW = 2MHz
EN1 = 0V
10
0
100
100
5000
1000
LOAD CURRENT (mA)
CHANNEL 2 EFFICIENCY
vs. LOAD CURRENT
CHANNEL 1
LOAD REGULATION
CHANNEL 2
LOAD REGULATION
3.318
3.316
VOUT2 = 2.5V
70
VOUT1 (V)
VOUT2 = 1.5V
60
VOUT2 = 1.0V
40
1.5055
3.312
1.5050
3.310
3.308
3.306
20
3.304
VPVIN2 = 5V
fSW = 2MHz
EN1 = 0V
1.5025
fSW = 2MHz
1.5020
0
3000
0.5
1.0
1.5 2.0 2.5 3.0
LOAD CURRENT (A)
3.5
4.0
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
LOAD CURRENT (A)
SWITCHING FREQUENCY
vs. TEMPERATURE
SWITCHING FREQUENCY
vs. RT RESISTANCE
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.5
CHANGE IN SWITCHING FREQUENCY (%)
MAX15022 toc07
4.5
MAX15022 toc08
1000
LOAD CURRENT (mA)
VPVIN2 = 3.3V
1.5040
1.5030
VPVIN1 = 5V
fSW = 2MHz
3.300
100
VPVIN2 = 5V
1.5045
1.5035
3.302
0
1.5060
3.314
30
10
1.5065
VOUT2 (V)
80
1.5070
MAX15022 toc05
MAX15022 toc04
3.320
3000
1000
LOAD CURRENT (mA)
90
SWITCHING FREQUENCY (MHz)
PVIN2 = 5V
50
LOAD CURRENT (mA)
100
50
60
20
VPVIN1 = 5V
fSW = 2MHz
EN2 = 0V
0
100
PVIN2 = 3.3V
70
30
10
0
EFFICIENCY (%)
70
90
MAX15022 toc06
60
80
EFFICIENCY (%)
VPVIN1 = 3.3V
90
EFFICIENCY (%)
80
100
MAX15022 toc02
90
EFFICIENCY (%)
100
MAX15022 toc01
100
70
CHANNEL 2 EFFICIENCY
vs. LOAD CURRENT
CHANNEL 1 EFFICIENCY
vs. LOAD CURRENT
MAX15022 toc03
CHANNEL 1 EFFICIENCY
vs. LOAD CURRENT
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
fSW = 2MHz
-0.5
0
0
5
10
15
20
25
RT RESISTANCE (kΩ)
30
35
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX15022
Typical Operating Characteristics
(VAVIN = VDVDD1 = VDVDD2 = VPVIN1 = VPVIN2 = 5V, VOUT1 = 3.3V, VOUT2 = 1.5V, VPGND_ = 0V, RT = 16.5kΩ. TA = +25°C, unless
otherwise noted.)
Typical Operating Characteristics (continued)
(VAVIN = VDVDD1 = VDVDD2 = VPVIN1 = VPVIN2 = 5V, VOUT1 = 3.3V, VOUT2 = 1.5V, VPGND_ = 0V, RT = 16.5kΩ. TA = +25°C, unless
otherwise noted.)
QUIESCENT CURRENT
vs. TEMPERATURE
4.50
SWITCHING CURRENT (mA)
MAX15022 toc09
4.25
4.00
3.75
3.50
3.25
3.00
2.75
NO SWITCHING
2.50
REGULATOR 1 ENABLED
VOUT1 = 3.3V
REGULATOR 2 ENABLED
VOUT2 = 1.5V
-40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
NORMALIZED UNDERVOLTAGE LOCKOUT
THRESHOLD vs. TEMPERATURE
EN_ THRESHOLD
vs. TEMPERATURE
1.260
MAX15022 toc11
1.030
1.025
1.255
1.250
EN_ THRESHOLD (V)
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
0.975
0.970
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
MAX15022 toc12
QUIESCENT CURRENT (mA)
4.75
MAX15022 toc10
SWITCHING CURRENT
vs. TEMPERATURE
5.00
NORMALIZED UVLO THRESHOLD
MAX15022
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
1.245
1.240
1.235
1.230
1.225
1.220
1.215
VUVLO (NOM) = 2.2V
1.210
-40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
COINCIDENT TRACKING SOFT-STOP
COINCIDENT TRACKING SOFT-START
MAX15022 toc14
MAX15022 toc13
VAVIN
5V/div
0V
VAVIN
5V/div
0V
VOUT1
1V/div
VOUT1
VOUT2
1V/div
VOUT2
EN1
1V/div
0V
0V
1ms/div
6
400μs/div
_______________________________________________________________________________________
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
CHANNEL 1 LOAD STEP RESPONSE
CHANNEL 1 LOAD STEP RESPONSE
MAX15022 toc15
MAX15022 toc16
EN2 = 0V
EN2 = 0V
VPVIN1
5V/div
0V
VPVIN1
5V/div
0V
VOUT1
3.3V, AC-COUPLED
100mV/div
VOUT1
3.3V, AC-COUPLED
100mV/div
IOUT1
2A/div
0A
IOUT1
2A/div
0A
20μs/div
20μs/div
CHANNEL 2 LOAD STEP RESPONSE
CHANNEL 2 LOAD STEP RESPONSE
MAX15022 toc18
MAX15022 toc17
EN1 = 0V
EN1 = 0V
VPVIN2
5V/div
0V
VPVIN2
5V/div
0V
VOUT2
1.5V, AC-COUPLED
100mV/div
VOUT2
1.5V, AC-COUPLED
100mV/div
IOUT2
1A/div
0A
IOUT2
1A/div
0A
20μs/div
180° OUT-OF-PHASE OPERATION
CHANNEL 3 AND CHANNEL 4 OUTPUTVOLTAGE DEVIATION vs. LOAD CURRENT
MAX15022 toc19
0V
VLX1
5V/div
0V
VLX2
5V/div
0V
IOUT1 = 3A
IOUT2 = 1.5A
OUTPUT-VOLTAGE DEVIATION (mV)
14
PVIN1 = PVIN2
5V/div
CHANNEL 3, VIN = 3.3V,
VOUT3 = 2.5V
NJT403OP PNP
12
MAX15022 toc20
20μs/div
10
8
6
4
CHANNEL 4, VIN = 2.5V,
VOUT4 = 1.5V
NJT403OP PNP
2
0
200ns/div
0
50 100 150 200 250 300 350 400 450 500
LOAD CURRENT (mA)
_______________________________________________________________________________________
7
MAX15022
Typical Operating Characteristics (continued)
(VAVIN = VDVDD1 = VDVDD2 = VPVIN1 = VPVIN2 = 5V, VOUT1 = 3.3V, VOUT2 = 1.5V, VPGND_ = 0V, RT = 16.5kΩ. TA = +25°C, unless
otherwise noted.)
Typical Operating Characteristics (continued)
(VAVIN = VDVDD1 = VDVDD2 = VPVIN1 = VPVIN2 = 5V, VOUT1 = 3.3V, VOUT2 = 1.5V, VPGND_ = 0V, RT = 16.5kΩ. TA = +25°C, unless
otherwise noted.)
2.480
2.475
IOUT3 = 500mA
2.470
2.465
IOUT4 = 500mA
1.205
OUTPUT VOLTAGE (V)
IOUT3 = 10mA
2.485
1.210
-20
1.200
1.195
1.190
VOUT3 = 2.5V
2.450
2.90
3.42
3.94
4.46
SUPPLY VOLTAGE (V)
4.98
-60
-70
VOUT4 = 1.5V
-80
1.170
5.50
-40
IOUT4 = 10mA
1.175
2.455
-30
-50
1.185
1.180
2.460
VIN = 3.3V, VOUT3 = 2.5V,
IOUT3 = 10mA,
100mVP-P SIGNAL
APPLIED TO VIN
-10
PSRR (dB)
2.490
0
MAX15022 toc22
2.495
LDO POWER-SUPPLY REJECTION RATIO
1.215
MAX15022 toc21
2.500
CHANNEL 4 OUTPUT VOLTAGE
vs. INPUT VOLTAGE
MAX15022 toc23
CHANNEL 3 OUTPUT VOLTAGE
vs. INPUT VOLTAGE
OUTPUT VOLTAGE (V)
MAX15022
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
2.90
3.42
3.94
4.46
4.98
5.50
SUPPLY VOLTAGE (V)
10
100
1000
FREQUENCY (Hz)
Pin Description
PIN
8
NAME
FUNCTION
1
SEL
Track/Sequence Select Input. Connect SEL to SGND to configure the device as a sequencer. Connect
SEL to AVIN for tracking with output 1 as the master. Leave SEL unconnected for tracking with output 2
as the master. Use the output with the higher voltage as the master and the output with the lower voltage
as the slave.
2, 7, 8
PGND1
3, 6
LX1
4, 5
PVIN1
Input Supply Voltage for Regulator 1. Connect PVIN1 to an external voltage source from 2.5V to 5.5V.
Bypass PVIN1 to PGND1 with a 1μF (min) ceramic capacitor.
9
DVDD1
Switch Driver Supply for Regulator 1. Connect externally to PVIN1.
10
EN1
Enable Input for Regulator 1. When configured as a sequencer, EN1 must exceed 1.225V (typ) for the
PWM controller to begin regulating output 1. When configured as a tracker, connect EN1 to the center
tap of a resistive divider from the regulator 2 output.
11
FB1
Feedback Regulation Point for Regulator 1. Connect FB1 to the center tap of a resistive divider from the
regulator 1 output to SGND to set the output voltage. The FB1 voltage regulates to 0.6V (typ).
12
COMP1
Power Ground Connection for Regulator 1. Connect the negative terminals of the input and output filter
capacitors to PGND1. Connect PGND1 externally to SGND at a single point, typically at the negative
terminal of the input bypass capacitor.
Inductor Connection for Regulator 1. LX1 is the drain connection of the internal high-side p-channel
MOSFET and the drain connection of the internal synchronous n-channel MOSFET for regulator 1.
Error-Amplifier Output for Regulator 1. Connect COMP1 to the compensation feedback network.
_______________________________________________________________________________________
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
PIN
NAME
FUNCTION
Transconductance Amplifier Open-Drain Output for LDO Controller 3. Connect B3 to the base of an
external PNP transistor to regulate output 3.
13
B3
14
FB3
Feedback Regulation Point for LDO Controller 3. Connect to the center tap of a resistive divider from the
output 3 to SGND to set the output voltage. The FB3 voltage regulates to 0.6V (typ).
15
EN3
LDO Enable Input for LDO Controller 3. EN3 must exceed 1.225V (typ) for the PWM controller to begin
regulating output 3.
16
DVDD2
Switch Driver Supply for Regulator 2. Connect externally to PVIN2.
17
PGND2
Power Ground Connection for Regulator 2. Connect the negative terminals of the input and output filter
capacitors to PGND2. Connect PGND2 externally to SGND at a single point, typically at the negative
terminal of the input bypass capacitor.
18
LX2
19
PVIN2
Input Supply Voltage for Regulator 2. Connect to an external voltage source from 2.5V to 5.5V. Bypass
PVIN2 to PGND2 with a 1μF (min) ceramic capacitor.
20
EN4
LDO Enable Input for LDO Controller 4. EN4 must exceed 1.225V (typ) for the PWM controller to begin
regulating output 4.
21
FB4
Feedback Regulation Point for LDO Controller 4. Connect to the center tap of a resistive divider from
output 4 to SGND to set the output voltage. The FB4 voltage regulates to 0.6V (typ).
22
B4
Transconductance Amplifier Open-Drain Output for LDO Controller 4. Connect B4 to the base of an
external PNP transistor to regulate output 4.
23
COMP2
24
FB2
Feedback Regulation Point for Regulator 2. Connect to the center tap of a resistive divider from the
regulator 2 output to SGND to set the output voltage. The FB2 voltage regulates to 0.6V (typ).
25
EN2
Enable Input for Regulator 2. When configured as a sequencer, EN2 must exceed 1.225V (typ) for the
PWM controller to begin regulating output 1. When configured as a tracker, connect EN2 to the center
tap of a resistive divider from the regulator 1 output.
26
SGND
Signal Ground. Connect SGND to PGND_ at a single point, typically near the negative terminal of the
input bypass capacitor.
27
AVIN
Inductor Connection for Regulator 2. LX2 is the drain connection of the internal high-side p-channel
MOSFET and the drain connection of the internal synchronous n-channel MOSFET for Regulator 2.
Error-Amplifier Output for Regulator 2. Connect COMP2 to the compensation feedback network.
Input Voltage. Bypass AVIN to SGND with a 100nF (min) ceramic capacitor.
28
RT
Oscillator Timing Resistor Connection. Connect a 4.2kΩ to 33kΩ resistor from RT to SGND to program
the switching frequency from 500kHz to 4MHz.
—
EP
Exposed Paddle. Connect EP to a large copper plane at SGND potential to improve thermal dissipation.
Do not use as the main SGND connection.
_______________________________________________________________________________________
9
MAX15022
Pin Description (continued)
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
MAX15022
Functional Diagrams
AVIN
SEL
SGND
ON1 ON2 SHDN
MAX15022
SEQ1
1.225V
1.1V
EN CONFIG
PWM CONTROLLER 1
SEQ2 SEL DECODE
SEQ1
0.6V
REF
VREF
THERMAL
SHDN
VREF
VR1
EN1
ON1
SEQ1 SEQ2
CLK1 DOWN1
DIGITAL
SOFT-START
AND SOFT-STOP
EN1
SHDN
OVL
CONFIG
SEQ1
1.225V
1.1V
OVL1
DVDD1
OVL2
PVIN1
CLK1 CLK2
E/A
HIGH-SIDE
CURRENT
SENSE
OVL1 RES
OVERLOAD
MANAGEMENT
FB1
ILIM1
AVIN
D
COMP1
RT
EN
OSC
CLK2
CPWM
CLK1
RAMP
LEVEL
SHIFT
Q
BREAKBEFOREMAKE
LX1
R
LOW-SIDE
CURRENT
SENSE
CLK
PGND1
10
______________________________________________________________________________________
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
EN4
EN3
FB3
1.225V
1.1V
MAX15022
B3
CLK1
PWM CONTROLLER 2
DUAL LDO CONTROLLERS
DIGITAL
SOFT-START
VREF
SHDN
SEQ2
EN2
ON2
FB4
1.225V
1.1V
1.25V
1.125V
B4
CLK2
SHDN
ON1 ON2
DIGITAL
SOFT-START
VREF
SEQ1
EN CONFIG
SHDN
SEQ2
SEQ1 SEQ2
VREF
CLK2 DOWN2
DIGITAL
SOFT-START
AND SOFT-STOP
VREF
VR2
EN2
OVL1
OVL
CONFIG
SEQ1
DVDD2
OVL2
PVIN2
E/A
CLK1 CLK2
FB2
HIGH-SIDE
CURRENT
SENSE
OVL2 RES
OVERLOAD
ILIM2
MANAGEMENT
AVIN
D
COMP2
CPWM
CLK2
RAMP
LEVEL
SHIFT
CLK
Q
BREAKBEFOREMAKE
LX2
R
LOW-SIDE
CURRENT
SENSE
PGND2
______________________________________________________________________________________
11
MAX15022
Functional Diagrams (continued)
MAX15022
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
Detailed Description
The MAX15022 incorporates dual-output, PWM, stepdown, DC-DC regulators and dual LDO controllers with
tracking and sequencing options. The device operates
over the input-voltage range of 2.5V to 5.5V. Each PWM
regulator provides an adjustable output down to 0.6V
and delivers up to 4A (regulator 1) and 2A (regulator 2)
of load current. The high switching frequency (up to
4MHz) and integrated power switches optimize the
MAX15022 for high-performance and small-size power
management solutions.
Each of the MAX15022 PWM regulator sections utilizes
a voltage-mode control scheme for good noise immunity and offers external compensation allowing for maximum flexibility with a wide selection of inductor values
and capacitor types. The device operates at a fixed
switching frequency that is programmable from 500kHz
to 4MHz with a single resistor. Operating the regulators
with 180° out-of-phase clocking, and at frequencies up
to 4MHz, significantly reduces the RMS input ripple
current. The resulting peak input current reduction (and
increase in the ripple frequency) significantly reduces
the required amount of input bypass capacitance.
The MAX15022 provides coincident tracking, ratiometric tracking, or sequencing to allow tailoring of powerup/power-down sequence depending on the system
requirements. When sequencing, it powers up glitchfree into a prebiased output. The MAX15022 features
two LDO controllers for external PNP pass transistors to
provide two additional outputs.
The MAX15022 includes internal undervoltage lockout
with hysteresis, digital soft-start/soft-stop for glitch-free
power-up and power-down. Protection features include
lossless, cycle-by-cycle current limit, hiccup-mode output short-circuit protection, and thermal shutdown.
surge currents during startup. The soft-start duration is
4096 clock cycles. The output voltage is incremented
through 64 equal steps. The output reaches regulation
when soft-start is completed, regardless of the output
capacitance and load.
For tracking applications, soft-stop commences when the
enable input falls below 1.1V (typ). The soft-stop circuitry
ramps down the reference voltage controlling the outputvoltage rate of fall. The output voltage is decremented
through 64 equal steps in 4096 clock cycles.
Oscillator
Use an external resistor at RT to program the
MAX15022 switching frequency from 500kHz to 4MHz.
Calculate the appropriate resistor value at RT for the
desired output switching frequency (fSW):
f [kHz] × 1.067[V]
RT [kΩ] = SW
32[μA] × 4[MHz]
Tracking/Sequencing
The MAX15022 features coincident/ratiometric tracking
and sequencing (see Figure 1). Connect SEL to ground
to configure the device as a sequencer. Connect SEL to
AVIN for tracking with output 1 as the master. Leave SEL
unconnected for tracking with output 2 as the master.
Assign the output with the higher voltage as the master.
VOUT1
VOUT2
a) COINCIDENT TRACKING OUTPUTS
VOUT1
Undervoltage Lockout (UVLO)
The supply voltage (VAVIN) must exceed the default
UVLO threshold before any operation starts. The UVLO
circuitry keeps the MOSFET drivers, oscillator, and all
the internal circuitry shut down to reduce current consumption. The UVLO rising threshold is 2.2V (typ) with
a 120mV (typ) hysteresis.
VOUT2
12
SOFT-STOP
SOFT-START
b) RATIOMETRIC TRACKING OUTPUTS
VOUT1
VOUT2
Digital Soft-Start/Soft-Stop
The MAX15022 soft-start feature allows the load voltage to ramp up in a controlled manner, eliminating output-voltage overshoot. Soft-start begins after VAVIN
exceeds the undervoltage lockout threshold and the
enable input is above 1.225V (typ). The soft-start circuitry ramps up the reference voltage, controlling the
rate of rise of the output voltage, and reducing input
SOFT-STOP
SOFT-START
SOFT-START
SOFT-STOP
c) SEQUENCED OUTPUTS
Figure 1. Graphical Representation of Coincident Tracking,
Ratiometric Tracking, and Sequencing
______________________________________________________________________________________
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
when the other output is shorted to ground. When the
slave is shorted and enters into hiccup mode, the master will soft-stop. When the master is shorted and the
part enters into hiccup mode, the slave will ratiometrically soft-stop. Coming out of hiccup mode, both outputs
will soft-start coincidently or ratiometrically depending
on their initial configuration. During the thermal shutdown or power-off when the input falls below its UVLO,
the output voltages track down depending on the
respective output capacitance and load.
See Figure 1 for a graphical representation of coincident/ratiometric tracking.
When the MAX15022 regulators are configured as voltage trackers, output short-circuit fault conditions at
either master or slave output are handled carefully—neither the master nor slave output will remain energized
Sequencing
When sequencing, the voltage at the enable inputs
must exceed 1.225V (typ) for each PWM controller to
start (see Figure 1c).
a)
RATIOMETRIC TRACKING
b)
COINCIDENT TRACKING
c)
COINCIDENT TRACKING
VPVIN1
VPVIN1
VPVIN2
EN1
EN1
EN2
EN2
VOUT1
VOUT2
RA
SEL
RC
AVIN
EN2
EN1
OUTPUT 1 IS THE MASTER AND
OUTPUT 2 IS THE SLAVE.
RB
RD
VPVIN2
VOUT2
VOUT1
RA
EN2
FB2
RC
FB1
RB
RD
EN1
SEL
UNCONNECTED
OUTPUT 2 IS THE MASTER AND
OUTPUT 1 IS THE SLAVE.
SEL
AVIN
OUTPUT 1 IS THE MASTER AND
OUTPUT 2 IS THE SLAVE.
SEL
UNCONNECTED
OUTPUT 2 IS THE MASTER AND
OUTPUT 1 IS THE SLAVE.
Figure 2. Ratiometric Tracking and Coincident Tracking Configurations
______________________________________________________________________________________
13
MAX15022
Coincident/Ratiometric Tracking
The enable inputs in conjunction with digital soft-start
and soft-stop provide coincident/ratiometric tracking.
Track an output voltage by connecting a resistive
divider from the output being tracked to its enable
input. For example, for VOUT2 to coincidentally track
V OUT1, connect the same resistive divider used for
FB2, from VOUT1 to EN2 to SGND (see Figure 2).
Track ratiometrically by connecting EN_ to SGND. This
synchonizes the soft-start and soft-stop of all the regulator references, and hence their respective output voltages will track ratiometrically (see Figure 2).
MAX15022
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
Error Amplifier
The output of the internal voltage-mode error amplifier
(COMP_) is provided for frequency compensation (see
the Compensation Design Guidelines section). FB_ is
the inverting input of the error amplifier. The error
amplifier has an 80dB open-loop gain and a 12MHz
gain bandwidth (GBW) product.
CURRENT LIMIT
IN
INITIATE HICCUP
TIMEOUT
NHT
COUNT OF 4
NCL
CLR
Output Short-Circuit
Protection (Hiccup Mode)
The MAX15022 features lossless, high-side peak current limit and low-side, valley current limit. At short duty
cycles, both limits are active. At high duty cycles, only
the high-side peak current limit is active. Either limit
causes the hiccup mode counter (NCL) to increment.
For duty cycles less than 50%, the low-side valley current limit is active. Once the high-side MOSFET turns off,
the voltage across the low-side MOSFET is monitored. If
this voltage does not exceed the current-limit threshold
at the end of the cycle, the high-side MOSFET turns on
normally at the start of the next cycle. If the voltage
exceeds the current-limit threshold just before the
beginning of a new PWM cycle, the controller skips that
cycle. During severe overload or short-circuit conditions, the switching frequency of the device appears to
decrease because the on-time of the low-side MOSFET
extends beyond a clock cycle.
If the current-limit threshold is exceeded for more than
four cumulative clock cycles (NCL), the device shuts
down for 8192 clock cycles (hiccup timeout) and then
restarts with a soft-start sequence. If three consecutive
cycles pass without a current-limit event, the count of
NCL is cleared (see Figure 3). Hiccup mode protects
the device against a continuous output short circuit.
The internal current limit is constant from 5.5V down to
3V and decreases linearly by 50% from 3V to 2V. See
the Electrical Characteristics table.
Thermal-Overload Protection
The MAX15022 features an integrated thermal-overload
protection with temperature hysteresis. Thermal-overload protection limits the die temperature of the device
and protects it in the event of an extended thermal fault
condition. When the die temperature exceeds +160°C,
an internal thermal sensor shuts down the device, turning off the internal power MOSFETs and allowing the die
to cool. After the die temperature falls by +15°C (typ),
the device restarts with a soft-start sequence.
Startup into a Prebiased Output
(Sequencing Mode)
In sequencing mode, the regulators start with minimal
glitch into a prebiased output and soft-stop is disabled.
14
IN
COUNT OF 3
NCLR
CLR
Figure 3. Hiccup-Mode Block Diagram
During soft-start, both switches are kept off until the
PWM comparator commands its first PWM pulse. Until
then, the converters do not sink current from the outputs. The first PWM pulse occurs when the ramping reference voltage increases above the FB_ voltage.
LDO Controllers
The MAX15022 provides two additional LDO controllers
to drive external PNP pass transistors. Connect the emitter of each PNP pass transistor to either the input supply
or one of the controller 1 or 2 outputs. Each LDO controller features an independent enable input and digital
soft-start. Connect FB3 and FB4 to the center tap of a
resistive divider from the output of the desired LDO controller to SGND to set the output voltage.
PWM Controllers
Design Procedure
Setting the Switching Frequency
Connect a 4.2kΩ to 33kΩ resistor from RT to SGND to
program the switching frequency (fSW) from 500kHz to
4MHz. Calculate the required resistor value RT to set
the switching frequency with the following equation:
f [kHz] × 1.067[V]
RT [kΩ] = SW
32[μA] × 4[MHz]
Higher frequencies allow designs with lower inductor
values and less output capacitance. At higher switching frequencies core losses, gate-charge currents,
and switching losses increase. When operating from
VAVIN < 3V, the fSW frequency should be derated to
3MHz (maximum).
______________________________________________________________________________________
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
VPVIN_MAX [V] ≤
VOUT_ [V]
t ON(MIN) [μs] × fSW [MHz]
where tON(MIN) is 0.06μs (typ).
The minimum input voltage (VPVIN_MIN) can be effectively limited by the maximum controllable duty cycle
and is calculated using the following equation:
VPVIN_MIN [V] ≥
VOUT_ [V]
1− (t OFF(MIN) [μs] × fSW [MHz])
where V OUT_ is the regulator output voltage and
tOFF(MIN) is the 0.06μs (typ) controllable off-time.
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX15022: inductance value (L),
peak inductor current (IPEAK), and inductor saturation
current (ISAT). The minimum required inductance is a
function of operating frequency, input-to-output voltage
differential, and the peak-to-peak inductor current
(ΔIP-P). Higher ΔIP-P allows for a lower inductor value. A
lower inductance minimizes size and cost and
improves large-signal and transient response.
However, efficiency is reduced due to higher peak currents and higher peak-to-peak output-voltage ripple for
the same output capacitor. A higher inductance
increases efficiency by reducing the ripple current;
however, resistive losses due to extra wire turns can
exceed the benefit gained from lower ripple current levels especially when the inductance is increased without
also allowing for larger inductor dimensions. Choose
the inductor’s peak-to-peak current, ΔIP-P, in the range
of 20% to 50% of the full load current; as a rule of
thumb 30% is typical.
Calculate the inductance, L, using the following equation:
L[μH] =
where VPVIN_ is the input supply voltage, VOUT_ is the
regulator output voltage, and fSW is the switching frequency. Use typical values for VPVIN_ and VOUT_ so
that efficiency is optimum for typical conditions. The
switching frequency (fSW) is programmable between
500kHz and 4MHz (see the Oscillator section).
The peak-to-peak inductor current (ΔI P-P ), which
reflects the peak-to-peak output ripple, is largest at the
maximum input voltage. See the Output-Capacitor
Selection section to verify that the worst-case output
current ripple is acceptable.
Select an inductor with a saturation current, ISAT, higher than the maximum peak current to avoid runaway
current during continuous output short-circuit conditions. Also, confirm that the inductor’s thermal performances and projected temperature rise above ambient
does not exceed its thermal capacity. Many inductor
manufacturers provide bias/load current versus temperature rise performance curves (or similar) to obtain
this information.
Input-Capacitor Selection
The discontinuous input current of the buck converter
causes large input ripple currents and therefore the
input capacitor must be carefully chosen to withstand
the input ripple current and keep the input-voltage ripple within design requirements.
The input-voltage ripple is comprised of ΔVQ (caused
by the capacitor discharge) and ΔVESR (caused by the
ESR of the input capacitor). The total voltage ripple is
the sum of ΔVQ and ΔVESR which peaks at the end of
the on-cycle. Calculate the required input capacitance
and ESR for a specified ripple using the following equations:
ESR[mΩ] =
ΔVESR[mV]
ΔIP −P ⎞
⎛
⎜ ILOAD(MAX) +
⎟ [A]
⎝
2 ⎠
⎛V
[V] ⎞
ILOAD(MAX)[A] × ⎜ OUT_ ⎟
⎝ VPVIN_ [V] ⎠
CPVIN_ [μF] =
ΔVQ[V] × fSW [MHz]
ΔIP −P [A] =
(VPVIN_ − VOUT_ )[V] × VOUT_ [V]
VPVIN_ [V] × fSW [MHz] × L[μH]
VOUT_ [V] × (VPVIN_ [V] − VOUT_ [V])
VPVIN_ [V] × fSW [MHz] × ΔIP−P [A]
ILOAD(MAX) is the maximum output current, ΔIP-P is the
peak-to-peak inductor current, and VPVIN_ is the input
supply voltage, VOUT_ is the regulator output voltage,
and fSW is the switching frequency.
______________________________________________________________________________________
15
MAX15022
Effective Input-Voltage Range
Although the MAX15022’s regulators can operate from
input supplies ranging from 2.5V to 5.5V, the input-voltage range can be effectively limited by the
MAX15022’s duty-cycle limitations for a given output
voltage (V OUT_ ). The maximum input voltage
(VPVIN_MAX) can be effectively limited by the controllable minimum on-time (tON(MIN)):
MAX15022
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
Use the following equation to calculate the input ripple
when only one regulator is enabled:
ICIN(RMS)[A] = ILOAD(MAX)[A] ×
(
)
VOUT_ [V] × VPVIN_ − VOUT_ [V]
VPVIN_ [V]
The MAX15022 includes UVLO hysteresis to avoid possible unintentional chattering during turn-on. Use additional
bulk capacitance if the input source impedance is high. If
using a lower input voltage, additional input capacitance
helps to avoid possible undershoot below the undervoltage lockout threshold during transient loading.
Output-Capacitor Selection
The allowed output-voltage ripple and the maximum
deviation of the output voltage during load steps determine the required output capacitance and its ESR. The
output ripple is mainly composed of ΔVQ (caused by
the capacitor discharge) and ΔVESR (caused by the
voltage drop across the equivalent series resistance of
the output capacitor). The equations for calculating the
output capacitance and its ESR are:
put-voltage deviation below the tolerable limits of the
electronics being powered.
Use the following equations to calculate the required
output capacitance, ESR, and ESL for minimal output
deviation during a load step:
ΔVESR [mV]
ISTEP [A]
I
[A] × t RESPONSE [μs]
COUT [μF] = STEP
ΔVQ [V]
[mV] × t STEP [μs]
ΔV
ESL[nH] = ESL
ISTEP [A]
ESR[mΩ] =
where ISTEP is the load step, tSTEP is the rise time of the
load step, and tRESPONSE is the response time of the
controller.
Compensation Design Guidelines
where ΔIP-P is the peak-to-peak inductor current, and
fSW is the switching frequency.
ΔVESR and ΔVQ are not directly additive since they are
out of phase from each other. If using ceramic capacitors, which generally have low ESR, ΔVQ dominates. If
using electrolytic capacitors, ΔVESR dominates.
The MAX15022 uses a fixed-frequency, voltage-mode
control scheme that regulates the output voltage by
comparing the output voltage against a fixed reference.
The subsequent “error” voltage that appears at the
error-amplifier output (COMP_) is compared against an
internal ramp voltage to generate the required duty
cycle of the PWM. A second order lowpass LC filter
removes the switching harmonics and passes the DC
component of the PWM signal to the output. The LC filter has an attenuation slope of -40dB/decade and introduces 180° of phase shift at frequencies above the LC
resonant frequency. This phase shift in addition to the
inherent 180° of phase shift of the regulator’s negative
feedback system turns the feedback into unstable positive feedback. The error amplifier and its associated
circuitry must be designed to achieve a stable closedloop system.
The allowable deviation of the output voltage during
fast load transients also affects the output capacitance,
its ESR, and its equivalent series inductance (ESL). The
output capacitor supplies the load current during a
load step until the controller responds with an
increased duty cycle. The response time (tRESPONSE)
depends on the gain bandwidth of the controller (see
the Compensation-Design Guidelines section). The
resistive drop across the output capacitor’s ESR
(ΔVESR), the drop across the capacitor’s ESL (ΔVESL),
and the capacitor discharge (ΔVQ) causes a voltage
droop during the load-step (ISTEP). Use a combination
of low-ESR tantalum/aluminum electrolyte and ceramic
capacitors for better load transient and voltage ripple
performance. Non-leaded capacitors and capacitors in
parallel help reduce the ESL. Keep the maximum out-
The basic controller loop consists of a power modulator
(comprised of the regulator’s PWM, associated circuitry,
and LC filter), an output feedback divider, and an error
amplifier. The power modulator has a DC gain set by
VAVIN/VRAMP where the ramp voltage (VRAMP) is a function of the VAVIN and results in a fixed DC gain of 4V/V,
providing effective feed-forward compensation of inputvoltage supply DC variations. The feed-forward compensation eliminates the dependency of the power modulator’s gain on the input voltage such that the feedback
compensation of the error amplifier requires no modifications for nominal input-voltage changes. The output
filter is effectively modeled as a double-pole and a single zero set by the output inductance (L), the DC resistance of the inductor (DCR), the output capacitance
(COUT), and its equivalent series resistance (ESR).
ΔIP−P [A]
8 × ΔVQ [V] × fSW [MHz]
2 × ΔVESR [mV]
ESR[mΩ] =
ΔIP−P [A]
COUT [μF] =
16
______________________________________________________________________________________
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
fESR =
1
2π × ESR × COUT
ROUT is the load resistance of the regulator, fLC is the
resonant break frequency of the filter, and fESR is the
ESR zero of the output capacitor. See the Closed-Loop
Response and Compensation of Voltage-Mode
Regulators for more information on fLC and fESR.
The switching frequency (f SW ) is programmable
between 500kHz and 4MHz. Typically, the crossover
frequency (fCO)—the frequency at which the system’s
closed-loop gain is equal to unity (crosses 0dB)—
should be set at or below one-tenth the switching frequency (fSW/10) for stable closed-loop response.
The MAX15022 provides an internal voltage-mode error
amplifier with its inverting input and its output available to
the user for external frequency compensation. The flexibility of external compensation for each controller offers
a wide selection of output filtering components, especially the output capacitor. For cost-sensitive applications,
MAX15022 fig04a
40
First, select the passive and active power components
that meet the application output ripple, component
size, and component cost requirements. Second,
choose the small-signal compensation components to
achieve the desired closed-loop frequency response
and phase margin as outlined below.
Closed-Loop Response and Compensation
of Voltage-Mode Regulators
The power modulator’s LC lowpass filter exhibits a variety of responses, dependent on the value of the L and
C and their parasitics. Higher resistive parasitics
reduce the Q of the circuit, reducing the peak gain and
phase of the system; however, efficiency is also
reduced under these circumstances.
One such response is shown in Figure 4a. In this example, the ESR zero occurs relatively close to the filter’s
resonant break frequency, fLC. As a result, the power
modulator’s uncompensated crossover is approximately one third the desired crossover frequency, fCO. Note
also, the uncompensated rolloff through the 0dB plane
follows a single-pole, -20dB/decade slope and 90° of
phase lag. In this instance, the inherent phase margin
ensures a stable system; however, the gain-bandwidth
product is not optimized.
fLC
-20
-45
fESR
< GMOD
-40
-90
-60
-135
MAGNITUDE (dB)
|GMOD|
0
10
100
1k
10k
100k
1M
-180
10M
FREQUENCY (Hz)
Figure 4a. Power Modulator Gain and Phase Response with
Lossy Bulk Output Capacitor(s) (Aluminum)
fCO
|GEA|
0
45
0
-20
-45
fESR
< GMOD
-40
-80
90
fLC
20
180
135
40
|GMOD| ASYMPTOTE
PHASE (DEGREES)
MAGNITUDE (dB)
0
<GEA
60
45
20
MAX15022 fig04b
80
90
-90
-60
-135
|GMOD|
-80
10
100
PHASE (DEGREES)
VAVIN
V
= AVIN = 4V/V
VRAMP VAVIN
4
1
1
fLC =
≈
2
L
π
×
× COUT
⎛R
+ ESR ⎞
2π × L × COUT × ⎜ OUT
⎟
⎝ ROUT + DCR ⎠
GainMOD(DC) =
use aluminum electrolytic capacitors while for spacesensitive applications, use low-ESR tantalum or multilayer ceramic chip (MLCC) capacitors at the output. The
higher switching frequencies of the MAX15022 allow the
use of MLCC as the primary filter capacitor(s).
1k
10k
100k
1M
-180
10M
FREQUENCY (Hz)
Figure 4b. Power Modulator and Type II Compensator Gain and
Phase Response with Lossy Bulk Output Capacitor(s) (Aluminum)
______________________________________________________________________________________
17
MAX15022
Below are equations that define the power modulator:
MAX15022 fig04c
40
|GMOD|
20
gentler response of the previous example. This is due
to the filter components’ lower parasitic (DCR and ESR)
and corresponding higher frequency of the inherent
ESR zero. In this example, the desired crossover frequency occurs below the ESR zero frequency.
In this example, a compensator with an inherent midfrequency double-zero response is required to mitigate
the effects of the filter’s double-pole phase lag. This is
available with the Type III topology.
As demonstrated in Figure 4d, the Type III’s midfrequency double-zero gain (exhibiting a +20dB/decade
slope, noting the compensator’s pole at the origin) is
designed to compensate for the power modulator’s
double-pole -40dB/decade attenuation at the desired
crossover frequency, fCO (again, GainE/A + GainMOD =
0dB at fCO) (see Figure 4d).
In the above example, the power modulator’s inherent
(midfrequency) -40dB/decade rolloff is mitigated by the
midfrequency double zero’s +20dB/decade gain to
extend the active regulation gain bandwidth of the voltage regulator. As shown in Figure 4d, the net result is
an approximate doubling in the controller’s gain bandwidth while providing greater than 55° of phase margin
(the difference between GainE/A and GainMOD respective phases at crossover, fCO).
Design procedures for both Type II and Type III compensators are shown below.
90
MAX15022 fig04d
80
60
45
-20
-45
< GMOD
-90
-40
MAGNITUDE (dB)
fESR
PHASE (DEGREES)
0
fLC
203
< GEA
40
0
|GEA|
135
fLC
20
68
fCO
0
-135
-20
< GMOD
100
1k
10k
100k
1M
-180
10M
FREQUENCY (Hz)
Figure 4c. Power Modulator Gain and Phase Response with
Low-Parasitic Capacitor(s) (MLCCs)
18
-68
-135
-60
-203
fESR
-80
10
0
|GMOD|
-40
|GMOD|
ASYMPTOTE
-60
270
PHASE (DEGREES)
As seen in Figure 4b, a Type II compensator provides for
stable closed-loop operation, leveraging the +20dB/
decade slope of the capacitor’s ESR zero, while extending the closed-loop gain bandwidth of the regulator. The
zero crossover now occurs at approximately three times
the uncompensated crossover frequency, fCO.
The Type II compensator’s midfrequency gain (approximately 12dB shown here) is designed to compensate
for the power modulator’s attenuation at the desired
crossover frequency, fCO (GainE/A + GainMOD = 0dB at
fCO). In this example, the power modulator’s inherent
-20dB/decade rolloff above the ESR zero (fZERO, ESR)
is leveraged to extend the active regulation gain bandwidth of the voltage regulator. As shown in Figure 4b,
the net result is a three times increase in the regulator’s
gain bandwidth while providing greater than 75° of
phase margin (the difference between Gain E/A and
GainMOD respective phases at crossover, fCO).
Other filter schemes pose their own problems. For
instance, when choosing high-quality filter capacitor(s),
e.g. MLCCs, the inherent ESR zero may occur at a
much higher frequency, as shown in Figure 4c.
As with the previous example, the actual gain and
phase response is overlaid on the power modulator’s
asymptotic gain response. One readily observes the
more dramatic gain and phase transition at or near the
power modulator’s resonant frequency, fLC, versus the
MAGNITUDE (dB)
MAX15022
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
-80
10
100
1k
10k
100k
1M
-270
10M
FREQUENCY (Hz)
Figure 4d. Power Modulator and Type III Compensator Gain
and Phase Response with Low Parasitic Capacitors (MLCCs)
______________________________________________________________________________________
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
fESR =
fLC ≈
1
2π × ESR × COUT
1
CCF
VOUT_
CF
RF
R1
FB_
COMP_
R2
VREF
Figure 5a. Type II Compensation Network
GAIN
(dB)
2π × L × COUT
where COUT is the regulator output capacitor and ESR
is the series resistance of C OUT . See the OutputCapacitor Selection section for more information on calculating COUT and ESR.
Set the compensator’s leading zero, fZ1, at or below the
filter’s resonant double-pole frequency from:
fZ1 ≤ fLC
Set the compensator’s high-frequency pole, fP1, at or
below one-half the switching frequency, fSW:
f
fP1 ≤ SW
2
To maximize the compensator’s phase lead, set the
desired crossover frequency, fCO, equal to the geometric mean of the compensator’s leading zero, fZ1, and
high-frequency pole, fP1, as follows:
fCO = fZ1 × fP1
Select the feedback resistor, RF, in the range of 3.3kΩ
to 30kΩ.
Calculate the gain of the modulator (GainMOD)—comprised of the regulator’s PWM, LC filter, feedback divider,
and associated circuitry—at the desired crossover frequency, fCO, using the following equation:
GainMOD = 4(V/V) ×
MAX15022
Type II: Compensation when fCO > fZERO, ESR
When the fCO is greater than fESR, a Type II compensation network provides the necessary closed-loop compensated response. The Type II compensation network
provides a midband compensating zero and a high-frequency pole (see Figures 5a and 5b).
R F C F provides the midband zero f MID,ZERO , and
RFCCF provides the high-frequency pole, fHIGH,POLE.
Use the following procedure to calculate the compensation network components.
Calculate the fESR and LC double pole, fLC:
ESR [mΩ]
(2π × fCO [kHz] × L[μH])
×
VFB [V]
VOUT_ [V]
where VFB is the 0.6V (typ) FB_ input-voltage set-point,
L is the value of the regulator inductor, ESR is the
1ST ASYMPTOTE
(ωR1CF)-1
2ND ASYMPTOTE
RF -1
RI
( )
1ST POLE
(AT ORIGIN)
3RD ASYMPTOTE
(ωRFCCF)-1
2ND POLE
(RFCCF)-1
1ST ZERO
(RFCF)-1
ω (rad/sec)
Figure 5b. Type II Compensation Network Response
series resistance of the output capacitor, and VOUT_ is
the desired output voltage.
The gain of the error amplifier (GainE/A) in the midband
frequencies is:
R [kΩ]
GainE/A = F
R1 [kΩ]
The total loop gain is the product of the modulator gain
and the error amplifier gain at fCO and should be set
equal to 1 as follows:
GainMOD x GainE/A = 1
So:
⎡ RF ⎤
⎡
4 ×ESR x VFB
⎤
20 × log10 ⎢⎣ R1 ⎥⎦ + 20 × log10 ⎢⎢ 2 π × fCO ×L x VOUT_ ⎥⎥ = 0dB
⎣
⎦
RF
4 × ESR x VFB
×
=1
R1 2π × fCO × L x VOUT_
______________________________________________________________________________________
19
MAX15022
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
Solving for R1:
VOUT_
R [kΩ] × 4 × ESR[mΩ] × VFB [V]
R1 [kΩ] = F
2π × fCO [kHz] × L[μH] × VOUT_ [V]
RI
CCF
CF
RF
R1
CI
where VFB is the 0.6V (typ) FB_ input-voltage set-point,
L is the value of the regulator inductor, ESR is the
series resistance of the output capacitor, and VOUT_ is
the desired output voltage.
FB_
COMP_
R2
VREF
1) CF is determined from the compensator’s leading
zero, fZ1, and RF as follows:
CF [μF] =
1
2π × RF [kΩ] × fZ1[kHz]
2) CCF is determined from the compensator’s high-frequency pole, fP1, and RF as follows:
1
CCF [μF] =
2π × RF [kΩ] × fP1[kHz]
Figure 6a. Type III Compensation Network
GAIN
(dB)
1ST ASYMPTOTE
(ωRICF)-1
5TH ASYMPTOTE
(RICCF)-1
( )
VFB [V]
VOUT_ [V] − VFB [V]
where VFB = 0.6V (typ) and VOUT_ is the output voltage
of the regulator.
Type III: Compensation when fCO < fESR
As indicated above, the position of the output capacitor’s inherent ESR zero is critical in designing an appropriate compensation network. When low-ESR ceramic
output capacitors (MLCCs) are used, the ESR zero frequency (fESR) is usually much higher than the desired
crossover frequency (fCO). In this case, a Type III compensation network is recommended (see Figure 6a).
As shown in Figure 6b, the Type III compensation network introduces two zeros and three poles into the control loop. The error amplifier has a low-frequency pole
at the origin, two zeros, and two higher frequency poles
at the following frequencies:
1
2π × R F × C F
1
fZ2 =
2π × CI × (R1 + RI )
fZ1 =
Two midband zeros (fZ1 and fZ2) are designed to compensate for the pair of complex poles introduced by the
LC filter.
20
( )
2ND ASYMPTOTE
3RD ASYMPTOTE
RF -1
(ωRFCI)-1
R1
3) Calculate R2 using the following equation:
R2 [kΩ] = R1[kΩ] ×
4TH ASYMPTOTE
RF
RI
1ST POLE
(AT ORIGIN)
1ST ZERO
(RFCF)-1
2ND POLE
(RICI)-1
2ND ZERO
(R1CI)-1
3RD POLE
(RFCCF)-1
ω (rad/sec)
Figure 6b. Type III Compensation Network Response
fP1 introduces a pole at zero frequency (integrator) for
nulling DC output-voltage errors.
fP1= at the origin (0Hz)
Depending on the location of the ESR zero (fESR), fP2
can be used to cancel it, or to provide additional attenuation of the high-frequency output ripple.
fP2 =
1
2π × RI × CI
fP3 attenuates the high-frequency output ripple.
fP3 =
1
(
2π × RF × CF CCF
)
=
1
C × CCF
2π × R F × F
CF + CCF
Since CCF << CF then:
fP3 =
1
2π × RF × CCF
______________________________________________________________________________________
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
Solving for CI:
60° of phase margin at fCO. Whichever technique, it is
important to place the two zeros at or below the double
pole to avoid the conditional stability issue.
The following procedure is recommended:
1) Select a crossover frequency, fCO, at or below onetenth the switching frequency (fSW):
6) For those situations where fLC < fCO < fESR < fSW/2,
as with low-ESR tantalum capacitors, the compensator’s second pole (fP2) should be used to cancel
fESR. This provides additional phase margin. On the
system Bode plot, the loop gain maintains its
+20dB/decade slope up to 1/2 of the switching frequency verses flattening out soon after the 0dB
crossover. Then set:
fP2 = fESR
If a ceramic capacitor is used, then the capacitor ESR
zero, fESR, is likely to be located even above 1/2 of the
switching frequency, that is fLC < fCO < fSW/2 < fESR. In
this case, the frequency of the second pole (fP2) should
be placed high enough not to significantly erode the
phase margin at the crossover frequency. For example,
fP2 can be set at 5 x fCO, so that its contribution to phase
loss at the crossover frequency fCO is only about 11°:
fP2 = 5 x fCO
Once fP2 is known, calculate RI:
f
[kHz]
fCO [kHz] ≤ SW
10
2) Calculate the LC double-pole frequency, fLC :
fLC [MHz] ≈
1
2π × L[μH] × COUT [μF]
where COUT is the output capacitor of the regulator.
3) Select the feedback resistor, RF, in the range of
3.3kΩ to 30kΩ.
1
4) Place the compensator’s first zero fZ1 =
2π × R F × C F
at or below the output filter’s double-pole, fLC , as follows:
CF [μF] =
1
2π × RF [kΩ] × 0.5 × fLC [kHz]
5) The gain of the modulator (GainMOD)—comprised of
the regulator’s PWM, LC filter, feedback divider, and
associated circuitry—at the crossover frequency is:
1
GainMOD = 4 ×
2
(2π × fCO [MHz]) × L[μH] × COUT [μF]
The gain of the error amplifier (GainE/A) in midband frequencies is:
GainE/A = 2π × fCO [kHz] × CI [μF] × RF [kΩ]
The total loop gain is the product of the modulator gain
and the error amplifier gain at fCO should be equal to 1,
as follows:
GainMOD x GainE/A = 1
So:
1
4×
2
(2π × fCO[kHz]) × COUT [μF] × L[μH]
× 2π × fCO[kHz] × CI[pF] × RF [kΩ] = 1
CI [pF] =
(2π × fCO [kHz] × L[μH] × COUT [μF])
4 × RF [kΩ]
RI [kΩ] =
1
2π × fP2 [kHz] × CI [μF]
7) Place the second zero (fZ2) at 0.2 x fCO or at fLC,
whichever is lower, and calculate R1 using the following equation:
R1[kΩ] =
1
2π × fZ2[kHz] × CI[μF]
8) Place the third pole (fP3) at 1/2 the switching frequency and calculate CCF from:
CCF [nF] =
1
(2π × 0.5 × fSW [MHz] × RF [kΩ])
9) Calculate R2 as:
R2 [kΩ] = R1[kΩ] ×
VFB [V]
VOUT_ [V] − VFB [V]
where VFB = 0.6V (typ).
______________________________________________________________________________________
21
MAX15022
The locations of the zeros and poles should be such
that the phase margin peaks around fCO.
Set the ratios of fCO-to-fZ and fP-to-fCO equal to one another, e.g., fCO = fP = 5 is a good number to get approximately
fZ fCO
MAX15022
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
LDO Controllers
Design Procedure
PNP Pass Transistors Selection
The pass transistors must meet specifications for current
gain (ß), input capacitance, collector-emitter saturation
voltage, and power dissipation. The transistor’s current
gain limits the guaranteed maximum output current to:
⎛
V [V] ⎞
×β
IOUT3/4 [A] = ⎜ IB3/4(MIN)[A] − BE
RPULL [Ω] ⎟⎠
⎝
where IB3/4(MIN) is the minimum base-drive current and
RPULL is the pullup resistor connected between the
transistor’s base and emitter.
In addition, to avoid premature dropout, VCE-SAT must
be less than or equal to (V PVIN_(MIN) - V OUT3/4_ ).
Furthermore, the transistor’s current gain increases the
linear regulator’s DC loop gain (see the Stability
Requirements section), so excessive gain destabilizes
the output. Therefore, transistors with high current gain
at the maximum output current, such as Darlington
transistors, are not recommended. The transistor’s
input capacitance and input resistance also create a
second pole, which could be low enough to destabilize
the LDO when the output is heavily loaded.
The transistor’s saturation voltage at the maximum output current determines the minimum input-to-output voltage differential that the linear regulator supports.
Alternately, the package’s power dissipation could limit
the useable maximum input-to-output voltage differential.
The maximum power-dissipation capability of the transistor’s package and mounting must support the actual
power dissipation in the device without exceeding the
maximum junction temperature. The power dissipated
equals the maximum load current multiplied by the
maximum input-to-output voltage differential.
Output 3 and Output 4 Voltage Selection
The MAX15022 positive linear-regulator output voltage
is set with a resistive divider from the desired output
(VOUT3/4) to FB3/4 to SGND (see Figures 7 and 8).
First, select the R2FB3/4 resistance value (below 30kΩ).
Then, solve for R1FB3/4:
⎛V
[V] ⎞
R1FB3/4 [kΩ] = R2FB3/4 [kΩ]⎜ OUT3/4
− 1⎟
⎝ VFB3/4 [V]
⎠
where VOUT3/4 can support output voltages as low as
0.6V and VFB3/4 is 0.6V (typ).
22
Stability Requirements
The MAX15022’s B3 and B4 outputs are designed to
drive bipolar PNP transistors. These PNP transistors
form linear regulators with positive outputs. An internal
transconductance amplifier drives the external pass
transistors. The transconductance amplifier, pass transistor’s specifications, the base-emitter resistor, and the
output capacitor determine the loop stability.
The total DC loop gain (AV) is the product of the gains of
the internal transconductance amplifier, the gain from
base to collector of the pass transistor, and the attenuation of the feedback divider. The transconductance amplifier regulates the output voltage by controlling the pass
transistor’s base current. Its DC gain is approximately:
⎛ R × RP1/2 ⎞
gC_ × ⎜ IN
⎟
⎝ RIN + RP1/2 ⎠
where g C_ is the transconductance of the internal
amplifier and is typically 1.2mA/mV, RP1/2 is the resistor
across the base and the emitter of the pass transistor in
kΩ, and RIN is the input resistance of the pass transistor, and can be calculated by:
⎛ 26[mV] ⎞
RIN[kΩ] = β x ⎜
⎟
⎝ IOUT3/4 [μA] ⎠
The DC gain for the pass transistor (AP), including the
feedback divider, is approximately:
⎡R
× (R1FB3/4 + R2FB3/4 ) ⎤
AP = gm−PNP × ⎢ OUT3/4
⎥
⎣ ROUT3/4 + R1FB3/4 + R2FB3/4 ⎦
R2FB3/4
×
R1FB3/4 + R2FB3/4
I
[mA] .
where gm−PNP = OUT3/4
26 [mV ]
The total DC loop gain for output 3 and output 4 is:
⎛ R × RP1/2 ⎞
A V = gC_ × ⎜ IN
⎟ × AP
⎝ RIN + RP1/2 ⎠
The output capacitance (COUT_) and the load resistance (ROUT_) create a dominant pole (fPOLE1) at:
fPOLE1[kHz] =
=
1
2π × COUT3/4 [μF] × ROUT3/4 [kΩ]
IOUT3/4(MAX)[mA]
2π × COUT3/4 [μF] × VOUT3/4 [V]
______________________________________________________________________________________
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
fPOLE2[kHz] =
1
2π(CBE + CQIN )[μF] × RTOTAL [kΩ]
where RTOTAL = RIN RP1/2.
To maintain the stability, at a minimum the following
condition must be satisfied:
A V × fPOLE1 < fPOLE2
i.e., the second pole must occur above the unity-gain
crossover. At heavy output load, we can simplify as follows:
ROUT3/4 << R1FB3/4 + R2FB3/4
CBE << CQIN ≈ gm −PNP × τF
RP1/2 >> RIN ≈
β
gm −PNP
And hence, the output capacitance (COUT3/4) must satisfy the following equation:
COUT3/4 > α × gC_ × τF × β2
where:
α=
R2FB3/4
R1FB3/4 + R2FB3/4
ß is the current gain of the PNP transistor, gC_ is the
transconductance of the internal amplifier (1.2mA/mV
typical), and τF is the forward transit time of the PNP
transistor. For example, using a PNP transistor with a ß
of 120, τF of 400ps, gC_ = 1.2mA/mV, and α = 0.5 for a
1.2V output voltage, COUT must be at least 3.9μF.
If the second pole occurs well after unity-gain crossover,
the linear regulator remains stable. If not, then increase
the output capacitance, COUT3/4, such that:
If the output capacitor is a high-ESR capacitor, then
cancel the ESR zero with a pole at FB3/4. This is
accomplished by adding a capacitor (CFB3/4_) from
FB3/4 to ground, such that:
CFB3/4 [μF] =
1
2π × (R1FB3/4 R2FB3/4 )[kΩ] × fESR[kHz]
For a sufficiently low output capacitance, choose a fast
PNP transistor without an excessively high ß. Note,
selecting a transistor with a ß that is too low can
adversely impact load regulation.
Output 3 and Output 4 Capacitors
Connect COUT (as determined above) between the linear regulator’s output and ground, as close as possible
to the MAX15022 and the external pass transistors.
Depending on the selected pass transistor, larger
capacitor values may be required for stability (see the
Stability Requirement section).
Once the minimum capacitor value for stability is determined, verify that the linear regulator’s output does not
contain excessive noise. Although adequate for stability, small capacitor values can provide too much bandwidth, making the linear regulator sensitive to noise.
Larger capacitor values reduce the bandwidth, thereby
reducing the regulator’s noise sensitivity.
Base-Drive Noise Reduction
The high-impedance base driver is susceptible to system noise, especially when the linear regulator is lightly
loaded. Capacitively coupled switching noise or inductively coupled EMI on the base drive may cause fluctuations in the base current, which appear as noise on
the linear regulator’s output. To avoid this, keep the
base-driver traces away from the step-down converter
and as short as possible to minimize noise coupling.
A bypass capacitor (CBE) can be placed across the
base-to-emitter resistor. This bypass capacitor, in addition to the transistor’s input capacitance, reduces the
frequency of the second pole (fPOLE2) that could destabilize the linear regulator. Therefore, the stability
requirements determine the maximum base-to-emitter
capacitance (CBE) that can be added. A capacitance
in the range of 470pF to 2200pF is recommended.
fPOLE2 > 2 × fCOUT_
______________________________________________________________________________________
23
MAX15022
The input capacitance to the base of the pass transistor
(CQIN), any external base-to-emitter capacitance (CBE,
see the Base-Drive Noise Reduction section), the transistor’s input resistance (RIN), and the base-to-emitter
pullup resistor (RP_) set a second pole:
MAX15022
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
Minimum Load Requirements
(Linear Regulators)
Under no-load conditions, leakage currents from the
pass transistors supply the output capacitor, even
when the transistor is off. Generally, this is not a problem since the feedback resistors’ current drains the
excess charge. However, charge can build up on the
output capacitor over temperature, making output voltage rise above its set point. Care must be taken to
ensure the feedback resistors’ current exceeds the
pass transistor’s leakage current over the entire temperature range.
Thermal Consideration
The power dissipated by the pass transistor is calculated by:
PP3/4 = ( VIN − VOUT3/4 ) × IOUT3/4
where VIN is the input to the transistor of the LDO.
Heatsink the transistor adequately to prevent a thermal
runaway condition. Refer to the transistor data sheet for
thermal calculations.
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve clean and stable operation. Follow these guidelines for good PCB
layout:
1) Place decoupling capacitors as close as possible to
the IC pins.
24
2) Keep SGND and PGND isolated. Connect them at
one single point typically close to the negative terminal of the input filter capacitor. Use as short a
trace as possible.
3) Route high-speed switching nodes (LX_) away from
sensitive analog areas (FB_, COMP_, B_, and EN_).
4) Distribute the power components evenly across the
board for proper heat dissipation.
5) Ensure all feedback connections are short and
direct. Place feedback resistors as close as possible to the IC.
6) Place the output capacitors close to the load.
7) Connect the MAX15022 exposed pad to a large
copper plane to maximize its power dissipation
capability. Thermal resistances can be obtained
using the method described in JEDEC specification
JESD51-7. Connect the exposed pad to SGND
plane. Do not connect the exposed pad to the
SGND pin directly underneath the IC.
8) Use 2oz. copper to keep trace inductance and
resistance to a minimum. Thin copper PCBs can
compromise efficiency since high currents are
involved in the application. Also thicker copper conducts heat more effectively, thereby reducing thermal impedance.
9) A reference PCB layout included in the MAX15022
Evaluation Kit is also provided to further aid layout.
______________________________________________________________________________________
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
VIN
CI2
R1FB2
RI2
C1
R1
CF2
RF2
R2FB2
C2
CIN2
CDD2
CCF2
VOUT2
AVIN
EN2 PVIN2
DVDD2
CE1
RP1
FB2 COMP2
LX2
L2
VOUT2
CP1
RS2
Q1
COUT2
B3
VOUT3
CS2
R1EN3
VOUT1
PGND2
COUT3
VIN
EN3
R1FB3
CDD1
DVDD1
FB3
EN1
R2FB3
VIN
R2EN3
VAVIN
CIN1
PVIN1
CP2
LX1
RP2
CE2
Q2
VOUT1
L1
MAX15022
RS1
B4
COUT1
CS1
PGND1
R1EN4
VOUT4
COUT4
R1FB4
EN4
FB4
R2FB4
CI1
R2EN4
RI1
R1FB1
R1EN2
R2FB1
R2EN2
FB1
RT
SGND
SEL
COMP1
VAVIN
RT
PGND
CT
CF1
RF1
CCF1
SGND
Figure 7. MAX15022 Double Buck with Tracking and Two Additional LDOs
______________________________________________________________________________________
25
MAX15022
Typical Operating Circuits
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
MAX15022
Typical Operating Circuits (continued)
VIN
CI2
R1FB2
RI2
C1
R1
CF2
RF2
R2FB2
C2
CIN2
AVIN
EN2 PVIN2
CDD2
DVDD2
FB2 COMP2
LX2
CE1
RP1
CCF2
L2
VOUT2
CP1
RS2
Q1
COUT2
B3
VOUT3
CS2
R1EN3
PGND2
COUT3
VIN
EN3
R1FB3
CDD1
DVDD1
FB3
EN1
R2FB3
VIN
R2EN3
VAVIN
CIN1
PVIN1
CP2
LX1
RP2
CE2
Q2
VOUT1
L1
MAX15022
RS1
B4
COUT1
CS1
PGND1
R1EN4
VOUT4
COUT4
R1FB4
EN4
FB4
R2FB4
CI1
R2EN4
RI1
R1FB1
FB1
RT
SGND
SEL
COMP1
R2FB1
CF1
RT
PGND
CT
RF1
CCF1
SGND
Figure 8. MAX15022 Double Buck with Sequencing and Two Additional LDOs
26
______________________________________________________________________________________
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
PROCESS: BiCMOS
For the latest package outline information, go to
www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
28 TQFN
T2855-6
21-0140
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
MAX15022
Package Information
Chip Information