PCS3P2537A Peak EMI Reduction IC Features PCS3P2537A modulates the output of a single PLL in order to “spread” the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This result in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal’s bandwidth is called ‘spread spectrum clock generation.’ • 1x Peak EMI Reduction IC • Input Frequency: 18MHz-36MHz • Output Frequency: 18MHz-36MHz • Frequency Deviation @ 27MHz: -0.25% • Modulation Rate @ 27MHz: 30.1KHz • Supply Voltage: 3.3V ± 0.3V • Operating current less than 8mA @ 27MHz • Spread Spectrum Enable Control PCS3P2537A has a frequency range of 18MHz-36MHz, and accepts input clock either from a Crystal or from an external reference and locks on to it delivering a 1x spread spectrum clock output. It has an SSON control for enabling and disabling Spread Spectrum function. • CMOS design • 8L-WDFN (8L-TDFN) package Product Description PCS3P2537A is a 1x spread spectrum frequency modulator designed to reduce electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of down stream clock and data dependent signals. The device allows significant system cost savings by reducing the number of circuit board layers, ferrite beads and shielding and other passive components that are traditionally required to pass EMI regulations. PCS3P2537A operates with a supply voltage of 3.3V, and is available in 8 L-WDFN package. Application PCS3P2537A is targeted towards PC peripheral devices and embedded systems. Block Diagram VDD CLKIN / XIN XOUT Crystal Oscillator SSON PLL ModOUT GND ©2010 SCILLC. All rights reserved. JANUARY 2010 – Rev. 1 Publication Order Number: PCS3P2537/D PCS3P2537A Pin Configuration (8L-WDFN Package) CLKIN / XIN 1 8 VDD 7 NC SSON 3 6 ModOUT NC 4 5 GND XOUT 2 PCS3P2537A Pin Description Pin# Pin Name Type Description 1 CLKIN / XIN I External reference Clock input or Crystal connection. This pin has dual functions. It can be connected either to an external crystal or an external reference clock. 2 XOUT O Crystal connection. If using an external reference, this pin must be left unconnected. 3 SSON I When SSON is HIGH, the spread spectrum is enabled and when LOW, it turns off the spread spectrum. 4 NC 5 GND P Ground connection. 6 ModOUT O Spread Spectrum Clock Output. 7 NC 8 VDD No Connect. No Connect. P Power supply for the entire chip. Rev. 1 | Page 2 of 7 | www.onsemi.com PCS3P2537A Absolute Maximum Ratings Symbol VDD, VIN TSTG Parameter Rating Unit Voltage on any pin with respect to Ground -0.5 to +4.6 V Storage temperature -65 to +125 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C TDV Static Discharge Voltage (As per JEDEC STD22- A114-B) 2 KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Operating Conditions Parameter VDD Description Supply Voltage Min Max Unit 3.0 3.6 V 0 TA Operating Temperature (Ambient Temperature) 70 °C CL Load Capacitance 15 pF CIN Input Capacitance 7 pF DC Electrical Characteristics for 3.3V Supply Symbol Parameter Max Unit VIL Input low voltage VSS-0.3 0.8 V VIH Input high voltage 2.0 VDD+0.3 V IIL Input low current -35 µA IIH Input high current 35 µA VOL Output low voltage (VDD = 3.3V, IOL = 8mA) VOH Output high voltage (VDD = 3.3V, IOH = 8mA) IDD Static supply current ICC Dynamic supply current (3.3V, 27MHz and no load) VDD tON ZOUT Min Typ 0.4 2.5 1 Operating Voltage 3 2.5 mA 5 8 mA 3.3 3.6 V 5 mS Power-up time (first locked cycle after power-up) Output impedance 36 Note: 1. CLKIN is pulled to GND. Rev. 1 | Page 3 of 7 | www.onsemi.com V V Ω PCS3P2537A AC Electrical Characteristics for 3.3V Supply Symbol CLKIN ModOUT fd Parameter Min Typ Max Unit Input frequency 18 27 36 MHz Output frequency 18 27 36 MHz -0.2 -0.25 -0.3 % 33 KHz 2 nS 1.5 nS ±200 ±300 pS 50 55 % Frequency Deviation @ 27MHz MR Modulation Rate @ 27MHz 1 tLH Output rise time (measured from 20% to 80%) tHL 1 30 Output fall time (measured at 80% to 20%) tJC Cycle-to-Cycle Jitter at 27MHz tD Output duty cycle 45 Note: 1. tLH and tHL are measured into a capacitive load of 15pF. Rev. 1 | Page 4 of 7 | www.onsemi.com PCS3P2537A Typical Application Schematic VDD CLKIN / XIN 1 CLKIN / XIN 2 XOUT NC 7 3 SSON ModOUT 6 VDD VDD 8 0.01uF 0Ω 0Ω 4 NC GND 5 Note: Refer to Pin Description table for Functionality Details. PCB Layout Recommendation For optimum device performance, the following guidelines are recommended. used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should • Dedicated VDD and GND planes. be kept as short as possible. All the VDD pins should • The device must be isolated from system power have decoupling capacitors. supply noise. A 0.01µF decoupling capacitor should • In an optimum layout all components are on the be mounted on the component side of the board as same side of the board, minimizing vias through close to the VDD pin as possible. No vias should be other signal layers. A typical layout is shown in the figure As short as possible CLKIN VDD XOUT NC SSON NC Modout GND GND Rev. 1 | Page 5 of 7 | www.onsemi.com PCS3P2537A Package Information 8L-WDFN package Symbol A A3 Dimensions Inches Millimeters Min Max Min Max 0.027 0.0315 0.70 0.008 BSC 0.80 0.203 BSC b 0.008 0.012 0.20 0.30 D 0.077 0.080 1.95 2.05 E 0.077 0.080 1.95 e L 0.020 BSC 0.020 0.024 2.05 0.50 BSC 0.50 Rev. 1 | Page 6 of 7 | www.onsemi.com 0.60 PCS3P2537A Ordering Code Part Number PCS3P2537AG-08CR Top Marking AM Package Temperature 8L-WDFN (8L-TDFN) - TAPE & REEL, Green 0°C to +70°C A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb-free. Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. Note: This product utilizes US Patent #6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003. 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