ComLink™ Series CY2DP814 1:4 Clock Fanout Buffer Features Description • • • • • • • • • Low voltage operation VDD = 3.3V 1:4 fanout Single-input configurable for LVDS, LVPECL, or LVTTL Four differential pairs of LVPECL outputs Drives 50-ohm load Low input capacitance Low output skew Low propagation delay — Typical (tpd < 4 ns) • Industrial versions available • Available packages include TSSOP, SOIC The Cypress CY2 series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic. The Cypress CY2DP814 fanout buffer features a single LVDSor a single LVPECL-compatible input and four LVPECL output pairs. Designed for data communications clock management applications, the fanout from a single input reduces loading on the input clock. The CY2DP814 is ideal for both level translations from single-ended to LVPECL and/or for the distribution of LVDS-based clock signals. The Cypress CY2DP814 has configurable input between logic families. The input can be selectable for an LVPECL/LVTTL or LVDS signal, while the output drivers support LVPECL capable of driving 50-ohm lines. EN1 1 EN2 8 EN1 CONFIG 16 Q1A 15 Q1B VDD VDD 14 Q2A 13 Q2B IN+ 6 IN- 7 GND IN+ IN- LVDS / LVPECL / LVTTL 12 Q3A 11 Q3B EN2 CONFIG 2 1 2 3 4 5 6 7 8 CY2DP814 Pin Configuration Block Diagram 16 15 14 13 12 11 10 9 Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B 16 pin TSSOP / SOIC 10 Q4A 9 Q4B OUTPUT LVPECL Cypress Semiconductor Corporation Document #: 38-07060 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 15, 2002 ComLink™ Series CY2DP814 Pin Description Pin Number Pin Name Pin Standard Interface Description 6, 7 IN+, IN– Configurable Differential input pair or single line. LVPECL default. See CONFIG below. 2 CONFIG LVTTL/LVCMOS Converts inputs from the default LVPECL/LVDS (logic = 0) to LVTTL/LVCMOS (logic = 1). See Figure 6 and Figure 7 for additional information 1, 8 EN1, EN2 LVTTL/LVCMOS Enable/disable logic. See Function Table below for details. 16, 15, 14, 13, 12, 11, 10, 9 Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B LVPECL Differential outputs. 3, 4 VDD POWER Positive supply voltage. 5 GND POWER Ground. Document #: 38-07060 Rev. *B Page 2 of 9 ComLink™ Series CY2DP814 Maximum Ratings[1][2] Storage Temperature: .................................–65°C to +150°C (Outputs only) ........................................ –0.3V to VDD + 0.3V Ambient Temperature:................................... –40°C to +85°C DC Input Voltage ................................... –0.3V to VDD + 0.3V Supply Voltage to Ground Potential DC Output Voltage................................. –0.3V to VDD + 0.9V (Inputs and VCC only)....................................... –0.3V to 4.6V Power Dissipation........................................................ 0.75W Supply Voltage to Ground Potential Table 1. EN1 EN2 Function Table Enable Logic Input EN1 EN2 IN+ H H H L L L L H Outputs IN– QnA QnB H L H L H L H L H L H L X X Z Z Table 2. Input Receiver Configuration for Differential or LVTTL/LVCMOS CONFIG Pin 2 Binary Value 1 0 Input Receiver Family Input Receiver Type LVTTL in LVCMOS Single ended, non-inverting, inverting, void of bias resistors. LVDS Low voltage differential signaling LVPECL Low voltage pseudo (positive) emitter coupled logic Table 3. Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal LVTTL/LVCMOS INPUT LOGIC Input Condition Ground Input Logic Output Logic Q pins Input True Input Invert Input Invert Input True IN- Pin 7 IN+ Pin 6 VCC IN- Pin 7 Ground IN+ Pin 6 VCC IN+ Pin 6 IN+ Pin 6 IN- Pin 7 IN- Pin 7 Table 4. Power Supply Characteristics Parameter Description Test Conditions Min. ICCD Dynamic Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Loaded IC Total Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Loaded, fL= 100 MHz Typ. Max. Unit 1.5 2.0 mA/MHz 90 100 mA Table 5. D.C. Electrical Characteristics: 3.3V–LVDS Input Parameter Description Conditions Min. Typ. Max. Unit VID Magnitude of Differential Input Voltage 100 VIC Common-Mode of Differential Input Voltage IVIDI (min. and max.) IVIDI /2 IIH Input High Current IIL II 600 mV 2.4– (IVIDI /2) V VDD = Max. VIN = VDD ±10 ±20 uA Input Low Current VDD = Max. VIN = VSS ±0 ±20 uA Input High Current VDD = Max., VIN = VDD(max.) ±20 uA Notes: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Document #: 38-07060 Rev. *B Page 3 of 9 ComLink™ Series CY2DP814 Table 6. D.C. Electrical Characteristics: 3.3V–LVPECL Input Parameter I VID I Description Condition Differential Input Voltage p-p Min. Guaranteed Logic High Level Typ. 400 VCM Common-mode Voltage IIH Input High Current VDD = Max. VIN = VDD 1650 ±10 IIL Input Low Current VDD = Max. VIN = VSS ±10 II Input High Current VDD = Max., VIN = VDD(max.) Max. Unit 2600 mV 2250 mV ±20 uA ±20 uA ±20 uA Max. Unit 0.8 V Table 7. D.C Electrical Characteristics: 3.3V–LVTTL/LVCMOS Input Parameter Description Condition VIH Input High Voltage Guaranteed Logic High Level VIL Input Low Voltage Guaranteed Logic Low Level Min. Typ. 2 V IIH Input High Current VDD = Max. VIN = 2.7V 1 uA IIL Input Low Current VDD = Max. VIN = 0.5V –1 uA II Input High Current VDD = Max., VIN = VDD(max.) 20 uA VIK Clamp Diode Voltage VDD = Min., IIN = –18 mA –1.2 V VH Input Hysteresis –0.7 80 mV Table 8. D.C Electrical Characteristics: 3.3V–LVPECL Output Parameter Description Condition Min. I VOD I Driver Differential Output Voltage p-p VDD = Min., VIN = VIH or VIL RL = 50 ohm I VOC I Driver common-mode p-p VDD = Min., VIN = VIH or VIL RL = 50 ohm Differential 20% to 80% CL–10 pF RL and CL to GND Rise Time Fall Time 1000 RL = 50 ohm VOH Output High Voltage VDD = Min., VIN = VIH or VIL VOL Output Low Voltage User-defined (see Figure 1) IOS Short Circuit Current VDD = Max., VOUT = GND Typ. IOH = –12 mA Max. Unit 3600 mV 226 mV 300 800 pS 2.1 3.0 V V –125 –150 mA Table 9. AC Switching Characteristics @ 3.3V VDD = 3.3V ±5%, Temperature = –40°C to +85°C Parameter Description Conditions Min. Typ. Max. Unit IN [+,-] to Q[A,B] Data & Clock Speed tPLH Propagation Delay–Low to High 3 4 5 nS tPHL Propagation Delay–High to Low VOD = 100 mV 3 4 5 nS tPD Propagation Delay 3 4 5 ns EN [1,2] to Q[A,B] Control Speed tPE Enable (EN) to functional operation 6 nS Tpd Functional operation to Disable 5 nS tSK(0) Output Skew: Skew between outputs of the same package (in phase) tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL–tPLH) tSK(t) Package Skew: Skew between outputs of different packages at the VID = 100 mV same power supply voltage, temperature and package type. Same input signal level and output load. Document #: 38-07060 Rev. *B 0.2 0.2 nS nS 1 nS Page 4 of 9 ComLink™ Series CY2DP814 VDD - 2V VDD Q Q Device concept User Defined VTT & RTT Figure 1. Differential PECL Output Table 10. High-frequency Parametrics Parameter Description Conditions Min. Typ. Max. Unit Fmax Maximum Frequency VDD = 3.3V 50% Duty Cycle tW(50–50) Standard Load Circuit 450 MHz Fmax(20) Maximum Frequency VDD = 3.3V 20% Duty Cycle tW(20–80) LVPECL Input Vin = VIH(Max.)/VIL(Min.) Vout = VOH(Min.)/VOL (Max.) (Limit) 175 MHz TW Minimum Pulse VDD = 3.3V LVPECL Input Vin = VIH(Max.)/VIL(Min.) F = 100 MHz Vout = VOH(Min.)/VOL(Max.).(Limit) 900 A TPA 150 P u lse G e ne ra to r pS 50 10pF B 150 T PC V D D -2V 50 GND TP B En1 En2 S tand ard Te rm in ation V1A 1.4 V 1 .2 V C M 0 V D if f e re n tia l V1B 1.0 V V 0Y 1.4 V 1 .2 V C M 0 V D if f e re n tia l 1.0 V V 0Z T P LH T PHL 80% 0 V D if f e r e n tia l V0Y V0Z 20% t R t F Figure 2. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3, 4, 5, 6, 7] Notes: 3. RL = 50 ohm ± 1%; Zline = 50 ohm 6 = Ó. 4. CL includes instrumentation and fixture capacitance within 6 mm of the UT. 5. TPA and B are used for prop delay and rise/fall measurements. TPC is used for VOC measurements only and otherwise connected to VDD – 2. 6. When measuring Tr/Tf, tpd, VOD point TPC is held at VDD – 2.0V. 7. LVCMOS/LVTTL single-ended input value. Ground either input: when on the B side, non-inversion takes place. If A side is grounded, the signal becomes the complement of the input on B side. See Table 3. Document #: 38-07060 Rev. *B Page 5 of 9 ComLink™ Series CY2DP814 A TPA 150 P u ls e G e n e ra to r 50 TPC B 50 GND 150 TPB En1 En2 VOC VOD S ta n d a rd T e rm in a tio n V I(A ) 1 .4 V V I(B ) 1 .0 V V o c (p p ) VDD V o c (s s ) Figure 3. Test Circuit & Voltage Definitions for the Driver Common-mode Output Voltage[3, 4, 5, 7, 8] A TPA 150 Pulse Generator 50 10pF B 150 TPC VDD-2V 50 GND TPB En1 En2 Standard Termination VI(A) 1.4V VI(B) 1.0V 100% 80% 0.0V 20% 0% tF tR Figure 4. Test Circuit & Voltage Definitions for the Differential Output Signal [3, 4, 5, 6, 7] P ulse G enerator P ulse G enerator VOC TPA 50 TPC VDD-2V 50 TPB En1 En2 Parallel Termination + DE Q tpd tpe Figure 5. Test Circuit & Voltage Definitions for the Driver Common-Mode Output Voltage[3, 4, 5, 8, 9] Notes: 8. VOC measurement requires equipment with a 3-dB bandwidth of at least 300 MHz. 9. All input pulses are supplied by a frequency generator with the following characteristics: TR and tF ≤ 1 nS; pulse re-rate = 50 Mpps; pulse width = 10 ± 0.2 nS. Document #: 38-07060 Rev. *B Page 6 of 9 ComLink™ Series CY2DP814 INPUT A LVPECL & LVDS LVCM OS / LVTTL INPUT B GND In C o n fig InConfig 0 1 L V D S /L V P E C L LVTTL/LVCMOS Figure 6. [7] Figure 7. [10] Ordering Information Part Number CY2DP814ZI Package Type Product Flow 16-pin TSSOP Industrial, –40°C to 85°C CY2DP814ZIT 16-pin TSSOP–Tape and Reel Industrial, –40°C to 85°C CY2DP814SI 16-pin SOIC Industrial, –40°C to 85°C CY2DP814SIT 16-pin SOIC–Tape and Reel Industrial, –40°C to 85°C CY2DP814ZC 16-pin TSSOP Commercial, 0°C to 70 °C CY2DP814ZCT 16-pin TSSOP–Tape and Reel Commercial, 0°C to 70 °C CY2DP814SC 16-pin SOIC Commercial, 0°C to 70 °C CY2DP814SCT 16-pin SOIC–Tape and Reel Commercial, 0°C to 70 °C Package Drawing and Dimensions 16-lead (150-mil) Molded SOIC S16 51-85068-A Note: 10. LVPECL or LVDS differential input value. Document #: 38-07060 Rev. *B Page 7 of 9 ComLink™ Series CY2DP814 Package Drawings and Dimensions (continued) 16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 51-85091 All product and company names mentioned in this document are the trademarks of their respective holders.cv Document #: 38-07060 Rev. *B Page 8 of 9 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. ComLink™ Series CY2DP814 Document Title: ComLink™Series CY2DP814 1:4 Clock Fanout Buffer Document Number: 38-07060 REV. ECN No. Issue Date Orig. of Change Description of Change ** 10785 06/07/01 IKA Convert from IMI to Cypress *A 115610 07/02/02 CTK Range of VCM *B 122746 12/15/02 RBI Added power-up requirements to maximum ratings information. Document #: 38-07060 Rev. *B Page 9 of 9