FAIRCHILD KA555

www.fairchildsemi.com
KA555
Single Timer
Features
Description
•
•
•
•
•
The KA555 is a highly stable controller capable of
producing accurate timing pulses. With monos table
operation, the time delay is controlled by one external
resistor and one capacitor. With astable operation, the
frequency and duty cycle are accurately controlled with two
external resistors and one capacitor.
High Current Drive Capability (200mA)
Adjustable Duty Cycle
Temperature Stability of 0.005%/°C
Timing From Msec to Hours
Turn Off Time Less Than 2Msec
Applications
•
•
•
•
8-DIP
Precision Timing
Pulse Generation
Time Delay Generation
Sequential Timing
1
8-SOP
1
Internal Block Diagram
R
GND
1
Trigger
2
R
Comp.
Output
Reset
3
OutPut
Stage
R
8
Vcc
7
Discharge
6
Threshold
5
Control
Voltage
Discharging Tr.
F/F
4
Vref
Comp.
Rev. 1.0.2
©2002 Fairchild Semiconductor Corporation
KA555
Absolute Maximum Ratings (TA = 25°°C)
Parameter
Value
Unit
VCC
16
V
TLEAD
300
°C
PD
600
mW
Operating Temperature Range
KA555/KA555I
TOPR
0 ~ +70 / -40 ~ +85
°C
Storage Temperature Range
TSTG
- 65 ~ +150
°C
Supply Voltage
Lead Temperature (Soldering 10sec)
Power Dissipation
2
Symbol
KA555
Electrical Characteristics
(TA = 25°C, VCC = 5 ~ 15V, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply Voltage
VCC
-
4.5
-
16
V
Supply Current *1(Low Stable)
ICC
VCC = 5V, RL = ∞
-
3
6
mA
VCC = 15V, RL = ∞
-
7.5
15
mA
-
1.0
50
0.1
3.0
%
ppm/°C
%/V
2.25
150
0.3
-
%
ppm/°C
%/V
Timing Error *2 (Monos Table)
Initial Accuracy
Drift with Temperature
Drift with Supply Voltage
Timing Error *2(Astable)
Initial Accuracy
Drift with Temperature
Drift with Supply Voltage
ACCUR
∆t/∆T
∆t/∆VCC
ACCUR
∆t/∆T
∆t/∆VCC
Control Voltage
VCC
Threshold Voltage
VTH
Threshold Current
*3
RA = 1KΩ to100KΩ
C = 0.1µF
RA = 1KΩ to 100KΩ
C = 0.1µF
VCC = 15V
9.0
10.0
11.0
V
VCC = 5V
2.6
3.33
4.0
V
VCC = 15 V
-
10.0
-
V
VCC = 5V
-
3.33
-
V
-
0.1
0.25
µA
VCC = 5V
1.1
1.67
2.2
V
VCC = 15V
4.5
ITH
-
Trigger Voltage
VTR
Trigger Current
ITR
Reset Voltage
VRST
-
Reset Current
IRST
-
Low Output Voltage
High Output Voltage
VOL
VOH
-
0.5
VTR = 0V
0.4
VCC = 15V
ISINK = 10mA
ISINK = 50mA
-
VCC = 5V
ISINK = 5mA
-
5
5.6
V
0.01
2.0
µA
0.7
1.0
V
0.1
0.4
mA
0.06
0.3
0.25
0.75
V
V
0.05
0.35
V
-
V
V
VCC = 15V
ISOURCE = 200mA
ISOURCE = 100mA
12.75
12.5
13.3
VCC = 5V
ISOURCE = 100mA
2.75
3.3
-
V
Rise Time of Output
tR
-
-
100
-
ns
Fall Time of Output
tF
-
-
100
-
ns
ILKG
-
-
20
100
nA
Discharge Leakage Current
Notes:
1. Supply current when output is high is typically 1mA less at VCC = 5V
2. Tested at VCC = 5.0V and VCC = 15V
3. This will determine maximum value of RA + RB for 15V operation, the max. total R = 20MΩ, and for 5V operation the max. total
R = 6.7MΩ
3
KA555
Application Information
Table1 below is the basic operating table of 555 timer:
Table 1. Basic Operating Table
Threshold Voltage
Trigger Voltage
Discharging Tr.
Reset(Pin4)
Output(Pin3)
(Vth)(Pin6)
(Vtr)(Pin2)
(Pin7)
Don't care
Don't care
Low
Low
ON
Vth > 2Vcc / 3
Vth > 2Vcc / 3
High
Low
ON
High
Vcc / 3 < Vth < 2 Vcc / 3 Vcc / 3 < Vth < 2 Vcc / 3
Vth < Vcc / 3
High
High
OFF
Vth < Vcc / 3
When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or
the trigger voltage. Only when the high signal is applied to the reset terminal, timer's output changes according to threshold
voltage and trigger voltage.
When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr.
turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained
low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal
discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high.
1. Monos Table Operation
+Vcc
10
THRES 6
3 OUT
C1
RL
CONT 5
1
10
Ω
10
M
Ω
1M
10
0k
Ω
10
kΩ
7
TRIG
GND
1
=1
kΩ
DISCH
2
10
A
Trigger
RA
R
8
Vcc
Capacitance(uF)
4
RESET
2
0
10
-1
10
-2
10
-3
C2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
Time Delay(s)
Figure 1. Monoatable Circuit
Figure 3. Waveforms of Monostable Operation
4
Figure 2. Resistance and Capacitance vs.
Time delay(td)
10
2
KA555
Figure 1 illustrates a monos table circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls
below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's
internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor
C1and setting the flip-flop output at the same time.
The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t=RA*C and reaches 2Vcc/3
at td=1.1RA*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant RAC, the longer it takes
for the VC1 to reach 2Vcc/3. In other words, the time constant RAC controls the output pulse width.
When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop,
turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low.
In this way, the timer operating in monos table repeats the above process. Figure 2 shows the time constant relationship based
on RA and C. Figure 3 shows the general waveforms during monos table operation.
It must be noted that, for normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timer
output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is
high, it may be affected and the waveform not operate properly if the trigger pulse voltage at the end of the output pulse
remains at below Vcc/3. Figure 4 shows such timer output abnormality.
Figure 4. Waveforms of Monos table Operation (abnormal)
2. Astable Operation
+Vcc
100
(RA+2RB)
RA
RB
OUT
C1
GND
RL
0.1
Ω
3
Ω
0k
10
6
Ω
THRES
1
M
10
7
1M
DISCH
TRIG
Capacitance(uF)
Ω
1k
8
Vcc
kΩ
10
2
4
RESET
10
0.01
CONT 5
1
C2
1E-3
100m
1
10
100
1k
10k
100k
Frequency(Hz)
Figure 5. Astable Circuit
Figure 6. Capacitance and Resistance vs. Frequency
5
KA555
Figure 7. Waveforms of Astable Operation
An astable timer operation is achieved by adding resistor RB to Figure 1 and configuring as shown on Figure 5. In astable
operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multi
vibrator. When the timer output is high, its internal discharging Tr. turns off and the VC1 increases by exponential
function with the time constant (RA+RB)*C.
When the VC1, or the threshold voltage, reaches 2Vcc/3, the comparator output on the trigger terminal becomes high,
resetting the F/F and causing the timer output to become low. This in turn turns on the discharging Tr. and the C1 discharges
through the discharging channel formed by RB and the discharging Tr. When the VC1 falls below Vcc/3, the comparator
output on the trigger terminal becomes high and the timer output becomes high again. The discharging Tr. turns off and the
VC1 rises again.
In the above process, the section where the timer output is high is the time it takes for the VC1 to rise from Vcc/3 to 2Vcc/3,
and the section where the timer output is low is the time it takes for the VC1 to drop from 2Vcc/3 to Vcc/3. When timer output
is high, the equivalent circuit for charging capacitor C1 is as follows:
RA
RB
Vcc
C1
V – V ( 0- )
dv
c1
cc
C 1 −−−−−−− = −−−−−−−−−−−−−−−−−−
R +R
dt
A
B
V C1 ( 0+ ) = V CC ⁄ 3

Vc1(0-)=Vcc/3
(1)
(2)

t
-  – −−−−−−−−−−−−−−−−−−−−−− 

 ( R A + R B )C1 

2
V (t) = V
1 – −e

C1
CC 
3



(3)
Since the duration of the timer output high state(tH) is the amount of time it takes for the VC1(t) to reach 2Vcc/3,
6
KA555

t

H

-  – −−−−−−−−−−−−−−−−−−−−−− 

2  ( R A + R B )C1 
2
=V
V (t) = −V
1 – −e

C1
3
3 CC
CC 



t
H
(4)
= C ( R + R )In2 = 0.693 ( R + R )C
1 A
B
A
B 1
(5)
The equivalent circuit for discharging capacitor C1 when timer output is low as follows:
RB
C1
VC1(0-)=2Vcc/3
RD
dv
1
C1
C 1 −−−−−−−− + −−−−−−−−−−−−− V C1 = 0
R +R
dt
A
B
2
V C1 ( t ) = − V
3 CC e
t
- −−−−−−−−−−−−−−−−−−−−−−
( R A + R D )C1
(6)
(7)
Since the duration of the timer output low state(tL) is the amount of time it takes for the VC1(t) to reach Vcc/3,
tL
−−−−−
- −(−R−−−−−−+−−−R−−−−−−)C1
1
A
D
2
(8)
− V CC = − V
3
3 CC e
t = C ( R + R )In2 = 0.693 ( R + R )C
L
1 B
D
B
D 1
(9)
Since RD is normally RB >> RD although related to the size of discharging Tr.,
(10)
tL=0.693RBC1
Consequently, if the timer operates in astable, the period is the same with
'T=tH+tL=0.693(RA+RB)C1+0.693RBC1=0.693(RA+2RB)C1' because the period is the sum of the charge time and discharge
time. And since frequency is the reciprocal of the period, the following applies.
frequency,
1
1.44
f = − = −−−−−−−−−−−−−−−−−−−−−−−−
T
( R + 2R )C
A
B 1
( 11 )
3. Frequency divider
By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure
8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle.
7
KA555
Figure 8. Waveforms of Frequency Divider Operation
4. Pulse Width Modulation
The timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the
reference of the timer's internal comparators. Figure 9. illustrates the pulse width modulation circuit.
When the continuous trigger pulse train is applied in the monos table mode, the timer output width is modulated according to
the signal applied to the control terminal. Sine wave as well as other waveforms may be applied as a signal to the control
terminal. Figure 10 shows an example of pulse width modulation waveform.
+Vcc
4
RA
8
RESET
Vcc
Trigger
7
DISCH
2
TRIG
6
THRES
Output
3
OUT
Input
GND
CONT
5
C
1
Figure 9. Circuit for Pulse Width Modulation
Figure 10. Waveforms of Pulse Width Modulation
5. Pulse Position Modulation
If the modulating signal is applied to the control terminal while the timer is connected for astable operation as in Figure 11, the
timer becomes a pulse position modulator.
In the pulse position modulator, the reference of the timer's internal comparators is modulated which in turn modulates the
timer output according to the modulation signal applied to the control terminal.
Figure 12 illustrates a sine wave for modulation signal and the resulting output pulse position modulation : however, any wave
shape could be used.
8
KA555
+Vcc
4
RA
8
RESET
Vcc
7
DISCH
2
TRIG
RB
6
THRES
Output
3
OUT
Modulation
CONT
GND
5
C
1
Figure 12. Waveforms of pulse position modulation
Figure 11. Circuit for Pulse Position Modulation
6. Linear Ramp
When the pull-up resistor RA in the monos table circuit shown in Figure 1 is replaced with constant current source, the VC1
increases linearly, generating a linear ramp. Figure 13 shows the linear ramp generating circuit and Figure 14 illustrates the
generated linear ramp waveforms.
+Vcc
RE
2
4
8
RESET
Vcc
DISCH
7
THRES
6
R1
Q1
TRIG
R2
Output
OUT
3
GND
C1
CONT 5
C2
1
Figure 13. Circuit for Linear Ramp
Figure 14. Waveforms of Linear Ramp
In Figure 13, current source is created by PNP transistor Q1 and resistor R1, R2, and RE.
I
C
–V
V
CC
E
= −−−−−−−−−−−−−−−−
R
E
Here, V
( 12 )
E is
R
2
+ −−−−−−−−−−−−− V
V = V
E
BE R + R CC
1
2
( 13 )
For example, if Vcc=15V, RE=20kΩ, R1=5kW, R2=10kΩ, and VBE=0.7V,
VE=0.7V+10V=10.7V
Ic=(15-10.7)/20k=0.215mA
When the trigger is started in a timer configured as shown in Figure 13, the current flowing to capacitor C1 becomes a constant
current generated by PNP transistor and resistors.
9
KA555
Hence, the VC is a linear ramp function as shown in Figure 14. The gradient S of the linear ramp function is defined as
follows:
Vp – p
S = −−−−−−−−−
T
( 14 )
Here the Vp-p is the peak-to-peak voltage.
If the electric charge amount accumulated in the capacitor is divided by the capacitance, the VC comes out as follows:
V=Q/C
(15)
The above equation divided on both sides by T gives us
Q⁄T
V
−− = −−−−−−−
C
T
( 16 )
and may be simplified into the following equation.
S=I/C
(17)
In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the constant
current flowing through the capacitor.
If the constant current flow through the capacitor is 0.215mA and the capacitance is 0.02uF, the gradient of the ramp function
at both ends of the capacitor is S=0.215m/0.022u=9.77V/ms.
10
KA555
Mechanical Dimensions
Package
Dimensions in millimeters
0.060 ±0.004
#5
1.524 ±0.10
#4
0.018 ±0.004
#8
2.54
0.100
9.60
MAX
0.378
#1
9.20 ±0.20
0.362 ±0.008
(
6.40 ±0.20
0.252 ±0.008
0.46 ±0.10
0.79
)
0.031
8-DIP
5.08
MAX
0.200
7.62
0.300
3.40 ±0.20
0.134 ±0.008
3.30 ±0.30
0.130 ±0.012
0.33
0.013 MIN
+0.10
0.25 –0.05
+0.004
0~15°
0.010 –0.002
11
KA555
Mechanical Dimensions (Continued)
Package
Dimensions in millimeters
8-SOP
MIN
#5
12
0~
8°
+0.10
0.15 -0.05
+0.004
0.006 -0.002
3.95 ±0.20
0.156 ±0.008
5.72
0.225
0.50 ±0.20
0.020 ±0.008
1.80
MAX
0.071
MAX0.10
MAX0.004
6.00 ±0.30
0.236 ±0.012
0.41 ±0.10
0.016 ±0.004
#4
1.27
0.050
#8
5.13
MAX
0.202
#1
4.92 ±0.20
0.194 ±0.008
(
0.56
)
0.022
1.55 ±0.20
0.061 ±0.008
0.1~0.25
0.004~0.001
KA555
Ordering Information
Product Number
Package
KA555
8-DIP
KA555D
8-SOP
KA555I
8-DIP
KA555ID
8-SOP
Operating Temperature
0 ~ +70°C
-40 ~ +85°C
13
KA555
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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 2002 Fairchild Semiconductor Corporation