CYPRESS CYS25G0101DX

CYS25G0101DX
SONET OC-48 Transceiver
Features
•
•
•
•
•
•
•
•
•
data recovery operations in a single chip, optimized for full
SONET compliance.
SONET OC-48 operation
Bellcore and ITU jitter compliance
2.488-GBaud serial signaling rate
Multiple selectable loopback/loop-through modes
Single 155.52-MHz reference clock
Transmit FIFO for flexible data interface clocking
16-bit parallel-to-serial conversion in transmit path
Serial-to-16-bit parallel conversion in receive path
Synchronous parallel interface
— LVPECL-compliant
— HSTL-compliant
• Internal transmit and receive phase-locked loops
(PLLs)
• Differential CML serial input
— 50-mV input sensitivity
•
•
•
•
•
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— 100Ω Internal termination and DC-restoration
Differential CML serial output
— Source matched for 50Ω transmission lines (100Ω
differential transmission lines)
Direct interface to standard fiber-optic modules
Less than 1.0W typical power
120-pin 14 mm × 14 mm TQFP
Standby power-saving mode for inactive loops
0.25µ BiCMOS technology
Functional Description
System or Telco Bus
The CYS25G0101DX SONET OC-48 Transceiver is a
communications building block for high-speed SONET data
communications. It provides complete parallel-to-serial and
serial-to-parallel conversion, clock generation, and clock and
SONET Data
Processor
16
Transmit Data
Interface
Host Bus
Interface
Receive Data
Interface
16
Transmit Path
New data is accepted at the 16-bit parallel transmit interface
at a rate of 155.52 MHz. This data is passed to a small
integrated FIFO to allow flexible transfer of data between the
SONET processor and the transmit serializer. As each 16-bit
word is read from the transmit FIFO, it is serialized and sent
out the high-speed differential line driver at a rate of 2.488
Gbits/second.
Receive Path
As serial data is received at the differential line receiver, it is
passed to a clock and data recovery (CDR) PLL, which
extracts a precision low-jitter clock from the transitions in the
data stream. This bit-rate clock is then used to sample the data
stream and receive the data. Every 16-bit-times, a new word
is presented at the receive parallel interface along with a clock.
Parallel Interface
The parallel I/O interface supports high-speed bus communications using HSTL signaling levels to minimize both power
consumption and board landscape. The HSTL outputs are
capable of driving unterminated transmission lines of less than
70 mm, and terminated 50Ω transmission lines of more than
twice that length.
The CYS25G0101DX Transceiver’s parallel HSTL I/O can
also be configured to operate at LVPECL signaling levels. This
can all be done externally by changing VDDQ, VREF, and
creating a simple circuit at the termination of the transceiver’s
parallel output interface.
Clocking
The source clock for the transmit data path is selectable from
either the recovered clock or an external BITS (Building
Integrated Timing Source) reference clock. The low jitter of the
CYS25G0101DX
TXD[15:0]
TXCLKI
FIFO_RST
FIFO_ERR
TXCLKO
2
REFCLK±
155.52 MHz
BITS Time
Reference
RXD[15:0]
RXCLK
Data & Clock
Direction
Control
LOOPTIME
DIAGLOOP
LOOPA
LINELOOP
Status and
System
Control
RESET
PWRDN
LOCKREF
LFI
IN+
IN–
SD
OUT–
OUT+
Serial Data
Serial Data
RD+
RD–
SD
TD–
TD+
Optical
XCVR
Optical
Fiber Links
Figure 1. CYS25G0101DX System Connections
Cypress Semiconductor Corporation
Document #: 38-02009 Rev. *J
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 30, 2002
CYS25G0101DX
CDR PLL allows loop-timed operation of the transmit data path
while still meeting all Bellcore and ITU jitter requirements.
Multiple loopback and loop-through modes are available for
both diagnostic and normal operation. For systems containing
redundant SONET rings that are maintained in standby, the
CYS25G0101DX may also be dynamically powered down to
conserve system power.
Logic Block Diagram
(155.52 MHz)
TXCLKI TXD[15:0]
FIFO_ERR
TXCLKO
(155.52 MHz)
RXCLK
(155.52 MHz)
REFCLK±
RXD[15:0]
FIFO_RST
16
16
Input
Register
Output
Register
FIFO
TX PLL
X16
÷16
Shifter
÷16
Recovered
Bit-Clock
TX Bit-Clock
Shifter
RX CDR
PLL
Retimed
Data
Lock-to-Ref
LOOPTIME
DIAGLOOP
Lock-to-Data/
Clock Control
Logic
LINELOOP
LOOPA
OUT±
Document #: 38-02009 Rev. *J
PWRDN LOCKREF
SD
LFI
RESET
IN±
Page 2 of 15
CYS25G0101DX
Pin Configuration[1, 2]
NC
NC
NC
VSSQ
NC
VSSQ
VCCQ
NC
NC
VCCQ
VSSQ
VCCQ
O U T+
O U T–
VSSQ
VCCQ
IN+
IN–
VSSQ
CM_SER
VCCQ
VCCQ \NC*
RXCP1
RXCN1
VSSQ \NC*
VCCQ
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
NC
VCCQ
VSSQ
REFCLK+
REFCLK–
NC
LOOPTIME
PWRDN
VSSN
VCCN
VSSN
TXCLKO
VSSN
VDDQ
TXD[0]
TXD[1]
TXD[2]
TXD[3]
VCCQ
VSSQ
VCCN
VSSN
TXD[4]
TXD[5]
TXD[6]
TXD[7]
TXD[8]
TXD[9]
TXD[10]
TXD[11]
VSSN
VD DQ
RXD[12]
RXD[13]
RXD[14]
RXD[15]
VSSN
VDDQ
VCC N
VSSN
FIFO_ERR
FIFO_RST
TXD[15]
TXD[14]
TXD[13]
TXD[12]
TXCLKI
VSSN
VCC N
VREF
74
73
72
71
70
69
68
67
66
65
64
63
62
61
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
RXD[9]
RXD[10]
RXD[11]
25
26
27
28
29
30
31
VSSQ
NC
17
18
19
20
21
22
23
24
CYS25G0101DX
VCCQ
NC
NC
VC CQ
RXD[8]
VSSN
SD
LOCKREF
RXD[0]
RXD[1]
RXD[2]
RXD[3]
VSSN
VDDQ
RXD[4]
RXD[5]
RXD[6]
RXD[7]
VSSN
VDDQ
RXCLK
VSSN
VDDQ
NC
NC
NC
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSSQ
LFI
RESET
DIAGLOOP
LINELOOP
LOOPA
VSSN
VCCN
VSSN
120
NC
VSSQ \NC*
RXCP2
RXCN2
120-pin Thin Quad Flatpack Pin Configuration
Notes:
1. No connect (NC) pins must be left unconnected or floating. Connecting any of these pins to the positive or negative power supply may cause improper operation
or failure of the device.
2. Pins 113 and 119 can be either no connect or VSSQ. Use VSSQ for compatibility with next generation of OC-48 SERDES devices. Pin 116 can be either no
connect or VCCQ. Use VCCQ for compatibility with next generation of OC-48 SERDES devices.
Document #: 38-02009 Rev. *J
Page 3 of 15
CYS25G0101DX
Pin Descriptions
CYS25G0101DX OC-48 SONET Transceiver
Pin Name
I/O Characteristics
Signal Description
Transmit Path Signals
TXD[15:0]
HSTL inputs,
Parallel Transmit Data Inputs. A 16-bit word, sampled by TXCLKI↑. TXD[15] is the most
sampled by TXCLKI↑ significant bit (the first bit transmitted).
TXCLKI
HSTL Clock input
Parallel Transmit Data Input Clock. The TXCLKI is used to transfer the data into the input
register of the serializer. The TXCLKI samples the data, TXD [15:0], on the rising edge of
the clock cycle.
TXCLKO
HSTL Clock output
Transmit Clock Output. Divide by 16 of the selected transmit bit-rate clock. It can be used
to coordinate byte-wide transfers between upstream logic and the CYS25G0101DX.
VREF
Input Analog
Reference
Reference Voltage for HSTL Parallel Input Bus. VDDQ/2.[3]
Receive Path Signals
RXD[15:0]
HSTL output,
synchronous
Parallel Receive Data Output. These outputs change following RXCLK↓. RXD[15] is the
most significant bit of the output word, and is received first on the serial interface.
RXCLK
HSTL Clock output
Receive Clock Output. Divide by 16 of the bit-rate clock extracted from the received serial
stream. RXD [15:0] is clocked out on the falling edge of the RXCLK.
CM_SER
Analog
Common Mode Termination. Capacitor shunt to VSS for common mode noise.
RXCN1
Analog
Receive Loop Filter Capacitor (Negative)
RXCN2
Analog
Receive Loop Filter Capacitor (Negative)
RXCP1
Analog
Receive Loop Filter Capacitor (Positive)
RXCP2
Analog
Receive Loop Filter Capacitor (Positive)
Device Control and Status Signals
REFCLK±
Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit and
input
receive PLLs. A derivative of this input clock may also be used to clock the transmit parallel
interface. The reference clock is internally biased allowing for an AC-coupled clock signal.
LFI
LVTTL output
Line Fault Indicator. When LOW, this signal indicates that the selected receive data
stream has been detected as invalid by either a LOW input on SD, or by the receive VCO
being operated outside its specified limits.
RESET
LVTTL input
Reset for all logic functions except the transmit FIFO.
LOCKREF
LVTTL input
Receive PLL Lock to Reference. When LOW, the receive PLL locks to REFCLK instead
of the received serial data stream.
SD
LVTTL input
Signal Detect. When LOW, the receive PLL locks to REFCLK instead of the received serial
data stream. The SD is to be connected to an external optical module to indicate a loss of
received optical power.
FIFO_ERR
LVTTL output
Transmit FIFO Error. When HIGH the transmit FIFO has either under or overflowed. When
this occurs, the FIFO’s internal clearing mechanism will clear the FIFO within 9 clock cycles.
In addition, FIFO_RST must be activated at device power-up to ensure that the in and out
pointers of the FIFO are set to maximum separation.
FIFO_RST
LVTTL input
Transmit FIFO Reset. When LOW, the in and out pointers of the transmit FIFO are set to
maximum separation. FIFO_RST must be activated at device power-up to ensure that the
in and out pointers of the FIFO are set to maximum separation. When the FIFO is being
reset, the output data is a 1010... pattern.
PWRDN
LVTTL input
Device Power Down. When LOW, the logic and drivers are all disabled and placed into a
standby condition where only minimal power is dissipated.
Loop Control Signals
DIAGLOOP
LVTTL input
Diagnostic Loopback Control. When HIGH, transmit data is routed through the receive
clock and data recovery and presented at the RXD[15:0] outputs. When LOW, received
serial data is routed through the receive clock and data recovery and presented at the
RXD[15:0] outputs.
Note:
3. VREF equals to (VCC – 1.33)V if interfacing to a parallel LVPECL interface.
Document #: 38-02009 Rev. *J
Page 4 of 15
CYS25G0101DX
CYS25G0101DX OC-48 SONET Transceiver (continued)
Pin Name
I/O Characteristics
Signal Description
LINELOOP
LVTTL input
Line Loopback Control. When HIGH, received serial data is looped back from receive to
transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data
passed to the OUT± line driver is controlled by LOOPA. When both LINELOOP and LOOPA
are LOW, the data passed to the OUT± line driver is generated in the transmit shifter.
LOOPA
LVTTL input
Analog Line Loopback. When LINELOOP is LOW and LOOPA is HIGH, received serial
data is looped back from receive input buffer to transmit output buffer, but is not routed
through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the
OUT± line driver is controlled by LINELOOP.
LOOPTIME
LVTTL input
Loop Time Mode. When HIGH, the extracted receive bit-clock replaces transmit bit-clock.
When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock.
OUT±
Differential CML
output
Differential Serial Data Output. This differential CML output (+3.3V referenced) is capable
of driving terminated 50Ω transmission lines or commercial fiber-optic transmitter modules.
IN±
Differential CML
input
Differential Serial Data Input. This differential input accept the serial data stream for
deserialization and clock extraction.
VCCN
Power
+3.3V supply (for digital and low-speed I/O functions)
VSSN
Ground
Signal and power ground (for digital and low-speed I/O functions)
VCCQ
Power
+3.3V quiet power (for analog functions)
VSSQ
Ground
Quiet ground (for analog functions)
VDDQ
Power
+1.5V supply for HSTL outputs[4]
Serial I/O
Power
CYS25G0101DX Operation
The CYS25G0101DX is a highly configurable device designed
to support reliable transfer of large quantities of data using
high-speed serial links. It performs necessary clock and data
recovery, clock generation, serial-to-parallel conversion, and
parallel-to-serial conversion. CYS25G0101DX also provides
various loopback functions.
CYS25G0101DX Transmit Data Path
Operating Modes
The transmit path of the CYS25G0101DX supports 16-bit
-wide data paths.
Phase-Align Buffer
Data from the input register is passed to a phase-align buffer
(FIFO). This buffer is used to absorb clock phase differences
between the transmit input clock and the internal character
clock.
Initialization of the phase-align buffer takes place when the
FIFO_RST input is asserted LOW. When FIFO_RST is
returned HIGH, the present input clock phase relative to
TXCLKO is set. Once set, the input clock is allowed to skew in
time up to half a character period in either direction relative to
REFCLK (i.e., ±180°). This time shift allows the delay path of
the character clock (relative to REFLCK) to change due to
operating voltage and temperature while not effecting the
desired operation. FIFO_RST is an asynchronous input.
FIFO_ERR is the transmit FIFO Error indicator. When HIGH,
the transmit FIFO has either under or overflowed. The FIFO
can be externally reset to clear the error indication or if no
action is taken, the internal clearing mechanism will clear the
FIFO in nine clock cycles. When the FIFO is being reset, the
output data is 1010.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a 155.52-MHz
external clock at the REFCLK input, and multiplies that clock
by 16 to generate a bit-rate clock for use by the transmit shifter.
The operating serial signaling rate and allowable range of
REFCLK frequencies is listed in Table 7. The REFCLK phase
noise limits to meet SONET compliancy are illustrated in
Figure 5. The REFCLK± input is a standard LVPECL input.
Serializer
The parallel data from the phase-align buffer is passed to the
Serializer which converts the parallel data to serial data using
the bit-rate clock generated by the Transmit PLL clock multiplier. TXD[15] is the most significant bit of the output word, and
is transmitted first on the serial interface.
Serial Output Driver
The serial interface Output Driver makes use of high-performance differential Current Mode Logic (CML) to provide a
source-matched driver for the transmission lines. This driver
receives its data from the Transmit Shifters or the receive
loopback data. The outputs have signal swings equivalent to
that of standard LVPECL drivers, and are capable of driving
AC-coupled optical modules or transmission lines.
Note:
4. VDDQ equals VCC if interfacing to a parallel LVPECL interface.
Document #: 38-02009 Rev. *J
Page 5 of 15
CYS25G0101DX
CYS25G0101DX Receive Data Path
Serial Line Receivers
A differential line receiver, IN±, is available for accepting the
input serial data stream. The serial line receiver inputs can
accommodate high wire interconnect and filtering losses or
transmission line attenuation (VSE > 25 mV, or 50 mV
peak-to-peak differential), and can be AC-coupled to +3.3V or
+5V powered fiber-optic interface modules. The commonmode tolerance of these line receivers accommodates a wide
range of signal termination voltages.
Lock to Data Control
Line Receiver routed to the clock and data recovery PLL is
monitored for
• status of signal detect (SD) pin
• status of LOCKREF pin.
This status is presented on the Line Fault Indicator (LFI)
output, which changes asynchronously in the cases in which
SD or LOCKREF go from HIGH to LOW. Otherwise, it changes
synchronously to the REFCLK.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of data bits from
received serial stream is performed by a Clock/Data Recovery
(CDR) block. The clock extraction function is performed by
high-performance embedded phase-locked loop (PLL) that
tracks the frequency of the incoming bit stream and aligns the
phase of the internal bit-rate clock to the transitions in the
selected serial data stream.
CDR accepts a character-rate (bit-rate * 16) reference clock
on the REFCLK input. This REFCLK input is used to ensure
that the VCO (within the CDR) is operating at the correct
frequency (rather than some harmonic of the bit-rate), to
improve PLL acquisition time, and to limit unlocked frequency
excursions of the CDR VCO when no data is present at the
serial inputs.
Regardless of the type of signal present, the CDR will attempt
to recover a data stream from it. If the frequency of the
recovered data stream is outside the limits set by the range
controls, the CDR PLL will track REFCLK instead of the data
stream. When the frequency of the selected data stream
returns to a valid frequency, the CDR PLL is allowed to track
the received data stream. The frequency of REFCLK is
required to be within ±100 ppm of the frequency of the clock
that drives the REFCLK signal of the remote transmitter to
ensure a lock to the incoming data stream.
For systems using multiple or redundant connections, the LFI
output can be used to select an alternate data stream. When
an LFI indication is detected, external logic can toggle
selection of the input device. When such a port switch takes
place, it is necessary for the PLL to reacquire lock to the new
serial stream.
External Filter
The CDR circuit uses external capacitors for the PLL filter. A
0.1-µF capacitor needs be connected between RXCN1 and
RXCP1. Similarly a 0.1-µF capacitor needs to be connected
between RXCN2 and RXCP2. The recommended packages
and dielectric material for these capacitors are 0805 X7R or
0603 X7R.
Deserializer
clocks these bits into the Deserializer at the bit-clock rate. The
Deserializer converts serial data into parallel data. RXD[15] is
the most significant bit of the output word and is received first
on the serial interface.
Loopback/Timing Modes
CYS25G0101DX supports various loopback modes, as
described below.
Facility Loopback (Line Loopback with Retiming)
When the LINELOOP signal is set HIGH, the Facility Loopback
mode is activated and the high-speed serial receive data (IN±)
is presented to the high-speed transmit output (OUT±) after
retiming. In Facility Loopback mode, the high-speed receive
data (IN±) is also converted to parallel data and presented to
the low-speed receive data output pins (RXD[15:0]). The
receive recovered clock is also divided down and presented to
the low-speed clock output (RXCLK).
Equipment Loopback (Diagnostic Loopback with Retiming)
When the DIAGLOOP signal is set HIGH, transmit data is
looped back to the RX PLL, replacing IN±. Data is looped back
from the parallel TX inputs to the parallel RX outputs. The data
is looped back at the internal serial interface and goes through
transmit shifter and the receive CDR. SD is ignored in this
mode.
Line Loopback Mode (Non-retimed Data)
When the LOOPA signal is set HIGH, the RX serial data is
directly buffered out to the transmit serial data. The data at the
serial output is not retimed.
Loop Timing Mode
When the LOOPTIME signal is set HIGH, the TX PLL is
bypassed and receive bit-rate clock is used for transmit side
shifter.
Reset Modes
ALL logic circuits in the device can be reset using RESET and
FIFO_RST signals. When RESET is set LOW, all logic circuits
except FIFO are internally reset. When FIFO_RST is set LOW,
the FIFO logic is reset.
Power-down Mode
CYS25G0101DX provides a global power-down signal
PWRDN. When LOW, this signal powers down the entire
device to a minimal power dissipation state. RESET and
FIFO_RST signals should be asserted LOW along with
PWRDN signal to ensure low power dissipation.
LVPECL Compliance
The CYS25G0101DX HSTL parallel I/O can be configured to
LVPECL compliance with slight termination modifications. On
the transmit side of the transceiver, the TXD[15:0] and TXCLKI
can be made LVPECL compliant by setting VREF (reference
voltage of a LVPECL signal) to VCC – 1.33V. To emulate an
LVPECL signal on the receiver side, VDDQ needs to be set to
3.3V and the transmission lines need to be terminated with the
Thévenin equivalent of Zο at LVPECL ref. The signal is then
attenuated using a series resistor at the driver end of the line
to reduce the 3.3V swing level to an LVPECL swing level (see
Figure 10). This circuit needs to be used on all 16 RXD[15:0]
pins, TXCLKO, and RXCLK. The voltage divider has been
calculated assuming the system is built with 50Ω transmission
lines.
The CDR circuit extracts bits from the serial data stream and
Document #: 38-02009 Rev. *J
Page 6 of 15
CYS25G0101DX
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
VCC Supply Voltage to Ground Potential ....... –0.5V to +4.2V
VDDQ Supply Voltage to Ground Potential ..... –0.5V to +4.2V
DC Voltage Applied to HSTL Outputs
in High-Z State .....................................–0.5V to VDDQ + 0.5V
DC Voltage Applied to Other Outputs
in High-Z State .......................................–0.5V to VCC + 0.5V
Power-up Requirements
Power supply sequencing is not required if you are configuring
VDDQ=3.3volts and all power supplies pins are connected to
the same 3.3 volt power supply.
Power supply sequencing is required if you are configuring
VDDQ=1.5volts. Power must be applied in the following
sequence: VCC (3.3) followed by VDDQ (1.5). Power supply
ramping may occur simultaneously as long as the VCC/VDDQ
relationship is maintained.
Operating Range
Output Current into LVTTL Outputs (LOW)..................30 mA
DC Input Voltage....................................–0.5V to VCC + 0.5V
Static Discharge Voltage ...........................................> 1100V
(per MIL-STD-883, Method 3015)
Ambient
Temperature
Range
VCC
1.4V to
1.6V[4]
3.3V ± 10%
–40°C to +85°C 1.4V to
1.6V[4]
3.3V ± 10%
Commercial
Industrial
VDDQ
0°C to +70°C
Latch-up Current .....................................................> 200 mA
Table 1. DC Specifications—LVTTL
Parameter
Description
Test Conditions
Min.
Max.
Unit
0.4
V
–20
–90
mA
LVTTL Outputs
VOHT
Output HIGH Voltage
VCC = Min., IOH = –10.0 mA
VOLT
Output LOW Voltage
VCC = Min., IOL = 10.0 mA
IOS
Output Short Circuit Current
VOUT = 0V
2.4
V
LVTTL Inputs
VIHT
Input HIGH Voltage
Low = 2.1V, High = VCC + 0.5V
2.1
VCC – 0.3
V
VILT
Input LOW Voltage
Low = –3.0V, High = 0.8
–0.3
0.8
V
IIHT
Input HIGH Current
VCC = Max., VIN = VCC
50
µA
IILT
Input LOW Current
VCC = Max., VIN = 0V
–50
µA
Input Capacitance
VCC = Max., @ f = 1 MHz
5
pF
Capacitance
CIN
Table 2. DC Specifications—Power
Parameter
Description
Test Conditions
Typ.
Max.
Unit
300
347
mA
5
mA
Min.
Max.
Unit
200
600
mV
Power
ICC1
Active Power Supply Current
ISB
Standby Current
Table 3. DC Specifications—Differential LVPECL Compatible Inputs (REFCLK) [5]
Parameter
Description
Test Conditions
VINSGLE
Input Single-ended Swing
VDIFFE
Input Differential Voltage
VIEHH
Highest Input HIGH Voltage
VIELL
Lowest Input LOW Voltage
IIEH
Input HIGH Current
VIN = VIEHH Max.
IIEL
Input LOW Current
VIN = VIELL Min.
400
1200
mV
VCC – 1.2
VCC – 0.3
V
VCC – 2.0
VCC – 1.45
V
750
µA
µA
–200
Capacitance
CINE
Input Capacitance
4
pF
Note:
5. See Figure 2 for differential waveform definition.
Document #: 38-02009 Rev. *J
Page 7 of 15
CYS25G0101DX
Table 4. DC Specifications—Differential CML[5]
Parameter
Description
Test Conditions
Min.
Max.
Unit
Transmitter CML-compatible Outputs
VOHC
Output HIGH Voltage (VCC Referenced)
100Ω differential load VCC – 0.5 VCC – 0.15
V
VOLC
Output LOW Voltage (VCC Referenced)
V
VDIFFOC
Output Differential Swing
100Ω differential load VCC – 1.2 VCC – 0.7
100Ω differential load
560
1600
mV
VSGLCO
Output Single-ended Voltage
100Ω differential load
280
800
mV
Receiver CML-compatible Inputs
VINSGLC
Input Single-ended Swing
25
1000
mV
VDIFFC
Input Differential Voltage
50
2000
mV
VICHH
Highest Input HIGH Voltage
VCC
V
VICLL
Lowest Input LOW Voltage
1.2
V
V (+ )
V SGL
V (-)
VD
V D IF F = V (+ )-V (-)
0 .0 V
Figure 2. Differential Waveform Definition
Table 5. DC Specifications—HSTL
Parameter
Description
Test Conditions
Min.
Max.
Unit
HSTL Outputs
VOHH
Output HIGH Voltage
VCC = min., IOH= –4.0 mA
VOLH
Output LOW Voltage
VCC = min., IOL= 4.0 mA
VDDQ – 0.4
0.4
V
V
IOSH
Output Short Circuit Current
VOUT = 0V
100
mA
HSTL Inputs
VIHH
Input HIGH Voltage
VILH
Input LOW Voltage
IIHH
Input HIGH Current
IILH
Input LOW Current
Input Capacitance
VDDQ = max., @ f = 1 MHz
VREF + 0.13 VDDQ + 0.3
–0.3
V
VREF – 0.1
V
VDDQ = max., VIN = VDDQ
50
µA
VDDQ = max., VIN = 0V
–40
µA
5
pF
Capacitance
CINH
Document #: 38-02009 Rev. *J
Page 8 of 15
CYS25G0101DX
AC Waveforms
VICHH
3.0V
3.0V
2.0V
Vth = 1.4V
2.0V
0.8V
GND
80%
Vth = 1.4V
0.8V
< 1 ns
20%
VICLL
< 150 ps
< 1 ns
(a) LVTTL Input Test Waveform
< 150 ps
(b) CML Input Test Waveform
VIHH
VIEHH
80%
80%
80%
Vth = 0.75V
80%
20%
Vth = 0.75V
20%
20%
VIHL
< 1 ns
80%
20%
20%
VIELL
< 1.0 ns
< 1 ns
< 1.0 ns
(d) LVPECL Input Test Waveform
(c) HSTL Input Test Waveform
AC Test Loads
1.5V
3.3V
R1
OUTPUT
R1 = 330Ω
R2 = 510Ω
CL ≤ 10 pF
(Includes fixture and
probe capacitance)
RL = 100Ω
OUT+
CL
R2
OUT–
(a) TTL AC Test Load
RL
OUTPUT
R1 = 100Ω
R2 = 100Ω
CL ≤ 7 pF
(Includes fixture and
probe capacitance)
(b) CML AC Test Load
R1
CL
R2
(c) HSTL AC Test Load
AC Specifications
Table 6. AC Specifications—Parallel Interface
Min.
Max.
Unit
tTS
Parameter
TXCLKI Frequency (must be frequency coherent to REFCLK)
Description
154.5
156.5
MHz
tTXCLKI
TXCLKI Period
6.38
6.47
ns
tTXCLKID
TXCLKI Duty Cycle
40
60
%
tTXCLKIR
TXCLKi Rise Time
0.3
1.5
ns
tTXCLKIF
TXCLKi Fall Time
0.3
1.5
ns
tTXDS
Write Data Set-up to ↑ of TXCLKI
1.5
ns
tTXDH
Write Data Hold from ↑ of TXCLKI
0.5
ns
tTOS
TXCLKO Frequency
154.5
156.5
MHz
tTXCLKO
TXCLKO Period
6.38
6.47
ns
tTXCLKOD
TXCLKO Duty Cycle
43
57
%
tTXCLKOR
TXCLKO Rise Time
0.3
1.5
ns
tTXCLKOF
TXCLKO Fall Time
0.3
1.5
ns
tRS
RXCLK Frequency
154.5
156.5
MHz
tRXCLK
RXCLK Period
6.38
6.47
ns
tRXCLKD
RXCLK Duty Cycle
43
57
%
Time[6]
tRXCLKR
RXCLK Rise
0.3
1.5
ns
tRXCLKF
RXCLK Fall Time[6]
0.3
1.5
ns
tRXDS
Recovered Data Set-up with reference to ↑ of RXCLK
2.2
ns
tRXDH
Recovered Data Hold with reference to ↑ of RXCLK
2.2
ns
tRXPD
Valid Propagation Delay
–1.0
Document #: 38-02009 Rev. *J
1.0
ns
Page 9 of 15
CYS25G0101DX
Table 7. AC Specifications—REFCLK[7]
Parameter
Description
Min.
Max.
Unit
tREF
REFCLK Input Frequency
154.5
156.5
MHz
tREFP
REFCLK Period
6.38
6.47
ns
tREFD
REFCLK Duty Cycle
tREFT
REFCLK Frequency Tolerance — (relative to received serial data)[8]
tREFR
tREFF
35
65
%
–100
+100
ppm
REFCLK Rise Time
0.3
1.5
ns
REFCLK Fall Time
0.3
1.5
ns
Max.
Unit
Table 8. AC Specifications–CML Serial Outputs
Parameter
Description
Min.
Typical
tRISE
CML Output Rise Time (20–80%, 100Ω balanced load)
60
170
ps
tFALL
CML Output Fall Time (80–20%, 100Ω balanced load)
60
170
ps
Table 9. Jitter Specifications
Parameter
tTJ-TXPLL
Description
Total Output Jitter for TX PLL (p-p)[9]
Typical[10] Max.[10]
Unit
0.03
0.04
Total Output Jitter for TX PLL (rms)
0.007
0.008
UI
Total Output Jitter for RX CDR PLL (p-p)[9]
0.035
0.05
UI
Total Output Jitter for RX CDR PLL (rms)[9, 11]
0.008
0.01
UI
[9, 11]
tTJ-RXPLL
Min.
UI
Notes:
6. RXCLk rise time and fall times are measured at the 20 to 80 percentile region of the rising and falling edge of the clock signal.
7. The 155.52 MHz Reference Clock Phase Noise Limits for the CYS25G0101DX are illustrated in Figure 5.
8. +20 ppm is required to meet the SONET output frequency specification.
9. The RMS and P-to-P jitter values are measured using a 12-KHz to 20-MHz SONET filter.
10. Typical values are measured at room temperature and the Max. values are measured at 0° C.
11. This device passes the Bellcore specification from -10° C to 85° C.
Document #: 38-02009 Rev. *J
Page 10 of 15
CYS25G0101DX
Jitter Waveforms
Figure 3. Jitter Transfer Waveform of CYS25G0101DX[12]
Figure 4. Jitter Tolerance Waveform of CYS25G0101DX[12]
Note:
12. The bench jitter measurements were performed using an Agilent Omni-bert SONET jitter tester.
Document #: 38-02009 Rev. *J
Page 11 of 15
CYS25G0101DX
CYS25G0101DX Reference Clock Phase Noise Limits
-75
-85
Phase Noise (dBc)
-95
-105
-115
-125
-135
-145
-155
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Frequency (Hz)
Figure 5. CYS25G0101DX Reference Clock Phase Noise Limits
Switching Waveforms
Transmit Interface Timing
tTXCLKI
tTXCLKIDH
tTXCLKIDL
TXCLKI
t TXDS tTXDH
TXD[15:0]
tTXCLKO
tTXCLKODL
tTXCLKODH
TXCLKO
Receive Interface Timing
tRXCLK
tRXCLKDL
tRXCLKDH
RXCLK
t RXPD
t RXDS
tRXDH
RXD[15:0]
Document #: 38-02009 Rev. *J
Page 12 of 15
CYS25G0101DX
Typical I/O Terminations
CYS25G0101DX
Limiting Amp
0.1 µ F
Zo=50 Ω
IN+
OUT+
100 Ω
OUT–
IN–
Zo=50 Ω
0.1 µF
Figure 6. Serial Input Termination
Optical Module
CY S25G0101DX
0.1 µ F
Zo=50 Ω
IN+
OUT+
100 Ω
OUT–
IN–
Zo=50 Ω
0.1 µF
Figure 7. Serial Output Termination[13]
CY S25G0101DX
FRAMER
VDDQ=1.5V
Zo=50 Ω
HSTL
OUTPU
T
100 Ω
HSTL
INPUT
100 Ω
Figure 8. TXCLKO/ RXCLK Termination
CY S25G0101DX
FRAMER
Zo=50 Ω
HSTL
OUTPU
T
HSTL
INPUT
Figure 9. RXD[15:0] Termination
VDDQ=3.3V
RXD[15;0],
RXCLK,
TXCLKO OUTPUT
FRAMER
VDDQ=3.3V
137 Ω
Zo=50 Ω
80.6Ω
LVPECL INPUT
121 Ω
CY S25G0101DX
Figure 10. LVPECL-compliant Output Termination
Clock Oscillator
Zo=50 Ω
LVPEC L
OUTPUT
130 Ω
82 Ω
Zo=50 Ω
CY S25G0101DX
VCC
82 Ω
0.1uF
VCC
130 Ω
0.1uF
Refcloc k I nter nall y
Biased
Figure 11. AC-Coupled Clock Oscillator Termination
Note:
13. Serial output of CYS25G0101DX is source matched to 50Ω transmission lines (100Ω differential transmission lines).
Document #: 38-02009 Rev. *J
Page 13 of 15
CYS25G0101DX
Clock Oscillator
Zo=50 Ω
LVPEC L
OUTPUT
CY S25G0101DX
VCC
130 Ω
82 Ω
VCC
130 Ω
Zo=50 Ω
82 Ω
Reference Cloc k Input
Figure 12. Clock Oscillator Termination
Ordering Information
Speed
Ordering Code
Package Name
Package Type
Operating Range
Standard
CYS25G0101DX-ATC
AT120
120-pin TQFP
Commercial
Standard
CYS25G0101DX-ATI
AT120
120-pin TQFP
Industrial
Package Diagram
120-pin Thin Quad Flatpack (14 × 14 × 1.4 mm) with Heat Slug AT120
51-85116-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-02009 Rev. *J
Page 14 of 15
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CYS25G0101DX
Document History Page
Document Title: CYS25G0101DX SONET OC-48 Transceiver
Document Number: 38-02009
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
105847
03/22/01
SZV
Change from Spec number: 38-00894 to 38-02009.
*A
108024
06/20/01
AMV
Changed Marketing part number.
*B
111834
12/18/01
CGX
Updated power specification in features and DC specs section. Changed
pinout to be compatible with CYS25G0102DX in pin diagram and descriptions. Verbiage added or changed for clarity in pin descriptions section.
Changed input sensitivity in Receive Data Path section, page 6. RXCLK rise
time corrected to 0.3 nSec min. CML and LVPECL input waveforms updated
in test load and waveform section. Diagrams replaced for clarity Figures 1-10.
Added two Refclock diagrams Figures 9 and 10.
*C
112712
02/06/02
TME
Updated temperature range, static discharge voltage, and max total RMS
jitter.
*D
113791
04/24/02
CGX
Updated the single ended swing and differential swing voltage for Receiver
CML compatible inputs. Created a separate table showing peak to peak and
RMS jitter for both TX PLL and RX PLL.
*E
115940
05/22/02
TME
Added Industrial temperature spec to pages 8, 11, and 15.
*F
117906
09/06/02
CGX
Added differential waveform definition.
Added BGA pinout and package information.
Changed LVTTL VIHT min. from 2.0 to 2.1 volts.
*G
119267
10/17/02
CGX
Added phase noise limits data.
Removed BGA pinout and package information.
Removed references to CYS25G0102DX.
*H
121019
11/06/02
CGX
Removed “Preliminary” from data-sheet
*I
122319
12/30/02
RBI
Add power up requirements to Maximum Ratings information
*J
124438
02/13/03
WAI
Revised power up requirements
Document #: 38-02009 Rev. *J
Page 15 of 15