CYPRESS CY62156ESL

CY62156ESL MoBL®
8-Mbit (512 K × 16) Static RAM
8-Mbit (512 K × 16) Static RAM
Features
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
in standby mode when deselected (CE1 HIGH or CE2 LOW). The
input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE1 HIGH or
CE2 LOW), the outputs are disabled (OE HIGH), Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or
a write operation is active (CE1 LOW, CE2 HIGH and WE LOW).
■
High Speed: 45 ns
■
Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■
Ultra Low Standby Power
❐ Typical standby current: 2 A
❐ Maximum standby current: 8 A
■
Ultra Low Active Power
❐ Typical active current: 1.8 mA at f = 1 MHz
■
Easy Memory Expansion with CE1, CE2, and OE Features
■
Automatic Power Down when Deselected
■
CMOS for Optimum Speed and Power
■
Available in Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) packages
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is
written into the location specified on the address pins (A0 through
A18). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A18).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See the Truth Table on page
11 for a complete description of read and write modes.
Functional Description
The CY62156ESL is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
512 K × 16
RAM Array
I/O0–I/O7
I/O8–I/O15
•
BHE
WE
CE
OE
BLE
A18
A17
A15
A16
A13
A14
A11
Cypress Semiconductor Corporation
Document Number: 001-54995 Rev. *D
A12
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 13, 2013
CY62156ESL MoBL®
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 001-54995 Rev. *D
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Page 2 of 16
CY62156ESL MoBL®
Pin Configurations
Figure 1. 48-ball VFBGA pinout (Top View) [1]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
A17
A7
I/O3
VCC
D
NC
A16
I/O4
VSS
E
I/O14 I/O13 A14
A15
I/O5
I/O6
F
VSS I/O11
VCC
I/O12
I/O15
NC
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
NC
H
Product Portfolio
Power Dissipation
Product
CY62156ESL
VCC Range (V) [2]
Range
Industrial
2.2 V to 3.6 V and 4.5 V to 5.5 V
Speed
(ns)
45
Operating ICC, (mA)
f = 1MHz
f = fmax
Standby, ISB2
(A)
Typ [3]
Max
Typ [3]
Max
Typ [3]
Max
1.8
3
18
25
2
8
Notes
1. NC pins are not connected on the die.
2. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-54995 Rev. *D
Page 3 of 16
CY62156ESL MoBL®
Maximum Ratings
Output Current into Outputs (LOW) ............................ 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 °C to + 150°C
Ambient Temperature with
Power Applied ........................................ –55 °C to + 125 °C
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. > 2,001V
Latch Up Current ................................................... > 200 mA
Operating Range
Supply Voltage to Ground Potential ...............–0.5 V to 6.0 V
Device
Range
DC Voltage Applied to Outputs
in High Z State [4, 5] ........................................–0.5 V to 6.0 V
CY62156ESL
Industrial
DC Input Voltage [4, 5] ....................................–0.5 V to 6.0 V
Ambient
Temperature
VCC[6]
–40 °C to +85 °C 2.2 V to 3.6 V,
and
4.5 V to 5.5 V
Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
45 ns
Min
Typ [1]
Max
2.2 < VCC < 2.7
IOH = –0.1 mA
2.0
–
–
2.7 < VCC < 3.6
IOH = –1.0 mA
2.4
–
–
4.5 < VCC < 5.5
IOH = –1.0 mA
2.4
–
–
2.2 < VCC < 2.7
IOL = 0.1 mA
–
–
0.4
2.7 < VCC < 3.6
IOL = 2.1mA
–
–
0.4
4.5 < VCC < 5.5
IOL = 2.1mA
–
–
0.4
2.2 < VCC < 2.7
1.8
–
VCC + 0.3
2.7 < VCC < 3.6
2.2
–
VCC + 0.3
4.5 < VCC < 5.5
2.2
–
VCC + 0.5
2.2 < VCC < 2.7
–0.3
–
0.6
2.7 < VCC < 3.6
–0.3
–
0.8
Unit
V
V
V
V
4.5 < VCC < 5.5
–0.5
–
0.8
IIX
Input Leakage Current
GND < VI < VCC
–1
–
+1
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
–1
–
+1
A
ICC
VCC Operating Supply Current
f = fmax = 1/tRC
–
18
25
mA
–
1.8
3
f = 1 MHz
VCC = VCCmax,
IOUT = 0 mA,
CMOS levels
A
ISB1
Automatic CE Power down
Current – CMOS Inputs
CE1 > VCC 0.2 V, CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = VCC(max)
–
2
8
A
ISB2 [7]
Automatic CE Power down
Current – CMOS Inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
–
2
8
A
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
7. Only chip enables (CE1 and CE2) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 001-54995 Rev. *D
Page 4 of 16
CY62156ESL MoBL®
Capacitance
Parameter [8]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
10
pF
10
pF
Test Conditions
48-ball BGA
Unit
Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit
board
72
C/W
8.86
C/W
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Thermal Resistance
Parameter [8]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
VCC
OUTPUT
30 pF
VCC
10%
GND
R2 Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V TH
Parameters
2.5 V
3.0 V
5.0 V
Unit
R1
16667
1103
1800

R2
15385
1554
990

RTH
8000
645
639

VTH
1.20
1.75
1.77
V
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-54995 Rev. *D
Page 5 of 16
CY62156ESL MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
ICCDR
Conditions
VCC for Data Retention
[10]
CE1 > VCC – 0.2 V, CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
VCC = 1.5 V
Data Retention Current
Min
Typ [9]
Max
Unit
1.5
–
–
V
–
2
5
A
tCDR [11]
Chip Deselect to Data Retention
Time
0
–
–
ns
tR [12]
Operation Recovery Time
45
–
–
ns
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
CE1
or
CE2
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
10. Only chip enables (CE1 and CE2) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-54995 Rev. *D
Page 6 of 16
CY62156ESL MoBL®
Switching Characteristics
Over the Operating Range
Parameter [13]
Description
45 ns
Unit
Min
Max
45
–
ns
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
–
45
ns
tOHA
Data Hold from Address Change
10
–
ns
tACE
CE1 LOW and CE2 HIGH to Data Valid
–
45
ns
tDOE
OE LOW to Data Valid
–
OE LOW to Low Z[14]
5
–
22
–
ns
tLZOE
18
–
ns
18
–
ns
45
ns
22
–
ns
18
ns
45
–
ns
ns
ns
Z[14, 15]
tHZOE
OE HIGH to High
tLZCE
CE1 LOW and CE2 HIGH to Low Z[14]
Z[14, 15]
10
–
tHZCE
CE1 HIGH and CE2 LOW to High
tPU
CE1 LOW and CE2 HIGH to Power Up
tPD
CE1 HIGH and CE2 LOW to Power Down
0
–
tDBE
BLE/BHE LOW to Data Valid
–
tLZBE
BLE/BHE LOW to Low
Z[14]
tHZBE
BLE/BHE HIGH to High Z[14, 15]
[16]
Write Cycle
tWC
Write Cycle Time
5
–
ns
ns
ns
ns
tSCE
tAW
CE1 LOW and CE2 HIGH to Write End
Address Setup to Write End
35
35
–
tHA
tSA
Address Hold from Write End
Address Setup to Write Start
0
0
–
–
ns
ns
tPWE
WE Pulse Width
35
–
ns
tBW
tSD
BLE/BHE LOW to Write End
Data Setup to Write End
35
25
–
–
ns
ns
tHD
Data Hold from Write End
0
–
ns
Z[14, 15]
–
18
–
ns
tHZWE
WE LOW to High
tLZWE
WE HIGH to Low Z[14]
10
–
ns
Notes
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels
of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5.
14. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
15. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
16. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write
and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates
the write.
Document Number: 001-54995 Rev. *D
Page 7 of 16
CY62156ESL MoBL®
Switching Waveforms
Figure 4. Read Cycle No. 1: Address Transition Controlled [17, 18]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2: OE Controlled [18, 19]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes
17. The device is continuously selected. OE, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH.
18. WE is HIGH for read cycle.
19. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document Number: 001-54995 Rev. *D
Page 8 of 16
CY62156ESL MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No 1: WE Controlled [20, 21, 22]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tHD
tSD
DATA I/O
NOTE 23
VALID DATA
tHZOE
Figure 7. Write Cycle 2: CE Controlled [20, 21, 22]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 23
tHD
VALID DATA
tHZOE
Notes
20. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write
and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the
write.
21. Data I/O is high impedance if OE = VIH.
22. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
23. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-54995 Rev. *D
Page 9 of 16
CY62156ESL MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle 3: WE controlled, OE LOW [24]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATA I/O
NOTE 25
tHD
VALID DATA
tLZWE
tHZWE
Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW [24]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 25
tHD
VALID DATA
Notes
24. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
25. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-54995 Rev. *D
Page 10 of 16
CY62156ESL MoBL®
Truth Table
CE1
CE2
WE
OE
BHE
BLE
H
X
X
X
X
X
X
L
X
X
X
X
L
H
X
X
H
L
H
H
L
L
L
H
H
L
L
H
H
L
L
H
H
L
H
H
L
H
L
H
L
L
Mode
Power
High Z
Deselect/Power Down
Standby (ISB)
High Z
Deselect/Power Down
Standby (ISB)
H
High Z
Output Disabled
Active (ICC)
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
H
L
Data Out (I/O0–I/O7);
High Z (I/O8–I/O15)
Read
Active (ICC)
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
H
L
H
High Z
Output Disabled
Active (ICC)
H
H
L
High Z
Output Disabled
Active (ICC)
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
H
L
X
H
L
Data In (I/O0–I/O7);
High Z (I/O8–I/O15)
Write
Active (ICC)
H
L
X
L
H
High Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC)
Document Number: 001-54995 Rev. *D
Inputs/Outputs
Page 11 of 16
CY62156ESL MoBL®
Ordering Information
Speed
(ns)
45
Ordering Code
CY62156ESL-45BVXI
Package
Diagram
Package Type
51-85150 48-ball VFBGA (Pb-free)
Operating
Range
Industrial
Ordering Code Definitions
CY 621 5
6
E
SL -
45 BV
X
I
Temperature Range:
I = Industrial
Pb-free
Package Type:
BV = 48-ball VFBGA
Speed Grade: 45 ns
Low Power
Process Technology: E = 90 nm
Buswidth: 6 = × 16
Density: 5 = 8-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-54995 Rev. *D
Page 12 of 16
CY62156ESL MoBL®
Package Diagrams
Figure 10. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-54995 Rev. *D
Page 13 of 16
CY62156ESL MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
chip enable
CMOS
complementary metal oxide semiconductor
°C
degree Celsius
I/O
input/output
MHz
megahertz
OE
output enable
µA
microampere
RAM
random access memory
µs
microsecond
SRAM
static random access memory
mA
milliampere
VFBGA
very fine-pitch ball grid array
mm
millimeter
WE
write enable
ns
nanosecond
Document Number: 001-54995 Rev. *D
Symbol
Unit of Measure

ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 14 of 16
CY62156ESL MoBL®
Document History Page
Document Title: CY62156ESL MoBL®, 8-Mbit (512 K × 16) Static RAM
Document Number: 001-54995
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
2751673
VKN
08/13/09
New data sheet
*A
2899866
AJU
03/26/10
Removed inactive parts from Ordering Information.
Updated Package Diagram
*B
3109032
AJU
12/13/2010
Obsolete document.
*C
3903222
AJU
02/19/2013
Changed from Obsolete to Active.
Description of Change
Removed all references of TSOP packages across the document and added
48-ball VFBGA package related information in the corresponding places.
Updated Features.
Updated Functional Description.
Updated Logic Block Diagram.
Updated Ordering Information (Updated part numbers) and added Ordering
Code Definitions.
Updated Package Diagrams:
Removed spec 51-85087 and spec 51-85183.
Added spec 51-85150.
Added Acronyms and Units of Measure.
Updated in new template.
*D
3996550
MEMJ
Document Number: 001-54995 Rev. *D
05/13/2013
Changed status from Preliminary to Final.
Page 15 of 16
CY62156ESL MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2009-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-54995 Rev. *D
Revised May 13, 2013
Page 16 of 16
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective
holders.