DS90LT012AQ Automotive LVDS Differential Line Receiver General Description Features The DS90LT012AQ is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise, and high data rates. The devices are designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Swing (LVDS) technology The DS90LT012AQ accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The DS90LT012AQ includes an input line termination resistor for point-to-point applications. The DS90LT012AQ and companion LVDS line driver DS90LV011AQ provide a new alternative to high power PECL/ECL devices for high speed interface applications. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Connection Diagram Truth Table AECQ-100 Grade 1 -40 to +125°C temperature range operation Compatible with ANSI TIA/EIA-644-A Standard >400 Mbps (200 MHz) switching rates 100 ps differential skew (typical) 3.5 ns maximum propagation delay Integrated line termination resistor (100Ω typical) Single 3.3V power supply design Power down high impedance on LVDS inputs LVDS inputs accept LVDS/CML/LVPECL signals Pinout simplifies PCB layout Low Power Dissipation (10mW typical@ 3.3V static) SOT-23 5-lead package INPUTS OUTPUT [IN+] − [IN−] TTL OUT VID ≥ 0V H VID ≤ −0.1V L Full Fail-safe OPEN/SHORT or Terminated H 30063926 (Top View) Order Number DS90LT012AQMF See NS Package Number MF05A Functional Diagram DS90LT012AQ 30063925 © 2009 National Semiconductor Corporation 300639 www.national.com DS90LT012AQ Automotive LVDS Differential Line Receiver July 29, 2009 DS90LT012AQ Maximum Junction Temperature ESD Rating HBM (Note 1) MM (Note 2) CDM (Note 3) Absolute Maximum Ratings (Note 4) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) −0.3V to +4V Input Voltage (IN+, IN−) −0.3V to +3.9V Output Voltage (TTL OUT) −0.3V to (VDD + 0.3V) Output Short Circuit Current −100mA Maximum Package Power Dissipation @ +25°C MF Package 794mW Derate MF Package 7.22 mW/°C above +25°C Package Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC) θJA 138.5°C/W θJC Lead Temperature Soldering (4 sec.) 107.0°C/W +135°C >8 kV >250V >1250V Note 1: Human Body Model, applicable std. JESD22-A114C Note 2: Machine Model, applicable std. JESD22-A115-A Note 3: Field Induced Charge Device Model, applicable std. JESD22-C101-C Recommended Operating Conditions Supply Voltage (VDD) Operating Free Air Temperature (TA) +260°C Min +3.0 Typ +3.3 Max +3.6 Units V −40 25 +125 °C Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 5, 6) Symbol Parameter Conditions VCM dependant on VDD Pin Min IN+, IN− Typ Max Units −30 0 mV VTH Differential Input High Threshold VTL Differential Input Low Threshold VCM Common-Mode Voltage VDD = 3.0V to 3.6V, VID = 100mV 0.10 2.35 V IIN Input Current VIN = +2.8V −10 ±1 +10 μA −10 ±1 +10 μA +20 μA 4.4 mA −100 VDD = 3.6V or 0V VIN = 0V VIN = +3.6V IIND Differential Input Current VDD = 0V −20 VIN+ = +0.4V, VIN− = +0V 3 VIN+ = +2.4V, VIN− = +2.0V RT Integrated Termination Resistor CIN Input Capacitance IN+ = IN− = GND VOH Output High Voltage IOH = −0.4 mA, VID = +200 mV 100 Ω 3 pF 2.4 3.1 V 2.4 3.1 V IOH = −0.4 mA, Inputs shorted 2.4 3.1 Output Low Voltage IOL = 2 mA, VID = −200 mV IOS Output Short Circuit Current VOUT = 0V (Note 7) VCL Input Clamp Voltage ICL = −18 mA IDD No Load Supply Current Inputs Open TTL OUT 3.9 mV IOH = −0.4 mA, Inputs terminated VOL www.national.com −30 VDD 2 V 0.3 0.5 V −15 −50 −100 mA −1.5 −0.7 5.4 V 9 mA Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 6, 8, 9, 10) Min Typ Max Units tPHLD Symbol Differential Propagation Delay High to Low Parameter CL = 15 pF Conditions 1.0 1.8 3.5 ns tPLHD Differential Propagation Delay Low to High VID = 200 mV 1.0 1.7 3.5 ns tSKD1 Differential Pulse Skew |tPHLD − tPLHD| (Note 11) (Figure 1 and Figure 2) 0 100 400 ps tSKD3 Differential Part to Part Skew (Note 12) 0 0.3 1.0 ns tSKD4 Differential Part to Part Skew (Note 13) 0 0.4 2.5 ns tTLH Rise Time 350 800 ps tTHL Fall Time 175 800 fMAX Maximum Operating Frequency (Note 14) 250 ps MHz Note 4: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 5: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified (such as VID). Note 6: All typicals are given for: VDD = +3.3V and TA = +25°C. Note 7: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. Note 8: These parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage, temperature) ranges. Note 9: CL includes probe and jig capacitance. Note 10: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0% to 100%) ≤ 3 ns for IN±. Note 11: tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel. Note 12: tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range. Note 13: tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. Note 14: fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.4V), load = 15 pF (stray plus probes). Parameter Measurement Information 30063903 FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit 30063904 FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms 3 www.national.com DS90LT012AQ Switching Characteristics DS90LT012AQ Typical Applications Balanced System 30063928 FIGURE 3. Point-to-Point Application (DS90LT012AQ) PC BOARD CONSIDERATIONS Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. Applications Information General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual (lit #550062-003), AN-808, AN-977, AN-971, AN-916, AN-805, AN-903. LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 3. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100Ω. The internal termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90LT012AQ differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0V to +2.4V (measured from each pin to ground). The device will operate for receiver input voltages up to VDD, but exceeding VDD will turn on the ESD protection circuitry which will clamp the bus voltages. DIFFERENTIAL TRACES Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result! (Note that the velocity of propagation, v = c/E r where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number of vias and other discontinuities on the line. Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. POWER DECOUPLING RECOMMENDATIONS Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended) 0.1μF and 0.001μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10μF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply and ground. www.national.com TERMINATION The DS90LT012AQ integrates the terminating resistor for point-to-point applications. The resistor value will be between 90Ω and 133Ω. THRESHOLD The LVDS Standard (ANSI/TIA/EIA-644-A) specifies a maximum threshold of ±100mV for the LVDS receiver. The DS90LT012AQ supports an enhanced threshold region of 4 0V, this small external fail-safe biasing of +25mV (with respect to 0V) gives a DNM of a comfortable 55mV. With the standard threshold region of ±100mV, the external fail-safe biasing would need to be +25mV with respect to +100mV or +125mV, giving a DNM of 155mV which is stronger fail-safe biasing than is necessary for the DS90LT012AQ. If more DNM is required, then a stronger fail-safe bias point can be set by changing resistor values. 30063929 FIGURE 4. VTC of the DS90LT012AQ LVDS Receiver Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100Ω. They should not introduce major impedance discontinuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. FAIL SAFE BIASING External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. Please refer to application note AN-1194, “Failsafe Biasing of LVDS Interfaces” for more information. PROBING LVDS TRANSMISSION LINES Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz) scope. Improper probing will give deceiving results. CABLES AND CONNECTORS, GENERAL COMMENTS When choosing cable and connectors for LVDS it is important to remember: 5 www.national.com DS90LT012AQ −100mV to 0V. This is useful for fail-safe biasing. The threshold region is shown in the Voltage Transfer Curve (VTC) in Figure 4. The typical DS90LT012AQ LVDS receiver switches at about −30mV. Note that with VID = 0V, the output will be in a HIGH state. With an external fail-safe bias of +25mV applied, the typical differential noise margin is now the difference from the switch point to the bias point. In the example below, this would be 55mV of Differential Noise Margin (+25mV − (−30mV)). With the enhanced threshold region of −100mV to DS90LT012AQ Pin Descriptions Package Pin Number SOT23 Pin Name Description 4 IN− Inverting receiver input pin 3 IN+ Non-inverting receiver input pin 5 TTL OUT 1 VDD Power supply pin, +3.3V ± 0.3V 2 GND Ground pin Receiver output pin Ordering Information www.national.com Operating Temperature Package Type/ Number Order Number −40°C to +125°C MF05A DS90LT012AQMF 6 DS90LT012AQ Physical Dimensions inches (millimeters) unless otherwise noted 5-Lead SOT23, JEDEC MO-178, 1.6mm Order Number DS90LT012AQMF NS Package Number MF05A 7 www.national.com DS90LT012AQ Automotive LVDS Differential Line Receiver Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Solutions www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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