ETC STK6031A

Preliminary data sheet
STK6031
8051-based
8-bit microcontroller
with
ISP-programmable 64K
flash progam memory
13761
755R
字 名人 13761755R
辨 名：CN = 13761755R, C =
CN, O = CCB, OU =
NET_BANK
原因：代理机 及 系方式：
MICRODIGITAL ELECTRONIC
LIMITED　麥道微電子技術有限公
司　光明 MP:
15899778870
日期：2007.09.26 18:14:22
+08'00'
DRAFT 2007
Apr 02
Syntek Semiconductors
1
STK6031
FEATURES
• 80C51 Central Processing Unit (CPU).
– Option for multiple CPU clock (XTAL1, XTAL1 x 2, or XTAL1 / 3.
– Industrial standard 80C51 instruction set.
– Normal mode, idle mode, and stop mode.
• Program Memory : 64 kbytes on-chip flash memory.
– with hardware ISP (In-System Programming).
– Program code protection.
• Main Data RAM: 256 bytes (upper 128 + lower 128 bytes) of on-chip SRAM.
• Aux Memory (AUX RAM): 768 bytes of SRAM.
• SFRs (Special Function Register): 46 SFRs.
• Timers: Timer 0, Timer 1, and Timer 2.
• On-chip Watchdog Timer.
• Full-duplex UART
• Five I/O ports: Port 0, Port 1, Port 2, Port 3, and Port 4 (P4.0 ~ P4.3).
• On-chip power-on-reset with low-voltage detection and reset.
• Interrupts: 6 sources, 2 priority level, 6 vectored addresses.
• Software enable/disable of ALE output pulse to reduce EMI.
• 4-channel, 6-bit ADC.
• 5-channel, 8-bit PWM.
• CPU operating frequency range: 2 to 30 MHz
• Operating temperature range: 0 to +70°C
• Operating voltage range: 2.7 to 3.6 V.
• ESD: ≥3 KV (HBM).
• Latch-up: 100 mA.
• Available in 3 types of Pb-free package: PLCC44, QFP44, LQFP48.
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STK6031
ORDERING INFORMATION
Table 1
Ordering information
TYPE NUMBER
PACKAGE
OUTLINE DRAWING
STK6031APLP
PLCC44 (Pb-free)
please contact Syntek
STK6031AQPP
QFP44 (Pb-free)
please contact Syntek
STK6031ALQP
LQFP48 (Pb-free)
please contact Syntek
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STK6031
FUNCTIONAL BLOCK DIAGRAM
ALE
PSEN
EA
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
Internal Bus
8051 CPU
Port 0
Program Flash
Memory (64K)
Port 2
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
Port 1
P1.0/PWM0/T2
P1.1/PWM1/T2EX
P1.2/PWM2
P1.3/PWM3
P1.4/PWM4
P1.5
P1.6
P1.7
Main Data Memory
(256 bytes)
ISP CONTROL
AUX Memory
(768 bytes)
P3.1/TXD
P3.0/RXD
Full-duplex
UART
P3.4/T0
P3.5/T1
Timer 0
Timer 1
Timer2
P3.2/INT0
P3.3/INT1
Interrupt
Control
P4.0/ ADC0
P4.1/ ADC1
P4.2 /ADC2
P4.3/ ADC3
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/ RD
Port 3
6-bit ADC
P1.0 / PWM0/T2
P1.1 /PWM1/T2EX
P1.2/ PWM2
P1.3/ PWM3
P1.4/ PWM4
data bus and
address bus for
external memory
access
P4.0/ ADC0
P4.1/ADC1
P4.2 /ADC2
P4.3/ ADC3
Port 4
8-bit PWM
Watchdog timer
RST
Power-On-Reset
Low-voltage detection
XTAL1
XTAL2
OSC
Fig.1 Functional block diagram
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STK6031
PINNING INFORMATION
4.1
Pinning diagram(QFP44 package)
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
P4.2/ADC2
P1.0/PWM0/T2
P1.1/PWM1/T2EX
P1.2/PWM2
P1.3/PWM3
P1.4/PWM4
34
35
36
37
38
39
40
41
42
43
44
P1.5
P1.6
P1.7
RST
P3.0/RXD/SCL
P4.3/ADC3
P3.1/TXD/SDA
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
1
2
3
4
5
6
7
8
9
10
11
STK6031
QFP44
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
P4.0/ADC0
VSS
XTAL1
XTAL22
P3.7/RD
P3.6/WR
Fig.2 Pin configuration of QFP44 package.
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5
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
P4.1/ADC1
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
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4.2
STK6031
Pinning diagram(LQFP48 package)
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
P4.2/ADC2
P1.0/PWM0/T2
P1.1/PWM1/T2EX
P1.2/PWM2
P1.3/PWM3
P1.4/PWM4
NC
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
10
11
P1.5
P1.6
P1.7
RST
P3.0/RXD/SCL
P4.3/ADC3
P3.1/TXD/SDA
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
NC
STK6031
LQFP48
12
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
NC
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
P4.0/ADC0
VSS
XTAL1
XTAL22
P3.7/RD
P3.6/WR
Fig.3 Pin configuration of LQFP48 version.
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6
NC
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
P4.1/ADC1
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
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4.3
STK6031
Pinning diagram(PLCC44)
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
P4.2/ADC2
P1.0/PWM0/T2
P1.1/PWM1/T2EX
P1.2/PWM2
P1.3/PWM3
P1.4/PWM4
40
41
42
43
44
1
2
3
4
5
6
P1.5
P1.6
P1.7
RST
P3.0/RXD/SCL
P4.3/ADC3
P3.1/TXD/SDA
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
7
8
9
10
11
12
13
14
15
16
17
STK6031
PLCC44
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
P4.0/ADC0
VSS
XTAL1
XTAL2
P3.7/RD
P3.6/WR
Fig.4 Pin configuration PLCC44 version.
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7
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
P4.1/ADC1
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
Syntek Semiconductors
4.4
STK6031
Pin description
Table 2 Pin description for QFP44 package
To avoid a latch-up effect at power-on: VSS − 0.5 V < voltage at any pin at any time < VDD + 0.5 V .
SYMBOL
PIN
TYPE
P1.5, P1.6, P1.7
1~3
I/O
RST
4
I
DESCRIPTION
Bits 5, 6, 7 of Port 1.
These pins are pure I/O pins.
External reset input pin, active HIGH.
A HIGH level on this pin for at least 8 XTAL1 clocks, while the oscillator is
running, resets the STK6031.
P3.0 / RXD / SCL
5
I/O
Bit 0 of Port 3, or data receiver pin of the UART, or clock pin for ISP
programming.
P4.3 / ADC3
6
I/O
Bit 3 of Port 4 or the third channel input of the 6-bit ADC.
P3.1 / TXD / SDA
7
I/O
Bit 1 of Port 3, data transmitter pin of the UART, or data pin for ISP progamming.
P3.2 / INT0
8
I/O
Bit 2 of Port 3 or input of External Interrupt 0.
P3.3 / INT1
9
I/O
Bit 3 of Port 3 or input of External interrupt 1.
P3.4 / T0
10
I/O
Bit 4 of Port 3 or timer/counter 0 input.
P3.5 / T1
11
I/O
Bit 5 of Port 3 or timer/counter 1 input.
P3.6 / WR
12
I/O
Bit 6 of Port 3 or external data memory (external AUX RAM) write strobe.
When selected as write strobe to external AUX RAM, the function of P3.6 is
disabled.
P3.7/RD
13
I/O
Bit 7 of Port 3, or external data memory (external AUX RAM) read strobe.
When selected as read strobe to external AUX RAM, the function of P3.7 is
disabled.
XTAL2
14
O
Crystal pin 2: output of the inverting amplifier that forms the oscillator. This pin
should be left open-circuit when an external oscillator clock is used.
XTAL1
15
I
Crystal pin 1: input to the inverting amplifier that forms the oscillator. Receives
the external oscillator clock signal when an external oscillator is used.
VSS
16
I
Ground pin.
P4.0 / ADC0
17
I/O
Bit 0 of Port 4 or channel 0 input of the 6-bit ADC.
P2.0/A8~
P2.7/A15
18~2
5
I/O
Port 2, or Address 8~15 when fetching external program ROM or AUX memory.
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have
1s written to them are pulled high by the internal pull-up PMOS and can be used
as inputs. As inputs, port 2 pins that are externally pulled low will source current
because of the internal pull-up PMOS.
Port 2 sends out the high-order address (A8 ~ A15) during fetches from external
program memory and during read/write access to external AUX memory, using
16-bit address lines (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s.
PSEN
26
O
Program Strobe Enable
This is read strobe to external program memory. When the CPU is executing
code coming from external program memory, PSEN is activated twice each
instruciton cycle. However, during each access to external data memory two
PSEN activations are skipped.
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STK6031
SYMBOL
PIN
TYPE
ALE
27
O
DESCRIPTION
Address Latch Enable
Output pulse for latching the low byte of the address during an access to
external memory. In normal operation, ALE is sent out at a constant rate of 1/4
oscillator frequency, and can be used for external clocking or timing. Note that
one ALE pulse is skipped during each access to external data memory.
The ALE output can be disabled by setting bit 3 (ALEDIS) of SFR CHIPCON at
location BF(hex) to HIGH. With this bit is set to HIGH, the pin is weakly pulled
high. The ALE disable feature is terminated by reset. Setting the ALEDIS bit has
no effect, if the CPU is in external memory access mode.
P4.1 / AD1
28
I/O
Bit 1 of Port 4 or channel 1 input of the on-chip ADC.
EA
29
I
External Access Enable.
If EA=0, the CPU fetches instruction from external (off-chip) program memory.
If EA=1, the CPU fetches instructions from internal (on-chip) program memory.
P0.0/AD0~
P0.7/AD7
30~3
7
I/O
Port 0, Address 0~7 or Data 0~7 when accessing external program/data
memory.
Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during access to
external program memory or AUX memory. In this application, it uses strong
internal pull-ups when emitting 1s.
VDD
38
P4.2 / ADC2
39
I/O
Power supply.
Bit 2 of Port 4 or channel 2 input of the 6-bit ADC.
P1.0/PWM0/T2
40
I/O
Bit 0 of Port 1, PWM0 output, or T2 input of Timer 2.
P1.1/PWM1/T2EX
41
I/O
Bit 1 of Port 1, PWM1 output, or T2EX input of Timer 2.
P1.2/PWM2,
P1.3/PWM3,
P1.4/PWM4
42,
43,
44
I/O
Bit 2, 3, 4 of Port 1 or outputs PWM 2, 3,4 of the Pulse Width Modulator.
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5
STK6031
REDUCING ELECTROMAGNETIC EMISSION
There are two recommended ways to reduce chip’s EMI emission: filtering and turning off ALE.
5.1
Filtering
Primary attention has been paid to the reduction of electromagnetic emission in the design of the STK6031. For example,
the internal clock routing has been carefully arranged and internal decoupling capacitance has been added. However, in
application, it is recommended that external capacitors should be connected across VDD and VSS pins. Lead length
should be as short as possible. Ceramic chip capacitors are recommended (100 nF).
5.2
Turning off ALE
For applications that require no external memory or temporarily no external memory: the ALE output (pulses at a
frequency of 1⁄4 × fOSC) can be disabled by setting CHIPCON.3= 1 (bit 3 of SFR CHIPCON at SFR address BF hex); if
disabled, no ALE pulse will occur. ALE pin will be weakly pulled high internally, switching an external address latch to a
quiet state. The MOVX instruction will still toggle ALE (when external Data Memory is accessed).
Additionally during internal access (EA = 1) ALE will toggle normally when the address exceeds the internal Program
Memory size. During external access (EA = 0) ALE will always toggle normally, without regard to if bit 3 of SFR CHIPCON
is set or not.
For detailed description of the SFR CHIPCON, please refer to Table 3 and Table 4.
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STK6031
CENTRAL PROCESSING UNIT (CPU)
6.1
Instruction Set and addressing modes
The STK6031’s instruction set and addressing modes are completely compatible with that of industrial standard 80C51.
User codes written in traditional 80C51 instruction set can be ported directly to the STK6031. Howerver, due to difference
in CPU instruction clocks, applications in which timer loops are used may need change in the number of loops.
6.2
CPU clock and Chip Configuration Register (SFR CHIPCON)
The STK6031 can be configured to run at different clock rates by use of bit 2 and bit 1 of the Chip Configuration Register
(SFR CHIPCON), as illustrated in Fig.5.
divided by 3
CPU clock control
0
CPU CLK
CPU CLK= XTAL1
0
1
CPU CLK= XTAL1 / 3.
1
1
CPU CLK= XTAL1 / 3.
1
0
CPU CLK= XTAL1 X 2.
X2
CPUCLK
CLKRATE
0
Fig.5 CPU clock
CPURATE
CPUCLK
multiplexer
XTAL1
The Chip Configuration Register (SFR CHIPCON, at SFR map address BF hex) controls the following:
• Enable or disable the on-chip AUX memory access,
• Enable or disable of the ALE output,
• CPU clock
• threshold voltage of low-power detecion
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11
CPU CLK
Syntek Semiconductors
Table 3
STK6031
Chip Configuration Register
Chip Configuraton Register (SFR CHIPCON), located at BF hex of the SFR map, Read/Write
Bit Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Mnemonics
x
x
x
XRAMEN
ALEDIS
CPUCLK
CLKRATE
LVR
Reset value
x
x
x
1
0
0
0
0
Table 4
Description of Chip Configuration Register (CHIPCON)
MNEMONIC
XRAMEN
BIT POSITION
FUNCTION
Bits 5, 6, 7
Not implemented.
CHIPCON.4
Enable or disable of the on-chip AUX memory access.
• XRAMEN= 1 enables the read/write access to the on-chip AUX memory.
• XRAMEN= 0 disable the read/write access to the address AUX memory.
ALEDIS
CHIPCON.3
Disable of the ALE output.
• When ALEDIS= 1, the ALE Disable is turned on, that is, the ALE output will not
toggle and EMI can be lowered.
• When ALEDIS= 0, the ALE output toggles.
CPUCLK
CHIPCON.2
CLKRATE
CHIPCON.1
This two bits are used to select the CPU clock rate. The CPU clock can be
selected to be XTAL1, XTAL1 ÷ 3, or XTAL1 x 2.
Please refer to Fig.5. for detail.
LVR
CHIPCON.0
Enable the low-voltage reset function.
• LVR= 0 enables the low-voltage reset function.
• LVR= 1 disables the low-voltage reset functon.
6.3
Instruciton Cycle
The following diagram illustrates the relation among system clock (CPU CLK), instruciton cycle, CPU cycle, and ALE.
Simple instructions can be executed in just one instruction cycle, which consists of 4 CPU clocks.
1
2
3
4
5
6
7
8
9
CPU CLK
instruction
cycle
cpu cycle
n+1
C1
C2
n+2
C3
C4
C1
C2
C3
C4
C1
ALE
Fig.6 CPU timing for single-cycle instruction.
6.4
Program Status Word
The current state of the CPU is reflected in the Program Status Word (PSW) register, which is located at SFR address
D0(hex).
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Table 5
STK6031
Program Status Word
PROGRAM STATUS WORD (SFR PSW), LOCATED AT D0H OF THE SFR MAP
Bit Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Mnemonics
CY
AC
F0
RS1
RS0
OV
F1
P
Table 6
Description of Program Status Word (PSW)
MNEMONIC
CY
BIT POSITION
PSW.7
FUNCTION
Carry flag.
The Carry flag receives Carry-out from bit 7 of ALU. It is set to HIGH, when last
arithmetic operation resulted in a carry (during addition) or borrow (during
subtraction); otherwise, it is cleared to LOW by all arithmetic operations.
AC
PSW.6
Auxiliary Carry Flag.
Auxiliary Carry Flag receives Carry-out from bit 3 of addition operands. It is set
to HIGH, when last arithmetic operation resulted in a carry into (during addition)
or borrow from (during subtraction) the high-order nibble; otherwise, it is cleared
to LOW by all arithmetic operations
F0
PSW.5
RS1, RS0
PSW.4,
PSW.3
General purpose flag.
This bit is uncommitted and may be used as general purpose status flag.
Register Bank select control bits.
• RS1, RS0 = 00 selects register bank 0, address 00h ~ 07h.
• RS1, RS0 = 01 selects register bank 1, address 08h ~ 0Fh.
• RS1, RS0 = 10 selects register bank 2, address 10h ~ 17h.
• RS1, RS0 = 11 selects register bank 3, address 18h ~ 1Fh.
OV
PSW.2
Overflow flag.
This bit is set to HIGH, when last arithmetic operation resulted in a carry
(addition), borrow (subtraction), or overflow (multiply or divide); otherwise, it is
cleared to LOW by all arithmetic operation.
F1
PSW.1
P
PSW.0
General purpose flag.
This bit is uncommitted and may be used as general purpose status flag.
Parity flag.
Set/Clear by hardware each instruction cycle to indicate an odd/even number of
1s in the accumulator, i.e., even parity.
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7
STK6031
MEMORY ORGANIZATION
The STK6031 has 4 blocks of on-chip memories. These are:
• 65536 bytes of flash program memory,
• 256 bytes of Main Data Memory,
• 768 bytes of AUX memory, and
• 53 bytes of Special Function Register.
The following diagram shows the overall memory spaces available in the microcontroller.
(1) The memory areas shown with dash lines are not
implemented on-chip.
(2) The area drawn for each memory block is not
proportional
l to its physical size.
65535
65535
FFFF(hex)
Internal
Program
ROM
Space
External
Program
ROM
Space
(on-chip)
(off-chip)
65535
External
AUX RAM
(off-chip)
768
767
Internal
AUX RAM
Main RAM
255
128 bytes
SFR
128 bytes
53 bytes
(on-chip)
128
127
0
0
(on-chip)
0
(on-chip)
Program Memory
on-chip Data Memory
External Data
Memory
Fig.7 The overall memory space
7.1
Program Memory
The STK6031 CPU fetches instructions either from the on-chip program memory or the off-chip program memory. For
both memories, the adddress range is from 0000(hex) to FFFF(hex).
If, during reset, the EA pin is held HIGH, the STK6031 always executes out of the on-chip Program Memory. If the EA
pin is held LOW during reset, the STK6031 fetches all instructions from the off-chip Program Memory. The EA input is
latched during reset and is ignored after reset. After reset, the CPU starts fetching program ROM code at location 0000H.
The on-chip program memory is implemented using flash memory, with ISP (In-System Programming) capability.
The off-chip memory is acceseed via Port 0 and Port 2.
The internal Program Memory content is protected by the software programmable security bit, i.e. it cannot be read out
at any time by any test mode or by any instruction in the external Program Memory space. The MOVC instructions are
the only ones which have access to program code in the internal or external Program Memory. The EA input is latched
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STK6031
during reset and is dont care after reset. This implementation prevents from reading internal program code by switching
from external Program Memory to internal Program Memory during MOVC instruction or an instruction that handles
immediate data. Table 5 lists the access to the internal and external Program Memory with MOVC instructions whether
the security feature has been activated or not.
Due to the maximum size of the internal Program Memory, the MOVC instructions can always operate either in the
internal or in the external Program Memory.
Table 7
Memory access by the MOVC instruction.
MOVC
INSTRUCTION
PROGRAM MEMORY ACCESS
INTERNAL
EXTERNAL
MOVC in internal
Program Memory
YES
NO(1)
MOVC in external
Program Memory
NO(1)
YES
Note
1. Not applicable due to 32 kbytes internal Program Memory.
Address=65535
(FFFFh)
Address=65535
(FFFFh)
External
Internal
( EA= 1 )
(EA= 0 )
Address=0
Address=0
Off-chip program memory,
(externally expandable)
on-chip program memory
(implemented on-chip)
Fig.8 Program Memory.
7.2
Main Data RAM and Special Function Register (SFR)
The STK6031 has 256 bytes of on-chip Main Data RAM and 53 bytes of SFR. Although the Main Data RAM and the
SFRs shares overlapped memory space, they are two physically separate blocks. The upper 128 bytes of the Main Data
RAM, from address 80H to FFH can be accessed only by Indirect Addressing. The lower 128 bytes of the Main RAM,
from address 00H to 7FH, can be accessed by Direct Addressing or Indirect Addressing.
The SFRs occupy the address range from 80H to FFH and are only accessible using Direct Addressing.
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STK6031
Lower 128 bytes
of Main Data RAM
7Fh
Indirect addressing
only
Direct RAM
Direct addressing
only
FF(hex)
upper
128 bytes
30h
2Fh
80(hex)
Bit-Addressable
Registers
20h
1Fh
18h
17h
10h
0Fh
08h
07h
00h
SFR
7F(hex)
lower
128 bytes
Bank 3
Direct or indirect
addressing
00(hex)
Bank 2
Main Data RAM
Bank 1
Bank 0
PSW SFR
7.3
Bit 4
Bit 3
1
1
active bank
3
1
0
2
0
1
1
0
0
0
Fig.9 Main Data Memory and SFRs
The lower 128 bytes of the Main Data RAM
The lower 128 bytes are organized as shown in Fig.9. The lower 32 bytes form 4 banks of eight registers (R0 - R7). Two
bits on the Program Status Word (PSW) select which bank is active (in use). The next 16 bytes, from 20 (hex) to 2F (hex)
, form a block of bit-addressable memory space, at bit address 00(hex) ~ 07(hex).
7.4
AUX Memory
The STK6031 has 64K-byte auxiliary memory (AUX RAM) space, which can be accessed by executing MOVX
instruction. The AUX RAM space is physically divided into two blocks: the on-chip block and the off-chip block. The
on-chip block has a capacity of 768 bytes and starts from address 0 to address 767(decimal). The off-chip block starts
from address 768(decimal) to address 65535.
The MOVX @Ri instruction, where i=0 or 1, can access only the lowest 256-bytes of the on-chip AUX RAM. The MOVX
@DTPR instruction can access the whole range of the AUX RAM space. When executing MOVX instruction from internal
program memory, an access (read or write) to the internal AUX RAM will not affect the status of Port 0, Port 2, P3.6(write)
and P3.7.(read)
AUX RAM space from address 768 to address 65535 is allocated as external AUX RAM and can only be accessed by
the MOVX @DPTR instruction. The external AUX RAM is externally expandable, with Port 0 used as low-byte
address/data, Port 2 used as high-byte address, P3.6 used as Write strobe, and P3.7 used as Read strobe.
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Syntek Semiconductors
STK6031
Total AUX Memory Space
65535
Externally
expandable
768
767
0
7.4.1
on-chip
AUX memory
Fig.10 The AUX Memory Spae
ON-CHIP AUX MEMORY
The on-chip AUX RAM from address 0 to address 767 can be accessed by the CPU as normal data memory. Read/Write
access to this memory can be disabled by setting bit 4 of the SFR CHIPCON to LOW.
Please refer to Table 3 and Table 4 for a detailed description of the SFR CHIPCON.
7.4.2
DUAL DATA POINTER (DATA POINTER 0 AND DATA POINTER 1) AND DPTR SELECT REGISTER (SFR DPS)
The STK6031 has two data pointers, Data Pointer 0 and Data Pointer 1. Data Pointer 0 is the traditional 8051 data pointer
for MOVX instrucitons. Data Pointer 1 is an extra data pointer for fast moving a block of data. Before executing a MOVX
instruction, an active data pointer must be selected by programming the Data Pointer Select Register (SFR DPS). Please
refer to Table 8 for detailed description of SFR DPS.
Table 8
Address
(Hex)
Data Pointer 0, Data Pointer 1, and DPTR Select Register
DESCRIPTION
Reset Value
R/W
SYMBOLS
82
R/W
DPL0
Data Pointer 0 Low (traditional 80C51 data pointer)
0000 0000
83
R/W
DPH0
Data Pointer 0 High (traditional 80C51 data pointer)
0000 0000
84
R/W
DPL1
Data Pointer 1 Low (extra data pointer), specific to the
STK6031.
0000 0000
85
R/W
DPH1
Data Pointer 1 High (extra data pointer), specific to the
STK6031.
0000 0000
86
R/W
DPS
DPTR Select Register (DPS), specific to the STK6031.
0000 0000
The DPS register has only one bit. Only its bit 0, called SEL bit,
is implemented on-chip. When SEL=0, instructions that use the
DPTR will use SFR DPL0 and SFR DPH0. When SEL=1,
instructions that use the DPTR will use SFR DPL1 and
SFR DPH1.
Bits 7~1 of SFR DPS can not be written to, and, when read,
always return a 0 for any of these 7 bits.
All DPTR-related instrucitons use the currently selected data pointer. To switch the active pointer, toggle the SEL bit, by
use of the instruciton INCS DPS. The 6 instructions that use the DPTR are given in the following table. An active DPTR
must be selected before executing these intructions.
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Syntek Semiconductors
Table 9
STK6031
Instructions that use the DPTR
INSTRUCITON
DESCRIPTION
INC DPTR
Increment the data pointer by1.
MOV DPTR, #data16
Load the DPTR with a 16-bit constant.
MOV A, @ A+DPTR
Move code byte relative to DPTR to Accumulator (ACC).
MOVX A, @DPTR
Move AUX Memory byte (16-bit address) to Accumulator (ACC)
MOVX @DPTR, A
Move ACC to AUX memory byte.
JMP @ A+DPTR
Jump indirect relative to DPTR.
7.4.3
STRETCH MEMORY CYCLES FOR ACCESSING EXTERNAL AUX MEMORY AND CLOCK CONTROL REGISTER
By default (after a reset), the MOVX instruction is executed in 3 instruciton cycles. However, it is possible to shorten or
lengthen, dynamically by user program, the instruction cycles needed to execute a MOVX instruction, by use of the M2,
M1, and M0 bits of the Clock Control Register (SFR CKCON).
The added extra cycles affects the width of the read/write strobe and all related timing. Using a higher stretch value
results in a wider read/write strobe, which then allows the memory more time to respond.
Table 10 and Table 11 give decription of the Clock Control Register and Table 12 gives decription about the stretched
cycles for various values of M2, M1, and M0.
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STK6031
Table 10 Clock Control Register, SFR CKCON
Clock Control Register (SFR CKCON), located at 8E(hex) of the SFR map
Bit Address
Bit 7
Mnemonics
Reserved
Bit 6
Reset value
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T2M
T1M
T0M
MD2
MD1
MD0
0
0
0
0
0
1
Table 11 Description of the CKCON Register
BIT
POSITION
MNEMONIC
T2M
FUNCTION
CKCON.5
Select Timer 2 clock frequecny.
When T2M= 0, Timer 2 uses (XTAL / 12) as clock frequency.
When T2M= 1, Timer 2 uses (XTAL1 / 4) as clock frequency.
T1M
CKCON.4
Select Timer 1 clock frequecny.
When T1M= 0, Timer 1 uses (XTAL1 / 12) as clock frequency.
When T1M= 1, Timer 1 uses (XTAL1 / 4) as clock frequency.
T0M
CKCON.3
Select Timer 0 clock frequecny.
When T0M= 0, Timer 0 uses (XTAL1 / 12) as clock frequency.
When T0M= 1, Timer 0 uses (XTAL / 4) as clock frequency.
M2
CKCON.2
M1
CKCON.1
M0
CKCON.0
Control the number of cycles to be used for accessing external AUX memory, using the
MOVX instruction.
Table 12 Data Memory Stretch Values
Read/Write
Strobe Width
(XTAL1)
Strobe Width
Time @25 MHz
2
2
80 ns
3 (default)
4
160 ns
0
4
8
320 ns
1
5
12
480 ns
0
0
6
16
640 ns
1
0
1
7
20
800 ns
1
1
0
8
24
960 ns
1
1
1
9
28
1120 ns
MD2
MD1
MD0
0
0
0
0
0
1
0
1
0
1
1
INTRUCTION
CYCLES
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Syntek Semiconductors
8
STK6031
SPECIAL FUNCTION REGISTERS
8.1
SFR Map Overview
The STK6031 has 46 bytes of SFRs implemented on-chip.
Address
(Hex)
DESCRIPTION
Reset Value
R/W
SYMBOLS
80
R/W
P0
Port 0 output latch (bit-addressable).
1111 1111
81
R/W
SP
Stack Pointer
0000 0111
82
R/W
DPL0
Data Pointer 0 Low (traditional 80C51 data pointer)
0000 0000
83
R/W
DPH0
Data Pointer 0 High (traditional 80C51 data pointer)
0000 0000
84
R/W
DPL1
Data Pointer 1 Low (extra data pointer), specific to the
STK6031.
0000 0000
85
R/W
DPH1
Data Pointer 1 High (extra data pointer), specific to the
STK6031.
0000 0000
86
R/W
DPS
DPTR Select Register (DPS), specific to the STK6031.
0000 0000
87
R/W
PCON
Power Control Register.
0011 0000
88
R/W
TCON
Timer0/1 Control Register (bit-addressable)
0000 0000
89
R/W
TMOD
Timer0/1 Mode Register
0000 0000
8A
R/W
TL0
Timer0, Low byte
0000 0000
8B
R/W
TL1
Timer1, Low byte
0000 0000
8C
R/W
TH0
Timer0, High byte
0000 0000
8D
R/W
TH1
Timer1, High byte
0000 0000
8E
R/W
CKCON
Clock Control register, specific to the STK6031.
0000 0001
The register is for controlling the frequency of the clock added
to Timer 0, Timer 1, and Timer 2, and memory stretch cycle for
the MOVX instruction.
8F
not used.
90
R/W
P1
Port 1 output latch (bit-addressable).
1111 1111
91, 92, 93, 94, 95, 96, 97, not used.
98
R/W
SCON0
Serial Port Control/Status Register 0(bit-addressable)
0000 0000
99
R/W
SBUF0
Serial Port Buffer Register 0
0000 0000
Port 2 output latch (bit-addressable )
1111 1111
Interrupt Enable Register (bit-addressable)
0000 0000
9A, 9B, 9C, 9D, 9E, 9F not used
A0
R/W
P2
A1, A2, A3, A4, A5, A6, A7 not used.
A8
R/W
IE
A9, AA, AB, AC, AD, AE, AF not used.
B0
R/W
P3
Port 3 output latch (bit-addressable)
1111 1111
B1, B2, B3, B4, B5, B6, B7, not used.
B8
R/W
IP
Interrupt Priority Register (bit-addressable)
1000 0000
B9, BA, BB, BC, BD, BE, not used.
BF
R/W
CHIPCON
Chip Configuration Register
xxx1 0000
C0
R/W
P4
Port 4 output latch.
1111 1111
C1, C2, C3, C4, C5, C6, C7, not used.
C8
R/W
T2CON
Timer 2 Control Register (bit-addressable)
C9 not used.
DRAFT 2007 Apr 02
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0000 0000
Syntek Semiconductors
STK6031
Address
(Hex)
R/W
SYMBOLS
CA
R/W
RCAP2L
Timer 2 Reload Capture Register, Low byte
0000 0000
CB
R/W
RCAP2H
Timer 2 Reload Capture Register, High byte
0000 0000
CC
R/W
TL2
Timer 2, Low byte
0000 0000
CD
R/W
TH2
Timer 2, High byte
0000 0000
DESCRIPTION
Reset Value
CE, CF not used.
D0
R/W
PSW
Program Status Word Register (bit-addressable)
0000 0000
D1
R/W
P1_OPT
Selecting Port 1 pin function, as normal port pin or PWM
output.
xxx0 0000
D2
R/W
PWM0D
Pulse width modulation, channel 0
1000 0000
D3
R/W
PWM1D
Pulse width modulation, channel 1
1000 0000
D4
R/W
PWM2D
Pulse width modulation, channel 2
1000 0000
D5
R/W
PWM3D
Pulse width modulation, channel 3
1000 0000
D6
R/W
PWM4D
Pulse width modulation, channel 4
1000 0000
D7, D8 not used.
D9
P4_OPT
Selecting Port 4 pin function, as normal port pin or ADC input.
DA
R/W
ADCSE
Configuring P4.0 ~ P4.3 pins as ADC input pins.
0xxx 0000
DB
R
ADCVAL
Buffer for storing the converted digital value of the 6-bit ADC.
xx00 0000
DD
P0_OPT
Port 0 pin option for normal I/O or external memory
address/data.
1111 1111
DE
P2_OPT
Port 2 pin option for normal I/O or external memory address.
1111 1111
DC, not used.
DF not used
E0
R/W
ACC
Accumulator (bit-addressable)
0000 0000
E1
R/W
WDT
Watchdog Timer Control.
00xx x000
E2
R/W
ISPSLV
ISP Control Slave address
0000 0000
E3
R/W
ISPEN
ISP Enable register (write 93hex to enable the ISP mode)
0000 0000
B
B Register (bit-addressable)
0000 0000
E4 ~EF not used.
F0
R/W
F1 ~ FF not used.
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8.2
STK6031
SFR of Each Functional Block
Table 13 SFR of each functional block
BLOCK
SYMBOL
NAME
Address
(Hex format)
CPU
ACC
Accumulator.
E0
0000 0000
B
B register
F0
0000 0000
SP
Stack Pointer
81
0000 0111
DPL0
Data Pointer 0, Low byte
82
0000 0000
DPH0
Data Pointer 0, High byte
83
0000 0000
DPL1
Data Pointer 1, Low byte
84
0000 0000
DPH1
Data Pointer 1, High byte
85
0000 0000
DPS
Selection for active Data Pointer
86
0000 0000
PCON
Power Control Register
87
0011 0000
PSW
Program Status Word
D0
0000 0000
CHIPCON
Chip Configuration Register
BF
xxx1 0000
IE
Interrupt Enable Register
A8
0000 0000
IP
Interrupt Priority Register
B8
x000 0000
P0
Port 0 latch
80
1111 1111
P0_OPT
Port 0 pin option for I/O or external memory
access
DD
1111 1111
P1
Port 1 latch
90
1111 1111
P1_OPT
Port 1 pin option for I/O or PWM outputs
D1
xxx0 0000
P2
Port 2
A0
1111 1111
P2_OPT
Port 2 pin option for I/O or external memory
access
DE
1111 1111
P3
Port 3 latch
B0
1111 1111
P4
Port 4 latch
C0
xxxx 1111
P4_OPT
Port 4 pin option for I/O or ADC inputs
D9
xxxx 0000
SBUF0
Serial Port Buffer Register
99
???? ????
SCON0
Serial Port Control/Status Register
98
0000 0000
TCON
Timer 0/1 Control Register
88
0000 0000
TMOD
Timer 0/1 Mode Register
89
0000 0000
TL0
Timer 0, Low byte
8A
0000 0000
TL1
Timer 1, Low byte
8B
0000 0000
TH0
Timer 0, High byte
8C
0000 0000
TH1
Timer 1, High byte
8D
0000 0000
T2CON
Timer 2 Control Register
C8
0000 0000
RCAP2L
Timer 2 Reload Capture Register, Low byte
CA
0000 0000
RCAP2H
Timer 2 Reload Capture Register, High byte CB
0000 0000
TL2
Timer 2, Low byte
CC
0000 0000
TH2
Timer 2, High byte
CD
0000 0000
WDT
Watchdog Timer Control Register
E1
00xx x000
Interrupt System
Ports
UART
Timer 0 / Time 1
Timer 2
Watchdog Timer
DRAFT 2007 Apr 02
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RESET
VALUE
Syntek Semiconductors
STK6031
BLOCK
SYMBOL
NAME
Address
(Hex format)
PWM
P1_OTP
Port 1 pin selection for PWM outputs
D1
xxx0 0000
PWM0D
PWM0 width
D2
1000 0000
PWM1D
PWM1 width
D3
1000 0000
PWM2D
PWM2 width
D4
1000 0000
PWM3D
PWM3 width
D5
1000 0000
PWM4D
PWM4 width
D6
1000 0000
P4_OPT
Selet Port 4 pin function
D9
xxxx 0000
ADCSEL
Select ADC input channel for conversion
DA
0xxx 0000
ADCVAL
Buffer for converted ADC value.
DB
xx00 0000
ISPSLV
ISP Control slave address
E2
0000 0000
ISPEN
Write 93 (hex) to enable the ISP mode
E3
0000 0000
ADC
ISP
DRAFT 2007 Apr 02
23
RESET
VALUE
Syntek Semiconductors
9
STK6031
PORT 0, PORT 1, PORT 2, PORT 3, AND PORT 4
9.1
General Description
The STK6031 has 4 8-bits ports (Ports 0 ~ 3)and one 4-bit port (Port 4). All bits of Port 0 are open-drain. All bits of Port
1, Port 2, Port 3 and Port 4 are quasi-bidirectional I/O ports.
9.2
Bi-directional I/O pins
Figure 11 shows the pull-up arrangements of Ports 1 to 4; Transistor 1 is turned on for 2 oscillator periods after Q makes
a HIGH-to-LOW transition. During this time, I1 also turns on P3 through the inverter to form an additional pull-up.
.
strong pull-up
k, full pagewidth
VDD
2 oscillator
periods
p2
p3
p1
I/O PIN
Q
from port latch
n
I1
input data
INPUT
BUFFER
read port pin
MLC926 - 1
Fig.11 I/O buffers in the STK6031 (Port 1 to Port 4).
9.3
MOVX instruction, Port 0, Port 2, P3.6, P3.7
When executing MOVX instruction from internal program memory, an access to the internal AUX RAM will not affect Port
0, Port 2, P3.6 and P3.7.
9.4
Multiple-Function Port Pins
Some port pins have multiple functions. Port pins which are not used for alternate functions may be used as normal
bidirectional I/O pins. The configuration of a port pin as an alternate function is carried out automatically by writing the
associated SFR bit with proper value.
Please refer to Table 2 for a detailed decription of multiple-function pins.
DRAFT 2007 Apr 02
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Syntek Semiconductors
STK6031
10 TIMER 0, TIMER 1
10.1
General Description
The microcontroller has two timer/counter, called Timer 0 and Timer 1. Timer 0 composes of SFR TH0 and SFR TL0.
Timer 1 composes of SFR TH1 and SFR TL1.
The mode and operation of Timer 0 and Timer1 are controlled by two SFRs, TMOD and TCON. TMOD is called Timer0/1
mode register and is located at address 89H of the SFR space. TCON is called Timer0/1 control register and is located
at 88H of the SFR space.
Timer0 and Timer1 can be programmed to carry out the following functions:
• Measure time intervals and pulse durations,
• Count events, and
• Generate interrupt request.
Both Timer 0 and Timer 1 can be programmed to be a timer or a counter by programming the TMOD.6 bit or the TMOD.2
bit of SFR TMOD.
10.2
Timer Function
In the timer function, Timer 0 and Timer 1 are incremented every machine cycle. Since each machine cycle consists of
12 oscillator clocks, the counting rate is 1/12 of the external crystal oscillator frequency.
10.3
Counter Function
In the counter function, Timer 0 and Timer 1 are incremented in response to a HIGH-to-LOW transition at their
corresponding input pins, P34/T0 and P35/T1. In this function, the external input is sampled during S5P2 of every
machine cycle. When the sampling action shows a HIGH in one machine cycle and a LOW in the next machine cycle,
the counter is incremented.The new count value appears in the register during S3P1 of the machine cycle following the
one in which the transition was detected. So, it takes two machine cycles ( 24 clock periods ) to recognize a
HIGH-to-LOW transition. There is no any restriction on the duty cycle of the external signal. But, to ensure that a given
level is sampled at least once before it changes, the signal should be held stable for at least one full machine cycle.
10.4
Operating Mode
Each of Timer 0 and Timer 1 can be programmed to be in one of the four operating modes: Mode 0, Mode1, Mode 2,
and Mode 3. Mode selection is controlled by bit pairs (M1,M0) of SFR TMOD, that is, bits TMOD.6, TMOD.5, TMOD.1,
and TMOD.0.
10.5
Mode 0
When in mode 0, either of Timer 0 and Timer1 acts as a 13-bit counter with a divide-by-32 prescaler. The following
diagrams shows the operation of both Timer 0 and Timer 1 in mode 0.
DRAFT 2007 Apr 02
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Syntek Semiconductors
STK6031
Xtal1
OSC
Divide-by-12
Prescaler
C/T=0
TL1 TH1
P35/T1 Pin
(5 bits) (8 bits)
C/T=1
(TMOD.7)
Gate
TR1
(TCON.6)
Interrupt
TF1
(TCON.7)
Control
P33/INT1 Pin
C/T=0
TL0
P34/T0 Pin
C/T=1
(TMOD.3)
Gate
TR0
(TCON.4)
TH0
(5 bits) (8 bits)
Interrupt
TF0
(TCON.5)
Control
P32/INT0 Pin
Fig.12 Mode 0 operation of Timer 0, Timer 1
In this mode, the Timer 0/Timer 1 registers are configured as a 13-bit register, which is composed of all the 8 bits of the
TH1/TH0 and the lower 5 bits of TL1/TL0. The upper 3 bits of the TL1/TL0 should be ignored. The Timer Interrupt flag
TF1/TF0 is set to HIGH when the 13-bit register, acting as a counter, rolls over from all 1s to all 0s.
The 13-bit register(counter) is enabled only under the following conditions:
1. TR0/TR1=1, and
2. Either Gate=0 or INT1/INT0=1.
10.6
Mode 1
The configuration and operation of Mode 1 is the same as that of Mode 0, except that the registers are now 16 bits,
instead of 13 bits when in Mode 0.
DRAFT 2007 Apr 02
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Syntek Semiconductors
Xtal1
OSC
STK6031
Divided-by-12
Prescaler
C/T=0
TL1 TH1
P35/T1 Pin
(8 bits)
(8 bits)
C/T=1
TR1
(TCON.6)
Interrupt
TF1
(TCON.7)
Control
Gate
(TMOD.7)
P33/INT1 Pin
C/T=0
TL0 TH0
P34/T0 Pin
(8 bits) (8 bits)
C/T=1
TR0
(TCON.4)
Interrupt
TF0
(TCON.5)
Control
Gate
(TMOD.3)
P32/INT0 Pin
Fig.13 Mode 1 operation of Timer 0, Timer 1
10.7
Mode 2
Mode 2 configures the Timer register as an 8-bit counter( TL1 or TL0 ) with automatic reloading. When the contents of
TL1/TL0 changes from all 1s to all 0,TF1/TF0 is set to HIGH and the content of TH1/TH0 is reloaded into TL1/TL0.The
action of this reloading does not change the content TH1/TH0. The content of TH1/TH0 is always changed via
programming these two SFRs.
The following diagram shows the operation of both Timer0 and Timer 1 in mode 2.
DRAFT 2007 Apr 02
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Syntek Semiconductors
Xtal1
OSC
STK6031
Divide-by-12
Prescaler
C/T=0
TL1
(8 bits)
P35/T1 Pin
C/T=1
TR1
(TCON.6)
Interrupt
TF1
(TCON.7)
Control
Gate
(TMOD.7)
TH1
(8 bits)
P33/INT1 Pin
C/T=0
TL0
(8 bits)
P34/T0 Pin
C/T=1
TR0
(TCON.4)
TF0
Interrupt
(TCON.5)
Control
Gate
(TMOD.3)
TH0
(8 bits)
P32/INT0 Pin
Fig.14 Mode 2 operation of Timer 0, Timer 1.
10.8
Mode 3
When in Mode 3, Timer 1 is stopped and Timer 0 is configured into two separate counters: TL0 and TH0. The logic of
Timer 0 in Mode 3 is shown below.
TL0 uses the Timer 0 control bits: C/T, GATE, TR0, INT0, and TF0. TH0 is configured into a timer function(counting
machines cycles) and takes over the use of TR1 and TF1 from Timer 1. Hence, TH0 now controls the Timer 1 interrupt.
DRAFT 2007 Apr 02
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Syntek Semiconductors
Xtal1
OSC
STK6031
Divide-by-12
Prescaler
C/T=0
P34/T0 Pin
C/T=1
TR0
(TCON.4)
TL0
(8 bits)
Interrupt
TF0
(TCON.5)
TH0
Interrupt
TF1
(TCON.7)
Control
Gate
(TMOD.3)
P32/INT0 Pin
(8 bits)
Control
TR1
(TCON.6)
Fig.15 Mode 3 operation of Timer 0, Timer 1
DRAFT 2007 Apr 02
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Syntek Semiconductors
10.9
STK6031
Timer 0/1 Mode Register (SFR TMOD)
Table 14 Timer 0/1 Mode Register
TIMER 0/1 MODE REGISTER (TMOD), LOCATED AT 89H OF THE SFR MAP
Bit Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Mnemonics
Gate
C/T
M1
M0
Gate
C/T
M1
M0
(Timer1)
(Timer1)
(Timer1)
(Timer1)
(Timer0)
(Timer0)
(Timer0)
(Timer 0)
Table 15 Description of Timer 0/1 Mode Register
MNEMONIC
GATE
BIT
POSITION
TMOD.7
FUNCTION
Gating control for Timer 1.
When set, Timer 1 is enabled only while INT1 pin is high and TR1 control bit is set.
When cleared, Timer 1 is enabled whenever TR1 control bit is set.
C/T
TMOD.6
Timer or Counter selection of Timer 1.
When set, counter operation is selected.
When cleared, timer operation is selected.
M1, M0
TMOD.5
Mode selection of Timer 1
TMOD.4
• (M1, M0) = 00 selects Mode 0 operation.
• (M1, M0) = 01 selects Mode 1 operation.
• (M1, M0) = 10 selects Mode 2 operation.
• (M1, M0) = 11 selects Mode 3 operation.( In mode 3, Timer/Counter 1 is stopped.)
GATE
TMOD.3
Gating control for Timer 0.
When set, Timer 0 is enabled only while INT0 pin is high and TR0 control bit is set.
When cleared, Timer 0 is enabled whenever TR0 control bit is set.
C/T
TMOD.2
Timer or Counter selection of Timer 0.
When set, counter operation is selected.
When cleared, timer operation is selected.
M1, M0
TMOD.1,
TMOD.0
Mode selection of Timer 0
• (M1, M0) = 00 selects Mode 0 operation.
• (M1, M0) = 01 selects Mode 1 operation.
• (M1, M0) = 10 selects Mode 2 operation.
• (M1, M0) = 11 selects Mode 3 operation. ( In mode 3, Timer/Counter 1 is stopped.)
10.10 Timer 0/1 Control Register (SFR TCON)
Table 16 Timer 0/1 Control Register
TIMER 0/1 CONTROL REGISTER ( TCON ), LOCATED AT 88H OF THE SFR MAP
Bit Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Mnemonics
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
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STK6031
Table 17 Description of Timer 0/1 Control Register
MNEMONIC
TF1
BIT
POSITION
TCON.7
FUNCTION
Timer 1 overflow flag.
Set by hardware on Timer/Counter 1 overflow.
Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in
software.
TR1
TCON.6
TF0
TCON.5
Timer 1 Run control bit.
Set/cleared by software to turn Timer/Counter on/off.
Timer 0 overflow flag.
Set by hardware on Timer/Counter 0 overflow.
Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in
software.
TR0
TCON.4
IE1
TCON.3
Timer 0 Run control bit.
Set/cleared by software to turn Timer/Counter on/off.
External Interrupt 1 Flag.
Set by hardware when external interrupt 1 is detected.
This bit is cleared after the interrupt is processed. That is, when the Return from Interrupt
instruction is executed.
IT1
TCON.2
IE0
TCON.1
Interrupt 1 Type Control bit.
Set/cleared by software to specify falling edge/low level triggered external interrupt.
External Interrupt 0 Flag.
Set by hardware when external interrupt 0 is detected.
This bit is cleared after the interrupt is processed. That is, when the Return from Interrupt
instruction is executed.
IT0
TCON.0
Interrupt 0 Type Control bit.
Set/cleared by software to specify falling edge/low level triggered external interrupt.
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11 TIMER 2
11.1
General Description
Timer 2 is a 16-bit timer/counter. It can operate either as a timer or as an event counter, depending on the state of the
C/T2 bit (bit 1) of SFR T2CON.
Timer 2 can operate in the following modes:
• 16-bit timer / counter,
• 16-bit timer with capture,
• 16-bit auto-reload timer / counter, and
• Baud-rate generator.
11.2
Special Function Registers of Timer 2
Timer 2 is associated with the 6 SFRs listed in Table 18.
Table 18 Timer 2 SFRs
VALUE AFTER
RESET
ADDRESS
R/W
8E
R/W
CKCON
Select clock frequency for Timer 0, Timer 1, and Timer 2,
and memory stretch cycle for the MOVX instruciton.
0000 0000
MNEMONICS
DESCRIPTION
C8
R/W
T2CON
Timer 2 Control Register ( bit-addressable )
0000 0000
CA
R/W
RCAP2L
Timer 2 Reload Capture Register, Low byte
0000 0000
CB
R/W
RCAP2H
Timer 2 Reload Capture Register, High byte
0000 0000
CC
R/W
TL2
Timer 2, Low byte
0000 0000
CD
R/W
TH2
Timer 2, High byte
0000 0000
11.2.1
THE CLOCK CONTROL REGISTER (SFR CKCON)
the T2M bit (bit 5) of the CKCON SFR, located at 8E(hex) of the SFR map, selects the frequency of the clock to be fed
into the 16-bit timer 2. When T2M= 0, Timer 2 uses (XTAL1 ÷ 12). When T2M= 1, Timer 2 uses (XTAL1 ÷ 4). This bit has
no effect when Timer 2 is configured as a baud rate generator.
For detailed description of the SFR CKCON, please refer to Table 10 and Table 11.
11.2.2
TIMER 2 CONTROL REGISTER (SFR T2CON)
Table 19 and Table 20 give a description for each bit of the SFR T2CON.
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Table 19 Timer 2 Control Register
Timer 2 Control Register ( T2CON ), located at C8(hex) of the SFR map
Bit Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Mnemonics
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Reset Value
0
0
0
0
0
0
0
0
Table 20 .Description of Timer 2 Control Register
MNEMONIC
TF2
BIT
POSITION
T2CON.7
FUNCTION
Timer 2 overflow flag.
• This bit is set to HIGH when Timer 2 overflow from FFFF(hex) and must be cleared by
software.
• TF2 will only be set to HIGH when both RCLK=0 and TCLK=0.
• Writing a 1 to TF2 forces a Timer 2 interrupt, if enable.
EXF2
T2CON.6
Timer 2 External flag.
• This bit is set to HIGH when either a capture or reload is caused by a high-to-low
transition on the T2EX input and when EXEN2=1.
• When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to Timer 2
interrupt routine. It must be cleared by software.
RCLK
T2CON.5
Receive clock flag.
• When RCLK=1 , UART uses Timer 2 overflow pulses for its receive clock in Modes 1
and 3.
• When RCLK=0 , UART uses Timer 1 overflow pulses for its receive clock.
TCLK
T2CON.4
Transmit clock flag.
• When TCLK=1 , UART uses Timer 2 overflow pulses for its transmit clock in Modes 1
and 3.
• When TCLK=0 , UART uses Timer 1 overflow pulses for its transmit clock.
EXEN2
T2CON.3
Timer 2 external enable.
• EXEN2=1 allows a capture or reload to occur as a result of a high-to-low transition on
the T2EX input, if Timer 2 is not generating baud rates for the UART.
• EXEN2=0 causes Timer 2 to ignore all events at T2EX input.
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MNEMONIC
STK6031
BIT
POSITION
TR2
T2CON.2
C/T2
T2CON.1
FUNCTION
Start/Stop control for Timer 2.
TR2= 1 starts the Timer 2. TR2= 0 stops Timer 2.
Select timer function or counter function of Timer 2.
• C/T2= 0 selects the timer fucntion. When used as a timer, Timer 2 runs at 4 XTAL1
clocks per increment or 12 XTAL1 clocks per increment, as programmed by the
CKCON.5 bit of the SFR CKCON, in all modes except baud rate generator mode.
When used in baud rate generator mode, Timer 2 runs at 2 XTAL1 per increment,
independent of the state of CKCON.5.
• C/T2=1 selects the external event counter function; falling-edge-triggered on the T2
input.
CP/RL2
T2CON.0
Capture/reload flag.
• When CP / RL2 = 1, captures will occur on high-to-low transitions at T2EX, if EXEN2=1.
• When CP / RL2 = 0, auto-reloads will occur either with Timer2 overflows or high-to-low
transitions at T2EX when EXEN2=1.
• When RCLK=1 or TCLK=1, this bit is ignored and the timer is forced to auto-reload on
a Timer 2 overflow.
11.3
16-bit Timer / Counter, or 16-bit Timer / Counter with Capture capability
Two options may be selected by the EXEN2 bit in T2CON.
• If EXEN2=0, then Timer 2 is a 16-bit timer or counter which, upon overflowing, sets the Timer 2 overflow bit TF2. This
may then be used to generate an interrupt.
• If EXEN2=1, then Timer 2 operates as described above, but with the additional feature that a High-to-Low transition at
the T2EX input causes the current value in TL2 and TH2 to be captured into registers RCAP2L and RCAP2H
respectively. In addition, the transition at T2EX causes the EXF2 bit in T2CON to be set; this may also be used to
generate an interrupt.
The following diagram shows Timer 2, working as a 16-bit Timer / Counter with Capture capability.
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Xtal1
clock
STK6031
1
-----12
C/T2=0
TL2 TH2
(8 bits) (8 bits)
P1.0/T2 Pin
C/T2=1
Control
TF2
(T2CON.7)
Timer 2
interrupt
TR2
capture
Transition
detection
RCAP2L RCAP2H
(8 bits) (8 bits)
P1.1/T2EX Pin
EXF2
(T2CON.6)
Control
EXEN2
Fig.16 Timer 2 - Timer / Counter with capture
11.4
Auto-Reload Mode
In the Auto-Reload mode, there are also two options selected by the EXEN2 bit in T2CON. If EXEN2=0, then, when
Timer 2 rolls over, it sets the TF2 bit but also causes the Timer 2 registers to be reloaded with the 16-bit value held in the
registers RCAP2L and RCAP2H. The 16-bit value held in these registers is pre-loaded by software.
If EXEN2= 1, Timer 2 operates as described above, but with the additional feature that a High-to-Low transition at the
external input pin T2EX will also trigger the16-bit reload and set the EXF2 bit. The following diagram shows Timer 2 in
Auto-reload mode.
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Xtal
OSC
STK6031
1----12
C/T2=0
TL2 TH2
(8 bits) (8 bits)
T2 Pin
C/T2=1
(T2CON.7)
Control
TR2
Transition
detection
OR
TF2
RCAP2L RCAP2H
(8 bits) (8 bits)
T2EX Pin
EXF2
(T2CON.6)
Control
EXEN2
Fig.17 Timer 2 in auto-reload mode
11.5
Baud Rate Generator Mode
When RTCLK=1, Timer 2 is in baud rate generator mode. Details is described in the UART section.
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Timer 2
interrupt
Syntek Semiconductors
11.6
STK6031
Timer 2 Operating modes
The following table describes the operating modes of Timer 2.
Table 21 Timer 2 operating modes
RTCLK
CP/RL2
TR2
OPERATING MODE
0
0
1
16-bit auto-reload.
0
1
1
16-bit capture.
1
x
1
baud rate generator
x
x
0
OFF
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12 RESET
12.1
Sources of RESET
There are 5 sources to reset STK6031:
• external RESET pin,
• power-on reset,
• low-voltage detection reset,
• watchdog timer overflow, and
• ISP programming.
The functional diagram of the reset circuitis is shown in Fig.18.
Low-voltage
detection and reset
Power-on-reset
RESET pin
Delay and Control
Reset
the whole chip
external
resistor
watchdog timer overflow
ISP programming mode
Fig.18 Functional diagram of reset circuit
12.2
Power-On- Reset (POR) with fast-rising power supply
The STK6031 can be reset by the on-chip power-on-reset, whose switching level is 2.7 ± 0.2 volts. The sequence of the
power-on-reset is as follows:
1. As soon as the power supply (VDD) reaches the POR switching level, the on-chip POR generates a pulse, called
POR Pulse.
2. This POR pulse then triggers an internal reset, POC. Also, this POR pulse resets the internal reset counter.
3. When the oscillator is stable enough, the oscillator clocks starts triggering the internal reset counter to count.
4. When the internal reset counter counts up to 2048 and overflows, the internal reset (POC) is released and the CPU
starts executing instruction.
The above sequence is further illustrated in Fig.19.
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Supply
Voltage
STK6031
Switching level of POR
= 2.7 volts
POR Pulse
Internal
Reset
Oscillator
CPU starts instruction fetch
from Program ROM address 0000H.
CPU running
2048 oscillator
period delay
Time = 0
Oscillator
Start-up
time
The oscillator clock is stable enough
to trigger the internal divided-by-2048
counter.
Fig.19 Timing of Power-On-Reset with fast rising VDD.
12.3
Asynchronous reset by adding a HIGH pulse to the RESET pin
The STK6031 can be reset by adding a HIGH pulse to the RESET pin. The RESET pin is an input with an internal
Schmitt-trigger for noise reduction. The CPU checks if there is a reset at cycle 4 (C4) of every instruction cycle. A reset
is accomplished by holding the RESET pin HIGH for at least two instruction cycles while the oscillator is running. The
CPU responds by executing an internal reset.
12.4
Low-power detection and reset
The STK6031 has the capability of low-power detection and reset. The reset due to low power can be enabled or disabled
by use of the LVR bit (bit 0) of SFR CHIPCON, at SFR address BF(hex). Setting LVR= 0 enables low-power reset and
setting LVR= 1 disables low-power reset.
Due to fabrication process variations from different production lots, the threshold voltage for low-power detection is in the
range of 2.52 ~ 2.94 volts, without regard to the supply voltage to the VDD pin. The typical low-power threshold voltage
is 2.7 volts.
12.5
Reset by the Watchdog Timer overflow
The microcontroller can also be reset by the Watchdog Timer overflow. Please refer to Chapter 18 .
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13 OSCILLATOR
13.1
The Oscillator Circuit
VDD_port
VDD_port
PMOS
VDD_port
PMOS
PMOS
XTAL2
XTAL1
NMOS
NMOS
NMOS
VSS_port
VSS_port
NMOS
VSS_port
500K ohm
STOP
CLK
20P
ceramic
C2
C1
20P
ceramic
Fig.20 Oscillator Circuit.
The oscillator circuit is a single-stage inverting amplifier in a Pierce oscillator configuration. The circuitry between pins
XTAL1 and XTAL2 is basically an inverter biased to the transfer point. Either a crystal or ceramic resonator can be used
as the feedback element to complete the oscillator circuitry. Both are operated in parallel resonance.
XTAL1 is the high gain amplifier input, and XTAL2 is the output. To drive the STK6031 externally, XTAL1 is driven from
an external source and XTAL2 is left open-circuit.
13.2
The Values of C1 and C2
Since the performance of the crystal oscillator is closely related to the characteristics of the crystal itself, the user should
contact the crystal manufacturer for the proper values of C1 and C2. The values given here is for reference only.
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14 INTERRUPTS
14.1
General Description
The STK6031 support s 6-source, 2-level, 6 vectored-address interrupt system. Interrupts come from the sources listed
below:
• External interrupt 0
• Enternal interrupt 1
• Timer 0 overflow
• Timer 1 overflow
• Timer 2 overflow or External event
• Tranmission or reception of the UART
Each interrupt can be individually enabled or disabled and can be assigned a low-level or high-level priority. All interrupts
can be globally disabled. When an interrupt event occurs, its corresponding interrupt flag is raised to HIGH. This flag
should be cleared by the user interrupt service routine.
In addition to being assigned a low level or a high-level, interrupts within a level have a natural priority level, as shown in
Table 22.
Table 22 gives an overview of the interrupt system.
Table 22 Overview of the interrupt system
Source
number
Interrupt sources
Flags generated
by the interrupt
Interrupt
enable bit
Interrupt
priority bit
Priority within
level
Vector
Address
1
External Interrupt 0
IE0 (TCON.1)
EX0 (IE.0)
PX0 (IP.0)
1 (the highest)
0003H
2
Timer 0 Overflow
TF0 (TCON.5)
ET0 (IE.1)
PT0 (IP.1)
2
000BH
3
External Interrupt 1
IE1 (TCON.3)
EX1 (IE.2)
PX1 (IP.2)
3
0013H
4
Timer 1 Overflow
TF1 (TCON.7)
ET1 (IE.3)
PT1 (IP.3)
4
001BH
5
UART Interrupt
(UART receive or
transmit)
TI (SCON0.1)
ES (IE.4)
PS (IP.4)
5
0023H
Timer 2 overflow
TF2 (T2CON.7)
EX2 (IE.5)
PT2 (IP.5)
6
002BH
T2EX pin
EXF2 (T2CON.6)
6
RI (SCON0.0)
Note:
1. Because Timer2 overflow and T2EX share the same interrupt vector address 002BH, it is the responsibility of
software programmer to check individual interrupt flag to see which one caused the interrupt.
14.2
Interrupt Enable Registers
Each of the interrupt sources can be individually enabled or disabled by setting its enable/disable bit in the Interrupt
Enable Registers (SFR IE), located at A8 (hex) of the SFR map. All interrupts can be globally disabled by clearing the
EA bit of SFR IE.
The Interrupt Enable Register is described in Table 23 and Table 25.
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Table 23 Interrupt Enable Register SFR IE
INTERRUPT ENABLE REGISTER ( SFR IE ), LOCATED AT A8H OF THE SFR MAP
Bit Address
Bit7
Mnemonics
EA
Reset value
0
Bit6
0
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ET2
ES0
ET1
EX1
ET0
EX0
0
0
0
0
0
0
Table 24 Description of Interrupt Enable Register SFR IE
MNEMONIC
EA
BIT POSITION
IE.7
FUNCTION
Global enable or disable of all interrupts.
When IE.7 = 0, all interrupts are globally disabled.
When IE.7 = 1, all interrupt sources are globaly enabled.
Please refer to Fig.21 for an overview of the interrupt system.
EX2
IE.6
Not implemented.
IE.5
Enable or disable interrupt due to Timer 2 overflow, or T2EX pin (shared with
P1.1) interrupt.
When IE.5 = 1, external interrupt 2 is enabled.
When IE.5 = 0, external interrupt 2 is disabled.
ES0
IE.4
Enable or disable UART interrupt.
When IE.4 = 1, UART interrupt is enabled.
When IE.4 = 0, UART interrupt is disabled.
ET1
IE.3
Enable Timer 1 overflow interrupt.
When IE.3 = 1, Timer 1 overflow interrupt is enabled.
When IE.3 = 0, Timer 1 overflow interrupt is disabled.
EX1
IE.2
Enable External Interrupt 1.
When IE.2 = 1, External Interrupt 1 is enabled.
When IE.2 = 0, External Interrupt 1 is disabled.
ET0
IE.1
Enable Timer 0 overflow interrupt.
When IE.1 = 1, Timer 0 overflow interrupt is enabled.
When IE.1 = 0, Timer 0 overflow interrupt is disabled.
EX0
IE.0
Enable External Interrupt 0.
When IE.0 = 1, External Interrupt 0 is enabled.
When IE.0 = 0, External Interrupt 0 is disabled.
14.3
Interrupt Priority Register SFR IP
Each interrupt source can be assigned one of two priority levels: high and low. Interrupt priority is defined by the Interrupt
Priority Register (SFR IP, at B8 hex of the SFR map), which is described in Table 25 and Table 26.
Interrupt priority levels are as follows:
• logic 0 = low priority
• logic 1 = high priority.
A low priority interrupt may be interrupted by a high priority interrupt. A high priority interrupt cannot be interrupted by any
other interrupt source. If two requests of different priority occur simultaneously, the high priority level request is serviced.
If requests of the same priority are received simultaneously, an internal polling sequence determines which request is
serviced. Thus, within each priority level, there is a second priority structure determined by the polling sequence. This
second priority structure is shown in Table 22.
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Table 25 .Interrupt Priority Register SFR IP
SFR Interrupt Priority Register ( SFR IP ), located at B8 hex of the SFR map
Bit Address
Bit7
Bit6
Mnemonics
Reset value
1
0
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PT2
PS0
PT1
PX1
PT0
PX0
0
0
0
0
0
0
Table 26 Description of Interrupt Priority Register SFR IP
MNEMONIC
PT2
BIT POSITION
FUNCTION
IP.7
not implemented, return a 1 when read.
IP.6
not implemented.
IP.5
Define the priority of Timer2 overflow interrupt, or T2EX-pin (shared with
P1.1) interrupt.
When IP.5 = 1, Timer 2 overflow is a high priority interrupt.
When IP.5 = 0, Timer 2 overflow is a low priority interrupt.
PS0
IP.4
Define the priority level of UART interrupt.
When IP.4 = 1, UART interrupt is a high priority interrupt.
When IP.4 = 0, UART interrupt is low priority interrupt.
PT1
IP.3
Define the interrupt level of Timer 1 overflow interrupt.
When IP.3 = 1, Timer 1 overflow interrupt is a high priority interrupt.
When IP.3 = 0, Timer 1 overflow interrupt is a low priority interrupt.
PX1
IP.2
Define the interrupt level of External Interrupt 1.
When IP.2 = 1, External Interrupt 1 is a high priority interrupt.
When IP.2 = 0, External Interrupt 1 is a low priority interrupt.
PT0
IP.1
Define the interrupt level of Timer 0 overflow interrupt.
When IP.1 = 1, Timer 0 overflow is a high priority interrupt.
When IP.1 = 0, Timer 0 overflow is a low priority interrupt.
PX0
IP.0
Define the interrupt level of External Interrupt 0.
When IP.0 = 1, External Interrupt 0 is a high priority interrupt.
When IP.1 = 0, External Interrupt 0 is a low priority level.
14.4
Interrupt Vectors
The vector indicates the Program Memory location where the appropriate interrupt service routine starts. Please refer to
Table 22 for interrupt vector addresses.
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15 OVERALL VIEW OF THE INTERRUPT SYSTEM
High
Priority
Timer0 Overflow
Timer1 Overflow
Timer2 overflow
P1.1/PWM1/T2EX
TF2
T2CON.7
TF0
TCON.5
TF1
TCON.7
RI
SCON0.0
TI
SCON0.1
P3.2/INT0
IT0
TCON.0
PT0
IP.1
ET1
IE.3
PT1
IP.3
EX2
IE.5
PX2
IP.5
ES
IE.4
PS
IP.4
EX0
IE.0
PX0
IP.0
EX1
PX1
IP.2
Low
Priority
OR
EXF2
T2CON.6
EXEN2
T2CON.3
UART
ET0
IE.1
OR
IE0
TCON.1
P3.3/INT1
IE1
TCON.3
TCON.2
IE.7
= Low-level-triggered
= Falling-edge-triggered
Fig.21 Overall view of interrupt system.
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STK6031
16 POWER-SAVING MODES
The STK6031 provides two power-saving modes: Idle mode and Stop mode. The bits that control entry into Idle mode
and Stop modes are bits 0 (Idle mode) and bit 1 (Stop mode) of the Power Control Register (SFR PCON) at SFR
adddress 87(hex). Table 27 gives a description of the Power Control Register (SFR PCON).
Table 27 Power Control Register, SFR PCON at address 87(hex) of the SFR map
Bit
Mnemonics
Function
PCON.7
SMOD0
UART baud-rate doubler enable.
When SMOD0 = 1, the baud rate for the UART is doubled.
PCON. 6 ~ 4
Reserved.
PCON.3
GF1
PCON.2
GF0
PCON.1
STOP
PCON.0
IDLE
General purpose flag 1.
Bit-addressable, general-purpose flag for software control.
General purpose flag 0.
Bit-addressable, general-purpose flag for software control.
STOP mode select.
Setting the STOP = 1 places the STK6031 in STOP mode.
IDLE mode select.
Setting the IDLE = 1 places the STK6031 in IDLE mode.
If the STOP Mode and the Idle Mode are selected at the same time, the STOP Mode has higher priority, as can be
obviously seen in Fig.22
XTAL2
XTAL1
OSC
interrupts,
serial port,
timers
Clock
Generator
CPU
STOP
IDLE
Fig.22 Power-saving modes.
16.1
Idle Mode
Idle mode operation permits the interrupt, serial ports and timers to function while the CPU is halted. The functions that
are switched off when the microcontroller enters the Idle mode are:
• CPU (halted)
The functions that remain active during Idle mode are:
• Timer 0, Timer 1, Timer 2, and Watchdog Timer
• UART
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STK6031
• External/Internal interrupts
• External reset or power-on-reset.
The instruction that sets PCON.0 (=1) is the last instruction executed in the normal operating mode before Idle mode is
activated.
Once in the Idle mode, the CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status
Word, Accumulator, RAM and all other registers maintain their current data during Idle mode. The status of external pins
during Idle mode is shown in Table 28.
There are three ways to terminate the Idle mode:
• Activation of any enabled interrupt from interrupt sources listed in Table 22 will cause PCON.0 to be cleared by
hardware, terminating Idle mode, but only if there is no interrupt in service with the same or higher priority. The interrupt
is serviced, and following return from interrupt instruction RETI, the next instruction to be executed will be the one
which follows the instruction that wrote a logic 1 to PCON.0.
The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or
during Idle mode.
For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits.
When Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits.
• The second way of terminating the Idle mode is with an external hardware reset. Since the oscillator is still running,
the hardware reset is required to be active for two instruction cycles to complete the reset operation.
• The third way of terminating the Idle mode is by internal watchdog reset.
16.2
Stop mode
The instruction that sets PCON.1 is the last executed, prior to going into the Stop mode. Once in Stop mode, the crystal
oscillator is stopped. The contents of the on-chip RAM (AUX Memory and Main Data Memory) and the SFRs are
preserved.
Note that the Stop mode can not be entered when the Watchdog Timer has been enabled.
The Stop mode can be terminated only by an external reset (RAM is saved, but SFRs are cleared due to reset).
The status of the external pins during Stop mode is shown in Table 28.
In the Stop mode, Vdd supplies to the CPU can be reduced to minimize power consumption. It must be ensured,
however, that Vdd is not reduced before the Stop mode is activated, and that the Vdd is restored to its normal operating
level before the Stop mode is terminated by hardware reset. The reset signal that terminates the Stop mode also restarts
the oscillator.The reset signal should not be activated before Vdd is restored to its normal operating level and must be
held active long enough to allow the oscillator to restart and stabilize( similar to power-on reset).
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16.3
STK6031
Status of external pins during power-saving modes
Table 28 Status of external pins during Idle and Stop modes.
MODE
Idle
Stop
16.4
ALE
PSEN
internal
Memory
1
1
port data
PORT 0
port data
PORT 1
port data
PORT 2
port data
PORT 3
port data
PORT 4
external
1
1
high-Z
port data
address
port data
port data
internal
0
0
port data
port data
port data
port data
port data
external
0
0
high-Z
port data
port data
port data
port data
Summary of Power-saving Modes
Table 29 .Summary of power-saving modes
MODE
Idle
Example for enabling
the mode
ORL PCON, #01H
TERMINATED BY
REMARKS
• Enabled interrupt
• CPU is gated off
• External hardware reset
• CPU status registers maintain their data.
• Watchdog Timer
overflow.
• Peripherals are active.
• Crystal oscillator is stopped.
Stop
ORL PCON, #02H
External hardware reset
• Contents of on-chip RAM and SFRs are
maintained.
• However, leaving Power- Down mode
means redefinition of SFR contents.
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STK6031
17 UART
17.1
General Description
The UART (Universal Asynchronous Receiver/Transmitter) is a full-duplex serial port, that is, it can transmit and receive
simultaneously. The serial port receiving and transmitting registers are both accessed via the SFR SBUF0. Writing to
SFR SBUF0 loads the transmit register and reading SFR SBUF0 accesses a physically separate receiving register.
The serial port has 4 operation modes, as shown in Table 30.
Table 30 UART Operation Modes
MODE
Mode 0
DESCRIPTION
8-bit serial transmission or reception.
In this mode, 8 bits of data enters or exits through the RxD pin. The TxD pin outputs the shift
clock.
The Least Significant Bit (LSB) is received or transmitted first.
The baud rate is fixed at 1/12 of the oscillator frequency.
Mode 1
10-bit serial transmission or reception.
In this mode, 10 binary bits are transmitted ( through TxD )or received (through RxD). The 10
binary bits are composed of a start bit(1), 8 data bits (LSB first), and a stop bit(1). On
reception, the stop bit goes into RB8 of the Special Function Register SCON0.
The baud rate is variable.
Mode 2
11-bit serial transmission or reception.
In this mode, 11 binary bits are transmitted ( through TxD )or received (through RxD). The 11
binary bits are composed of a start bit(1), 8 data bits (LSB first), a programmable 9th data bit,
and a stop bit(1).
On transmission, the 9th data bit(TB8 inSCON0) can be programmed to be 1 or 0. For example,
in application, the parity bit P of SFR PSW can be moved into TB8 of SCON0.
On reception, the 9th data bit goes into RB8 in SCON0, while the stop bit is ignored.
The baud rate is programmable to be 1/32 or 1/64 of the oscillator frequency.
Mode 3
11-bit serial transmission or reception.
In this mode, 11 binary bits are transmitted ( through TxD )or received (through RxD). The 11
binary bits are composed of a start bit(1), 8 data bits (LSB first), a programmable 9th data bit,
and a stop bit(1).
Actually, Mode 3 is the same as Mode 2 in all respects except baud rate.
The baud rate in Mode 3 is variable.
17.2
Initiation of Serial Transmission
In all four modes, transmission is initiated by executing any instruction that uses SFR SBUF0 as a destination register.
In mode 0, reception is initiated by the condition RI= 0 and REN=1. In all other 3 modes, reception is initiated by the
incoming start bit if REN=1.
17.3
Serial Port Control/Status Register ( SFR SCON0)
The Serial Port Control and Status Register is the SFR SCON0, located at address 98H of the SFR space. The following
tables give a detailed description of this register.
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STK6031
Table 31 Serial Port Control and Status Register
SERIAL PORT CONTROL AND STATUS REGISTER, SCON0, LOCATED AT 98H OF THE SFR MAP
Bit Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Mnemonics
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Table 32 Description of Serial Port Control and Status Register
MNEMONIC
BIT POSITION
FUNCTION
SM0
SCON0.7
These two bits are used to select the operation mode.
SM1
SCON0.6
Please refer to Table Table 33.
SM2
SCON0.5
Enable the multiprocessor communication feature of Mode 2 and Mode
3. In these modes, if SM2=1, then RI will not be activated if the received
9th data bit(RB8) is a logic 0.
In Mode 1, if SM2=1, then RI will be activated only when a valid stop
bit is received.
In Mode 0, SM2 should be programmed to be a logic 0.
REN
SCON0.4
Enable or disable the serial reception. When REN=1, serial reception is
enabled. When REN=0, serial reception is disabled.
TB8
SCON0.3
TB8 is the 9th data bit that will be transmitted in Mode 2 or Mode 3. Set
or cleared by software as desired.
RB8
SCON0.2
In Mode 2 and Mode 3, RB8 is the 9th data bit received.
In Mode 1, if SM2=0, the RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
TI
SCON0.1
The Transmit Interrupt Flag.
In mode 0, this bit is set to a logic 1 by hardware at the end of the 8th bit
time.
In mode 1, mode 2, and mode 3, this bit is set to a logic 1 by hardware
at the beginning of the stop bit time.
This bit can only be cleared via software.
RI
SCON0.0
The Receive Interrupt Flag.
In mode 0, this bit is set to a logic 1 by hardware at the end of the 8th bit
time.
In mode 1, mode 2, and mode 3, this bit is set to a logic 1 by hardware
at the middle of the stop bit time.
This bit can only be cleared via software.
17.4
Selection of Operation Modes
Table 33 Selection of Operation Modes
MODE
SM0
SM1
DESCRIPTION
BAUD RATE
0
0
0
Shift Register
1/12 fosc
1
0
1
8-bit UART
Variable.
2
1
0
9-bit UART
1/64 fosc or 1/32 fosc
3
1
1
9-bit UART
Variable
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17.5
STK6031
Baud Rates
In Mode 0, the baud rate is 1/12 of the XTAL1 oscillator frequency.
In Mode 2, the baud rate depends on the value of the SMOD bit in the Special Function Register PCON. If SMOD=0, the
default value of SMOD after reset, the baud rate is 1/64 of the oscillator frequency. If SMOD=1, the baud rate is 1/32 of
the oscillator frequency.
In Mode 1 and Mode 3, the baud rate is determined by Timer 1 or Timer 2 overflow rate.
17.6
Using Timer 1 to generate baud rates
When Timer1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer1 overflow
rate and the value of the SMOD bit of the SFR PCON, as follows:
SMOD
2
Baud rate = ---------------------- × Timer1 overflow rate
32
The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either timer or counter
operation in any of its 3 running modes. In most typical applications, it is configured for timer operation, in the
Auto-Reload mode (high nibble of TMOD=0010B). In this case the baud rate is given by the formula:
SMOD
2
1
Baud rate = --------------------- × fosc × ---------------------------------------------------32
[ 12 × ( 256 – TH1 ) ]
By configuring Timer1 to run as a 16-bit timer (high nibble of TMOD=0001B), and using the Timer1 interrupt to do a 16-bit
software reload, very low baud rate can be achieved
Table Table 34 lists various commonly used baud rates and how they can be obtained from Timer1.
Table 34 Using Timer 1 to generate baud rates
BAUD RATE
FOSC(MHZ)
SMOD
TIMER 1
MODE
C/T
RELOAD
VALUE
Mode 0 max: 1 Mbits/S
12
X
X
X
X
Mode 2 max: 375 kbits/S
12
1
X
X
X
Modes 1 and 3: 62.5 kbit/S
12
1
0
2
FFH
19.2 kbits/S
11.059
1
0
2
FDH
9.6 kbits/S
11.059
0
0
2
FDH
4.8 kbits/S
11.059
0
0
2
FAH
2.4 kbits/S
11.059
0
0
2
F4H
1.2 kbits/S
11.059
0
0
2
E8H
137.5 kbits/S
11.986
0
0
2
1DH
110
6
0
0
2
72H
110
12
0
0
1
FEEBH
17.7
Using Timer 2 to generate baud rates
Timer 2 is selected as a baud rate generator by setting the RTCLK bit of SFR T2CON. The baud rate generator mode
is similar to the Auto-reload mode, in that a roll-over in TH2 causes Timer 2 registers to be reloaded with the 16-bit value
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STK6031
held in the registers RCAP2H and RCAP2L, which are preloaded by software. Baud rates in Modes 1 and 3 are
determined by the overflow rate of Timer 2, as specified below.
Timer 2 overflow rate
Baud Rate = -------------------------------------------------------16
Timer 2 can be configured for either timer or counter operation. In typical applications, it is configured for timer operation
(C/T = 0). Timer operation is slightly different for Timer 2 when it is being used as a baud rate generator. Normally, as a
timer, it increments every machine cycle at a frequency of 1/12 fosc. However, as a baud rate generator, it increments
every state time at a frequency of 1/2 fosc. In this case , the baud rate is determined, as specified below.
fosc
Baud Rate = -------------------------------------------------------------------------------------------------32 × [ 65536 – ( RCAP2H ; RCAP2L ) ]
where (RCAP2H ; RCAP2L) is the content of registers RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
The baud rate generator mode of Timer 2 is shown in the following figure.
Note that the Xtal1 clock is divided by 2, not by 12..
Xtal1
Clock
Timer1
overflow
1⁄2
1⁄2
0
1
SMOD
C/T2=0
TL2 TH2
(8 bits) (8 bits)
T2 Pin
C/T2=1
1
0
RCLK
Control
1 ⁄ 16
TR2
RX CLOCK
RCAP2L RCAP2H
(8 bits) (8 bits)
Transition
detection
T2EX Pin
EXF2
Control
Timer2 Interrupt
(additional external
interrupt)
(T2CON.6)
EXEN2
Fig.23 Timer 2 in baud rate generator mode.
This figure is only valid if RTCLK=1. At roll-over, TH2 does not set the TF2 bit of T2CON and therefore will not generate
interrupt. Consequently, the Timer 2 interrupt does not need to be disabled when in the baud rate generator mode. If
EXEN2 is set to HIGH, a HIGH-to-LOW transition on T2EX will set the EXF2 bit of T2CON, but will not cause a reload
from (RCAP2H; RCAP2L) to (TH2; TL2). Therefore, in this mode T2EX may be used as an additional external interrupt.
When Timer 2 is operating as a timer(TR2=1), in the baud rate generator mode, registers TH2 and TL2 should not be
accessed. Under these conditions, the timer is being incremented every state time and therefore the results of a read or
write may not be accurate. The RCAP registers, however, may be read out but not written to. A write might overlap a
reload and cause write and/or reload errors. If a write operation is required, Timer 2 should first be turned off by clearing
the TR2 bit.
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STK6031
18 WATCHDOG TIMER
18.1
Functional Block Diagram
The Watchdog Timer is a counter that is used to reset the STK6031 when it enters into an erroneous state, possibly due
to disturbance from external world. Only one SFR (SFR WDT, at SFR map address E1hex) is associated with the
Watchdog Timer.
The functional block diagram of the Watchdog Timer is given below.
XTAL1
÷6
÷ 1024
÷ 1024
3-bit
Programmable
Counter
RESET
WDT0
WDTCLR
EWDT
WDT1
WDT2
Fig.24 Watchdog Timer.
18.2
Watchdog Timer Control Register
The Watchdog Timer Control Register (SFR WDT) is the only SFR associated with the Watchdog Timer. It can be written
to or read from, and is given in Table 35.
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Table 35 Watchdog Timer Register
WATCHDOG TIMER REGISTER, SFR WDT, AT E1 (HEX) OF THE SFR MAP
Bit Address
Bit7
Bit6
Bit5
Bit2
Bit1
Bit0
Mnemonics
EWDT
WDTCLR
not implemented
Bit4
Bit3
WDT2
WDTI
WDT0
RESET value
0
0
x
0
0
0
Table 36 Description of SFR WDT
MNEMONIC
EWDT (bit 7)
FUNCTION
Enable Watchdog Timer.
Setting EWDT=1 enables the Watchdog Timer. Setting EWDT=0 disables the Watchdog Timer.
WDTCLR (bit 6)
Clear the Watchdog Timer programmable counter.
The bit must be regulary cleared before the 3-bit programmable counter overflows to generate
a reset pulse.
WDT2, WDT1,
WDT0 (bits 2, 1, 0)
These 3 bits decides the overflow period of the Watchdog Timer. The following table gives the
overflow period versus the values of these 3 bits, assuming that XTAL1=24 MHz.
WDT2
Overflow interval
Notes
0
0
0
8 x 0.25 seconds
0
0
1
1 x 0.25 seconds
Assuming
XTAL1=24 MHz.
0
1
0
2 x 0.25 seconds
0
1
1
3 x 0.25 seconds
1
0
0
4 x 0.25 seconds
1
0
1
5 x 0.25 seconds
1
1
0
6 x 0.25 seconds
1
1
1
7 x 0.25 seconds
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WDT0
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STK6031
19 PWM (PULSE WIDTH MODULATED) OUTPUTS
The STK6031 contains 5 Pulse Width Modulated (PWM) output channels. These channels generate pulses of
programmable length and interval. Six SFRs are associated with the PWM. They are listed in Table 37.
Table 37 SFRs for PWM channels
BLOCK
SYMBOL
NAME
Address
(Hex format)
RESET
VALUE
PWM
P1_OTP
Port 1 pin selection for PWM outputs
D1
xxx0 0000
PWM0D
PWM0 width
D2
1000 0000
PWM1D
PWM1 width
D3
1000 0000
PWM2D
PWM2 width
D4
1000 0000
PWM3D
PWM3 width
D5
1000 0000
PWM4D
PWM4 width
D6
1000 0000
When a PWM register (PWM0 ~ PWM4) is loaded with a new value, the associated output is updated immediately. It
does not have to wait until the end of the current counter period. Both PWMn output pins are driven by push-pull drivers.
19.1
Port 1 Option Register (SFR P1_OPT) l Register
The SFR P1_OPT is used to configure Port 1 pins to be Port 1 I/O pins or PWM output pins.
Table 38 Port 1 Option Register(address D1H)
Bit position
7
6
5
Mnemonics
x
Reset value
x
x
4
3
2
1
0
PWM4E
PWM3E
PWM2E
PWM1E
PWM0E
0
0
0
0
0
Table 39 Description of SFR P1_OPT bits
BIT
SYMBOL
DESCRIPTION
7, 6, 5
not implemented
4 to 0
PWM4E to PWM0E
When PWM4E=0, P4.0 pin works as an I/O pin
When PWM4E=1, P4.1 pin works as PWM 4 output.
Other bits can be configured in the same way.
19.2
Pulse Width Register 0 ~ 4 (PWM0D ~ PWM4D)
Table 40 Pulse width register (address D2 ~ D6 hex, R/W)
Register
Name
Address
(hex)
PWM0D
D2
Pulse width of PWM channel 0.
PWM1D
D3
Pulse width of PWM channel 1.
PWM2D
D4
Pulse width of PWM channel 2.
PWM3D
D5
Pulse width of PWM channel 3.
PWM4D
D6
Pulse width of PWM channel 4.
Reset
value
BIT 7
1
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BIT 6
0
BIT 5
0
54
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
Syntek Semiconductors
STK6031
20 ANALOG-TO-DIGITAL CONVERTER (ADC)
20.1
ADC functional description
The STK6031 has a 6-bit successive approximation ADC with 4 multiplexed analog input channels. ADC channel inputs
share with Port 4 pins. Analog input voltage range can be from Vref(n)(A) (typical 0 V) to Vref(p)(A) (typical +3.3 V).
Three SFRs (P4_OPT, ADCSEL, and ADCVAL) perform the user software interface to the ADC; see Table 41 for an
overview of the ADC SFRs.
Figure 25 shows the relation between SFRs and the ADC.
P4.1/ADC1
P4.0/ADC0
6-bit ADC
SFR ADCVAL
P4.2/ADC2
SFR ADCSEL
P4.3/ADC3
SFR P4_OPT
enable ADC
Fig.25 ADC SFRs
20.2
ADC during Idle and Stop mode
The analog-to-digital converter is active only when the microcontroller is in normal operating mode. If the Idle or
Stop mode is activated, then the ADC is switched off and put into a power saving idle state - a conversion in progress is
aborted. The conversion result register (SFR ADCVAL) is not affected.
20.3
ADC SFRs and their reset value
Three SFRs (P4_OPT, ADCSEL, and ADCVAL) are associated with ADC. An overview of these three registers is given
in Table 41.
Table 41 ADC Special Function Registers overview
ADDRESS
NAME
R/W
DESCRIPTION
D9(hex)
P4_OPT
R/W
Selection of Port 4 pin function.
DA(hex)
ADCSEL
R/W
Channel selection.
DB(hex)
ADCVAL
R/W
ADC value.
20.3.1
P4_OPT REGISTER
The P4_OPT SFR has only 4 bits. It is used to configure Port 4 pins either as a port pin or as an analog input pin for the
6-bit ADC.
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Table 42 P4_OPT register (address D9 hex)
Bit Number
BIT 7
BIT 6
4 BIT
not physically implemented
Bit Name
Rest Value
BIT 5
x
x
x
x
BIT 3
BIT 2
BIT 1
BIT 0
ADC3E
ADC2E
ADC1E
ADC0E
0
0
0
0
Table 43 Description of P4_OPT Register bits
BIT
SYMBOL
3
ADC3E
ADC3E=1 configures pin P4.3 / ADC3 as an analog input pin.
ADC3E=0 configures pin P4.3 / ADC3 as a port pin (P4.3)
2
ADC2E
ADC2E=1 configures pin P4.2 / ADC2 as an analog input pin.
ADC2E=0 configures pin P4.2 / ADC2 as a port pin (P4.2)
1
ADC1E
ADC1E=1 configures pin P4.1 / ADC1 as an analog input pin.
ADC1E=0 configures pin P4.1 / ADC1 as a port pin (P4.1)
0
ADC0E
ADC0E=1 configures pin P4.0 / ADC0 as an analog input pin.
ADC0E=0 configures pin P4.0 / ADC0 as a port pin (P4.0)
20.3.2
DESCRIPTION
THE ADCSEL REGISTER
The ADCSEL Register is used to select an input channel for conversion. For proper conversion of the input analog
voltage, do the following:
1. Select a channel for analog signal input,
2. Then, enable the ADC by setting the EADC bit to HIGH.
Table 44 ADCSEL Register (address DA hex)
Bit Number
BIT 7
Bit Name
EADC
Reset Value
0
BIT 6
BIT 5
4 BIT
not physically implemented
x
x
x
BIT 3
BIT 2
BIT 1
BIT 0
SAD3
SAD2
SAD1
SAD0
0
0
0
0
Table 45 Description of ADC Register bits
BIT
SYMBOL
7
EADC
Enable the ADC.
3
SADC3
SADC3=1 selects analog signal from P4.3 / ADC3 pin for conversion.
SADC3=0 un-selects this pin.
2
SADC2
SADC2=1 selects analog signal from P4.2 / ADC2 pin for conversion.
SADC2=0 un-selects this pin for conversion.
1
SADC1
SADC1=1 selects analog signal from P4.1 / ADC1 pin for conversion.
SADC1=0 un-selects this pin for conversion.
0
SADC0
SADC0=1 selects analog signal from P4.0 / ADC0 pin for conversion.
SADC0=0 un-selects this pin for conversion.
20.3.3
DESCRIPTION
ADCVAL REGISTERS
The binary result code of the analog-to-digital conversions is stored in the ADCVAL Register.
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STK6031
Table 46 ADCVAL Register (address DB hex)
Bit
Number
BIT 7
BIT 6
Bit Name
x
x
Reset
Value
x
x
20.4
BIT 5
4 BIT
BIT 3
BIT 2
BIT 1
BIT 0
Binary code of the ADC coversion.
0
0
0
0
0
0
ADC resolution and characteristics
The analog input voltage should be stable when the ADC is enabled to perform conversion. An RC low pass filter may
be added to the analog input pins to filter out high frequency noises.The capacitor between an analog input pin and the
ground pin shall be placed as close to the pins as possible, in order to have maximum effect in minimizing input noise
coupling.
Fig.26 gives the converted digital value (given in decimal unit) versus input analog voltages.
70
60
Digital Value ( Decimal )
50
Cal 3.3V ADC
40
Ch0 ADC
Ch1 ADC
Ch2 ADC
30
Ch3 ADC
20
10
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
Vin
Fig.26 Converted digital code versus analog input voltage.
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STK6031
21 INSTRUCTION SET
The STK6031 uses the powerful instruction set of the PCB80C51. It consists of 49 single byte, 45 two byte and 17 three
byte instructions. Using a 16 MHz crystal, 64 of the instructions are executed in 0.75 µs, 45 in 1,5 µs and the multiply,
divide instructions in 3 µs.
A summary of the instruction set is given in Tables Table 48, Table 49, Table 50, Table 51 and Table 52.
The P8xC234 has additional Special Function Registers to control the on-chip peripherals.
21.1
Addressing modes
Most instructions have a destination, source field that specifies the data type, addressing modes and operands involved.
For all these instructions, except for MOVs, the destination operand is also the source operand (e.g. ADD A,R7).
There are five kinds of addressing modes:
• Register Addressing
– R0 to R7 (4 banks)
– A,B,C (bit), AB (2 bytes), DPTR (double byte)
• Direct Addressing
– lower 128 bytes of internal main RAM (including the four R0 to R7 register banks)
– Special Function Registers
– 128 bits in a subset of the internal main RAM
– 128 bits in a subset of the Special Function Registers
• Register-Indirect Addressing
– internal main RAM (@R0, @R1, @SP [PUSH/POP])
– internal auxiliary RAM (@R0, @R1, @DPTR)
– external Data Memory (@R0, @R1, @DPTR)
• Immediate Addressing
– Program Memory (in-code 8 bit or 16 bit constant)
• Base-Register-plus-Index-Register-Indirect Addressing
– Program Memory look-up table (@DPTR+A, @PC+A).
The first three addressing modes are usable for destination operands.
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21.2
STK6031
80C51 family instruction set
Table 47 Instructions that affect flag settings; note 1
FLAG(2)
INSTRUCTION
C
OV
AC
ADD
X
X
X
ADDC
X
X
X
SUBB
X
X
X
MUL
0
X
DIV
0
X
DA
X
X
RRC
X
RLC
X
SETB C
1
CLR C
0
CPL C
X
ANL C, bit
X
ANL C,/bit
X
ORL C, bit
X
ORL C,/bit
X
MOV C, bit
X
CJNE
X
Note
1. Note that operations on SFR byte address 208 or bit addresses 209 to 215 (i.e. the PSW or bits in the PSW) will also
affect flag settings.
2. X = dont care.
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21.3
STK6031
Instruction set description
For the description of the Data Addressing Modes and Hexadecimal opcode cross-reference see Table 52.
Table 48 Instruction set description: Arithmetic operations
MNEMONIC
DESCRIPTION
BYTES
CYCLES
OPCODE
(HEX)
Arithmetic operations
ADD
A,Rr
Add register to A
1
1
2*
ADD
A,direct
Add direct byte to A
2
1
25
ADD
A,@Ri
Add indirect RAM to A
1
1
26, 27
ADD
A,#data
Add immediate data to A
2
1
24
ADDC
A,Rr
Add register to A with carry flag
1
1
3*
ADDC
A,direct
Add direct byte to A with carry flag
2
1
35
ADDC
A,@Ri
Add indirect RAM to A with carry flag
1
1
36, 37
ADDC
A,#data
Add immediate data to A with carry flag
2
1
34
SUBB
A,Rr
Subtract register from A with borrow
1
1
9*
SUBB
A,direct
Subtract direct byte from A with borrow
2
1
95
SUBB
A,@Ri
Subtract indirect RAM from A with borrow
1
1
96, 97
SUBB
A,#data
Subtract immediate data from A with borrow
2
1
94
INC
A
Increment A
1
1
04
INC
Rr
Increment register
1
1
0*
INC
direct
Increment direct byte
2
1
05
INC
@Ri
Increment indirect RAM
1
1
06, 07
DEC
A
Decrement A
1
1
14
DEC
Rr
Decrement register
1
1
1*
DEC
direct
Decrement direct byte
2
1
15
DEC
@Ri
Decrement indirect RAM
1
1
16, 17
INC
DPTR
Increment data pointer
1
2
A3
MUL
AB
Multiply A and B
1
4
A4
DIV
AB
Divide A by B
1
4
84
DA
A
Decimal adjust A
1
1
D4
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STK6031
Table 49 Instruction set description: Logic operations
MNEMONIC
DESCRIPTION
BYTES
CYCLES
OPCODE
(HEX)
Logic operations
ANL
A,Rr
AND register to A
1
1
5*
ANL
A,direct
AND direct byte to A
2
1
55
ANL
A,@Ri
AND indirect RAM to A
1
1
56, 57
ANL
A,#data
AND immediate data to A
2
1
54
ANL
direct,A
AND A to direct byte
2
1
52
ANL
direct,#data
AND immediate data to direct byte
3
2
53
ORL
A,Rr
OR register to A
1
1
4*
ORL
A,direct
OR direct byte to A
2
1
45
ORL
A,@Ri
OR indirect RAM to A
1
1
46, 47
ORL
A,#data
OR immediate data to A
2
1
44
ORL
direct,A
OR A to direct byte
2
1
42
ORL
direct,#data
OR immediate data to direct byte
3
2
43
XRL
A,Rr
Exclusive-OR register to A
1
1
6*
XRL
A,direct
Exclusive-OR direct byte to A
2
1
65
XRL
A,@Ri
Exclusive-OR indirect RAM to A
1
1
66, 67
XRL
A,#data
Exclusive-OR immediate data to A
2
1
64
XRL
direct,A
Exclusive-OR A to direct byte
2
1
62
XRL
direct,#data
Exclusive-OR immediate data to direct byte
3
2
63
CLR
A
Clear A
1
1
E4
CPL
A
Complement A
1
1
F4
RL
A
Rotate A left
1
1
23
RLC
A
Rotate A left through the carry flag
1
1
33
RR
A
Rotate A right
1
1
03
RRC
A
Rotate A right through the carry flag
1
1
13
SWAP
A
Swap nibbles within A
1
1
C4
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61
Syntek Semiconductors
STK6031
Table 50 Instruction set description: Data transfer
MNEMONIC
DESCRIPTION
BYTES
CYCLES
OPCODE
(HEX)
Data transfer
MOV
A,Rr
1
1
E*
MOV
A,direct (note 1) Move direct byte to A
Move register to A
2
1
E5
MOV
A,@Ri
Move indirect RAM to A
1
1
E6, E7
MOV
A,#data
Move immediate data to A
2
1
74
MOV
Rr,A
Move A to register
1
1
F*
MOV
Rr,direct
Move direct byte to register
2
2
A*
MOV
Rr,#data
Move immediate data to register
2
1
7*
MOV
direct,A
Move A to direct byte
2
1
F5
MOV
direct,Rr
Move register to direct byte
2
2
8*
MOV
direct,direct
Move direct byte to direct
3
2
85
MOV
direct,@Ri
Move indirect RAM to direct byte
2
2
86, 87
MOV
direct,#data
Move immediate data to direct byte
3
2
75
MOV
@Ri,A
Move A to indirect RAM
1
1
F6, F7
MOV
@Ri,direct
Move direct byte to indirect RAM
2
2
A6, A7
MOV
@Ri,#data
Move immediate data to indirect RAM
2
1
76, 77
MOV
DPTR,#data 16
Load data pointer with a 16-bit constant
3
2
90
MOVC
A,@A+DPTR
Move code byte relative to DPTR to A
1
2
93
MOVC
A,@A+PC
Move code byte relative to PC to A
1
2
83
MOVX
A,@Ri
Move external RAM (8-bit address) to A
1
2
EB, E3
MOVX
A,@DPTR
Move external RAM (16-bit address) to A
1
2
E0
MOVX
@Ri,A
Move A to external RAM (8-bit address)
1
2
F2, F3
MOVX
@DPTR,A
Move A to external RAM (16-bit address)
1
2
F0
PUSH
direct
Push direct byte onto stack
2
2
C0
POP
direct
Pop direct byte from stack
2
2
D0
XCH
A,Rr
Exchange register with A
1
1
C*
XCH
A,direct
Exchange direct byte with A
2
1
C5
XCH
A,@Ri
Exchange indirect RAM with A
1
1
C6, C7
XCHD
A,@Ri
Exchange LOW-order digit indirect RAM with A
1
1
D6, D7
Note
1. MOV A,ACC is not permitted.
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62
Syntek Semiconductors
STK6031
Table 51 Instruction set description: Boolean variable manipulation, Program and machine control
MNEMONIC
DESCRIPTION
BYTES
CYCLES
OPCODE
(HEX)
Boolean variable manipulation
CLR
C
Clear carry flag
1
1
C3
CLR
bit
Clear direct bit
2
1
C2
SETB
C
Set carry flag
1
1
D3
SETB
bit
Set direct bit
2
1
D2
CPL
C
Complement carry flag
1
1
B3
CPL
bit
Complement direct bit
2
1
B2
ANL
C,bit
AND direct bit to carry flag
2
2
82
ANL
C,/bit
AND complement of direct bit to carry flag
2
2
B0
ORL
C,bit
OR direct bit to carry flag
2
2
72
ORL
C,/bit
OR complement of direct bit to carry flag
2
2
A0
MOV
C,bit
Move direct bit to carry flag
2
1
A2
MOV
bit,C
Move carry flag to direct bit
2
2
92
Program and machine control
ACALL
addr11
Absolute subroutine call
2
2
•1
LCALL
addr16
Long subroutine call
3
2
12
RET
Return from subroutine
1
2
22
RETI
Return from interrupt
1
2
32
AJMP
addr11
Absolute jump
2
2
♦1
LJMP
addr16
Long jump
3
2
02
SJMP
rel
Short jump (relative address)
2
2
80
JMP
@A+DPTR
Jump indirect relative to the DPTR
1
2
73
JZ
rel
Jump if A is zero
2
2
60
JNZ
rel
Jump if A is not zero
2
2
70
JC
rel
Jump if carry flag is set
2
2
40
JNC
rel
Jump if carry flag is not set
2
2
50
JB
bit,rel
Jump if direct bit is set
3
2
20
JNB
bit,rel
Jump if direct bit is not set
3
2
30
JBC
bit,rel
Jump if direct bit is set and clear bit
3
2
10
CJNE
A,direct,rel
Compare direct to A and jump if not equal
3
2
B5
CJNE
A,#data,rel
Compare immediate to A and jump if not equal
3
2
B4
CJNE
Rr,#data,rel
Compare immediate to register and jump if not equal
3
2
B*
CJNE
@Ri,#data,rel Compare immediate to indirect and jump if not equal
3
2
B6, B7
DJNZ
Rr,rel
Decrement register and jump if not zero
2
2
D*
DJNZ
direct,rel
Decrement direct and jump if not zero
3
2
D5
No operation
1
1
00
NOP
DRAFT 2007 Apr 02
63
Syntek Semiconductors
STK6031
Table 52 Description of the mnemonics in the Instruction set
MNEMONIC
DESCRIPTION
Data addressing modes
Rr
Working register R0-R7.
direct
128 internal RAM locations and any special function register (SFR).
@Ri
Indirect internal RAM location addressed by register R0 or R1 of the actual register bank.
#data
8-bit constant included in instruction.
#data 16
16-bit constant included as bytes 2 and 3 of instruction.
bit
Direct addressed bit in internal RAM or SFR.
addr16
16-bit destination address. Used by LCALL and LJMP.
The branch will be anywhere within the 64 kbytes Program Memory address space.
addr11
11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes
page of Program Memory as the first byte of the following instruction.
rel
Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps.
Range is −128 to +127 bytes relative to first byte of the following instruction.
Hexadecimal opcode cross-reference
*
8, 9, A, B, C, D, E, F.
•
1, 3, 5, 7, 9, B, D, F.
♦
0, 2, 4, 6, 8, A, C, E.
DRAFT 2007 Apr 02
64
↓
0
0
NOP
1
AJMP
addr11
2
LJMP
addr16
3
RR
A
4
INC
A
5
INC
direct
6
0
ACALL
addr11
LCALL
addr16
RRC
A
DEC
A
DEC
direct
0
2
JB
bit,rel
AJMP
addr11
RET
RL
A
ADD
A,#data
ADD
A,direct
0
3
JNB
bit,rel
ACALL
addr11
RETI
RLC
A
ADDC
A,#data
ADDC
A,direct
4
JC
rel
AJMP
addr11
ORL
direct,A
ORL
direct,#data
ORL
A,#data
ORL
A,direct
5
JNC
rel
ACALL
addr11
ANL
direct,A
ANL
direct,#data
ANL
A,#data
ANL
A,direct
6
JZ
rel
AJMP
addr11
XRL
direct,A
XRL
direct,#data
XRL
A,#data
XRL
A,direct
65
JBC
bit,rel
JNZ
rel
ACALL
addr11
ORL
C,bit
JMP
@A+DPTR
MOV
A,#data
8
9 A B C D E F
1
0
1
INC Rr
2
DEC @Ri
1
7
7
INC @Ri
1
0
1
2
0
1
2
ADD A,@Ri
1
1
0
1
1
2
0
1
2
1
1
MOV
direct,#data
1
AJMP
addr11
ANL
C,bit
MOVC
A,@A+PC
DIV
AB
MOV
direct,direct
9
MOV
DTPR,#data16
ACALL
addr11
MOV
bit,C
MOVC
A,@A+DPTR
SUBB
A,#data
SUBB
A,direct
SUBB A,@Ri
A
ORL
C,/bit
AJMP
addr11
MOV
bit,C
INC
DPTR
MUL
AB
0
1
B
ANL
C,/bit
ACALL
addr11
CPL
bit
CPL
C
CJNE
A,#data,rel
CJNE
A,direct,rel
CJNE @Ri,#data,rel
C
PUSH
direct
AJMP
addr11
CLR
bit
CLR
C
SWAP
A
XCH
A,direct
XCH A,@Ri
D
POP
direct
ACALL
addr11
SETB
bit
SETB
C
DA
A
DJNZ
direct,rel
1
1
0
1
0
0
0
1
7
3
4
6
7
6
7
5
6
7
5
6
7
5
6
7
6
7
6
7
6
7
6
7
5
3
4
5
3
4
2
3
4
1
1
1
1
2
3
4
2
3
4
5
MOV direct,Rr
0
1
2
3
4
5
SUB A,Rr
0
1
2
3
4
5
MOV Rr,direct
0
1
2
3
4
5
CJNE Rr,#data,rel
0
1
2
3
4
5
6
7
6
7
6
7
XCH A,Rr
0
1
XCHD A,@Ri
0
6
MOV Rr,#data
MOV @Ri,direct
0
5
2
3
4
5
DJNZ Rr,rel
0
1
2
3
4
5
Product specification
SJMP
rel
0
4
STK6031
8
MOV direct,@Ri
0
3
XRL A,Rr
MOV @Ri,#data
0
7
ANL A,Rr
XRL A,@Ri
0
6
ORL A,Rr
ANL A,@Ri
0
5
ADDC A,Rr
ORL A,@Ri
0
4
ADD A,Rr
ADDC A,@Ri
0
3
DEC Rr
Syntek Semiconductors
← Second hexadecimal character of opcode →
First hexadecimal character of opcode
8-bit microcontroller
DRAFT 2007 Apr 02
Table 53 Instruction map
0
1
E
MOVX
A,@DTPR
AJMP
addr11
F
MOVX
@DTPR,A
ACALL
addr11
2
3
MOVX A,@Ri
0
1
MOVX @Ri,A
0
Note
1. MOV A, ACC is not a valid instruction.
1
4
5
CLR
A
MOV
A,direct (1)
CPL
A
MOV
direct,A
6
7
8
9 A B C D E F
MOV A,@Ri
0
1
MOV A,Rr
0
1
MOV @Ri,A
0
1
2
3
4
5
6
7
6
7
MOV Rr,A
0
1
2
3
4
5
Syntek Semiconductors
↓
8-bit microcontroller
DRAFT 2007 Apr 02
← Second hexadecimal character of opcode →
First hexadecimal character of opcode
66
Product specification
STK6031
Syntek Semiconductors
STK6031
22 ABSOLUTE MAXIMUM RATING
Table 54 Absolute Maximum Rating
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
voltage on VDD with respect to ground, and SCL, SDA to
ground.
−0.3
+3.8
volts
VI (note 1)
input voltage on any other pin with respect to ground.
−0.3
VDD + 0.3
volts
II, IO
input/output current on any I/O pin
−
±15
mA
Itotal
Absolute sum of all input currents during overload
condition.
100
mA
Ptot
total power dissipation (note 2)
−
1.5
W
Tstg
storage temperature range
−25
+125
°C
Tamb
operating ambient temperature range.
0
+ 70
°C
Notes
1. The following applies to the Absolute Maximum Ratings:
a) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only and functional operation of the device should refer to the normal DC and AC characteristics.
b) This product includes ESD-protection circuits, specifically designed for the protection of its internal circuit.
However, its suggested that conventional ESD precautions be taken.
c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect
to ground.
2. This value is based on the maximum allowable die temperature and the thermal resistance of the package, not on
device power consumption.
Notes to the DC characteristics
1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with
tr = tf = 5ns; VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; Port 0 = VDD; EA = VSS.
2. The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns;
VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; XTAL2 not connected; EA = Port 0 = VDD.
3. The Stop current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = VDD;
EA = XTAL1 = VSS.
4. Pins of Ports 1, 2, 3, and 4 source a transition current when they are being externally driven from HIGH to LOW. The
transition current reaches its maximum value when VIN is approximately 1.6 V.
5. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOL of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make
HIGH-to-LOW transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on
the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an
address latch with a Schmitt Trigger STROBE input.
6. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD ;
VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; XTAL2 not connected; Port 0 = VDD; EA = XTAL1 = VSS.
DRAFT 2007 Apr 02
67
Syntek Semiconductors
STK6031
23 PACKAGE OUTLINE DWRAWING
Please contact Syntek
DRAFT 2007 Apr 02
68
Syntek Semiconductors
STK6031
24 LIFE SUPPORT APPLICATIONS
The STK6031 is not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Syntek customers using or selling STK6031 for use in such applications do so
at their own risk and agree to fully indemnify Syntek for any damages resulting from
such improper use or sale.
DRAFT 2007 Apr 02
69