INFINEON PMB2240

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page
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Revision History
3
1
General Overview
4
1.1
Features
4
1.2
Applications
4
1.3
Functional Description
4
2
Pinning
5
2.1
Pin Description
5
2.2
Pin Configuration
6
2.3
Package Outline
6
3
Functional Block Diagram
7
4
Circuit Description
8
4.1
Block Level Description
8
4.2
Supply Concept
9
4.3
Power Down Conditions
10
4.4
Matching with Timing Signals of GOLD-uC
10
5
Internal Input/Output Circuits
11
6
Electrical Characteristics
12
6.1
Absolute Maximum Ratings
12
6.2
Operational Range
13
6.3
AC/DC Characteristics
14
6.4
Typical modulator measurement results
18
7
Test Circuits
20
7.1
Test Circuit 1
20
7.2
Test board Layout top
21
7.3
Test board Top place
22
7.4
Test board Layout bottom
23
7.5
Test board Bottom place
24
8
Application
25
8.1
Frequency plan for GSM application
25
8.2
Application hint for phase adjust
26
9
S-Parameters and Input/Output impedances
27
9.1
S-Parameters: Transmit Mixer Output MO/MOX
28
9.2
S-Parameters: IF Input IF/IFX
28
9.3
S-Parameters: RF Input RFB1/RFB2
29
9.4
S-Parameters: Output to Receiver RF/RFX
30
9.5
S-Parameters: Modulator Output E/EX
31
9.6
S-Parameters: Modulatór Input LO/LOX
31
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Changes from Data sheet PMB2240 V1.5 ( 08.96 ) to Data sheet PMB2240 V1.6 ( 5.97 )
1
2
6XEMHFW
General
Overview
Pinning
'DWDVKHHW9
3DJH
,WHP
4
1
'DWDVKHHW9
3DJH
,WHP
4
1
&KDQJH
Revised
5
2.1
5
2.1
7
3
7
3
8,9,10
4
8,9,10
4
Pin 9 changed to
VCCPR;
Pin 13 changed to
SLEEP;
Pins 17,18,20,21
changed to GND pins
Prescaler with separate
VCCPR-pin;
Former SLEEP/PR and
SLEEP/RF are merged
to SLEEP;
Oscillator/Buffer for
RFIN removed;
Revised
11
5
11
5
Revised
12
6.1
12
6.1
ESD integrity revised;
Item symbols revised
Operational
range
Prescaler
13
6.2
13
6.2
15
23
15
23
Electrical
Characteristics
10 AC/DC
characteristics
11 S-Parameters
12-18
6
12-17
6
14
6.3 #4
14
6.3 #4
27-30
9
27-31
9
Temperature range 30°C - 85°C
minimum H-voltage
increased to 2.3V
Spec item symbols
revised
Now referred to
Test circuit 1
Smith diagrams of
simulated S-Params
replaced by measured
S-Param-table and I/O
impedances
3
Functional block
diagram
4
Circuit
description
Internal I/O
Circuits
Asolute Maximum ratings
5
6
7
8
9
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Transmitter with I/Q modulator
Direct I/Q modulation
Generation of orthogonal carriers with possibility of phase adjust with external
resistors at OFF1/OFF2
32dB minimum carrier rejection, 35dB minimum SSB rejection with 1 Vpp I/Q drive level
50dB rejection of third order products with 1 Vpp I/Q drive level
-3dBm output power at 1 Vpp I/Q drive level with 200 Ohms load according testcircuit 1
RF oscillator signal is AC-coupled to internal buffer stage (symmetrical or unsymmetrical)
The RF oscillator-signal is buffered for off-chip use, especially for receiver chip PMB2405.
Prescaler for the RF oscillator signal
Possibility to build RF-PLL with integrated prescaler + PMB2306
Possibility to use the IF oscillator signal from the IF-VCO on PMB2405
Possibility to use external source for IF oscillator-signal
Digital parts of fixed IF frequency PLL (fixed-PLL) for IF-VCO on PMB2405
Supply voltage range from 2.7 V to 4.5 V
P-TQFP-48 package
Temperature range -30° to 85°C
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-
Vector modulated digital mobile cellular systems as GSM, DAMPS, PDC,WLAN etc.
Various modulation schemes, such as PM, PSK, FSK, QAM, QPSK, GMSK etc.
Analog systems with FM and AM modulation
Space and power saving optimizations of existing discrete transmitter circuits
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The PMB2240 is a single-chip transmitter which includes a prescaler for the main oscillator signal and
a fixed frequency PLL for the IF oscillator. The transmitter is designed for use in conjunction with the
single-chip receiver PMB2405 and the CMOS PLL PMB2306.
The RF oscillator signal can be supplied from an external source symmetrically as well as
unsymmetrically. The oscillator signal can be buffered for off-chip use, depending on a separate power
down pin.
There is a prescaler by 64/65 for the RF oscillator signal on chip, which can be used to implement a
PLL together with the PMB2306.
The on-chip fixed-PLL consists of the system clock divider, the IF oscillator signal divider, the phase
detector and the charge pump. The IF oscillator signal divider is driven by the oscillator on the
PMB2405 or by an external discrete VCO.
The two oscillator signals are combined in the transmit mixer, and the image sideband and other
mixing products are suppressed with an external interstage filter. The filtered signal reenters the chip
at the modulator inputs LO/LOX. The modulator generates two orthogonal carriers which are mixed
with the modulation signals I and Q in two Gilbert multipliers. The phase between the two carriers can
be fine-adjusted to 90 ° (orthogonality) by two external resistors at OFF1/OFF2 for best SSB
suppression. The outputs of the Gilbert cells are added and amplified by a linear output stage.
The PMB2240 is designed for digital mobile telephones according to the GSM-Standard. The chip can
also be used for other digital systems and the dual mode system.
As part of the Siemens GSM/DCS chipset the derivatives PMB2245 and PMB2247 are offered for the
DCS 1800 and DCS 1900 frequency range.
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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1, 44, 46
GND2
Ground for the PLL-parts and their bias
2
PUPLO2/FP
Power down for fixed-PLL-dividers and phase detector
3
IF
Input for external IF oscillator signal
4
IFX
Input for inverted external IF oscillator signal
5
VCC2
Supply voltage for PLL parts (IF and RF) and their biasing
6
PUPLO2/BU
Power down for IF/IFX input buffer
7
RF
RF oscillator signal to receiver
8
RFX
Inverted RF oscillator signal to receiver
9
VCCPR
Separate supply voltage for RF-PLL prescaler
10
TOUT
Output of RF-PLL prescaler
11
IREF/PLL
Output for reference current for external RF-PLL-chip
12
FMOD
Modulus control for prescaler
13
SLEEP
Power down of RF oscillator input- and output buffer and the prescaler
14,17,18,20
GND3
Ground for RF oscillator + BufRX
15
VCC3
Supply voltage for BufRX and BufRF
16
RFB1
RF oscillator input buffer (inverting input)
19
RFB2
RF oscillator input buffer (non-inverting input)
21,24
GND4
Ground for internal shielding
22
LO
Modulator LO frequency input
23
LOX
Inverted Modulator LO frequency input
25,33
GND1
Ground for modulator and mixer parts + Bias1
26
MO
Mixer output, open collector
27
MOX
Inverted mixer output, open collector
28
GND5
Ground for substrate contacts in the modulator
29
QX
Quadratur modulating inverting input, open base
30
Q
Quadratur modulating input, open base
31
I
In phase modulating input, open base
32
IX
In phase inverted modulating input, open base
34
E
Non-inverting output of modulator, open collector; ESD disconnected
35
EX
Inverting output of modulator, open collector; ESD disconnected
36
VCC1
Supply voltage for modulator and mixer parts + Bias1
37
TREF
Temperature compensated DC reference voltage output for modulator
I/Q -inputs via GMSK baseband circuit
38
TXON1
Power down for modulator and mixer parts + Bias1
39
OFF1
Phase error adjustment of orthogonal carriers with constant R
40
OFF2
Phase error adjustment of orthogonal carriers with constant R
41
T3
Test pin 3
42
PDBUFRX
Power down for "BufRX"
43
n.c.
not bonded
45
CHP
Phase-detector output for external loop filter (charge pump)
47
RREF/PLL
To be connected to GND via resistor to determine IREF for RF-PLL
48
FREF
Input of system reference clock
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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The GSM transmitter PMB2240 contains a number of functions that have been realised with multiple
chips earlier:
- Oscillator signal input balanced or unbalanced
- RF-PLL prescaler
- IF-PLL dividers and phase detection
- TX - mixer
- I/Q modulator
The PMB2240 V1.6 is designed to be used with an external RF oscillator module. On chip this signal is
AC-coupled to an internal buffer stage. Therefore the RF input is suitable for symmetrical or single
ended use. There is no need for an external DC-bias of the RF input. The active parts of the IF
oscillator are located on the receive chip PMB2405.
A buffer BufRX, which can be powered down by pin PDBUFRX, is used to transmit the RF oscillator
signal to the receiver chip to drive the RF receive mixer. A special input buffer BufTX receives the IF
oscillator signal from the receive chip or an external source.
The RF oscillator signal is divided by the integrated 64/65 prescaler which can be connected to the
CMOS PLL circuit PMB2306 for the RF oscillator PLL. The supply pin VCCPR is a separate prescaler
supply, which openes the possilility to run the prescaler and the rest of the RF synthesizer on a supply
voltage that is different from the supplies of the rest of the chip.
For the IF-PLL the active oscillator structures on the PMB2405 or an external VCO module can be
used. The PMB2240 V1.6 contains the digital parts tor the IF oscillator PLL (fixed-PLL): the IFfrequency and system clock dividers and a phase detector plus charge pump are integrated to lock the
IF oscillator to the external system clock. The oscillator signal drives the divider by 2 in front of the
transmit mixer. The phase locked IF- and RF- signals are converted into the transmit band (e.g. 880 915 MHz for GSM) by the TX- mixer. The mixer output signal leaves the chip at MO/MOX and passes
an external interstage filter to provide suppression of unwanted products. This signal reenters the chip
at the modulator input LO/LOX.
The LO signal is divided into two orthogonal carriers at the transmit frequency. The phase between the
two carriers can be fine-adjusted to 90 ° (orthogonality) by two external resistors at OFF1/OFF2 for
maximum SSB suppression. The modulator consists of two Gilbert multipliers, where the modulating
signals I(t) and Q(t) are multiplied with the RF-carriers. The outputs of both Gilbert cells are added and
amplified by a linear output stage. The modulated transmit signal is available at E/EX and is fed into a
transmitter power amplifier.
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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There are four independent supply voltages ( VCC1-3,VCCPR ) and ground rails ( GND1-4 ) to
decouple the modulator/mixer parts, the synthesizer parts, and the RFVCO parts.
The supply pin VCCPR is a separate prescaler supply, which openes the possilility to run the prescaler
together with the rest of the RF synthesizer on a supply voltage that is different from the supplies of the
rest of the chip
GND4 is a special shielding ground to decrease crosstalk between the separately supplied blocks.
GND5 collects the substrate contacts in the modulator and mixer.
It is recommended to connect all GND pins to a common GND on the board.
In the following figure the chip schematic is partitioned according to its supply rails.
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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The PMB 2240 has five Power down inputs.
PD = Low means that the respective part of the chip is in power down mode.
TXON1:
TXON1 /\ PUPLO2/FP
SLEEP:
PUPLO2/BU:
PUPLO2/FP:
PDBUFRX /\ SLEEP
Modulator, mixer, Bufmi1, Bufmi2
%2 divider
BufRF, prescaler with its input buffer BufPLL
Input buffer BufTX for external IF oscillator-signal
fixed-PLL, (%492; %13; phase detector, charge pump)
BufRX
For normal operation only three modes are used: sleep mode, TX-mode, RX-mode. Depending on the
application some power down-pins can be combined, and others can be fixed to supply rails.
0DWFKLQJZLWK7LPLQJ6LJQDOVRI*2/'X&
In application with PMB2405 and GOLD-uC the power down pins of PMB2240 must be connected to
the timing signals of GOLD-uC as follows:
PMB 2240
TXON1
PUPLO2/BU, PUPLO2/FP
SLEEP, PDBUFRX
connected to
connected to
connected to
GOLD-uC
TXON1
PUPLO2
general purpose port pin
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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The maximum ratings may not be exceeded under any circumstances, not even momentarily and
individually, as permanent damage to the IC will result.
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PD[
1
Supply Voltage
VCC
-0.3
5.0
V
2
Input/Output Voltage
VIO
-0.3
5.0
V
3
Open Collector Output
Voltage at E/EX
VOCE
VCC - 1.5
VCC + 1.0
V
4
Open Collector Output
Voltage at MO/MOX
VOCM
-0.3
5.0
V
5
Differential Input
Voltage
(any differential Input)
VID
2
V
6
Junction Temperature
TJ
-40
125
°C
7
Storage Temperature
TS
-55
125
°C
8
Thermal Resistance
(junction to ambient)
RthJA
165
K/W
9
ESD integrity *
VESD
+1000
V
* exception:
-1000
5HPDUNV
according
MIL-Std. 883D,
method 3015.7
Pin 47 to GND and a negative Pulse to pin 11
=> 800V ESD-integrity
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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Within the operational range the IC operates as described in the circuit description. The AC/DC
characteristics limits are not guaranteed.
VCC = 2.7V to 4.5V; TA = -30 to 85°C;
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1
RFB1/RFB2 Input Level
PRFIN
-10
0
dBm
2
RFB1/RFB2 Input
Frequency
fRFIN
900
1300
MHz
3
IF/IFX Input Level
PIFIN
-15
0
dBm
4
IF/IFX Input Frequency
fIFIN
400
600
MHz
5
LO/LOX Input Level
PLO
-15
0
dBm
6
LO/LOX Input Frequency
fLO
800
1000
MHz
7
Mixer output Frequency
Range
fMO
800
1000
MHz
8
PD-Signals Voltage-L
VPDL
0
0.8
V
9
PD-Signals Voltage-H
VPDH
2.0
VCC
V
wanted
sideband
Note:
Power levels are referred to impedance of 50 Ohms
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and
ambient temperature range. Typical characteristics are the median of the production.
VCC = 2.7V/4.5V; TA = 25°C;
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Supply Current
all powered up
Ivcc1
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Imo+
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Ivcc2
Ivcc3
Ivccpr
1
2
Supply Current
all powered down
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TXON1
& PUPLO2/FP
& PUPLO2/BU
& SLEEP
& PDBUFRX
=
HIGH
1
TXON1
& PUPLO2/FP
& PUPLO2/BU
& SLEEP
& PDBUFRX
=
LOW
1
900 MHz
1
PLQ
W\S
PD[
16
9
7
22
13
10
29
18
13
mA
mA
mA
5
9.3
2.5
6.3
11
3.3
7.5
13.2
4
mA
mA
mA
2
2
2
uA
uA
uA
2
2
2
uA
uA
uA
Ivcc1
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Imox
Ivcc2
Ivcc3
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3
Output impedance
(open collector diff.
output)
see S-parameter 9.1
4
Output level
PMO
-18
-15
5
Carrier suppression
aCmix
25
30
6
Output Frequency
fMO
800
1000
MHz
-12
dBm
dB
1
wanted sideband
1
,)LQSXWDW,),);
7
Input Level
PIFIN
-15
110
0
600
dBm
mVpp
*
1
8
Input Frequency
fIFIN
400
600
MHz
1
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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9
lock in time
10
Power on delay
11
Input level at
FREF
12
Output current at
CHP
tI
250
usec
Application hint
tpo
0.3
usec
Application hint
high input levels
may cause spurious
problems
VFREFI
0.4
1
2
Vpp
1
ICHP
+-450
+-600
+-750
uA
1
V
1
2XWSXWWRUHFHLYHU5)5);
13
Internal DC bias
14
Output impedance
15
Output level
VRFDC
VCC 0.6
see S-parameter 9.4
PRFOUT
-11
-8
-5
dBm
f = 1200 MHz
1
5)LQSXWDW5)%5)%
16
Input Level
PRFIN
-10
0
dBm
1
17
Input Frequency
fRFIN
900
1300
MHz
1
/2LQSXWDW/2/2;
18
Input impedance
see S-parameter 9.6
19
Input Level
PLO
-15
0
dBm
20
Input Frequency
fLO
800
1000
MHz
21
suppression of
image in mixer
output signal
aIM
14
dB
into 50 Ohm
1
1
Application hint
3UHVFDOHU
22
Input at FMOD
voltage-L
VFMOD
0
0.8
V
1
23
Input at FMOD
voltage-H
VFMOD
2.3
VCC
V
1
24
Output DC level
at TOUT
VTOUTDC
VCC-1
VCC0.7
V
1
25
Output AC
amplitude at TOUT
VTOUTAC
160
300
mVpp
f = 13.5MHz to
20.5MHz
1
The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All
rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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26
External voltage
of current sink
fed to IREF/PLL
VIREF/PLL
27
Current sourced
at IREF/PLL
IIREF/PLL
100**
28
Temperature
dependency of
current sourced
at IREF/PLL *
IIREF/PLL
+-2
1.2
V
1
360
uA
dependent of
resistor value at
RREF/PLL ***
%
temperature range:
-30 to 85 °C
nominal current:
300uA
1
0RGXODWRULQSXWV,,;DQG44;
29 I-IX and Q-QX
VI-IX,
differential input level V
Q-QX
500
30 Recommended
VDCext
range for ext DC
voltage to compensate internal offset at
I-IX and Q/QX *
31 Reference voltage
for I,Q modulating
inputs
VTREF
1.25
32 Resistive load at
TREF *
RTREF
3
33 Input base current
II/Q_DC
1
34 Differential input
resistance *
RI-IX
50
35 Differential input
capacitance *
CI-IX
36 Input frequency *
fI-IX
fQ-QX
1.35
1000
mVpp
15
mV
1.45
V
Reference to external
GMSK
basebandcircuit to
bias I and Q
of PMB2240
(temperature
compensated)
kOhm
6
12
uA
kOhm
1
at 200 kHz
pF
10
MHz
* Design hint
** required by PMB2306 R19 = 6.8kΩ
*** R19 at pin RREF/PLL gives constant PLL reference current at pin IREF/PLL:
( R19max = open
-> IIREF/PLLmin = 0,
R19min = 2 KOhm -> IIREF/PLLmax =360uA)
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0RGXODWRURXWSXW((;fLO = 900 MHz; fI-IX = fQ-QX =10MHz;
37 Output impedance
see S-parameter 9.5
(open collector diff.
output)
38 Output power
PE_b
’
39 Carrier suppression
aCmod
40 Single sideband
suppression
aSSB
41 Suppression of
third order
distortion products
aIM3
42 Signal to noise
ratio *
-12
-9
-6
dBm
cond1 **
1
-6
-3
0
dBm
cond2 ***
1
26
32
dB
cond1 **
1
32
38
dB
cond2 ***
1
dB
with 90° phase shift
between I and Q;
ROFF1,ROFF2 tuned
to maximum SSB
suppression ( appl.
hint: fig.1,sec. 8.3)
1
62
dB
cond1 **
1
50
dB
cond2 ***
1
-139
dBc/Hz
cond1 **
PLO = -8 dBm foffset
= 20MHz
1
-142
dBc/Hz
cond2 ***
PLO = -8 dBm foffset
= 20MHz
1
35
S/N
* Design hint
** cond1 means VI-IX = VQ-QX = 500 mVpp
*** cond2 means VI-IX = VQ-QX = 1 Vpp
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The following measurements refer to Testcircuit 1 ( item , page 21)
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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V
A
ROFF1/ROFF2 = 0 ... 600 Ohm; see application hint on page 26
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GSM-Transmitter
7.2
PMB 2240 V 1.6
Test board Layout top, (M 2:1)
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rights created by patent grant or registration of a utility model or design, are reserved.
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GSM-Transmitter
7.3
PMB 2240 V 1.6
Test board Top place
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rights created by patent grant or registration of a utility model or design, are reserved.
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GSM-Transmitter
PMB 2240 V 1.6
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rights created by patent grant or registration of a utility model or design, are reserved.
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GSM-Transmitter
PMB 2240 V 1.6
The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including
rights created by patent grant or registration of a utility model or design, are reserved.
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In the application the IF oscillator on the receive chip is locked at a frequency of 492 MHz by the fixed-PLL
circuit. The RF oscillator module is tuned from 1126 MHz to 1206 MHz.
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The LO level for maximum SSB suppression can be tuned to every value within its operational range (
-15 dBm to 0 dBm ) by appropriate choice of ROFF1/ROFF2.
At pins OFF1 and OFF2 always a resistor or a short cicuit to ground is required. The recommended
range of values is:
0 > ROFF1,ROFF2 < 600 Ohm.
In fig. 1 the maximum single sideband suppression (assb) is tuned to -7dBm LO input power
accordinng test circuit 1. ROFF1=0 and ROFF2=200 Ohms.
The LO level can vary +/- 4dB around its optimum value with assb < -35dB.
6LQJOH6LGHEDQGVXSSUHVVLRQDVVEYHUVXVORLQSXWSRZHU3OR
DVVEG%
3ORG%P
ILJ Phase adjust with ROFF1=short, ROFF2=200 Ohms
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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*607UDQVPLWWHU
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63DUDPHWHUVDQG,QSXW2XWSXW,PSHGDQFHV
The S-parameters provided in this section are based on measurements.
Measurement setup for differential in-/outputs:
In/Out
Inx/Outx
Port1
DUT
Port2
The input/output impedances are calculated from these parameters.
The impedances are given as equivalent circuit with lumped elements for differential and single ended
in-/outputs.
The high frequency in-/outputs in this section are base inputs or collector outputs.
As equivalent circuit for these in-/outputs a resistor Rp in parallel to a capacitance Cp is derived:
differential
Rpd
single
ended
Cpd
Rps
Cps
The S-parameters are available on disk.
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rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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*607UDQVPLWWHU
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7UDQVPLW0L[HU2XWSXW0202;
S-parameters:
f
S11
GHz
MAG
0.80
0.957
0.85
0.951
0.90
0.946
0.95
0.940
1.00
0.935
S21
ANG
-23.7
-25.5
-27.1
-28.9
-30.7
MAG
0.093
0.098
0.103
0.107
0.111
S12
ANG
70.4
69.3
68.2
67.2
66.8
MAG
0.092
0.097
0.102
0.106
0.109
S22
ANG
71.7
70.7
69.4
68.4
68.0
MAG
0.952
0.944
0.932
0.913
0.892
ANG
-22.4
-24.3
-26.2
-28.0
-28.5
Output impedance at MO/MOX:
5SG
5SV
P
K
2
N
LQ
5
)
S
LQ
&
&SG
&SV
ILQ0+]
ILQ0+]
,),QSXW,),);
S-parameters:
f
S11
GHZ
MAG
0.40
0.978
0.45
0.974
0.50
0.970
0.55
0.967
0.60
0.963
S21
ANG
-15.0
-16.8
-18.8
-20.9
-23.0
MAG
0.057
0.063
0.070
0.076
0.082
S12
ANG
74.0
72.5
70.8
69.2
67.5
MAG
0.057
0.064
0.070
0.076
0.082
S22
ANG
73.7
72.0
70.2
68.4
66.7
MAG
0.977
0.972
0.968
0.963
0.957
ANG
-14.7
-16.6
-18.5
-20.5
-22.5
Input impedance at IF/IFX:
5SG
5SV
P
K
2
N
Q
L
5
&SG
&SV
)
S
Q L
&
ILQ0+]
ILQ0+]
The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All
rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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*607UDQVPLWWHU
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5),QSXW5)%5)%
S-parameters:
f
GHZ
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.300
S11
MAG
0.850
0.840
0.832
0.823
0.815
0.807
0.799
0.792
0.785
S21
ANG
-29.7
-31.5
-33.2
-34.8
-36.5
-38.1
-39.7
-41.3
-42.8
MAG
0.020
0.020
0.021
0.022
0.022
0.022
0.023
0.023
0.023
S12
ANG
43.1
41.8
41.0
40.3
39.1
37.8
37.7
35.8
36.0
MAG
0.021
0.022
0.024
0.025
0.026
0.027
0.028
0.028
0.028
S22
ANG
47.5
46.1
45.4
43.9
41.5
38.8
36.6
33.1
31.1
MAG
0.843
0.836
0.830
0.823
0.817
0.810
0.803
0.797
0.790
ANG
-31.8
-33.6
-35.4
-37.2
-39.0
-40.8
-42.6
-44.3
-46.0
Input impedance:
SG
SV
P
K
2
N
LQ
5 )
S
LQ
&
&SG
&SV
ILQ0+]
ILQ0+]
The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All
rights, including rights created by patent grant or registration of a utility model or design, are reserved.
Siemens AG
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*607UDQVPLWWHU
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2XWSXWWR5HFHLYHU5)5);
S-parameters:
f
GHZ
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
S11
MAG
0.556
0.543
0.532
0.524
0.520
0.524
0.534
0.551
0.572
ANG
-19.6
-19.5
-19.2
-18.3
-17.2
-16.0
-14.8
-14.2
-14.1
S21
MAG
0.164
0.165
0.164
0.161
0.155
0.144
0.132
0.116
0.101
S12
MAG
0.149
0.168
0.187
0.207
0.228
0.248
0.267
0.283
0.297
ANG
21.2
14.7
7.5
-0.6
-9.8
-19.6
-31.1
-43.9
-59.6
ANG
122.2
117.8
113.2
108.3
103.1
97.3
91.5
85.2
78.7
S22
MAG
0.789
0.795
0.800
0.805
0.806
0.803
0.796
0.783
0.765
ANG
-20.8
-23.4
-26.3
-29.4
-32.8
-36.3
-40.0
-43.6
-47.2
Output impedance at RF/RFX:
P
K
2
N
)
S
LQ
5
SG
SV
&SG
&SV
LQ
&
ILQ0+]
ILQ0+]
The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All
rights, including rights created by patent grant or registration of a utility model or design, are reserved.
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*607UDQVPLWWHU
30%9
0RGXODWRU2XWSXW((;
S-parameters:
f
S11
GHz
MAG
0.80
0.972
0.85
0.960
0.90
0.951
0.95
0.948
1.00
0.949
S21
ANG
-26.2
-28.0
-29.4
-30.8
-32.4
MAG
0.116
0.120
0.125
0.131
0.137
S12
ANG
65.2
64.1
63.3
62.4
60.9
MAG
0.126
0.131
0.136
0.142
0.148
S22
ANG
64.7
63.2
61.9
60.7
58.9
MAG
0.957
0.947
0.946
0.948
0.950
ANG
-25.2
-26.4
-27.8
-29.3
-31.2
Output impedance at E/EX:
SG
SV
P
K
2
N
LQ
5
)
S
LQ
&
&SG
&SV
ILQ0+]
S22
MAG
0.887
0.871
0.863
0.854
0.850
ANG
-32.1
-34.1
-35.9
-37.9
-40.0
ILQ0+]
0RGXODWRU,QSXW/2/2;
S-parameters:
f
S11
GHZ
MAG
0.80
0.896
0.85
0.888
0.90
0.879
0.95
0.871
1.00
0.861
ANG
-29.6
-31.7
-33.9
-36.1
-38.4
S21
MAG
0.125
0.130
0.136
0.140
0.145
S12
MAG
0.126
0.131
0.136
0.141
0.145
ANG
62.4
61.2
59.9
58.7
57.1
ANG
62.4
61.2
59.6
58.4
56.8
Input impedance at LO/LOX:
5SG
5SV
P
K
2
N
Q
L
5
)
S
Q
L
&
&SG
&SV
ILQ0+]
ILQ0+]
The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All
rights, including rights created by patent grant or registration of a utility model or design, are reserved.
Siemens AG
31
05.97