ICS9220
Integrated
Circuit
Systems, Inc.
TM
TM
Programmable Rambus XDR Clock Generator
General Description
Features
The ICS9220 clock generator provides Programmable
TM
clock signals to support the Rambus XDR memory
subsystem and Redwood logic interface. The ICS9220
has been optimized for 100MHz reference input that may
or may not be modulated for spread spectrum. The
ICS9220 provides 2 differential clock pairs in a space
saving 28-pin TSSOP package and provides an off-theshelf high-performance interface solution.
•
•
Figure 1 shows the major components of the ICS9220
XDR Clock Generator. These include the a PLL, a Bypass
Multiplexer and two differential output buffers. The outputs
can be disabled by a logic low on the OE pin. An output
is enabled by the combination of the OE pin being high,
and 1 in its SMBus Output control register bit.
The PLL receives a reference clock, CLK_INT/C and
outputs a clock signal at a frequency equal to the input
frequency times a multiplier. Table 2 shows the multipliers
selectable via the SMBus interface. This clock signal is
then fed to the differential output buffers to drive the
enabled clocks. Disabled outputs are set to Hi-Z. The
Bypass mode routes the input clock, CLK_INT/C, directly
to the differential output buffers, bypassing the PLL.
•
•
•
•
•
300 - 700 MHz clock source
2 open-drain differential output drives with short
term jitter < 40ps
Spread spectrum compatible
Reference clock is differential or single-ended
100MHz
SMBus programmability for:
- frequency multiplier
- output enable
- operating mode
Support systems where XDR subsystem is
asynchronous to other system clocks
2.5V power supply
Up to four ICS9220 devices can be cascaded on the same
SMBus. Table 3 shows the SMBus addressing and control
for the four devices.
Block Diagram
Pin Configuration
OE
RegA
BYPASS#/PLL
CLK_INT
CLK_INC
Bypass
MUX
ODCLK_T0
ODCLK_C0
OE
RegB
ODCLK_T1
ODCLK_C1
PLL
SMBCLK
SMBDAT
AS1
AS2
AVDD2.5
AGND
IREFY
AGND
CLK_INT
CLK_INC
VDD2.5
GND
SMBCLK
SMBDAT
OE
AS1
AS2
BYPASS#/PLL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ICS9220
OE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD2.5
GND
GND
ODCLK_T0
ODCLK_C0
GND
VDD2.5
VDD2.5
GND
ODCLK_T1
ODCLK_C1
GND
GND
VDD2.5
28-Pin 4.4mm TSSOP
1227G—11/05/07
XDR is a trademark of Rambus
ICS9220
Pin Descriptions
PIN #
1
2
PIN NAME
AVDD2.5
AGND
PIN TYPE
PWR
PWR
3
IREFY
OUT
4
5
6
7
8
9
10
AGND
CLK_INT
CLK_INC
VDD2.5
GND
SMBCLK
SMBDAT
PWR
IN
IN
PWR
PWR
IN
I/O
11
OE
IN
12
13
AS1
AS2
IN
IN
14
BYPASS#/PLL
IN
15
16
17
VDD2.5
GND
GND
PWR
PWR
PWR
18
ODCLK_C1
OUT
19
ODCLK_T1
OUT
20
21
22
23
GND
VDD2.5
VDD2.5
GND
PWR
PWR
PWR
PWR
24
ODCLK_C0
OUT
25
ODCLK_T0
OUT
26
27
28
GND
GND
VDD2.5
PWR
PWR
PWR
DESCRIPTION
2.5V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
This pin establishes the reference current for the differential clock
pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current.
Analog Ground pin for Core PLL
"True" reference clock input.
"Complementary" reference clock input.
Power supply, nominal 2.5V
Ground pin.
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Default SMBus Address Select.
Default SMBus Address Select.
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Power supply, nominal 2.5V
Ground pin.
Ground pin.
"Complementary" side of open drain differential clock output. This
open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open drain
output needs an external resistor network..
Ground pin.
Power supply, nominal 2.5V
Power supply, nominal 2.5V
Ground pin.
"Complementary" side of open drain differential clock output. This
open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open drain
output needs an external resistor network..
Ground pin.
Ground pin.
Power supply, nominal 2.5V
1227G—11/05/07
2
ICS9220
General SMBus serial interface information for the ICS9220
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address per table 3
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Write Operation
Controlle r (Host)
starT bit
T
Controller (host) will send start bit.
Controller (host) sends the write address per table 3
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address per table 3
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
ICS (Sla ve/Re ce ive r)
T
Slave Address table 3
WR
W Rite
Controlle r (Host)
starT bit
ICS (Sla ve/Re ce ive r)
Slave Address table 3
WR
W Rite
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
Data Byte Count = X
RT
ACK
Slave Address table 3
RD
ReaD
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
Repeat starT
stoP bit
Byte N + X - 1
N
P
1227G—11/05/07
3
Not acknowledge
stoP bit
ICS9220
SMBus Table: Output Enable Control Register
Byte 0
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
-
Test Mode
Reserved For Vendor
RW
Disable
Enable
0
Bit 6
-
Reserved
Reserved
RW
-
-
0
Bit 5
-
Reserved
Reserved
RW
-
-
0
Bit 4
-
Reserved
Reserved
RW
-
-
0
Bit 3
-
Reserved
Reserved
RW
-
-
0
Bit 2
-
Reserved
Reserved
RW
-
-
0
Bit 1
-
ODCLK_T/C1
Output Control
RW
Disable
Enable
1
Bit 0
-
ODCLK_T/C0
Output Control
RW
Disable
Enable
1
Name
Control Function
Type
0
1
PWD
-
-
0
SMBus Table: Address Control Register
Byte 1
Pin #
Bit 7
-
Reserved
Reserved
R
Bit 6
-
AS2
SMBus Address Select
R
Bit 5
-
AS1
SMBus Address Select
R
Bit 4
-
Reserved
Reserved
R
-
-
0
Bit 3
-
Reserved
Reserved
R
-
-
0
Bit 2
-
Reserved
Reserved
R
-
-
0
Bit 1
-
Reserved
Reserved
R
-
-
0
Bit 0
-
Reserved
Reserved
R
-
-
0
Control Function
Type
0
1
PWD
R
-
-
0
R
-
-
0
x
See Table 3
x
SMBus Table: Vendor & Revision ID Register
Byte 2
Pin #
Name
Bit 7
-
RID 3
Bit 6
-
RID 2
Bit 5
-
RID 1
R
-
-
0
Bit 4
-
RID 0
R
-
-
0
Bit 3
-
VID 3
R
-
-
0
Bit 2
-
VID 2
R
-
-
0
Bit 1
-
VID 1
R
-
-
0
Bit 0
-
VID 0
R
-
-
1
Revision ID
Vendor ID
1227G—11/05/07
4
ICS9220
SMBus Table: Reserved Register
Byte 3
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
-
Reserved
Reserved
RW
-
-
0
Bit 6
-
Reserved
Reserved
RW
-
-
0
Bit 5
-
Reserved
Reserved
RW
-
-
0
Bit 4
-
Reserved
Reserved
RW
-
-
0
Bit 3
-
Reserved
Reserved
RW
-
-
0
Bit 2
-
Reserved
Reserved
RW
-
-
0
Bit 1
-
Reserved
Reserved
RW
-
-
0
Bit 0
-
Reserved
Reserved
RW
-
-
0
Name
Control Function
Type
0
1
PWD
SMBus Table: Reserved Register
Byte 4
Pin #
Bit 7
-
Reserved
Reserved
RW
-
-
0
Bit 6
-
Reserved
Reserved
RW
-
-
0
Bit 5
-
Reserved
Reserved
RW
-
-
0
Bit 4
-
Reserved
Reserved
RW
-
-
0
Bit 3
-
Reserved
Reserved
RW
-
-
0
Bit 2
-
Reserved
Reserved
RW
-
-
0
Bit 1
-
Reserved
Reserved
RW
-
-
0
Bit 0
-
Reserved
Reserved
RW
-
-
0
SMBus Table: VCO Frequency Control Register
Byte 5
Name
Control Function
Type
0
1
PWD
Bit 7
-
Pin #
Post Divider
PLL Post Divide
RW
Divide by 2
Divide by 4
1
Bit 6
-
Reserved
Reserved
RW
-
-
0
Bit 5
-
Reserved
Reserved
RW
-
-
0
Bit 4
-
Reserved
Reserved
RW
-
-
0
Bit 3
-
M DIV3
Bit 2
-
M DIV2
Bit 1
-
M DIV1
Bit 0
-
M DIV0
RW
M Divider Programming
b(3:0)
RW
RW
RW
1227G—11/05/07
5
The decimal representation of M
and N Divider in Byte 5 and 6 will
configure the PLL VCO frequency.
VCO frequency = 100 x
{[NDIV(5:0)+2]/[MDIV(3:0)+2]}
0
0
1
0
ICS9220
SMBus Table: VCO Frequency Control Register
Byte 6
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
-
Reserved
RW
-
-
0
Bit 6
-
Reserved
RW
-
-
0
Bit 5
-
N DIV5
RW
Bit 4
-
N DIV4
Bit 3
-
N DIV3
Bit 2
-
N DIV2
RW
Bit 1
-
N DIV1
RW
Bit 0
-
N DIV0
RW
N Divider Programming
b(5:0)
RW
RW
0
The decimal representation of M
and N Divider in Byte 5 and 6 will
configure the PLL VCO frequency.
VCO frequency = 100 x
{[NDIV(5:0)+2]/[MDIV(3:0)+2]}
0
1
0
1
0
SMBus Table: Byte Count Register
Byte 7
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
Reserved
0
Bit 6
Reserved
0
Bit 5
Reserved
0
Bit 4
-
BC4
Bit 3
-
BC3
Bit 2
-
BC2
Bit 1
-
BC1
RW
Bit 0
-
BC0
RW
RW
RW
Byte Count
Programming
1227G—11/05/07
6
RW
0
Writing to this register will configure
how many bytes will be read back,
default is 07 = 7 bytes
0
1
1
1
ICS9220
PLL Multiplier
Table 2 shows the frequency multipliers in the PLL, selectable by programming the MULT0, MULT1 and MULT2 bits
in the SMBus Multiplier Control register. Power up default is 4.
Table 2. PLL Multiplier Programming Selection
PostDiv
M
N
OUTPUT
VCO
B5b7
B5b(3:0) B6b(5:0)
ASIC Multiplier
6
8
300.00000
4
1200.0000
6
18
Byte 5
Hex
84
325.00000
4
1300.0000
4
13
82
0B
1300.00
1950.00
2600.00
350.00000
4
1400.0000
6
21
84
13
1400.00
2100.00
2800.00
366.66667
4
1466.6667
6
22
84
14
1466.67
2200.00
2933.33
375.00000
4
1500.0000
4
15
82
0D
1500.00
2250.00
3000.00
383.33333
4
1533.3333
6
23
84
15
1533.33
2300.00
3066.67
400.00000
4
1600.0000
6
24
84
16
1600.00
2400.00
3200.00
416.66667
4
1666.6667
6
25
84
17
1666.67
2500.00
3333.33
425.00000
2
850.0000
4
17
02
0F
1700.00
2550.00
3400.00
433.33333
2
866.6667
6
26
04
18
1733.33
2600.00
3466.67
450.00000
2
900.0000
6
27
04
19
1800.00
2700.00
3600.00
466.66667
2
933.3333
6
28
04
1A
1866.67
2800.00
3733.33
475.00000
2
950.0000
4
19
02
11
1900.00
2850.00
3800.00
483.33333
2
966.6667
6
29
04
1B
1933.33
2900.00
3866.67
500.00000
2
1000.0000
6
30
04
1C
2000.00
3000.00
4000.00
516.66667
2
1033.3333
6
31
04
1D
2066.67
3100.00
4133.33
533.33333
2
1066.6667
6
32
04
1E
2133.33
3200.00
4266.67
550.00000
2
1100.0000
6
33
04
1F
2200.00
3300.00
4400.00
566.66667
2
1133.3333
6
34
04
20
2266.67
3400.00
4533.33
583.33333
2
1166.6667
6
35
04
21
2333.33
3500.00
4666.67
600.00000
2
1200.0000
6
36
04
22
2400.00
3600.00
4800.00
616.66667
2
1233.3333
6
37
04
23
2466.67
3700.00
4933.33
633.33333
2
1266.6667
6
38
04
24
2533.33
3800.00
5066.67
25
26
2600.00
3900.00
5200.00
2666.67
4000.00
5333.33
2
1300.0000
6
39
04
650.00000
2
1333.3333
6
40
04
666.66667
NOTE: All output values based on 100.000000MHz input clock
1227G—11/05/07
7
Byte 6
Hex
4
10
1200.00
1800.00
2400.00
ICS9220
Device ID and SMBus Device Address
The device ID (SMB_A(2:1)) is part of the SMBus device address. The least significant bit of the address designates
a write or read operation. Table 3 shows the addresses for four ICS9220 devices on the same SMBus.
Table 3. SMBus Device Addresses
ICS 9220
Device
Operation
Hex
Address
Write
D8
0
1
2
3
Read
D9
Write
DA
Read
DB
Write
DC
Read
DD
Write
DE
Read
DF
8 bit SMBus De vice Addre ss Including Oper.
Control Function
AS2
AS1
0
0
Wr#/Rd
0
1
0
1
0
1
11011
1
0
0
1
1
1
0
1
Operating Modes
Table 4: Operating Modes
Byte 1
Byte 0
OE
BYPASS#/
PLL
Bit 7
Bit 1
Bit 0
L
X
X
X
X
H
X
1
X
X
H
L
0
X
X
H
H
0
0
0
Z
Z
H
H
0
0
1
Z
CLK_INT/C
H
H
0
1
0
CLK_INT/C
Z
H
H
0
1
1
CLK_INT/C
CLK_INT/C
ODCLK_T/C1 ODCLK_T/C0
Z
Z
Reserved for Vendor Test
CLK_INT/C
Notes
1 Bypass Mode
2 Power up default mode
1227G—11/05/07
8
ICS9220
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
DC Characteristics - Inputs
TA = 0°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
VDD2.5,
AVDD
2.375
2.625
V
High-level input voltage
VIHCLK
0.6
0.95
V
-0.15
0.15
V
0.2
0.55
V
0.15
V
0.35
0.5VDD2.5
V
VTH +
0.3
2.625
V
-0.15
VTH - 0.3
V
1.4
2.625
V
-0.15
0.8
V
Low-level input voltage
VILCLK
Crossing point voltage
VIXCLK
Difference in crossing point voltage
VIXCLK
Input threshold voltage
VTH
High-level input voltage for single-ended
CLK_IN
VIHSE
Low-level input voltage for single-ended
CLK_IN
VILSE
High-level input voltage
VIH
Low-level input voltage
VIL
High-level input voltage - SMBus
Low-level input voltage - SMBus
VIHSMB
VILSMB
CLK_INT, CLK_INC
1
Singled-ended CLK_IN
OE, AS1, AS2, BYPASS#/PLL
SMBCLK, SMBDAT
1.4
-0.15
2
3.465
0.8
V
V
Notes:
1 When using singled-ended clock input, VTH is supplied to CLK_INTC as shown in Figure 2. Duty cycle of
singled-ended CLK_IN is measured at VTH.
2 This range of SMBus input high voltages allows the 9220 to co-exist with 3.3V, 2.5V and 1.8V devices on
the same SMBus.
1227G—11/05/07
9
ICS9220
DC Characteristics - Outputs
TA = 0°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Power within spec to outputs
tPU
Power up latency
within spec
MAX
UNITS
3
ms
3
ms
State transition latency1
tCO
SMBus or Mode Select
transition to outputs valid and
within spec
Differential output crossing voltage
VOX
Measured as shown in Fig. 3
0.9
1.1
V
Output Voltage Swing (peak-to-peak
singled ended)
VCOS
Measured as shown in Fig. 3.
Excludes over and undershoot.
300
350
mV
Absolute output low voltage
VOL, ABS
Measured at ODCLK_T/C pins
0.85
Reference Voltage for swing control
current
VISET
VDD = 2.3V, VOUT = 1V
0.98
Ratio of output low current to reference
current at typical VDD2.5
IOL/IREF
IREF is equal to VISET/RRC.
Tolerance of RRC <=+/-1%.
6.8
Minimum current at VOLABS
IOL, ABS
Low-level output voltage SMBus
Low-level output current SMBus
Tristate output current
VOLSMB
IOLSMB
IOZ
Measured at ODCLK_T/C pins
with termination per Figure 3.
IOL = 4 mA
VOL= 0.8 V
Differential clock output pins
V
1.02
V
7.2
-
45
-
mA
6
-
0.4
50
V
mA
µΑ
7
Notes:
1 There is no output latency or glitches if a value written to an output register is the same as its current contents.
AC Characteristics-Outputs
TA = 0°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
SYMBOL
CONDITION
MIN
TYP
PARAMETER1
Short term jitter (over 1 to 6 clock
cycles)
tJ2
Phase noise spectral purity
L20
MAX
UNITS
f = 300 to 636 MHz
-
36
40
ps
f = 635 to 800 MHz
-
26
30
ps
-128
ps
fOFFSET = 20MHz,
fOUT = 400MHz
Duty cycle
DC
45
55
%
Output rise and fall times
tR, tF
20% to 80% of output voltage
140
300
ps
Difference between output rise and fall
time on same pin of a single device
tR-F
20% to 80% of output voltage
-
100
ps
Dynamic output impedance
ZOUT2
V OL = 0.9 V
1000
-
Ω
Notes:
1 Guaranteed by design and characterization, not 100% tested in production
2 Zout is defined at the output pins.
1227G—11/05/07
10
ICS9220
AC Characteristics-Inputs
TA = 0°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
1
CLK_INT/CLK_INC cycle time
Cycle-to-Cycle Jitter
tCYCLEIN
9
MAX
UNITS
11
ns
185
ps
10
2
Input clock duty cycle
tcyc-tcyc
dtin
over 10,000 cycles
40
60
%
CLK_INT/CLK_INC rise and fall time
tR, tF
20% to 80% of input voltage
175
700
ps
Difference between input rise and fall
time on same pin of a single device
tR-F
20% to 80% of input voltage
-
150
ps
Spread spectrum modulation frequency
fINM3
33
kHz
Triangular modulation
30
0.6
%
Non-triangular modulation
0.54
%
4
V/ns
Spread spectrum modulation index
mINDEX3
Input clock slew rate
tsl(I)
20% to 80% of input voltage
5
1
Input Capacitance
CINCLK
CLK_INT, CLK_INC
7
pF
Input Capacitance5
CLK_INT cycle time
CIN
VI = VDD2.5 or GND
10
pF
tCYCLETST
Bypass Mode
4
40
ns
SMBus clock frequency
fSMB
10
100
kHz
Notes:
1 Measured at (VIH(nom) - VIL(nom))/2 and is the absolute value of the worst case deviation.
2 Measured at crossing points for differential clock input or at VTH for single- ended clock input.
3 If input modulation is used. Input modulation is not necessary.
4 The amount of allowed spreading for non-triangular modulation is determined by the induced downstream
tracking skew.
5 Capacitance measured at f = 1 MHz, DC bias = 0.9V, VAC <100mV.
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Thermal Resistance Junction to Top of
Case
Maximum Case Temp
Symbol
Conditions
θJA
θJA
θJA
θJC
Still air
1 m/s air flow
3 m/s air flow
ΨJT
Still Air
Min.
Typ.
Max.
120
95
80
20
°C/W
°C/W
°C/W
°C/W
°C/W
4.5
120
1227G—11/05/07
11
Units
°C
ICS9220
Clock Output Drivers
Figure 2 shows the clock driver equivalent circuit. The differential driver produces a specified voltage swing on the
channel by switching the currents going into ODCLK_T and ODCLK_C. The external resistor RRC at the IREFY pin sets
the maximum current. The minimum current is zero.
The voltage at the IREFY pin, VIREFY, is by design equal to 1 V nominally, and the driver current is seven times the current
flowing through RRC. So, the output low current can be estimated as IOL = 7/ RRC.
The driver output characteristics are defined together with the external resistors, R1, R2, and R3. The output clock
signals are specified at the measurement points indicated in Figure 2. Table 5 shows example values for the resistors.
R1, R2, and R3 and the clock driver output impedance, ZOUT, must match the impedance of the channel, ZCH , to
minimize secondary reflections. ZOUT is specified as 1000 Ohms, minimum to accomplish this. The effective
impedance can be estimated by:
(1000R1/(1000+R1)+R2) R3/(1000R1/(1000+R1)+R2+R3)
Pull-up resistor RT terminates the transmission line at the load to minimize clock signal reflection signal reflections.
Table 5 shows the resistor values for establishing and effective source termination impedance of 49.2 Ohms to match
a 50 Ohm channel. The termination voltages are 2.5 V for VTS and 1.2 V for VT. The resistor values R1 = 38.3 Ohms,
R2 = 19.1 Ohms, R3 = 54.9 Ohms and RRC = 200 Ohms can be used to match a 28 Ohm channel.
Table 5. Example Resistor Values and Termination Voltages for a 50 Ohm Channel1
Symbol
Parameter
Value
Tolerance
Unit
R1
Termination resistor
39.2
+/- 1%
Ω
R2
Termination resistor
66.5
+/- 1%
Ω
R3
Termination resistor
93.1
+/- 1%
Ω
RT
Termination resistor
49.9
+/- 1%
Ω
RRC
Swing control resistor
200
+/- 1%
Ω
VTS
VT
Source termination voltage
2.5
+/-5%
V
Termination voltage
1.2
+/-5%
V
Notes:
1 A different set of resistors is used in Figure 2 when testing
for maximum output current of the clock driver (IOLABS).
These resistors are: R1 = 23Ω, R2 = 36.5Ω, R3 = 52.3Ω,
RT=28Ω, RRC = 118Ω
Supply Voltage
CLK_INC
VTH
Input
CLK_INT
CLK_INT
XDR
Input
Clock Generator
XDR
Clock Generator
a. Differential input
b. Single-ended input
Figure 1. Differential and single-ended reference clock inputs
1227G—11/05/07
12
ICS9220
Input Clock Signal
The ICS9220 receives either a differential or single-ended reference clock (CLK_INT/C). When the reference input clock
is from a differential clock source, it must meet the voltage levels and timing requirements listed in the DC
Characteristics – Inputs and AC Characteristics – Inputs tables.
For a singled-ended clock input, an external voltage divider and a supply voltage, as shown in Figure 2, provide a
reference voltage VTH at the CLK_INC pin to determine the proper switching point for CLK_INT. The range of VTH is
specified in the DC Characteristics – Inputs table.
VTS
ODCLK_T
R1
Measurement
Point
ZCH
R2
VT
RT
R3
Swing Current
Control
ISET
Differential Driver
VTS
ODCLK_C
Measurement
Point
R1
ZCH
R2
RRC
VT
RT
R3
Figure 2. Example System Clock Driver Equivalent Circuit
VH
80%
V(t)
20%
VL
tF
tR
Figure 3. Input and Output Voltage Waveforms
ODCLK_T
Vx+
Vx,nom
Vx-
ODCLK_C
Figure 4. Crossing-point Voltage
1227G—11/05/07
13
ICS9220
Power Sequencing
Supply voltages for the ICS9220 must be applied before, or at the same time and external input and output signals.
ODCLK_T
ODCLK_C
tCYCLE,i+1
tCYCLE,i
tJ = tCYCLE,i - tCYCLE, i+1 over 10,000 consecutive cycles
Figure 5. Cycle-to-cycle Jitter
ODCLK_T
ODCLK_C
t4CYCLE, i+1
t4CYCLE, i
tJ = t4CYCLE, i - t4CYCLE, i+1 over 10,000 consecutive cycles
Figure 6. Short-term Jitter
Cycle (i)
ODCLK_T
ODCLK_C
tPW- (i)
Cycle (i+1)
tPW+ (i)
tPW- (i+1)
tCYCLE (i)
tCYCLE (i+1)
tDC,ERR = tPW+(i) - tPW+(i+1) and tPW-(i) - tPW-(i+1)
Figure 7. Cycle-to-cycle Duty Cycle Error
1227G—11/05/07
14
tPW+ (i+1)
ICS9220
fNOM
(1-PM,IN)*fNOM
0.5/fM,IN
t
1/fM,IN
Figure 8. Input frequency Modulation
1227G—11/05/07
15
ICS9220
4.40 mm. Body, 0.65 mm. Pitch TSSOP
(173 mil)
c
N
SYMBOL
L
E1
INDEX
AREA
A
A1
A2
b
c
D
E
E1
e
L
N
a
aaa
E
1 2
α
D
A
A2
In Inches
COMMON DIMENSIONS
MIN
MAX
-.047
.002
.006
.032
.041
.007
.012
.0035
.008
SEE VARIATIONS
0.252 BASIC
.169
.177
0.0256 BASIC
.018
.030
SEE VARIATIONS
0°
8°
-.004
VARIATIONS
N
A1
-Ce
(25.6 mil)
In Millimeters
COMMON DIMENSIONS
MIN
MAX
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
SEE VARIATIONS
6.40 BASIC
4.30
4.50
0.65 BASIC
0.45
0.75
SEE VARIATIONS
0°
8°
-0.10
SEATING
PLANE
b
aaa C
28
D mm.
MIN
9.60
D (inch)
MAX
9.80
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
Ordering Information
ICS9220yG LF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
1227G—11/05/07
16
MIN
.378
MAX
.386
ICS9220
Revision History
Rev.
D
E
F
G
Issue Date
10/11/06
04/06/07
04/09/07
11/05/07
Description
Final Release
Updated AC output short term jitter specifications
Updated AC output short term jitter specifications
Updated to extended temperature range
1227G—11/05/07
17
Page #
10
10
-