19-3706; Rev 4; 6/12 Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL The MAX7030 crystal-based, fractional-N transceiver is designed to transmit and receive ASK/OOK data at factory-preset carrier frequencies of 315MHz or 433.92MHz with data rates up to 33kbps (Manchester encoded) or 66kbps (NRZ encoded). This device generates a typical output power of +10dBm into a 50Ω load and exhibits typical sensitivity of -114dBm. The MAX7030 features separate transmit and receive pins (PAOUT and LNAIN) and provides an internal RF switch that can be used to connect the transmit and receive pins to a common antenna. The MAX7030 transmit frequency is generated by a 16bit, fractional-N, phase-locked loop (PLL), while the receiver’s local oscillator (LO) is generated by an integer-N PLL. This hybrid architecture eliminates the need for separate transmit and receive crystal reference oscillators because the fractional-N PLL is preset to be 10.7MHz above the receive LO. Retaining the fixed-N PLL for the receiver avoids the higher current-drain requirements of a fractional-N PLL and keeps the receiver current drain as low as possible. All frequencygeneration components are integrated on-chip, and only a crystal, a 10.7MHz IF filter, and a few discrete components are required to implement a complete antenna/digital data solution. The MAX7030 is available in a small, 5mm x 5mm, 32pin thin QFN package, and is specified to operate over the automotive -40°C to +125°C temperature range. Features ♦ +2.1V to +3.6V or +4.5V to +5.5V Single-Supply Operation ♦ Single-Crystal Transceiver ♦ Factory-Preset Frequency (No Serial Interface Required) ♦ ASK/OOK Modulation ♦ +10dBm Output Power into 50Ω Load ♦ Integrated TX/RX Switch ♦ Integrated Transmit and Receive PLL, VCO, and Loop Filter ♦ > 45dB Image Rejection ♦ Typical RF Sensitivity*: -114dBm ♦ Selectable IF Bandwidth with External Filter ♦ < 12.5mA Transmit-Mode Current ♦ < 6.7mA Receive-Mode Current ♦ < 800nA Shutdown Current ♦ Fast-On Startup Feature, < 250µs ♦ Small, 32-Pin, Thin QFN Package *0.2% BER, 4kbps Manchester-encoded data, 280kHz IF BW Ordering Information Applications 2-Way Remote Keyless Entry Security Systems Home Automation Remote Controls Remote Sensing PART TEMP RANGE MAX7030_ATJ+ -40°C to +125°C PIN-PACKAGE 32 Thin QFN-EP** +Denotes a lead(Pb)-free/RoHS-compliant package. **EP = Exposed pad. Note: The MAX7030 is available with factory-preset operating frequencies. See the Product Selector Guide for complete part numbers. Smoke Alarms Garage Door Openers Product Selector Guide Local Telemetry Systems PART Pin Configuration, Typical Application Circuit, and Functional Diagram appear at end of data sheet. CARRIER FREQUENCY (MHz) MAX7030LATJ+ 315 MAX7030HATJ+ 433.92 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX7030 General Description MAX7030 Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL ABSOLUTE MAXIMUM RATINGS HVIN to GND .........................................................-0.3V to +6.0V PAVDD, AVDD, DVDD to GND..............................-0.3V to +4.0V ENABLE, T/R, DATA, AGC0, AGC1, AGC2 to GND .......................................-0.3V to (VHVIN+ 0.3V) All Other Pins to GND .............................-0.3V to (V_VDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 32-Pin Thin QFN (derate 21.3mW/°C above +70°C).............................................................1702mW Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, 50Ω system impedance, VAVDD = VDVDD = VHVIN = VPAVDD = +2.1V to +3.6V, fRF = 315MHz or 433.92MHz, T A = -40°C to +125°C, unless otherwise noted. Typical values are at V AVDD = V DVDD = V HVIN = V PAVDD = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage (3V Mode) VDD HVIN, PAVDD, AVDD, and DVDD connected to power supply 2.1 2.7 3.6 V Supply Voltage (5V Mode) HVIN PAVDD, AVDD, and DVDD unconnected from HVIN, but connected together 4.5 5.0 5.5 V Supply Current Transmit mode, PA off, VDATA at 0% duty cycle (Note 2) fRF = 315MHz 3.5 5.4 fRF = 434MHz 4.3 6.7 Transmit mode, VDATA at 50% duty cycle (Notes 3, 4) fRF = 315MHz 7.6 12.3 fRF = 434MHz 8.4 13.6 Transmit mode, VDATA at 100% duty cycle (Note 2) fRF = 315MHz 11.6 19.1 fRF = 434MHz 12.4 20.4 Receiver 315MHz 6.1 7.9 Receiver 434MHz 6.4 8.3 Deep-sleep (3V mode) 0.8 8.8 Deep-sleep (5V mode) 2.4 10.9 Receiver 315MHz 6.4 8.2 Receiver 434MHz 6.7 8.4 Deep-sleep (3V mode) 8.0 34.2 Deep-sleep (5V mode) 14.9 39.3 IDD TA < +85°C, typ at +25°C (Note 4) TA < +125°C, typ at +125°C (Note 2) Voltage Regulator VREG mA µA mA µA VHVIN = 5V, ILOAD = 15mA 3.0 V DIGITAL I/O Input-High Threshold VIH (Note 2) Input-Low Threshold VIL (Note 2) 2 0.9 x VHVIN V 0.1 x VHVIN V Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL (Typical Application Circuit, 50Ω system impedance, VAVDD = VDVDD = VHVIN = VPAVDD = +2.1V to +3.6V, fRF = 315MHz or 433.92MHz, T A = -40°C to +125°C, unless otherwise noted. Typical values are at V AVDD = V DVDD = V HVIN = V PAVDD = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL Pulldown Sink Current CONDITIONS MIN AGC0-2, ENABLE, T/R, DATA (VHVIN = 5.5V) Output-Low Voltage VOL ISINK = 500µA Output-High Voltage VOH ISOURCE = 500µA TYP MAX 20 UNITS µA 0.15 V VHVIN - 0.26 V AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, 50Ω system impedance, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V to +3.6V, fRF = 315MHz or 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD = VAVDD = VDVDD = VHVIN = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL CHARACTERISTICS Frequency Range Maximum Input Level PRFIN 315/433.92 MHz 0 dBm Transmit Efficiency 100% Duty Cycle fRF = 315MHz (Note 6) 32 fRF = 434MHz (Note 6) 30 Transmit Efficiency 50% Duty Cycle fRF = 315MHz (Note 6) 24 fRF = 434MHz (Note 6) 22 ENABLE or T/R transition low to high, transmitter frequency settled to within 50kHz of the desired carrier 200 ENABLE or T/R transition low to high, transmitter frequency settled to within 5kHz of the desired carrier 350 ENABLE transition low to high, or T/R transition high to low, receiver startup time (Note 5) 250 Power-On Time t ON % % μs RECEIVER 0.2% BER, 4kbps Manchester data rate, 280kHz IF BW, average RF power Sensitivity 315MH z 434MH z -114 dBm -113 Image Rejection 46 dB POWER AMPLIFIER Output Power POUT TA = +25°C (Note 4) 4.6 10.0 TA = +125°C, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V (Note 2) 3.9 6.7 Reference Spur dBm TA = -40°C, VPAVDD = VAVDD = VDVDD = VHVIN = +3.6V (Note 4) 13.1 82 dB With output-matching network -40 dBc -50 dBc Modulation Depth Maximum Carrier Harmonics 15.5 15.8 3 MAX7030 DC ELECTRICAL CHARACTERISTICS (continued) MAX7030 Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, 50Ω system impedance, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V to +3.6V, fRF = 315MHz or 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD = VAVDD = VDVDD = VHVIN = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER PHASE-LOCKED LOOP Transmit VCO Gain SYMBOL CONDITIONS KVCO Transmit PLL Phase Noise MIN TYP 340 10kHz offset, 200kHz loop BW -68 1MHz offset, 200kHz loop BW -98 Receive VCO Gain 340 Receive PLL Phase Noise Loop Bandwidth 10kHz offset, 500kHz loop BW -80 1MHz offset, 500kHz loop BW -90 Transmit PLL 200 Receive PLL 500 Reference Frequency Input Level 0.5 MAX UNITS MHz/V dBc/Hz MHz/V dBc/Hz kHz VP-P LOW-NOISE AMPLIFIER/MIXER (Note 8) LNA Input Impedance ZINLNA Normalized to 50 High-gain state Voltage-Conversion Gain Low-gain state Input-Referred, 3rd-Order Intercept Point IIP3 fRF = 315MHz 1 - j4.7 fRF = 434MHz 1- j3.3 fRF = 315MHz 50 fRF = 434MHz 45 fRF = 315MHz 13 fRF = 434MHz dB 9 High-gain state -42 Low-gain state -6 dBm Mixer-Output Impedance 330 LO Signal Feedthrough to Antenna -100 dBm RSSI Input Impedance Operating Frequency f IF 330 10.7 MHz 3dB Bandwidth 10 MHz Gain 15 mV/dB ANALOG BASEBAND Maximum Data-Filter Bandwidth 50 kHz Maximum Data-Slicer Bandwidth 100 kHz 50 kHz Maximum Peak-Detector Bandwidth Maximum Data Rate 4 Manchester coded 33 Nonreturn to zero (NRZ) 66 kbps Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL (Typical Application Circuit, 50Ω system impedance, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V to +3.6V, fRF = 315MHz or 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD = VAVDD = VDVDD = VHVIN = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CRYSTAL OSCILLATOR Crystal Frequency f XTAL (fRF -10.7) /24 MHz 2 ppm/V 4.5 pF Frequency Pulling by VDD Crystal Load Capacitance Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: (Note 7) Supply current, output power, and efficiency are greatly dependent on board layout and PAOUT match. 100% tested at TA = +125°C. Guaranteed by design and characterization overtemperature. 50% duty cycle at 10kHz ASK data (Manchester coded). Guaranteed by design and characterization. Not production tested. Time for final signal detection; does not include baseband filter settling. Efficiency = POUT/(VDD x IDD). Dependent on PCB trace capacitance. Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 12nH inductive degeneration from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from the LNA source to ground. The equivalent input circuit is 50Ω in series with ~2.2pF. The voltage conversion is measured with the LNA input-matching inductor, the degeneration inductor, and the LNA/mixer tank in place, and does not include the IF filter insertion loss. Typical Operating Characteristics (Typical Application Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) RECEIVER 6.6 +85°C 6.4 6.2 +25°C 6.0 6.6 6.5 +85°C 6.4 6.1 5.6 6.0 2.7 3.0 SUPPLY VOLTAGE (V) +25°C 6.3 5.8 2.4 3.3 3.6 -40°C 18 MAX7030 toc03 +125°C 6.2 -40°C 2.1 MAX7030 toc02 6.7 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) MAX7030 toc01 +125°C 6.8 DEEP-SLEEP CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. RF FREQUENCY 6.8 16 DEEP-SLEEP CURRENT (μA) SUPPLY CURRENT vs. SUPPLY VOLTAGE 7.0 14 VCC = +3.6V 12 VCC = +3.0V 10 VCC = +2.1V 8 6 4 2 0 300 325 350 375 400 RF FREQUENCY (MHz) 425 450 -40 -15 -10 35 60 85 110 TEMPERATURE (°C) 5 MAX7030 AC ELECTRICAL CHARACTERISTICS (continued) Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030 Typical Operating Characteristics (continued) (Typical Application Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) RECEIVER BIT-ERROR RATE vs. AVERAGE INPUT POWER 1.6 1.4 fRF = 434MHz 1 0.2% BER -111 1.0 0.8 AGC SWITCH POINT 0.6 -114 fRF = 315MHz 0.4 LOW-GAIN MODE -117 0.2 AGC HYSTERESIS: 3dB 0 -120 -115 -113 -111 -40 -15 50 2.5 40 1.5 30 1.2 0.5 0.9 -0.5 -1.5 DELTA 0.3 0 -90 -70 -50 -30 -10 DELTA (%) RSSI 3.5 SYSTEM GAIN (dBm) 1.8 0.6 -130 -110 110 10 -10 -3.5 -20 10 -50 -30 48 fRF = 433MHz 46 44 42 5 10 15 20 25 30 -40 -15 10 35 60 85 IF FREQUENCY (MHz) TEMPERATURE (°C) S11 vs. RF FREQUENCY S11 SMITH PLOT OF RFIN MAX7030 toc11 0 S11 (dB) 433MHz -12 433.92MHz -12 -18 -16 -20 400MHz -24 1 10 IF FREQUENCY (MHz) 100 10 fRF = 315MHz -6 -8 -10 LOWER SIDEBAND 0 MAX7030 toc10 -70 IMAGE REJECTION vs. TEMPERATURE 0 -2.5 -90 RF INPUT POWER (dBm) FROM RFIN TO MIXOUT fRF = 434MHz 48dB IMAGE REJECTION 20 NORMALIZED IF GAIN vs. IF FREQUENCY -4 85 UPPER SIDEBAND IF INPUT POWER (dBm) 0 60 SYSTEM GAIN vs. IF FREQUENCY MAX7030 toc07 1.5 35 TEMPERATURE (°C) RSSI AND DELTA vs. IF INPUT POWER 2.1 10 MAX7030 toc09 -117 AVERAGE INPUT POWER (dBm) IMAGE REJECTION (dB) -119 MAX7030 toc08 -121 200 250 300 350 400 RF FREQUENCY (MHz) 450 500 110 MAX7030 toc12 0.01 6 HIGH-GAIN MODE 1.2 fRF = 434MHz RSSI (V) SENSITIVITY (dBm) BIT-ERROR RATE (%) 10 -108 MAX7030 toc06 -105 fRF = 315MHz RSSI (V) 1.8 MAX7030 toc05 MAX7030 toc04 -102 0.1 NORMALIZED IF GAIN (dB) RSSI vs. RF INPUT POWER SENSITIVITY vs. TEMPERATURE 100 500MHz Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL RECEIVER INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION -220 90 -230 80 MAX7030 toc14 -240 60 -250 50 -260 40 -270 REAL IMPEDANCE 20 1 IMAGINARY IMPEDANCE 70 -180 50 -190 40 -200 -280 30 -290 20 REAL IMPEDANCE -220 MAX7030 toc15 fRF = 315MHz PHASE NOISE vs. OFFSET FREQUENCY -50 -70 -80 -90 -100 -110 fRF = 433MHz -60 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) 100 INDUCTIVE DEGENERATION (nH) PHASE NOISE vs. OFFSET FREQUENCY -60 -210 10 1 INDUCTIVE DEGENERATION (nH) -50 -170 60 100 10 -160 MAX7030 toc16 30 REAL IMPEDANCE (Ω) REAL IMPEDANCE (Ω) IMAGINARY IMPEDANCE 70 IMAGINARY IMPEDANCE (Ω) fRF = 315MHz 80 -150 fRF = 434MHz IMAGINARY IMPEDANCE (Ω) MAX7030 toc13 90 -70 -80 -90 -100 -110 -120 -120 100 1k 10k 100k OFFSET FREQUENCY (Hz) 1M 10M 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) 7 MAX7030 Typical Operating Characteristics (continued) (Typical Application Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (Typical Application Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) TRANSMITTER SUPPLY CURRENT vs. SUPPLY VOLTAGE TA = +85°C TA = +125°C TA = -40°C TA = +25°C 10 5.0 TA = +125°C 4.5 TA = +85°C 4.0 3.5 3.0 3.0 2.4 TA = +125°C 5.0 TA = +85°C 4.5 4.0 3.0 3.3 3.6 2.1 TA = +25°C 10 9 PA ON 8 7 TA = -40°C 3.0 2.4 2.7 3.0 3.3 3.6 -6 -2 2 MAX7030 toc23-1 POWER 14 12 4 10 0 SUPPLY CURRENT (mA) CURRENT -10 2 16 12 8 4 CURRENT -8 -12 4 -16 2 10k POWER -4 6 1k MAX7030 toc23-2 8 -8 100 -2 0 6 fRF = 315MHz PA ON -6 -12 fRF = 433MHz PA ON -16 0.1 6 AVERAGE OUTPUT POWER (dBm) 10 -4 10 MAX7030 toc19 50% DUTY CYCLE -14 10 6 12 8 EXTERNAL RESISTOR (Ω) 8 SUPPLY CURRENT (mA) 8 OUTPUT POWER (dBm) 14 1 8 18 16 16 0.1 9 SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR 12 2 PA ON 10 AVERAGE OUTPUT POWER (dBm) SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR 4 11 5 -10 SUPPLY VOLTAGE (V) 16 3.6 6 -14 18 3.3 12 7 4 2.1 3.0 fRF = 434MHz PA ON ENVELOPE SHAPING ENABLED 13 50% DUTY CYCLE 5 2.7 SUPPLY CURRENT vs. OUTPUT POWER 14 6 3.5 2.4 SUPPLY VOLTAGE (V) fRF = 315MHz PA ON ENVELOPE SHAPING ENABLED 11 SUPPLY CURRENT (mA) fRF = 434MHz PA OFF 5.5 2.7 SUPPLY CURRENT vs. OUTPUT POWER 12 MAX7030 toc20 6.0 TA = +25°C SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. SUPPLY VOLTAGE TA = -40°C TA = +125°C 13 9 2.1 3.6 3.3 SUPPLY CURRENT (mA) 2.7 MAX7030 toc21 2.4 TA = +85°C TA = -40°C TA = +25°C 2.0 2.1 15 11 2.5 8 fRF = 434MHz PA ON WITHOUT ENVELOPE SHAPING MAX7030 toc22 14 12 fRF = 315MHz PA OFF 5.5 1 10 100 EXTERNAL RESISTOR (Ω) 1k 10k OUTPUT POWER (dBm) fRF = 315MHz PA ON WITHOUT ENVELOPE SHAPING SUPPLY CURRENT vs. SUPPLY VOLTAGE 17 SUPPLY CURRENT (mA) MAX7030 toc17 6.0 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 16 MAX7030 toc18 SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT (mA) MAX7030 Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL 10 Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL TRANSMITTER TA = +125°C TA = +85°C 6 8 TA = +125°C TA = +85°C 6 2.7 3.0 3.3 2.4 OUTPUT POWER vs. SUPPLY VOLTAGE 3.0 MAX7030 25-2 fRF = 434MHz PA ON ENVELOPE SHAPING ENABLED 12 fRF = 315MHz PA ON 2.1 3.6 2.4 TA = -40°C TA = +25°C 10 MAX7030 25-1 3.3 3.6 fRF = 434MHz PA ON TA = -40°C 35 TA = +85°C 25 TA = +125°C 3.0 EFFICIENCY vs. SUPPLY VOLTAGE 40 TA = +25°C 30 2.7 SUPPLY VOLTAGE (V) TA = -40°C 35 8 3.3 EFFICIENCY vs. SUPPLY VOLTAGE 40 EFFICIENCY (%) OUTPUT POWER (dBm) 2.7 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 14 TA = +125°C TA = +85°C 4 2.1 3.6 EFFICIENCY (%) 2.4 MAX7030 toc26 2.1 8 6 4 4 10 MAX7030 toc27 8 TA = +25°C 10 fRF = 434MHz PA ON ENVELOPE SHAPING DISABLED TA = -40°C TA = +25°C 12 OUTPUT POWER (dBm) 10 fRF = 315MHz PA ON ENVELOPE SHAPING ENABLED TA = -40°C 12 OUTPUT POWER (dBm) OUTPUT POWER (dBm) TA = -40°C TA = +25°C 14 MAX7030 24-2 fRF = 315MHz PA ON ENVELOPE SHAPING DISABLED 12 14 MAX7030 24-1 14 OUTPUT POWER vs. SUPPLY VOLTAGE OUTPUT POWER vs. SUPPLY VOLTAGE OUTPUT POWER vs. SUPPLY VOLTAGE TA = +25°C TA = +85°C 30 25 TA = +125°C TA = +125°C TA = +85°C 20 20 2.7 3.0 3.3 2.1 3.6 2.4 SUPPLY VOLTAGE (V) TA = -40°C EFFICIENCY (%) EFFICIENCY (%) 3.3 TA = +25°C 20 TA = +85°C TA = +125°C fRF = 434MHz 50% DUTY CYCLE 25 TA = +25°C 20 2.7 3.0 3.3 3.6 3.3 3.6 -40 fRF = 315MHz -50 -60 -70 -80 -90 -100 -110 -130 15 SUPPLY VOLTAGE (V) 3.0 -120 TA = +125°C 10 2.7 PHASE NOISE vs. OFFSET FREQUENCY TA = +85°C 2.4 2.4 SUPPLY VOLTAGE (V) TA = -40°C 15 2.1 2.1 3.6 EFFICIENCY vs. SUPPLY VOLTAGE 30 MAX7030 toc28 fRF = 315MHz 50% DUTY CYCLE 25 3.0 SUPPLY VOLTAGE (V) EFFICIENCY vs. SUPPLY VOLTAGE 30 2.7 PHASE NOISE (dBc/Hz) 2.4 MAX7030 toc29 2.1 MAX7030 toc30 6 -140 2.1 2.4 2.7 3.0 SUPPLY VOLTAGE (V) 3.3 3.6 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) 9 MAX7030 Typical Operating Characteristics (continued) (Typical Application Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (Typical Application Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) TRANSMITTER REFERENCE SPUR MAGNITUDE vs. SUPPLY VOLTAGE PHASE NOISE vs. OFFSET FREQUENCY -70 -80 -90 -100 -110 -120 -45 MAX7030 toc32 -60 REFERENCE SPUR MAGNITUDE (dBc) fRF = 434MHz -50 -40 MAX7030 toc31 -40 PHASE NOISE (dBc/Hz) 434MHz -50 315MHz -55 -60 -65 -130 -70 -140 100 1k 10k 100k 1M 2.1 10M FREQUENCY STABILITY vs. SUPPLY VOLTAGE MAX7030 toc33 10 8 6 fRF = 434MHz 4 2 0 -2 fRF = 315MHz -4 -6 -8 -10 2.1 2.4 2.7 3.0 SUPPLY VOLTAGE (V) 10 2.4 2.7 3.0 SUPPLY VOLTAGE (V) OFFSET FREQUENCY (Hz) FREQUENCY STABILITY (ppm) MAX7030 Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL 3.3 3.6 3.3 3.6 Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL PIN NAME 1 PAVDD FUNCTION Power-Amplifier Supply Voltage. Bypass to GND with 0.01µF and 220pF capacitors placed as close as possible to the pin. 2 ROUT Envelope-Shaping Output. ROUT controls the power-amplifier envelope’s rise and fall times. Connect ROUT to the PA pullup inductor or optional power-adjust resistor. Bypass the inductor to GND as close as possible to the inductor with 680pF and 220pF capacitors, as shown in the Typical Application Circuit. 3 TX/RX1 Transmit/Receive Switch Throw. Drive T/R high to short TX/RX1 to TX/RX2. Drive T/R low to disconnect TX/RX1 from TX/RX2. Functionally identical to TX/RX2. 4 TX/RX2 Transmit/Receive Switch Pole. Typically connected to ground. See the Typical Application Circuit. 5 PAOUT Power-Amplifier Output. Requires a pullup inductor to the supply voltage (or ROUT if envelope shaping is desired), which can be part of the output-matching network to an antenna. 6 AVDD 7 LNAIN Analog Power-Supply Voltage. AVDD is connected to an on-chip +3.0V regulator in 5V operation. Bypass AVDD to GND with a 0.1µF and 220pF capacitor placed as close as possible to the pin. Low-Noise Amplifier Input. Must be AC-coupled. 8 LNASRC Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set the LNA input impedance. 9 LNAOUT Low-Noise Amplifier Output. Must be connected to AVDD through a parallel LC tank filter. AC-couple to MIXIN+. 10 MIXIN+ Noninverting Mixer Input. Must be AC-coupled to the LNA output. 11 MIXIN- Inverting Mixer Input. Bypass to AVDD with a capacitor as close as possible to the LNA LC tank filter. 12 MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz filter. 13 14 15 16 17 18 19 20 21, 25 IFINIFIN+ PDMIN PDMAX DSDS+ OP+ DF N.C. Inverting 330Ω IF Limiter-Amplifier Input. Bypass to GND with a capacitor. Noninverting 330Ω IF Limiter-Amplifier Input. Connect to the output of the 10.7MHz IF filter. Minimum-Level Peak Detector for Demodulator Output Maximum-Level Peak Detector for Demodulator Output Inverting Data Slicer Input Noninverting Data Slicer Input Noninverting Op-Amp Input for the Sallen-Key Data Filter Data-Filter Feedback Node. Input for the feedback capacitor of the Sallen-Key data filter. No Connection. Do not connect to this pin. 22 T/R Transmit/Receive. Drive high to put the device in transmit mode. Drive low or leave unconnected to put the device in receive mode. It is internally pulled down. 23 ENABLE Enable. Drive high for normal operation. Drive low or leave unconnected to put the device into shutdown mode. 24 DATA Receiver Data Output/Transmitter Data Input 26 DVDD Digital Power-Supply Voltage. Bypass to GND with a 0.01µF and 220pF capacitor placed as close as possible to the pin. 27 HVIN High-Voltage Supply Input. For 3V operation, connect HVIN to AVDD, DVDD, and PAVDD. For 5V operation, connect only HVIN to 5V. Bypass HVIN to GND with a 0.01µF and 220pF capacitor placed as close as possible to the pin. 11 MAX7030 Pin Description Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030 Pin Description (continued) PIN NAME 28 AGC2 AGC Enable/Dwell Time Control 2 (MSB). See Table 1. Bypass to GND with a 10pF capacitor. FUNCTION 29 AGC1 AGC Enable/Dwell Time Control 1. See Table 1. Bypass to GND with a 10pF capacitor. 30 AGC0 AGC Enable/Dwell Time Control 0 (LSB). See Table 1. Bypass to GND with a 10pF capacitor. 31 XTAL1 Crystal Input 1. Bypass to GND if XTAL2 is driven by an AC-coupled external reference. 32 XTAL2 Crystal Input 2. XTAL2 can be driven from an external AC-coupled reference. — EP Exposed Pad. Solder evenly to the board’s ground plane for proper operation. Detailed Description The MAX7030 315MHz and 433.92MHz CMOS transceiver and a few external components provide a complete transmit and receive chain from the antenna to the digital data interface. This device is designed for transmitting and receiving ASK data. All transmit frequencies are generated by a fractional-N-based synthesizer, allowing for very fine frequency steps in increments of fXTAL/4096. The receive LO is generated by a traditional integer-N-based synthesizer. Depending on component selection, data rates as high as 33kbps (Manchester encoded) or 66kbps (NRZ encoded) can be achieved. Receiver Low-Noise Amplifier (LNA) The LNA is a cascode amplifier with off-chip inductive degeneration that achieves approximately 30dB of voltage gain that is dependent on both the antenna-matching network at the LNA input and the LC tank network between the LNA output and the mixer inputs. The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to GND. This inductor sets the real part of the input impedance at LNAIN, allowing for a more flexible match for low-input impedances such as a PCB trace antenna. A nominal value for this inductor with a 50Ω input impedance is 12nH at 315MHz and 10nH at 434MHz, but the inductance is affected by PCB trace length. LNASRC can be shorted to ground to increase sensitivity by approximately 1dB, but the input match must then be reoptimized. 12 The LC tank filter connected to LNAOUT consists of L5 and C9 (see the Typical Application Circuit). Select L5 and C9 to resonate at the desired RF input frequency. The resonant frequency is given by: f= 1 2π L TOTAL × C TOTAL where LTOTAL = L5 + LPARASITICS and CTOTAL = C9 + CPARASITICS. LPARASITICS and CPARASITICS include inductance and capacitance of the PCB traces, package pins, mixerinput impedance, LNA-output impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center frequency. Lab experimentation should be done to optimize the center frequency of the tank. The total parasitic capacitance is generally between 5pF and 7pF. Automatic Gain Control (AGC) When the AGC is enabled, it monitors the RSSI output. When the RSSI output reaches 1.28V, which corresponds to an RF input level of approximately -55dBm, the AGC switches on the LNA gain-reduction attenuator. The attenuator reduces the LNA gain by 36dB, thereby reducing the RSSI output by about 540mV to 740mV. The LNA resumes high-gain mode when the RSSI output level drops back below 680mV (approximately -59dBm at the RF input) for a programmable interval called the AGC dwell time (see Table 1). The AGC has a hysteresis of approximately 4dB. With the AGC function, the RSSI dynamic range is increased, allowing the MAX7030 to reliably produce an ASK output for RF input levels up to 0dBm with a modulation depth of 18dB. AGC is not required and can be disabled (see Table 1). Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL AGC2 AGC1 AGC0 0 0 0 AGC disabled, high gain selected DESCRIPTION 0 0 1 K = 11 0 1 0 K = 13 0 1 1 K = 15 1 0 0 K = 17 1 0 1 K = 19 1 1 0 K = 21 1 1 1 K = 23 AGC Dwell-Time Settings The AGC dwell timer holds the AGC in low-gain state for a set amount of time after the power level drops below the AGC switching threshold. After that set amount of time, if the power level is still below the AGC threshold, the LNA goes into high-gain state. This is important for ASK since the modulated data may have a high level above the threshold and low level below the threshold, which without the dwell timer would cause the AGC to switch on every bit. The MAX7030 uses the three AGC control pins (AGC0, AGC1, AGC2) to set seven user-controlled, dwell-timer settings. The AGC dwell time is dependent on the crystal frequency and the bit settings of the AGC control pins. To calculate the dwell time, use the following equation: Dwell Time = 2K fXTAL where K is an odd integer in decimal from 11 to 23, determined by the control pin settings shown in Table 1. To calculate the value of K, use the following equation and use the next integer higher than the calculated result: K ≥ 3.3 x log10 (Dwell Time x fXTAL) For Manchester Code (50% duty cycle), set the dwell time to at least twice the bit period. For nonreturn-tozero (NRZ) data, set the dwell to greater than the period of the longest string of zeros or ones. For example, using Manchester Code at 315MHz (f XTAL = 12.679MHz) with a data rate of 2kbps (bit period = 250µs), the dwell time needs to be greater than 500µs: K ≥ 3.3 x log10 (500µs x 12.679) ≈ 12.546 Choose the AGC pin settings for K to be the next oddinteger value higher than 12.546, which is 13. This says that AGC1 is set high and AGC0 and AGC2 are set low. Mixer A unique feature of the MAX7030 is the integrated image rejection of the mixer. This eliminates the need for a costly front-end SAW filter for many applications. The advantage of not using a SAW filter is increased sensitivity, simplified antenna matching, less board space, and lower cost. The mixer cell is a pair of double-balanced mixers that perform an IQ downconversion of the RF input to the 10.7MHz intermediate frequency (IF) with low-side injection (i.e., fLO = fRF - fIF). The image-rejection circuit then combines these signals to achieve a typical 46dB of image rejection over the full temperature range. Lowside injection is required as high-side injection is not possible due to the on-chip image rejection. The IF output is driven by a source follower, biased to create a driving impedance of 330Ω to interface with an off-chip 330Ω ceramic IF filter. The voltage-conversion gain driving a 330Ω load is approximately 20dB. Note that the MIXIN+ and MIXIN- inputs are functionally identical. Integer-N Phase-Locked Loop (PLL) The MAX7030 utilizes a fixed-integer-N PLL to generate the receive LO. All PLL components, including the loop filter, voltage-controlled oscillator, charge pump, asynchronous 24x divider, and phase-frequency detector are integrated internally. The loop bandwidth is approximately 500kHz. The relationship between RF, IF, and crystal reference frequencies is given by: fXTAL = (fRF - fIF)/24 13 MAX7030 Table 1. AGC Dwell Time Settings for MAX7030 MAX7030 Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL Intermediate Frequency (IF) The IF section presents a differential 330Ω load to provide matching for the off-chip ceramic filter. The internal six AC-coupled limiting amplifiers produce an overall gain of approximately 65dB, with a bandpass filter type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 10MHz. For ASK data, the RSSI circuit demodulates the IF to baseband by producing a DC output proportional to the log of the IF signal level with a slope of approximately 15mV/dB. Data Filter The data filter for the demodulated data is implemented as a 2nd-order, lowpass, Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. Set the corner frequency in kHz to approximately 3 times the fastest expected Manchester data rate in kbps from the transmitter (1.5 times the fastest expected NRZ data rate). Keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. The configuration shown in Figure 1 can create a Butterworth or Bessel response. The Butterworth filter offers a very-flat-amplitude response in the passband and a rolloff rate of 40dB/decade for the two-pole filter. The Bessel filter has a linear phase response, which works well for filtering digital data. To calculate the value of the capacitors, use the following equations, along with the coefficients in Table 2: Data Slicer The data slicer takes the analog output of the data filter and converts it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold voltage. The threshold voltage is set by the voltage on the DS- pin, which is connected to the negative input of the data slicer comparator. Numerous configurations can be used to generate the data-slicer threshold. For example, the circuit in Figure 2 shows a simple method using only one resistor and one capacitor. This configuration averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. With this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. The values of R and C affect how fast the threshold tracks the analog amplitude. Be sure to keep the corner frequency of the RC circuit much lower (about 10 times) than the lowest expected data rate. With this configuration, a long string of NRZ zeros or ones can cause the threshold to drift. This configuration works best if a coding scheme, such as Manchester coding, which has an equal number of zeros and ones, is used. Figure 3 shows a configuration that uses the positive and negative peak detectors to generate the threshold. This configuration sets the threshold to the midpoint between a high output and a low output of the data filter. MAX7030 RSSI b CF1 = a(100kΩ)(π)(fc ) a CF2 = 4(100kΩ)(π)(fc ) 100kΩ 100kΩ DS+ where fC is the desired 3dB corner frequency. For example, choose a Butterworth filter response with a corner frequency of 5kHz: OP+ DF CF2 CF1 Figure 1. Sallen-Key Lowpass Data Filter 1.000 CF1 = ≈ 450pF (1.414)(100kΩ)(3.14)(5kHz) 1.414 CF2 = ≈ 225pF (4)(100kΩ)(3.14)(5kHz) Choosing standard capacitor values changes CF1 to 470pF and CF2 to 220pF. In the Typical Application Circuit, CF1 and CF2 are named C16 and C17, respectively. 14 Table 2. Coefficients to Calculate CF1 and CF2 FILTER TYPE a b Butterworth (Q = 0.707) 1.414 1.000 Bessel (Q = 0.577) 1.3617 0.618 Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030 MAX7030 MAX7030 DATA SLICER DATA DS- DS+ PEAK DET PEAK DET DATA SLICER R C DATA Figure 2. Generating Data-Slicer Threshold Using a Lowpass Filter Peak Detectors The maximum peak detector (PDMAX) and minimum peak detector (PDMIN), with resistors and capacitors shown in Figure 3, create DC output voltages equal to the high- and low-peak values of the filtered demodulated signal. The resistors provide a path for the capacitors to discharge, allowing the peak detectors to dynamically follow peak changes of the data filter output voltages. The maximum and minimum peak detectors can be used together to form a data slicer threshold voltage at a value midway between the maximum and minimum voltage levels of the data stream (see the Data Slicer section and Figure 3). Set the RC time constant of the peak detector combining network to at least 5 times the data period. If there is an event that causes a significant change in the magnitude of the baseband signal, such as an AGC gain-switch or a power-up transient, the peak detectors may “catch” a false level. If a false peak is detected, the slicing level is incorrect. The MAX7030 peak detectors correct these problems by temporarily tracking the incoming baseband filter voltage when an AGC state switch occurs, or forcing the peak detectors to track the baseband filter output voltage until all internal circuits are stable following an enable pin low-to-high transition and also T/R pin high-to-low transition. The peak detectors exhibit a fast attack/slow decay response. This feature allows for an extremely fast startup or AGC recovery. Transmitter Power Amplifier (PA) The PA of the MAX7030 is a high-efficiency, opendrain, switch-mode amplifier. The PA with proper output-matching network can drive a wide range of antenna impedances, which includes a small-loop PCB trace and a 50Ω antenna. The output-matching network PDMAX R C PDMIN R C Figure 3. Generating Data-Slicer Threshold Using the Peak Detectors for a 50Ω antenna is shown in the Typical Application Circuit. The output-matching network suppresses the carrier harmonics and transforms the antenna impedance to an optimal impedance at PAOUT (pin 5). The optimal impedance at PAOUT is between 100Ω and 150Ω to transmit +10dBm with a 2.7V supply. When the output-matching network is properly tuned, the PA transmits power with a high overall efficiency of up to 32%. The efficiency of the PA itself is more than 46%. The output power is set by an external resistor at PAOUT and is also dependent on the external antenna and antenna-matching network at the PA output. Envelope Shaping The MAX7030 features an internal envelope-shaping resistor, which connects between the open-drain output of the PA and the power supply (see the Typical Application Circuit ). The envelope-shaping resistor slows the turn-on/turn-off of the PA in ASK mode and results in a smaller spectral width of the modulated PA output signal. Fractional-N Phase-Locked Loop (PLL) The MAX7030 utilizes a fully integrated, fractional-N, PLL for its transmit frequency synthesizer. All PLL components, including the loop filter, are integrated internally. The loop bandwidth is approximately 200kHz. Power-Supply Connections The MAX7030 can be powered from a 2.1V to 3.6V supply or a 4.5V to 5.5V supply. If a 4.5V to 5.5V supply is used, then the on-chip linear regulator reduces the 5V supply to the 3V needed to operate the chip. To operate the MAX7030 from a 3V supply, connect PAVDD, AVDD, DVDD, and HVIN to the 3V supply. When using a 5V supply, connect the supply to HVIN 15 only and connect AVDD, PAVDD, and DVDD together. In both cases, bypass DVDD, HVIN, and PAVDD to GND with 0.01µF and 220pF capacitors and bypass AVDD to GND with 0.1µF and 220pF capacitors. Bypass T/R, ENABLE, DATA, and AGC0-2 with 10pF capacitors to GND. Place all bypass capacitors as close as possible to the respective pins. Transmit/Receive Antenna Switch The MAX7030 features an internal SPST RF switch that, when combined with a few external components, allows the transmit and receive pins to share a common antenna (see the Typical Application Circuit). In receive mode, the switch is open and the power amplifier is shut down, presenting a high impedance to minimize the loading of the LNA. In transmit mode, the switch closes to complete a resonant tank circuit at the PA output and forms an RF short at the input to the LNA. In this mode, the external passive components couple the output of the PA to the antenna and protect the LNA input from strong transmitted signals. The switch state is controlled by the T/R pin (pin 22). Drive T/R high to put the device in transmit mode; drive T/R low to put the device in receive mode. In actuality, the oscillator pulls every crystal. The crystal’s natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is already accounted for in the specification of the load capacitance. Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by: fP = ⎞ Cm ⎛ 1 1 − x 106 ⎜ 2 ⎝ CCASE + CLOAD CCASE + CSPEC ⎟⎠ where: fp is the amount the crystal frequency is pulled in ppm. Cm is the motional capacitance of the crystal. CCASE is the case capacitance. CSPEC is the specified load capacitance. CLOAD is the actual load capacitance. When the crystal is loaded as specified, i.e., CLOAD = CSPEC, the frequency pulling equals zero. Control Interface Considerations 16 ENABLE T/R N.C. DF OP+ DS+ DS- 24 23 22 21 20 19 18 17 N.C. 25 16 DVDD 26 15 PDMIN 14 IFIN+ 13 IFINMIXOUT HVIN 27 AGC2 28 AGC1 29 12 MAX7030 PDMAX XTAL2 32 9 LNAOUT + 1 2 3 4 5 6 7 8 LNAIN MIXIN+ LNASRC MIXIN- 10 AVDD 11 31 PAOUT 30 TX/RX2 AGC0 XTAL1 ROUT The XTAL oscillator in the MAX7030 is designed to present a capacitance of approximately 3pF between the XTAL1 and XTAL2 pins. In most cases, this corresponds to a 4.5pF load capacitance applied to the external crystal when typical PCB parasitics are added. It is very important to use a crystal with a load capacitance that is equal to the capacitance of the MAX7030 crystal oscillator plus PCB parasitics. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. Crystals designed to operate with higher differential load capacitance always pull the reference frequency higher. TOP VIEW TX/RX1 Crystal Oscillator (XTAL) Pin Configuration DATA When operating the MAX7030 with a +4.5V to +5.5V supply voltage, the AGC0, ACG1, AGC2, DATA, ENABLE and T/R pins may be driven by a microcontroller with either 3V or 5V interface logic levels. When operating the MAX7030 with a +2.1V to +3.6V supply, the microcontroller must produce logic levels which conform to the VIH and VIL specifications in the DC Electrical Characteristics for the MAX7030. PAVDD MAX7030 Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL THIN QFN Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030 Table 3. Component Values for Typical Application Circuit COMPONENT VALUE FOR 433.92MHz RF VALUE FOR 315MHz RF DESCRIPTION C1 220pF 220pF 5% C2 680pF 680pF 5% C3 6.8pF 12pF 5% C4 6.8pF 10pF 5% C5 10pF 22pF 5% C6 220pF 220pF 5% 10% C7 0.1μF 0.1μF C8 100pF 100pF 5% C9 1.8pF 2.7pF ±0.1pF C10 100pF 100pF 5% C11 220pF 220pF 5% C12 100pF 100pF 5% C13 1500pF 1500pF 10% C14 0.047μF 0.047μF 10% C15 0.047μF 0.047μF 10% C16 470pF 470pF 5% C17 220pF 220pF 5% C18 220pF 220pF 5% C19 0.01μF 0.01μF 5% C20 100pF 100pF 5% C21 100pF 100pF 5% C22 220pF 220pF 5% C23 0.01μF 0.01μF 10% C24 0.01μF 0.01μF 10% L1 22nH 27nH 5% or better* L2 22nH 30nH 5% or better* L3 22nH 30nH 5% or better* L4 10nH 12nH 5% or better* L5 16nH 30nH 5% or better* L6 68nH 100nH 5% or better* R1 100k 100k 5% R2 100k 100k 5% R3 0 0 — X1 17.63416MHz 12.67917MHz Crystal, 4.5pF CLOAD, Crystek or Hong Kong Crystal Y1 10.7MHz ceramic filter 10.7MHz ceramic filter Murata *Wire Wound recommended. Note: Component values vary depending on PCB layout. 17 Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030 Typical Application Circuit AGC0 AGC1 AGC2 VDD X1 VDD 27 26 25 N.C. 28 DVDD 29 HVIN 30 AGC2 PAVDD 31 AGC1 32 1 AGC0 VDD XTAL1 C23 C24 C19 C18 C20 C21 XTAL2 3.0V 2 24 DATA C22 ROUT 23 ENABLE R3* C1 4 L1 5 21 N.C. 20 DF PAOUT VDD 6 C5 OP+ 19 C17 C6 L4 LNAIN LNASRC 9 11 10 C10 12 C12 C9 13 C13 14 PDMIN 8 PDMAX DS+ 7 IFIN+ L6 IFIN- C8 EXPOSED PAD AVDD MIXOUT C7 L3 MAX7030 MIXIN- C4 C3 TRANSMIT/ RECEIVE TX/RX2 MIXIN+ L2 TX/RX1 LNAOUT C2 ENABLE 22 T/R 3 DATA 15 16 DS- C16 18 17 R1 C15 VDD L5 IN GND C11 Y1 R2 OUT C14 *OPTIONAL POWER-ADJUST RESISTOR Chip Information PROCESS: CMOS 18 Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 32 Thin QFN-EP T3255+3 21-0140 90-0001 Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL LNAOUT MIXIN+ MIXIN9 10 MIXOUT IFIN+ IFIN- 12 14 13 11 IF LIMITING AMPS 0° LNAIN 7 LNASRC 8 LNA Σ 90° I Q 20 DF RSSI 100kΩ 19 OP+ RX FREQUENCY DIVIDER XTAL1 DATA FILTER 18 DS+ 31 CRYSTAL OSCILLATOR XTAL2 100kΩ RX VCO PHASE DETECTOR 32 TX FREQUENCY DIVIDER 15 PDMIN CHARGE PUMP 16 PDMAX TX VCO HVIN 27 3.0V REGULATOR ΔΣ MODULATOR LOOP FILTER 17 DSRX DATA AVDD 6 EXPOSED PAD MAX7030 30 AGC0 PA 29 AGC1 DIGITAL LOGIC 28 AGC2 24 DATA 2 1 5 3 4 22 ROUT PAVDD PAOUT TX/RX1 TX/RX2 T/R 26 23 DVDD ENABLE 19 MAX7030 Functional Diagram MAX7030 Low-Cost, 315MHz and 433.92MHz ASK Transceiver with Fractional-N PLL Revision History PAGES CHANGED REVISION NUMBER REVISION DATE 0 5/05 Initial release — 1 9/08 Added + to each part to denote lead-free/RoHS-compliant package and explicitly calling out the odd frequency as contact factory for availability 1 2 6/09 Made correction in Power Amplifier (PA) section 15 3 11/10 4 6/12 DESCRIPTION Updated AC Electrical Characteristics, Absolute Maximum Ratings, and Package Information Deleted the MAX7030MATJ+ from the Selector Guide and all references to the MAX7030MATJ+ throughout the data sheet; updated fXTAL reference in the PhaseLocked Loop section; updated Power Amplifier section; inserted Control Interface Considerations; updated Table 3 2, 5, 18 1, 13, 15, 16, 17, 18 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical. Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 20 ____________________Maxim Integrated Products, 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.