SN6501 www.ti.com SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 Transformer Driver for Isolated Power Supplies Check for Samples: SN6501 FEATURES APPLICATIONS • • • • 1 • • Push-Pull Driver for Small Transformers Single 3.3 V or 5 V Supply High Primary-side Current Drive: – 5 V Supply: 350 mA (max) – 3.3 V Supply: 150 mA (max) Low Ripple on Rectified Output Permits Small Output Capacitors Small 5-pin SOT23 Package • • • Isolated Interface Power Supply for CAN, RS485, RS-422, RS-232, SPI, I2C, Low-Power LAN Industrial Automation Process Control Medical Equipment DESCRIPTION The SN6501 is a monolithic oscillator/power-driver, specifically designed for small form factor, isolated power supplies in isolated interface applications. It drives a low-profile, center-tapped transformer primary from a 3.3 V or 5 V DC power supply. The secondary can be wound to provide any isolated voltage based on transformer turns ratio. The SN6501 consists of an oscillator followed by a gate drive circuit that provides the complementary output signals to drive the ground referenced N-channel power switches. The internal logic ensures break-before-make action between the two switches. The SN6501 is available in a small SOT23-5 package, and is specified for operation at temperatures from –40°C to 125°C. VIN = 3.3V 10µF SN6501 4 3 GND 1:2.2 MBR0520L TPS76350 VOUT D2 2 2 10µF 0.1µF Vcc 5 1 GND 1 3 IN OUT 5 GND EN NC 4 VOUT-REG = 5V 10µF D1 MBR0520L Figure 1. Typical Operating Circuit 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated SN6501 SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM SN6501 D1 Q VCC Gate Drive OSC D2 Q GND GND PIN FUNCTIONS D1 1 VCC 2 D2 3 5 GND 4 GND PIN No. NAME 1 D1 Drain 1 DESCRIPTION 2 Vcc Supply voltage 3 D2 Drain 2 4,5 GND Ground TEST CIRCUIT VIN SN6501 4 GND D2 VCC 5 GND D1 3 50W 10µF 2 1 50W Figure 2. Test Circuit for RON, fOSC, fSt, tr-D, tf-D, tBBM VIN 10µF SN6501 4 T1 3 GND MBR0520L 1 D2 VCC 5 2 2 10µF 0.1µF 3 1 GND LDO TP1 IN TP2 OUT 5 GND EN VOUT 10µF NC 4 D1 0.1µF MBR0520L Figure 3. Test Circuit for Output Voltage and Efficiency at TP1 and TP2 (see Figure 4 to Figure 23) 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 SN6501 www.ti.com SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUES VCC Supply voltage VD1, VD2 Output switch voltage –0.3 V to +6 V ID1P, ID2P Peak output switch current 500 mA PTOT Continuous power dissipation 250 mW ESD Human Body Model ESDA/JEDEC JS-001-2012 Charged Device Model JEDEC JESD22-C101E Machine Model JEDEC JESD22-A115-A 14 V TSTG Storage temperature range TJ Junction temperature (1) ±4 kV All Pins ±1.5 kV ±200 V –65°C to 150°C 170°C Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under RECOMMENDED OPERATING CONDITIONS is not implied. Exposure to absolute-maximum-rated conditions for extended periods affects device reliability. THERMAL INFORMATION SN6501 THERMAL METRIC (1) DBV 5-PINS θJA Junction-to-ambient thermal resistance 208.3 θJCtop Junction-to-case (top) thermal resistance 87.1 θJB Junction-to-board thermal resistance 40.4 ψJT Junction-to-top characterization parameter 5.2 ψJB Junction-to-board characterization parameter 39.7 θJCbot Junction-to-case (bottom) thermal resistance N/A UNITS °C/W need space between thermal table note and ROC title (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS VCC Supply voltage VD1, VD2 Output switch voltage ID1, ID2 D1 and D2 output switch current – Primary-side TA VCC = 5 V ± 10%, MIN TYP MAX 3 5.5 0 11 0 7.2 VCC = 3.3 V ± 10% When connected to Transformer with primary winding Center-tapped VCC = 5 V ± 10% VD1, VD2 Swing ≥ 3.8 V, see Figure 27 for typical characteristics 350 VCC = 3.3 V ± 10% VD1, VD2 Swing ≥ 2.5 V, see Figure 26 for typical characteristics 150 Ambient temperature 125 Submit Documentation Feedback Product Folder Link(s) :SN6501 V V mA –40 Copyright © 2012, Texas Instruments Incorporated UNIT °C 3 SN6501 SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS Over full-range of recommended operating conditions, unless otherwise noted PARAMETER RON Switch-on resistance ICC Average supply current (1) fST Startup frequency fOSC Oscillator frequency tr-D D1, D2 output rise time tf-D D1, D2 output fall time tBBM Break-before-make time (1) 4 TEST CONDITIONS MIN TYP MAX VCC = 3.3 V ± 10%, See Figure 2 1 3 VCC = 5.0 V ± 10%, See Figure 2 0.6 2 VCC = 3.3 V ± 10%, no load 150 400 VCC = 5.0 V ± 10%, no load 300 700 VCC = 2.4 V, See Figure 2 300 250 360 550 VCC = 5.0 V ± 10%, See Figure 2 300 410 620 70 VCC = 5.0 V ± 10%, See Figure 2 80 VCC = 3.3 V ± 10%, See Figure 2 110 VCC = 5.0 V ± 10%, See Figure 2 60 VCC = 3.3 V ± 10%, See Figure 2 150 VCC = 5.0 V ± 10%, See Figure 2 50 Ω uA kHz VCC = 3.3 V ± 10%, See Figure 2 VCC = 3.3 V ± 10%, See Figure 2 UNIT kHz ns ns ns Average supply current is the current used by SN6501 only. It does not include load current. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 SN6501 www.ti.com SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 TYPICAL OPERATING CHARACTERISTICS Typical Curves in Figure 4 through Figure 23 are measured with Circuit in Figure 3 at TP1 and TP2. TA = 25°C unless otherwise noted. 9 90 8 80 TP1 TP1 7 70 Efficiency - % VOUT - V 6 TP2 5 4 3 50 40 30 2 20 T1 = 1:1.5 (DA2303-AL from Coilcraft) VIN = 5 V, Vout = 5 V LDO = TPS73250 1 0 TP2 60 0 40 80 T1 = 1:1.5 (DA2303-AL from Coilcraft) VIN = 5 V, Vout = 5 V LDO = TPS73250 10 120 160 ILOAD - mA 200 240 0 280 0 40 Figure 4. Output Voltage vs Load Current 80 120 160 ILOAD - mA 200 240 280 Figure 5. Efficiency vs Load Current 9 90 8 80 7 70 6 60 TP1 5 Efficiency - % VOUT - V TP2 TP1 4 TP2 3 50 40 30 2 20 T1 = 1:1.5 (DA2303-AL from Coilcraft) VIN = 3.3 V, Vout = 3.3 V LDO = TPS76333 1 0 0 T1 = 1:1.5 (DA2303-AL from Coilcraft) VIN = 3.3 V, Vout = 3.3 V LDO = TPS76333 10 0 20 40 60 80 0 100 20 40 60 ILOAD - mA ILOAD - mA Figure 6. Output Voltage vs Load Current 100 120 Figure 7. Efficiency vs Load Current 90 9 8 80 TP1 7 TP1 70 Efficiency - % 6 VOUT - V 80 5 TP2 4 3 TP2 60 50 40 30 2 20 T1 = 1:2.2 (DA2304-AL from Coilcraft) VIN = 3.3 V, Vout = 5 V LDO = TPS76350 1 0 0 0 10 20 30 40 ILOAD - mA T1 = 1:2.2 (DA2304-AL from Coilcraft) VIN = 3.3 V, Vout = 5 V LDO = TPS76350 10 50 60 70 0 Figure 8. Output Voltage vs Load Current 10 20 30 40 50 ILOAD - mA 60 70 Figure 9. Efficiency vs Load Current Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 80 5 SN6501 SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com TYPICAL OPERATING CHARACTERISTICS (continued) Typical Curves in Figure 4 through Figure 23 are measured with Circuit in Figure 3 at TP1 and TP2. TA = 25°C unless otherwise noted. 9 90 8 80 TP1 7 70 TP2 TP1 Efficiency - % VOUT - V 6 TP2 5 4 3 60 50 40 30 2 20 T1 = 1:2.0 (MA5632-AL from Coilcraft) VIN = 3.3 V, Vout = 5 V LDO = TPS76350 1 10 0 0 10 20 30 40 50 ILOAD - mA 60 70 T1 = 1:2.0 (MA5632-AL from Coilcraft) VIN = 3.3 V, Vout = 5 V LDO = TPS76350 0 0 80 10 Figure 10. Output Voltage vs Load Current 20 30 40 50 ILOAD - mA 60 70 80 Figure 11. Efficiency vs Load Current 8 90 7 80 TP1 TP1 VOUT - V Efficiency - % TP2 5 TP2 70 6 4 3 60 50 40 30 2 20 T1 = 1:1.31 (78253/55MC from Murata) VIN = 5 V, Vout = 5 V LDO = TPS73250 1 0 0 0 0 20 40 60 80 T1 = 1:1.31 (78253/55MC from Murata) VIN = 5 V, Vout = 5 V LDO = TPS73250 10 100 120 ILOAD - mA 140 160 180 200 20 Figure 12. Output Voltage vs Load Current 40 60 80 100 120 ILOAD - mA 140 160 180 200 Figure 13. Efficiency vs Load Current 8 90 7 80 TP1 70 Efficiency - % 6 VOUT - V 5 TP1 4 TP2 3 50 40 30 2 20 T1 = 1:1.31 (78253/55MC from Murata) 1 VIN = 3.3 V, Vout = 3.3 V LDO = TPS76333 0 0 TP2 60 T1 = 1:1.31 (78253/55MC from Murata) VIN = 3.3 V, Vout = 3.3 V LDO = TPS76333 10 0 10 20 30 40 50 60 70 ILOAD - mA 80 90 100 110 120 0 10 Figure 14. Output Voltage vs Load Current 6 Submit Documentation Feedback 20 30 40 50 60 70 ILOAD - mA 80 90 100 110 120 Figure 15. Efficiency vs Load Current Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 SN6501 www.ti.com SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 TYPICAL OPERATING CHARACTERISTICS (continued) Typical Curves in Figure 4 through Figure 23 are measured with Circuit in Figure 3 at TP1 and TP2. TA = 25°C unless otherwise noted. 90 8 TP1 TP1 80 7 70 6 VOUT - V Efficiency - % TP2 5 4 3 TP2 50 40 30 2 20 T1 = 1:2.27 (78253/35MC from Murata) VIN = 3.3 V, Vout = 5 V LDO = TPS76350 1 0 60 T1 = 1:2.27 (78253/35MC from Murata) VIN = 3.3 V, Vout = 5 V LDO = TPS76350 10 0 0 10 20 30 40 ILOAD - mA 50 60 70 0 10 Figure 16. Output Voltage vs Load Current 20 30 40 ILOAD - mA 60 70 Figure 17. Efficiency vs Load Current 8 90 TP1 TP1 80 7 70 6 TP2 5 Efficiency - % VOUT - V 50 4 3 60 TP2 50 40 30 2 20 T1 = 1:1.5 (750310999 from Wurth Electronics Midcom) 1 V = 5 V, V = 5 V IN out LDO = TPS73250 0 0 40 80 120 160 ILOAD - mA 10 T1 = 1:1.5 (750310999 from Wurth Electronics Midcom) VIN = 5 V, Vout = 5 V LDO = TPS73250 0 200 240 0 40 80 Figure 18. 160 200 240 Figure 19. 90 6 TP1 80 5 TP1 70 Efficiency - % 4 VOUT - V 120 ILOAD - mA TP2 3 60 TP2 50 40 30 2 20 T1 = 1:1.5 (750310999 from Wurth Electronics Midcom) VIN = 3.3 V, VOUT = 3.3 V LDO = TPS76333 1 10 T1 = 1:1.5 (750310999 from Wurth Electronics Midcom) VIN = 3.3 V, VOUT = 3.3 V LDO = TPS76333 0 0 0 10 20 30 40 50 60 ILOAD - mA 70 80 90 100 0 10 Figure 20. 20 30 40 50 60 ILOAD - mA 70 80 90 100 Figure 21. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 7 SN6501 SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com TYPICAL OPERATING CHARACTERISTICS (continued) Typical Curves in Figure 4 through Figure 23 are measured with Circuit in Figure 3 at TP1 and TP2. TA = 25°C unless otherwise noted. 10 90 9 80 8 70 Efficiency - % TP1 7 VOUT - V TP1 6 TP2 5 4 TP2 60 50 40 30 3 20 2 T1 = 1:2.2 (750310995 from Wurth Electronics Midcom) 1 VIN = 3.3 V, Vout = 5 V LDO = TPS76350 0 0 10 20 30 40 50 ILOAD - mA T1 = 1:2.2 (750310995 from Wurth Electronics Midcom) VIN = 3.3 V, Vout = 5 V LDO = TPS76350 10 0 60 0 70 10 Figure 22. Output Voltage vs Load Current 20 30 40 ILOAD - mA 50 60 70 Figure 23. Efficiency vs Load Current 400 460 350 440 VCC = 5 V VCC = 5 V 300 f - Frequency - kHz 420 ICC - mA 250 200 VCC = 3.3 V 150 400 380 VCC = 3.3 V 360 100 340 50 0 -55 -35 -15 5 25 45 65 TA - Free-Air Temperature - °C 85 105 320 -55 125 Figure 24. Average Supply Current vs Free-Air Temperature -35 -15 5 25 45 65 TA - Free-Air Temperature - °C 85 105 125 Figure 25. D1, D2 Oscillator Frequency vs Free-Air Temperature 5 3.3 VCC = 5 V VCC = 3.3 V 4.95 3.25 VD1, VD2 Voltage Swing - V VD1, VD2 Voltage Swing - V 4.9 3.2 3.15 3.1 4.85 4.8 4.75 4.7 4.65 3.05 4.6 3 0 4.55 50 100 ID1, ID2 - mA 150 200 Figure 26. D1, D2 Primary-side Output Switch Voltage Swing vs Current 8 0 100 200 ID1, ID2 - mA 300 400 Figure 27. D1, D2 Primary-side Output Switch Voltage Swing vs Current Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 SN6501 www.ti.com SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 TYPICAL OPERATING CHARACTERISTICS (continued) Typical Curves in Figure 4 through Figure 23 are measured with Circuit in Figure 3 at TP1 and TP2. TA = 25°C unless otherwise noted. 500 mV/div D2 D1 2 V/div 2 V/div D2 D1 500 mV/div Time - 400 ns/div Figure 28. D1, D2 Switching Waveforms Time - 200 ns/div Figure 29. D1, D2 Break-Before-Make Waveform Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 9 SN6501 SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com APPLICATION INFORMATION The SN6501 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC converters utilizing the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive, comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output signals which alternately turn the two output transistors on and off. Vcc SN6501 Q2 off Q1 off D2 OSC fOSC S G2 Freq. Divider S BBM Logic G1 Q2 D1 Q1 Q1 on GND tBBM Q2 on GND Figure 30. SN6501 Block Diagram and Output Timing with Break-Before-Make Action The output frequency of the oscillator is divided down by an asynchronous divider that provides two complementary output signals, S and S, with a 50% duty cycle. A subsequent break-before-make logic inserts a dead-time between the high-pulses of the two signals. The resulting output signals, G1 and G2, present the gatedrive signals for the output transistors Q1 and Q2. As shown in Figure 31, before either one of the gates can assume logic high, there must be a short time period during which both signals are low and both transistors are high-impedance. This short period, known as break-before-make time, is required to avoid shorting out both ends of the primary. fOSC S S G1 G2 Q1 Q2 Figure 31. Detailed Output Signal Waveforms PUSH-PULL CONVERTER Push-pull converters require transformers with center-taps to transfer power from the primary to the secondary (see Figure 32). 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 SN6501 www.ti.com SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 CR1 CR1 VOUT C C RL VIN RL VIN CR2 Q2 VOUT CR2 Q1 Q2 Q1 Figure 32. Switching Cycles of a Push-Pull Converter When Q1 conducts, VIN drives a current through the lower half of the primary to ground, thus creating a negative voltage potential at the lower primary end with regards to the VIN potential at the center-tap. At the same time the voltage across the upper half of the primary is such that the upper primary end is positive with regards to the center-tap in order to maintain the previously established current flow through Q2, which now has turned high-impedance. The two voltage sources, each of which equaling VIN, appear in series and cause a voltage potential at the open end of the primary of 2×VIN with regards to ground. Per dot convention the same voltage polarities that occur at the primary also occur at the secondary. The positive potential of the upper secondary end therefore forward biases diode CR1. The secondary current starting from the upper secondary end flows through CR1, charges capacitor C, and returns through the load impedance RL back to the center-tap. When Q2 conducts, Q1 goes high-impedance and the voltage polarities at the primary and secondary reverse. Now the lower end of the primary presents the open end with a 2×VIN potential against ground. In this case CR2 is forward biased while CR1 is reverse biased and current flows from the lower secondary end through CR2, charging the capacitor and returning through the load to the center-tap. CORE MAGNETIZATION Figure 33 shows the ideal magnetizing curve for a push-pull converter with B as the magnetic flux density and H as the magnetic field strength. When Q1 conducts the magnetic flux is pushed from A to A’, and when Q2 conducts the flux is pulled back from A’ to A. The difference in flux and thus in flux density is proportional to the product of the primary voltage, VP, and the time, tON, it is applied to the primary: B ≈ VP × tON. B VIN A’ VP H RDS VDS A VIN = VP + VDS Figure 33. Core Magnetization and Self-Regulation Through Positive Temperature Coefficient of RDS(on) This volt-seconds (V-t) product is important as it determines the core magnetization during each switching cycle. If the V-t products of both phases are not identical, an imbalance in flux density swing results with an offset from the origin of the B-H curve. If balance is not restored, the offset increases with each following cycle and the transformer slowly creeps toward the saturation region. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 11 SN6501 SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com Fortunately, due to the positive temperature coefficient of a MOSFET’s on-resistance, the output FETs of the SN6501 have a self-correcting effect on V-t imbalance. In the case of a slightly longer on-time, the prolonged current flow through a FET gradually heats the transistor which leads to an increase in RDS-on. The higher resistance then causes the drain-source voltage, VDS, to rise. Because the voltage at the primary is the difference between the constant input voltage, VIN, and the voltage drop across the MOSFET, VP = VIN – VDS, VP is gradually reduced and V-t balance restored. CONVERTER DESIGN The following recommendations on components selection focus on the design of an efficient push-pull converter with high current drive capability. Contrary to popular belief, the output voltage of the unregulated converter output drops significantly over a wide range in load current. The characteristic curve in Figure 8 for example shows that the difference between VOUT at minimum load and VOUT at maximum load exceeds a transceiver’s supply range. Therefore, in order to provide a stable, load independent supply while maintaining maximum possible efficiency the implementation of a low dropout regulator (LDO) is strongly advised. The final converter circuit is shown in Figure 3. The measured VOUT and efficiency characteristics for the regulated and unregulated outputs are shown in Figure 4 to Figure 23. SN6501 DRIVE CAPABILITY The SN6501 transformer driver is designed for low-power push-pull converters with input and output voltages in the range of 3 V to 5.5 V. While converter designs with higher output voltages are possible, care must be taken that higher turns ratios don’t lead to primary currents that exceed the SN6501 specified current limits. LDO SELECTION The minimum requirements for a suitable low dropout regulator are: • Its current drive capability should slightly exceed the specified load current of the application to prevent the LDO from dropping out of regulation. Therefore for a load current of 100 mA, choose a 100 mA to 150 mA LDO. While regulators with higher drive capabilities are acceptable, they also usually possess higher dropout voltages that will reduce overall converter efficiency. • The internal dropout voltage, VDO, at the specified load current should be as low as possible to maintain efficiency. For a low-cost 150 mA LDO, a VDO of 150 mV at 100 mA is common. Be aware however, that this lower value is usually specified at room temperature and can increase by a factor of 2 over temperature, which in turn will raise the required minimum input voltage. • The required minimum input voltage preventing the regulator from dropping out of line regulation is given with: VI-min = VDO-max + VO-max. This means in order to determine VI for worst-case condition, the user must take the maximum values for VDO and VO specified in the LDO data sheet for rated output current (i.e., 100 mA) and add them together. Also specify that the output voltage of the push-pull rectifier at the specified load current is equal or higher than VImin. If it is not, the LDO will lose line-regulation and any variations at the input will pass straight through to the output. Hence below VI-min the output voltage will follow the input and the regulator behaves like a simple conductor. • The maximum regulator input voltage must be higher than the rectifier output under no-load. Under this condition there is no secondary current reflected back to the primary, thus making the voltage drop across RDS-on negligible and allowing the entire converter input voltage to drop across the primary. At this point the secondary reaches its maximum voltage of VS-max = VIN-max × n with VIN-max as the maximum converter input voltage and n as the transformer turns ratio. Thus to prevent the LDO from damage the maximum regulator input voltage must be higher than VS-max. Table 1 lists the maximum secondary voltages for various turns ratios commonly applied in push-pull converters with 100 mA output drive. Table 1. Required maximum LDO Input Voltages for Various Push-pull Configurations PUSH-PULL CONVERTER 12 LDO CONFIGURATION VIN-max [V] TURNS-RATIO VS-max [V] VI-max [V] 3.3 VIN to 3.3 VOUT 3.6 1.5 ± 3% 5.6 6 to 10 3.3 VIN to 5 VOUT 3.6 2.2 ± 3% 8.2 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 SN6501 www.ti.com SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 Table 1. Required maximum LDO Input Voltages for Various Push-pull Configurations (continued) PUSH-PULL CONVERTER LDO CONFIGURATION VIN-max [V] TURNS-RATIO VS-max [V] VI-max [V] 5 VIN to 5 VOUT 5.5 1.5 ± 3% 8.5 10 DIODE SELECTION A rectifier diode should always possess low-forward voltage to provide as much voltage to the converter output as possible. When used in high-frequency switching applications, such as the SN6501 however, the diode must also possess a short recovery time. Schottky diodes meet both requirements and are therefore strongly recommended in push-pull converter designs. An excellent choice for low-volt applications is the MBR0520L with a typical forward voltage of 275 mV at 100 mA forward current. For higher output voltages such as ±10 V and above use the MBR0530 which provides a higher DC blocking voltage of 30 V. 1 Forward Current, IF - A Forward Current, IF - A 1 0°C TJ = 100°C 75°C 25°C -25°C 0.1 0.01 TJ = 125°C 75°C 25°C -40°C 0.1 0.01 0.1 0.2 0.3 0.4 Forward Voltage, VF - V 0.5 0.2 0.3 0.4 Forward Voltage, VF - V 0.5 Figure 34. Diode Forward Characteristics for MBR0520L (left) and MBR0530 (right) CAPACITOR SELECTION The capacitors in the converter circuit in Figure 3 are multi-layer ceramic chip (MLCC) capacitors. As with all high speed CMOS ICs, the SN6501 requires a bypass capacitor in the range of 10 nF to 100 nF. The input bulk capacitor at the center-tap of the primary supports large currents into the primary during the fast switching transients. For minimum ripple make this capacitor 10 μF to 22 μF. In a 2-layer PCB design with a dedicated ground plane, place this capacitor close to the primary center-tap to minimize trace inductance. In a 4layer board design with low-inductance reference planes for ground and VIN, the capacitor can be placed at the supply entrance of the board. To ensure low-inductance paths use two vias in parallel for each connection to a reference plane or to the primary center-tap. The bulk capacitor at the rectifier output smoothes the output voltage. Make this capacitor 10 μF to 22 μF. The small capacitor at the regulator input is not necessarily required. However good analog design practice suggests, using a small value of 47 nF to 100 nF improves the regulator’s transient response and noise rejection. The LDO output capacitor buffers the regulated output for the subsequent isolator and transceiver circuitry. The choice of output capacitor depends on the LDO stability requirements specified in the data sheet. However, in most cases, a low-ESR ceramic capacitor in the range of 4.7 μF to 10 μF will satisfy these requirements. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 13 SN6501 SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com TRANSORMER SELECTION V-t Product Calculation To prevent a transformer from saturation its V-t product must be greater than the maximum V-t product applied by the SN6501. The maximum voltage delivered by the SN6501 is the nominal converter input plus 10%. The maximum time this voltage is applied to the primary is half the period of the lowest frequency at the specified input voltage. Therefore, the transformer’s minimum V-t product is determined through: T V Vtmin ³ VIN-max ´ max = IN-max 2 2 ´ fmin (1) Inserting the numeric values from the data sheet into the equation above yields the minimum V-t products of 3.6 V Vtmin ³ = 7.2 Vμs for 3.3 V, and 2 ´ 250 kHz Vtmin ³ 5.5 V = 9.1 Vμs for 5 V applications. 2 ´ 300 kHz (2) Common V-t values for low-power center-tapped transformers range from 22 Vμs to 150 Vμs with typical footprints of 10 mm x 12 mm. However, transformers specifically designed for PCMCIA applications provide as little as 11 Vμs and come with a significantly reduced footprint of 6 mm x 6 mm only. While Vt-wise all of these transformers can be driven by the SN6501, other important factors such as isolation voltage, transformer wattage, and turns ratio must be considered before making the final decision. Turns Ratio Estimate Assume the rectifier diodes and linear regulator has been selected. Also, it has been determined that the transformer choosen must have a V-t product of at least 11 Vμs. However, before searching the manufacturer websites for a suitable transformer, the user still needs to know its minimum turns ratio that allows the push-pull converter to operate flawlessly over the specified current and temperature range. This minimum transformation ratio is expressed through the ratio of minimum secondary to minimum primary voltage multiplied by a correction factor that takes the transformer’s typical efficiency of 97% into account: VP-min = VIN-min - VDS-max (3) VS-min must be large enough to allow for a maximum voltage drop, VF-max, across the rectifier diode and still provide sufficient input voltage for the regulator to remain in regulation. From the LDO SELECTION section, this minimum input voltage is known and by adding VF-max gives the minimum secondary voltage with: VS-min = VF-max + VDO-max + VO-max (4) VF VI VS VIN VDO VO RL VP VDS RDS Q Figure 35. Establishing the Required Minimum Turns Ratio Through nmin = 1.031 × VS-min / VP-min Then calculating the available minimum primary voltage, VP-min, involves subtracting the maximum possible drainsource voltage of the SN6501, VDS-max, from the minimum converter input voltage VIN-min: 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 SN6501 www.ti.com SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 VP-min = VIN-min – VDS-max (5) VDS-max however, is the product of the maximum RDS(on) and ID values for a given supply specified in the SN6501 data sheet: VDS-max = RDS-max × IDmax (6) Then inserting Equation 6 into Equation 5 yields: VP-min = VIN-min - RDS-max x IDmax (7) and inserting Equation 7 and Equation 4 into Equation 3 provides the minimum turns ration with: V + VDO-max + VO-max nmin = 1.031 ´ F-max VIN-min - RDS-max ´ ID-max (8) Example: For a 3.3 VIN to 5 VOUT converter using the rectifier diode MBR0520L and the 5 V LDO TPS76350, the data sheet values taken for a load current of 100 mA and a maximum temperature of 85°C are VF-max = 0.2 V, VDO-max = 0.2 V, and VO-max = 5.175 V. Then assuming that the converter input voltage is taken from a 3.3 V controller supply with a maximum ±2% accuracy makes VIN-min = 3.234 V. Finally the maximum values for drain-source resistance and drain current at 3.3 V are taken from the SN6501 data sheet with RDS-max = 3 Ω and ID-max = 150 mA. Inserting the values above into Equation 8 yields a minimum turns ratio of: 0.2V + 0.2V + 5.175 V nmin = 1.031 ´ =2 3.234 V - 3 Ω ´ 150 mA (9) Most commercially available transformers for 3-to-5 V push-pull converters offer turns ratios between 2.0 and 2.3 with a common tolerance of ±3%. HIGHER OUTPUT VOLTAGE DESIGNS The SN6501 can drive push-pull converters that provide high output voltages of up to 30 V, or bipolar outputs of up to ±15 V. Using commercially available center-tapped transformers, with their rather low turns ratios of 0.8 to 5, requires different rectifier topologies to achieve high output voltages. Figure 36 to Figure 39 show some of these topologies together with their respective open-circuit output voltages. n n VOUT+ = n·VIN VIN VOUT = 2n·VIN VIN VOUT- = n·VIN Figure 36. Bridge Rectifier with Center-Tapped Secondary Enables Bipolar Outputs n Figure 37. Bridge Rectifier Without Center-Tapped Secondary Performs Voltage Doubling VOUT+ = 2n·V IN VIN n VOUT = 4n·VIN VIN VOUT- = 2n·V IN Figure 38. Half-wave Rectifier Without Centertapped Secondary Performs Voltage Doubling, Centered Ground provides Bipolar Outputs Figure 39. Half-wave Rectifier Without Centered Ground and Center-tapped Secondary Performs Voltage Doubling Twice, Hence Quadrupling VIN Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 15 SN6501 SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com APPLICATION CIRCUITS The following application circuits are shown for a 3.3 V input supply commonly taken from the local, regulated micro-controller supply. For 5 V input voltages requiring different turn ratios refer to the transformer manufacturers and their websites listed in Table 2. Table 2. Transformer Manufacturers Coilcraft Inc. http://www.coilcraft.com Halo-Electronics Inc. http://www.haloelectronics.com Murata Power Solutions http://www.murata-ps.com Wurth Electronics Midcom Inc http://www.midcom-inc.com VS 3.3V 10 µF 2 Vcc D2 1:2.2 MBR0520L 3 1 SN6501 D1 IN OUT 5 ISO 5V TPS76350 10µF 0.1µF 3 1 EN GND 10µF 2 MBR0520L GND2 GND1 4 5 ISO-BARRIER 0.1µF 0.1µF 0.1µF 1µF 1 Vcc1 7,17,22 5 RST VDD 9 OSC0 STELLARIS 10 LM3S102 OSC1 6MHz 6 18pF 18pF 1µF LDO 0.1µF GND 8,18,21 U0Rx PA2 PA3 U0Tx 11 3 13 4 14 5 12 6 16 Vcc2 R RE ISO3082 DE ISO3088 B A 13 10 W(opt) 12 10 W (opt) D GND1 2,7,8 GND2 9,10,15 SM712 4.7nF/ 2kV Figure 40. Isolated RS-485 Interface 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 SN6501 www.ti.com SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 VS 10 µF 3.3V 2 Vcc D2 1:2.2 MBR0520L 3 1 SN6501 OUT ISO 5V 5 TPS76350 10µF 0.1µF D1 IN 3 EN 1 GND 10µF 2 MBR0520L GND2 GND1 5 4 ISO-BARRIER 0.1µF* 0.1µF 18pF 18pF 0.1µF* 10* 4 8 1 40 12* 3 37 VDDC RST VDD VDDA VBAT 25 30 CAN0Rx OSC0 STELLARIS 31 26 OSC1 LM3S5Y36 CAN0Tx 7 LDO GND GNDA WAKE 9* 6MHz 0.1µF 2 3 Vcc1 Vcc2 RXD CANH ISO1050 TXD GND1 CANL GND2 4 32 7 10 W (opt) 6 10 W (opt) SM712 5 4.7nF/ 2kV * = multiple pins and capacitors omitted for clarity purpose Figure 41. Isolated CAN Interface VIN 3.3V 0.1µF 2 Vcc D2 3 1:2.2 MBR0520L 1 SN6501 10µF 0.1µF GND D1 1 10µF 4,5 3 IN OUT 5 VISO 5 LP2985-50 ON MBR0520L 4 BP GND 2 10nF 3.3 µF 0.1µF ISO-BARRIER 0.1µF 0.1µF 16 1µF 0.1µF 16 1 4.7 k 2 DVcc 5 6 XOUT XIN 7 UCA0TXD 15 3 16 5 MSP430 UCA0RXD 12 F2132 P3.1 DVss 4 P3.0 11 4 6 Vcc1 Vcc2 EN1 INA EN2 ISO7242 OUTC INB OUTD GND1 2,8 OUTA INC OUTB IND GND2 1 4.7k 10 2 1µF 3 14 11 12 12 13 10 11 9 9,15 Vcc VS+ C1+ C1- VS- TRS232 C2+ C2- T1IN T1OUT R1OUT R1IN T2OUT T2IN R2IN R2OUT GND 6 1µF 4 5 1µF 14 13 7 8 TxD RxD RST CST 15 ISOGND Figure 42. Isolated RS-232 Interface Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 17 SN6501 SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com VIN 0.1µF 2 Vcc D2 3 HV Supply bus 1:2.2 MBR0520L 1 5 VISO 5 OUT 3.3µF IN SN6501 GND D1 10µF 0.1µF 3 ON 1 10 µF 4,5 15 BP 4 GND 2 10 nF MBR0520L 4 6 8 10 0.1µF 12 0.1µF 17 0.1µF 19 16 1 2 7 DVcc 5 6 XOUT XIN P3.0 11 3 14 4 MSP430 UCB0CLK F2132 UCB0SOMI 13 P3.1 DVss 12 4 5 6 Vcc1 EN1 EN2 INA OUTA INB 21 Vcc2 ISO7242 OUTB INC OUTC IND GND2 OUTD GND1 2,8 10 V..34 V 0V 0.1µF LP2985-50 10 27 14 26 13 25 12 23 11 16 Vcc RE0 IP0 RE1 IP1 RE2 IP2 RE3 IP3 SN65HVS885 3.3V RE4 RE5 RE6 RE7 IP4 IP5 IP6 IP7 SIP DB0 LD DB1 CLK RLIM SOP NC HOT CE GND 3 5 7 9 11 18 20 22 1 2 13 14 44.8 k 24 28 9,15 Figure 43. Isolated Digital Input Module VS 3.3V 0.1µF 2 Vcc D2 3 1:1.5 MBR0520L 4 SN6501 10µF 0.1µF GND D1 1 OUT 1 3.3 VISO TLV70733 3 EN GND 2 10µF 2 10µF 4,5 IN MBR0520L 1µF VIN VOUT 6 22 µF REF5025 4 GND ISO-BARRIER 0.1µF 0.1µF 0.1µF 0.1µF 4.7 k 2 DVcc 6 P1.4 XOUT MSP430 SCLK 7 G2132 8 6 SDO XIN (14-PW) 9 SDI DVss 5 4 7 3 4 5 6 1 16 VCC1 EN1 VCC2 INA INB EN2 ISO7641 OUTA OUTB INC OUTC OUTD GND1 IND GND2 2,8 4.7 k 10 14 13 12 11 9,15 3 2 28 32 31 AINP MXO VBD VA REFP 23 20 CS CH0 24 SCLK ADS7953 25 SDI 26 5 SDO CH15 BDGND AGND REFM 27 1,22 16 Analog Inputs 30 Figure 44. Isolated SPI Interface for an Analog Input Module with 16 Inputs 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 SN6501 www.ti.com SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 VS 3.3V 0.1µF 2 Vcc D2 3 1:2.2 MBR0520L 1 SN6501 GND D1 IN 5 VISO 5 3 ON 1 GND 0.1µF 8 10 µF LP2981-50 10 µF 0.1µF 9 2 10 1W 10 µF 4,5 OUT 1 MBR0520L VDD SDA ADDR 0.1µF 0.1µF 1.5k GND RDY 1.5k 5 6 DVcc XOUT SDA MSP430 G2132 XIN SCL 9 2 8 3 DVss Vcc1 SDA1 11 10 Vcc2 ISO1541 SCL1 GND1 4 1.5 k SDA2 SCL2 GND2 4 7 7 9 6 14 6 22 µF 15 8 1 AIN3 2 0.1µF 0.1µF 1.5 k 2 4 Analog Inputs 5VISO SCL SDA 5 VISO 4 SCL ADS1115 3 ISO-BARRIER AIN0 4 12 VOUT 5 VISO 2 VIN 1µF REF5040 GND 3 4 A2 VDD IOVDD VREFH 1 SDA VOUTA SCL 4 Analog Outputs DAC8574 LDAC A1 VOUTD 8 A0 A3 GND VREFL 13 16 5 6 5 Figure 45. Isolated I2C Interface for an Analog Data Acquisition System with 4 Inputs and 4 Outputs VS 3.3V 0.1µF 2 Vcc D2 3 1:1.5 MBR0520L 1 SN6501 GND D1 3 1 10 µF OUT TPS76333 10 µF 0.1µF 4,5 IN EN GND 5 3.3 VISO 10 µF 2 MBR0520L ISO-BARRIER 20 W 0.1µF 0.1µF 0.1µF 0.1µF 15 10 2 5 6 DVcc XOUT XIN 8 1 11 MSP430 P3.0 12 G2132 P3.1 DVss 4 2 3 Vcc1 OUTA Vcc2 ISO7421 INB GND1 4 INA OUTB GND2 5 8 7 5 6 4 LOW 0.1µF VA VD BASE ERRLVL DBACK LOOP+ 3 DAC161P997 DIN OUT 9 C1 C2 C3 COMA COMD 14 13 12 1 0.1µF 1µF 16 20 W LOOP- 2 3 x 2.2 nF Figure 46. Isolated 4-20mA Current Loop Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 19 SN6501 SLLSEA0C – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com REVISION HISTORY Changes from Original (February 2012) to Revision A Page • Changed the device From: Product Preview To: Production ................................................................................................ 1 • Added Figure 18 to Figure 21 ............................................................................................................................................... 7 • Changed Equation 8 ........................................................................................................................................................... 15 • Changed Equation 9 ........................................................................................................................................................... 15 • Changed Table 2, From: Wuerth-Elektronik / Midcom To: Wurth Electronics Midcom Inc ................................................ 16 • Changed Figure 44 ............................................................................................................................................................. 18 Changes from Revision A (March 2012) to Revision B Page • Changed Feature From: Small 5-pin DBV Package To: Small 5-pin SOT23 Package ........................................................ 1 • Changed Figure 3 title .......................................................................................................................................................... 2 Changes from Revision B (March 2012) to Revision C Page • Changed the fOSC Oscillator frequency values ...................................................................................................................... 4 • Changed Equation 2 ........................................................................................................................................................... 14 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :SN6501 PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp SN6501DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN6501DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Mar-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) SN6501DBVR SOT-23 DBV 5 3000 178.0 9.0 SN6501DBVT SOT-23 DBV 5 250 178.0 9.0 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 3.23 3.17 1.37 4.0 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 31-Mar-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN6501DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN6501DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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