MCP4706/4716/4726 8-/10-/12-Bit Voltage Output Digital-to-Analog Converter with EEPROM and I2C™ Interface Features: • Output Voltage Resolutions: - 12-bit: MCP4726 - 10-bit: MCP4716 - 8-bit: MCP4706 • Rail-to-Rail Output • Fast Settling Time of 6 µs (typical) • DAC Voltage Reference Options: - VDD - VREF Pin • Output Gain Options: - Unity (1x) - 2x, only when VREF pin is used as voltage source • Nonvolatile Memory (EEPROM): - Auto Recall of Saved DAC register setting - Auto Recall of Saved Device Configuration (Voltage Reference, Gain, Power-Down) • Power-Down modes: - Disconnects output buffer - Selection of VOUT pull-down resistors (640 kΩ, 125 kΩ, or 1 kΩ) • Low-Power Consumption: - Normal Operation: 210 µA typical - Power-Down Operation: 60 nA typical (PD1:PD0 = 11) • Single-Supply Operation: 2.7V to 5.5V • I2C™ Interface: - Eight Available Addresses - Standard (100 kbps), Fast (400 kbps), and High-Speed (3.4 Mbps) modes • Small 6-lead SOT-23 and DFN (2x2) Packages • Extended Temperature Range: -40°C to +125°C Applications: • • • • • • Set Point or Offset Trimming Sensor Calibration Low-Power Portable Instrumentation PC Peripherals Data Acquisition Systems Motor Control © 2011-2012 Microchip Technology Inc. Package Types MCP4706/16/26 2x2 DFN-6* SOT-23-6 VOUT 1 6 VREF VSS 2 5 SCL VDD 3 4 SDA VREF 1 SCL 2 SDA 3 6 VOUT EP 7 5 VSS 4 VDD * Includes Exposed Thermal Pad (EP); see Table 3-1. Description: The MCP4706/4716/4726 are single channel 8-bit, 10-bit, and 12-bit buffered voltage output Digital-toAnalog Converters (DAC) with nonvolatile memory and an I2C serial interface. This family will also be referred to as MCP47X6. The VREF pin or the device VDD can be selected as the DAC’s reference voltage. When VDD is selected, VDD is connected internally to the DAC reference circuit. When the VREF pin is used, the user can select the output buffer’s gain to 1 or 2. When the gain is 2, the VREF pin voltage should be limited to a maximum of VDD/2. The DAC register value and Configuration bits can be programmed to nonvolatile memory (EEPROM). The nonvolatile memory holds the DAC register and Configuration bit values when the device is powered off. A device Reset (such as a Power-on Reset) latches these stored values into the volatile memory. Power-Down modes enable system current reduction when the DAC output voltage is not required. The VOUT pin can be configured to present a low, medium, or high resistance load. These devices have a two-wire I2C™ compatible serial interface for standard (100 kHz), fast (400 kHz), or High-Speed (3.4 MHz) mode. These devices are available in small 6-pin SOT-23 and DFN 2x2 mm packages. DS22272C-page 1 MCP4706/4716/4726 Block Diagram VREF PD1:PD0 SCL DS22272C-page 2 DAC Register EEPROM Control Logic Resistor Ladder SDA I2C™ Interface Logic Buffer VOUT Op Amp PD1:PD0 VW 640 kΩ VSS 125 kΩ VDD Gain (1x or 2x) (G = 0 or 1) VRL 1 kΩ VDD Reference Selection VREF1:VREF0 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Voltage on VDD with respect to VSS .......................................................................................................... -0.6V to +6.5V Voltage on all pins with respect to VSS ..............................................................................................-0.3V to VDD + 0.3V Input clamp current, IIK (VI < 0, VI > VDD) ............................................................................................................ ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .................................................................................................. ±20 mA Maximum input current source/sunk by SDA, SCL pins ..........................................................................................2 mA Maximum output current sunk by SDA Output pin .................................................................................................25 mA Maximum current out of VSS pin .............................................................................................................................50 mA Maximum current into VDD pin ................................................................................................................................50 mA Maximum current sourced by the VOUT pin ............................................................................................................40 mA Maximum current sunk by the VOUT pin..................................................................................................................40 mA Maximum current sunk by the VREF pin ...................................................................................................................40 µA Package power dissipation (TA = +50°C, TJ = +150°C) SOT-23-6...................................................................................................................................................452 mW DFN-6......................................................................................................................................................1098 mW Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ...............................................................................................-55°C to +125°C ESD protection on all pins............................................................................................................................≥ 6 kV (HBM) ......................................................................................................................................................................≥ 400V (MM) Maximum Junction Temperature (TJ) ................................................................................................................... +150°C † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2011-2012 Microchip Technology Inc. DS22272C-page 3 MCP4706/4716/4726 ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5 kΩ from VOUT to GND, CL = 100 pF, TA = -40°C to +125°C. Typical values at +25°C. Parameters Power Requirements Input Voltage Input Current Symbol Min Typical Max Units VDD IDD 2.7 — — 210 5.5 400 V µA — 210 400 µA Power-Down Current IDDP — 0.09 2 µA Power-On Reset Threshold Power-Up Ramp Rate DC Accuracy Offset Error VPOR — 2.2 — V VRAMP 1 — — V/S ±0.02 0.75 Offset Error Temperature Coefficient Zero-Scale Error Full-Scale Error Gain Error (Note 2) VOS VOS/°C EZS EFS gE Gain Error Drift Resolution ΔG/°C n INL Error (Note 7) INL DNL Error (Note 7) DNL Note 1: 2: 3: 4: 5: 6: 7: Conditions VREF1:VREF0 = 00, SCL = SDA = VSS, VOUT is unloaded, volatile DAC Register = 0x000 VREF1:VREF0 = 11, VREF = VDD, SCL = SDA = VSS, VOUT is unloaded, volatile DAC Register = 0x000 PD1:PD0 = 01 (Note 6), VOUT not connected RAM retention voltage, (VRAM) < VPOR (Note 1, Note 4) % of FSR Code = 0x000h VREF1:VREF0 = 00, G = 0 — ±1 — ppm/°C -40°C to +25°C — ±2 — ppm/°C +25°C to +85°C — 0.13 2.0 LSb MCP4706, Code = 0x00h — 0.52 7.7 LSb MCP4716, Code = 0x000h — 2.05 30.8 LSb MCP4726, Code = 0x000h — 0.3 5.2 LSb MCP4706, Code = 0xFFh — 1.1 20.5 LSb MCP4716, Code = 0x3FFh — 4.1 82.0 LSb MCP4726, Code = 0xFFFh -2 -0.10 2 % of FSR MCP4706, Code = 0xFFh VREF1:VREF0 = 00, G = 0 -2 -0.10 2 % of FSR MCP4716, Code = 0x3FFh VREF1:VREF0 = 00, G = 0 -2 -0.10 2 % of FSR MCP4726, Code = 0xFFFh VREF1:VREF0 = 00, G = 0 — -3 — ppm/°C 8 bits MCP4706 10 bits MCP4716 12 bits MCP4726 -0.907 ±0.125 +0.907 LSb MCP4706 (codes: 6 to 250) -3.625 ±0.5 +3.625 LSb MCP4716 (codes: 25 to 1000) -14.5 ±2 +14.5 LSb MCP4726 (codes: 100 to 4000) -0.05 ±0.0125 +0.05 LSb MCP4706 (codes: 6 to 250) -0.188 ±0.05 +0.188 LSb MCP4716 (codes: 25 to 1000) -0.75 ±0.2 +0.75 LSb MCP4726 (codes: 100 to 4000) This parameter is ensured by design and is not 100% tested. This Gain error does not include Offset error. See Section 1.0 “Electrical Characteristics” for more details in plots. Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device). The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of VDD over time. This parameter is ensured by characterization, and not 100% tested. The PD1:PD0 = 10, and ‘11’ configurations should have the same current. VDD = VREF = 5.5V. DS22272C-page 4 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5 kΩ from VOUT to GND, CL = 100 pF, TA = -40°C to +125°C. Typical values at +25°C. Parameters Output Amplifier Minimum Output Voltage Maximum Output Voltage Phase Margin Slew Rate Short Circuit Current Settling Time Power-Down Output Disable Time Delay Power-Down Output Enable Time Delay Symbol Min Typical Max Units VOUT(MIN) — 0.01 — V Output Amplifier’s minimum drive VOUT(MAX) — — V Output Amplifier’s maximum drive PM — VDD – 0.04 66 — SR ISC tSETTLING TPDD — 7 — — 0.55 15 6 1 — 24 — — Degree (°) V/µs mA µs µs TPDE — 10.5 — µs — V V kΩ pF kHz External Reference (VREF) (Note 1) Input Range VREF 0.04 Input Impedance Input Capacitance -3 dB Bandwidth Total Harmonic Distortion RVREF C_REF THD Dynamic Performance (Note 1) Major Code Transition Glitch Digital Feedthrough Note 1: 2: 3: 4: 5: 6: 7: 0 — — — — 210 29 86.5 VDD 0.04 VDD — — — — 67.7 — kHz — -73 — dB — 45 — nV-s — <10 — nV-s Conditions CL = 400 pF, RL = ∞ Note 3 PD1:PD0 = 00 -> 11, ‘10’, or ‘01’ started from falling edge SCL at end of ACK bit. VOUT = VOUT - 10 mV. VOUT not connected. PD1:PD0 = 11, ‘10’, or ‘01’ -> “00” started from falling edge SCL at end of ACK bit. Volatile DAC Register = FFh, VOUT = 10 mV. VOUT not connected. Buffered mode Unbuffered mode Unbuffered mode Unbuffered mode VREF = 2.048V ± 0.1V, VREF1:VREF0 = 10, G = 0 VREF = 2.048V ± 0.1V, VREF1:VREF0 = 10, G = 1 VREF = 2.048V ± 0.1V, VREF1:VREF0 = 10, G = 0, Frequency = 1 kHz 1 LSb change around major carry (800h to 7FFh) This parameter is ensured by design and is not 100% tested. This Gain error does not include Offset error. See Section 1.0 “Electrical Characteristics” for more details in plots. Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device). The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of VDD over time. This parameter is ensured by characterization, and not 100% tested. The PD1:PD0 = 10, and ‘11’ configurations should have the same current. VDD = VREF = 5.5V. © 2011-2012 Microchip Technology Inc. DS22272C-page 5 MCP4706/4716/4726 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5 kΩ from VOUT to GND, CL = 100 pF, TA = -40°C to +125°C. Typical values at +25°C. Parameters Digital Interface Output Low Voltage Input High Voltage (SDA and SCL Pins) Input Low Voltage (SDA and SCL Pins) Input Leakage Pin Capacitance EEPROM EEPROM Write Time Data Retention Endurance Note 1: 2: 3: 4: 5: 6: 7: Symbol Min Typical Max Units VOL VIH — 0.7VDD — — 0.4 — V V VIL — — 0.3VDD V ILI — — ±1 µA CPIN — — 3 pF TWRITE — — 1 25 200 — 50 — — ms Years Million Cycles Conditions IOL = 3 mA SCL = SDA = VSS or SCL = SDA = VDD (Note 5) At +25°C, (Note 1) At +25°C, (Note 1) This parameter is ensured by design and is not 100% tested. This Gain error does not include Offset error. See Section 1.0 “Electrical Characteristics” for more details in plots. Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device). The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of VDD over time. This parameter is ensured by characterization, and not 100% tested. The PD1:PD0 = 10, and ‘11’ configurations should have the same current. VDD = VREF = 5.5V. DS22272C-page 6 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 I2C Mode Timing Waveforms and Requirements 1.1 VPOR (VBOR) VDD tPORD SCL tBORD VIH VIH SDA VOUT pulled down by internal 500 kΩ (typical) resistor VOUT I2C™ Interface is operational FIGURE 1-1: Power-On and Brown-Out Reset Waveforms. Stop ACK Start ACK SDA SCL tPDE tPDD VOUT I2C Power-Down Command Timing. FIGURE 1-2: TABLE 1-1: RESET TIMING Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +125°C (extended) Timing Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Parameters Sym Min Typ Max Units Conditions Power-Up Reset Delay tPORD — 60 — µs Monitor ACK bit response to ensure device responds to command. Brown-Out Reset Delay tBORD — 1 — µs VDD transitions from VDD(MIN) → > VPOR VOUT driven to VOUT disabled Power-Down Disable Time Delay TPDD — 2.5 — µs VDD = 5V PD1:PD0 → 00 (from ‘01’, ‘10’, or ‘11’), from falling edge SCL at end of ACK bit. — 5 — µs VDD = 3V PD1:PD0 → 00 (from ‘01’, ‘10’, or ‘11’), from falling edge SCL at end of ACK bit. — 10.5 — µs PD1:PD0 → 01, ‘10’, or ‘11’ (from ‘00’), from falling edge SCL at end of ACK bit. Power-Down Enable Time Delay TPDE © 2011-2012 Microchip Technology Inc. DS22272C-page 7 MCP4706/4716/4726 VIH SCL 93 91 90 92 111 SDA VIL Start Condition Stop Condition I2C Bus Start/Stop Bits Timing Waveforms. FIGURE 1-3: I2C BUS START/STOP BITS REQUIREMENTS TABLE 1-2: I2C™ AC Characteristics Param. Symbol No. FSCL D102 90 91 92 93 Cb TSU:STA THD:STA TSU:STO Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in Electrical Characteristics Characteristic SCL pin Frequency Bus capacitive loading Min Max Units Standard mode 0 100 kHz Cb = 400 pF, 2.7V - 5.5V Fast mode 0 400 kHz Cb = 400 pF, 2.7V - 5.5V High-Speed 1.7 0 1.7 MHz Cb = 400 pF, 4.5V - 5.5V High-Speed 3.4 0 3.4 MHz Cb = 100 pF, 4.5V - 5.5V 100 kHz mode — 400 pF 400 kHz mode — 400 pF 1.7 MHz mode — 400 pF 3.4 MHz mode — 100 pF Start condition 100 kHz mode 4700 — ns Setup time 400 kHz mode 600 — ns 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns Start condition 100 kHz mode 4000 — ns Hold time 400 kHz mode 600 — ns 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns Stop condition 100 kHz mode 4000 — ns Setup time 400 kHz mode 600 — ns 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns THD:STO Stop condition Hold time Conditions 100 kHz mode 4000 — ns 400 kHz mode 600 — ns 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns Only relevant for repeated Start condition After this period, the first clock pulse is generated 94 THVCSU HVC to SCL Setup time 25 — uS High Voltage Commands 95 THVCHD SCL to HVC Hold time 25 — uS High Voltage Commands DS22272C-page 8 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 103 102 100 101 SCL 90 106 91 92 107 SDA In 110 109 109 SDA Out I2C Bus Data Timing. FIGURE 1-4: TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) I2C™ AC Characteristics Param. No. Sym Characteristic 100 THIGH Clock high time 101 Note 1: 2: 3: 4: 5: 6: 7: 8: TLOW Clock low time Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in Electrical Characteristics Min Max Units 100 kHz mode 4000 — ns 2.7V-5.5V 400 kHz mode 600 — ns 2.7V-5.5V 1.7 MHz mode 120 ns 4.5V-5.5V 3.4 MHz mode 60 — ns 4.5V-5.5V 100 kHz mode 4700 — ns 2.7V-5.5V 400 kHz mode 1300 — ns 2.7V-5.5V 1.7 MHz mode 320 ns 4.5V-5.5V 3.4 MHz mode 160 ns 4.5V-5.5V — Conditions As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit to the SDA line. TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. The MCP47X6 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested. This parameter ensured by characterization. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than tSP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. Ensured by the TAA 3.4 MHz specification test. The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA). © 2011-2012 Microchip Technology Inc. DS22272C-page 9 MCP4706/4716/4726 I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) TABLE 1-3: I2C™ AC Characteristics Param. No. Sym 102A(5) TRSCL 102B(5) 103A 103B (5) (5) Note 1: 2: 3: 4: 5: 6: 7: 8: TRSDA TFSCL TFSDA Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in Electrical Characteristics Characteristic SCL rise time SDA rise time SCL fall time SDA fall time Min Max Units 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 80 ns 1.7 MHz mode 20 160 ns Conditions Cb is specified to be from 10 to 400 pF (100 pF maximum for 3.4 MHz mode) After a Repeated Start condition or an Acknowledge bit 3.4 MHz mode 10 40 ns 3.4 MHz mode 10 80 ns After a Repeated Start condition or an Acknowledge bit 100 kHz mode — 1000 ns Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode) 400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 80 ns 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 80 ns 3.4 MHz mode 10 40 ns 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb(4) 300 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 80 ns Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode) Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode) As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit to the SDA line. TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. The MCP47X6 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested. This parameter ensured by characterization. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than tSP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. Ensured by the TAA 3.4 MHz specification test. The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA). DS22272C-page 10 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) I2C™ AC Characteristics Param. No. 106 107 109 110 Note 1: 2: 3: 4: 5: 6: 7: 8: Sym Characteristic THD:DAT Data input hold time TSU:DAT Data input setup time TAA TBUF Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in Electrical Characteristics Output valid from clock Bus free time Min Max Units Conditions 100 kHz mode 0 — ns 2.7V-5.5V, Note 6 400 kHz mode 0 — ns 2.7V-5.5V, Note 6 1.7 MHz mode 0 — ns 4.5V-5.5V, Note 6 3.4 MHz mode 0 — ns 4.5V-5.5V, Note 6 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 1.7 MHz mode 10 — ns 3.4 MHz mode 10 — ns 100 kHz mode — 3750 ns 400 kHz mode — 1200 ns 1.7 MHz mode — 150 ns Cb = 100 pF, Note 1, Note 7, Note 8 — 310 ns Cb = 400 pF, Note 1, Note 5, Note 8 3.4 MHz mode — 150 ns Cb = 100 pF, Note 1, Note 8 100 kHz mode 4700 — ns Time the bus must be free before a new transmission can start 400 kHz mode 1300 — ns 1.7 MHz mode N/A — ns 3.4 MHz mode N/A — ns Note 1, Note 8 As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit to the SDA line. TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. The MCP47X6 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested. This parameter ensured by characterization. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than tSP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. Ensured by the TAA 3.4 MHz specification test. The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA). © 2011-2012 Microchip Technology Inc. DS22272C-page 11 MCP4706/4716/4726 I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) TABLE 1-3: I2C™ AC Characteristics Param. No. Sym Characteristic 111 TSP Input filter spike suppression (SDA and SCL) Note 1: 2: 3: 4: 5: 6: 7: 8: Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in Electrical Characteristics Min Max Units Conditions 100 kHz mode — 50 ns 400 kHz mode — 50 ns 1.7 MHz mode — 10 ns Spike suppression 3.4 MHz mode — 10 ns Spike suppression NXP Spec states N/A As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit to the SDA line. TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. The MCP47X6 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested. This parameter ensured by characterization. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than tSP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. Ensured by the TAA 3.4 MHz specification test. The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA). DS22272C-page 12 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Symbol Min Typical Max Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 6L-SOT-23 θJA — 190 — °C/W Thermal Resistance, 6L-DFN (2 x 2) θJA — 91 — °C/W Conditions Temperature Ranges Note 1 Thermal Package Resistances Note 1: The MCP47X6 devices operate over this extended temperature range, but with reduced performance. Operation in this range must not cause TJ to exceed the Maximum Junction Temperature of +150°C. © 2011-2012 Microchip Technology Inc. DS22272C-page 13 MCP4706/4716/4726 NOTES: DS22272C-page 14 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. 12 8 -40C +25C +85C +125C 8 4 INL Error (LSb) INL Error (LSb) 12 -40C +25C +85C +125C 0 -4 -8 4 0 -4 -8 -12 -12 0 1024 2048 3072 4096 0 1024 Volatile DAC Register Code FIGURE 2-1: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = 00. -40C +25C +85C +125C 2 1 INL Error (LSb) INL Error (LSb) 4096 3 -40C +25C +85C +125C 0 -1 -2 1 0 -1 -2 -3 -3 0 128 256 384 512 640 768 896 1024 0 128 Volatile DAC Register Code 256 384 512 640 768 896 1024 Volatile DAC Register Code FIGURE 2-2: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = 00. FIGURE 2-5: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = 00. 1.0 1.0 -40C +25C +85C +125C -40C +25C +85C +125C 0.5 0.5 INL Error (LSb) INL Error (LSb) 3072 FIGURE 2-4: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = 00. 3 2 2048 Volatile DAC Register Code 0.0 -0.5 0.0 -0.5 -1.0 -1.0 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-3: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = 00. © 2011-2012 Microchip Technology Inc. 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-6: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = 00. DS22272C-page 15 MCP4706/4716/4726 0.4 0.4 0.3 0.3 0.2 0.2 DNL Error (LSb) DNL Error (LSb) Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. 0.1 0.0 -0.1 -0.2 0.1 0.0 -0.1 -0.2 -40C +25C +85C +125C -0.3 -40C +25C +85C +125C -0.3 -0.4 -0.4 0 1024 2048 3072 4096 0 1024 Volatile DAC Register Code 0.3 0.3 0.2 0.2 0.1 0.1 0.0 -0.1 -40C +25C +85C +125C 4096 0.0 -0.1 -40C +25C +85C +125C -0.2 -0.3 -0.3 0 128 256 384 512 640 768 896 0 1024 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-8: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = 00. FIGURE 2-11: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = 00. 0.20 0.20 0.15 0.15 0.10 0.10 DNL Error (LSb) DNL Error (LSb) 3072 FIGURE 2-10: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = 00. DNL Error (LSb) DNL Error (LSb) FIGURE 2-7: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = 00. -0.2 2048 Volatile DAC Register Code 0.05 0.00 -0.05 -0.10 0.05 0.00 -0.05 -0.10 -40C +25C +85C +125C -0.15 -40C +25C +85C +125C -0.15 -0.20 -0.20 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-9: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = 00. DS22272C-page 16 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-12: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = 00. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. -18.0 2.7V 5.0V 5.5V -20.0 Full Scale Error (LSb) Zero Scale Error (LSb) 2.0 1.5 1.0 0.5 -22.0 -24.0 -26.0 -28.0 2.7V 5.0V 5.5V -30.0 0.0 -32.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 Temperature (°C) FIGURE 2-13: Zero-Scale Error (ZSE) vs. VDD and Temperature (MCP4726). VREF1:VREF0 = 00. 80 100 120 -4.0 2.7V 5.0V 5.5V 0.4 0.3 0.2 -5.0 -6.0 -7.0 0.1 2.7V 5.0V 5.5V 0.0 -8.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 Temperature (°C) 0.20 40 60 80 100 120 Temperature (°C) FIGURE 2-14: Zero-Scale Error (ZSE) vs. VDD and Temperature (MCP4716). VREF1:VREF0 = 00. FIGURE 2-17: Full-Scale Error (FSE) vs. VDD and Temperature (MCP4716). VREF1:VREF0 = 00. 0.0 2.7V 5.0V 5.5V Full Scale Error (LSb) Zero Scale Error (LSb) 60 FIGURE 2-16: Full-Scale Error (FSE) vs. VDD and Temperature (MCP4726). VREF1:VREF0 = 00. Full Scale Error (LSb) Zero Scale Error (LSb) 0.5 40 Temperature (°C) 0.15 0.10 0.05 -0.5 -1.0 -1.5 2.7V 5.0V 5.5V 0.00 -2.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-15: Zero-Scale Error (ZSE) vs. VDD and Temperature (MCP4706). VREF1:VREF0 = 00. © 2011-2012 Microchip Technology Inc. -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-18: Full-Scale Error (FSE) vs. VDD and Temperature (MCP4706). VREF1:VREF0 = 00. DS22272C-page 17 MCP4706/4716/4726 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. 12 12 -40C +25C +85C +125C 8 4 INL Error (LSb) INL Error (LSb) 8 -40C +25C +85C +125C 0 -4 -8 4 0 -4 -8 -12 -12 0 1024 2048 3072 4096 0 1024 Volatile DAC Register Code FIGURE 2-19: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = VDD. 4096 3 -40C +25C +85C +125C 2 -40C +25C +85C +125C 2 1 INL Error (LSb) INL Error (LSb) 3072 FIGURE 2-22: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = 10, G = 0, VREF = VDD. 3 0 -1 -2 1 0 -1 -2 -3 -3 0 128 256 384 512 640 768 896 1024 0 128 Volatile DAC Register Code 256 384 512 640 768 896 1024 Volatile DAC Register Code FIGURE 2-20: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = VDD. FIGURE 2-23: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = 10, G = 0, VREF = VDD. 1.0 1.0 -40C +25C +85C +125C -40C +25C +85C +125C 0.5 INL Error (LSb) 0.5 INL Error (LSb) 2048 Volatile DAC Register Code 0.0 -0.5 0.0 -0.5 -1.0 -1.0 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-21: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = VDD. DS22272C-page 18 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-24: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = 10, G = 0, VREF = VDD. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 0.4 0.4 0.3 0.3 0.2 0.2 DNL Error (LSb) DNL Error (LSb) Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. 0.1 0.0 -0.1 -0.2 0.1 0.0 -0.1 -0.2 -40C +25C +85C +125C -0.3 -40C +25C +85C +125C -0.3 -0.4 -0.4 0 1024 2048 3072 4096 0 1024 Volatile DAC Register Code 0.3 0.3 0.2 0.2 0.1 0.1 0.0 -0.1 -40C +25C +85C +125C 4096 0.0 -0.1 -40C +25C +85C +125C -0.2 -0.3 -0.3 0 128 256 384 512 640 768 896 0 1024 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-26: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = VDD. FIGURE 2-29: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = 10, G = 0, VREF = VDD. 0.20 0.20 0.15 0.15 0.10 0.10 DNL Error (LSb) DNL Error (LSb) 3072 FIGURE 2-28: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = 10, G = 0, VREF = VDD. DNL Error (LSb) DNL Error (LSb) FIGURE 2-25: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = VDD. -0.2 2048 Volatile DAC Register Code 0.05 0.00 -0.05 -0.10 0.05 0.00 -0.05 -0.10 -40C +25C +85C +125C -0.15 -40C +25C +85C +125C -0.15 -0.20 -0.20 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-27: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = VDD. © 2011-2012 Microchip Technology Inc. 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-30: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = 10, G = 0, VREF = VDD. DS22272C-page 19 MCP4706/4716/4726 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. -18.0 2.7V 5.0V 5.5V -20.0 Full Scale Error (LSb) Zero Scale Error (LSb) 2.0 1.5 1.0 0.5 -22.0 -24.0 -26.0 -28.0 2.7V 5.0V 5.5V -30.0 0.0 -32.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 Temperature (°C) FIGURE 2-31: Zero-Scale Error (ZSE) vs. Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = VDD. 80 100 120 -4.0 2.7V 5.0V 5.5V 0.4 0.3 0.2 -5.0 -6.0 -7.0 0.1 2.7V 5.0V 5.5V 0.0 -8.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 Temperature (°C) 0.20 40 60 80 100 120 Temperature (°C) FIGURE 2-32: Zero-Scale Error (ZSE) vs. Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = VDD. FIGURE 2-35: Full-Scale Error (FSE) vs. Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = 10, G = 0, VREF = VDD. 0.0 2.7V 5.0V 5.5V Full Scale Error (LSb) Zero Scale Error (LSb) 60 FIGURE 2-34: Full-Scale Error (FSE) vs. Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = 10, G = 0, VREF = VDD. Full Scale Error (LSb) Zero Scale Error (LSb) 0.5 40 Temperature (°C) 0.15 0.10 0.05 -0.5 -1.0 -1.5 2.7V 5.0V 5.5V 0.00 -2.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-33: Zero-Scale Error (ZSE) vs. Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = VDD. DS22272C-page 20 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-36: Full-Scale Error (FSE) vs. Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = 10, G = 0, VREF = VDD. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. 12 12 -40C +25C +85C +125C 8 4 INL Error (LSb) INL Error (LSb) 8 -40C +25C +85C +125C 0 -4 -8 4 0 -4 -8 -12 -12 0 1024 2048 3072 4096 0 1024 Volatile DAC Register Code FIGURE 2-37: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = VDD. 4096 3 -40C +25C +85C +125C 2 -40C +25C +85C +125C 2 1 INL Error (LSb) INL Error (LSb) 3072 FIGURE 2-40: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = 11, G = 0, VREF = VDD. 3 0 -1 -2 1 0 -1 -2 -3 -3 0 128 256 384 512 640 768 896 1024 0 128 Volatile DAC Register Code 256 384 512 640 768 896 1024 Volatile DAC Register Code FIGURE 2-38: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = VDD. FIGURE 2-41: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = 11, G = 0, VREF = VDD. 1.0 1.0 -40C +25C +85C +125C -40C +25C +85C +125C 0.5 INL Error (LSb) 0.5 INL Error (LSb) 2048 Volatile DAC Register Code 0.0 -0.5 0.0 -0.5 -1.0 -1.0 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-39: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = VDD. © 2011-2012 Microchip Technology Inc. 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-42: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = 11, G = 0, VREF = VDD. DS22272C-page 21 MCP4706/4716/4726 0.4 0.4 0.3 0.3 0.2 0.2 DNL Error (LSb) DNL Error (LSb) Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. 0.1 0.0 -0.1 -0.2 0.1 0.0 -0.1 -0.2 -40C +25C +85C +125C -0.3 -40C +25C +85C +125C -0.3 -0.4 -0.4 0 1024 2048 3072 4096 0 1024 Volatile DAC Register Code 0.3 0.3 0.2 0.2 0.1 0.1 0.0 -0.1 -40C +25C +85C +125C 4096 0.0 -0.1 -40C +25C +85C +125C -0.2 -0.3 -0.3 0 128 256 384 512 640 768 896 0 1024 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-44: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = VDD. FIGURE 2-47: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = 11, G = 0, VREF = VDD. 0.20 0.20 0.15 0.15 0.10 0.10 DNL Error (LSb) DNL Error (LSb) 3072 FIGURE 2-46: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = 11, G = 0, VREF = VDD. DNL Error (LSb) DNL Error (LSb) FIGURE 2-43: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = VDD. -0.2 2048 Volatile DAC Register Code 0.05 0.00 -0.05 -0.10 0.05 0.00 -0.05 -0.10 -40C +25C +85C +125C -0.15 -40C +25C +85C +125C -0.15 -0.20 -0.20 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-45: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = VDD. DS22272C-page 22 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-48: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = 11, G = 0, VREF = VDD. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. -18.0 2.7V 5.0V 5.5V -20.0 Full Scale Error (LSb) Zero Scale Error (LSb) 2.0 1.5 1.0 0.5 -22.0 -24.0 -26.0 -28.0 2.7V 5.0V 5.5V -30.0 0.0 -32.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 Temperature (°C) FIGURE 2-49: Zero-Scale Error (ZSE) vs. Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = VDD. 80 100 120 -4.0 2.7V 5.0V 5.5V 0.4 0.3 0.2 -5.0 -6.0 -7.0 0.1 2.7V 5.0V 5.5V 0.0 -8.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 Temperature (°C) 0.20 40 60 80 100 120 Temperature (°C) FIGURE 2-50: Zero-Scale Error (ZSE) vs. Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = VDD. FIGURE 2-53: Full-Scale Error (FSE) vs. Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = 11, G = 0, VREF = VDD. 0.0 2.7V 5.0V 5.5V Full Scale Error (LSb) Zero Scale Error (LSb) 60 FIGURE 2-52: Full-Scale Error (FSE) vs. Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = 11, G = 0, VREF = VDD. Full Scale Error (LSb) Zero Scale Error (LSb) 0.5 40 Temperature (°C) 0.15 0.10 0.05 -0.5 -1.0 -1.5 2.7V 5.0V 5.5V 0.00 -2.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-51: Zero-Scale Error (ZSE) vs. Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = VDD. © 2011-2012 Microchip Technology Inc. -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-54: Full-Scale Error (FSE) vs. Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = 11, G = 0, VREF = VDD. DS22272C-page 23 MCP4706/4716/4726 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. 16 0.5 2.7V 5.0V 5.5V 0.4 0.3 0.2 8 DNL Error (LSb) INL Error (LSb) 12 4 0 0.1 0.0 -0.1 -0.2 -0.3 -4 2.7V 5.0V 5.5V -0.4 -8 -0.5 0 1024 2048 3072 0 4096 1024 Volatile DAC Register Code FIGURE 2-55: INL vs. Code (code = 100 to 4000) and VDD (2.7V, 5V, 5.5V) (MCP4726). VREF1:VREF0 = 10, G = 1, VREF = VDD/2, Temp = +25°C. 3 2048 3072 4096 Volatile DAC Register Code FIGURE 2-58: DNL vs. Code (code = 100 to 4000) and VDD (2.7V, 5V, 5.5V) (MCP4726). VREF1:VREF0 = 10, G = 1, VREF = VDD/2, Temp = +25°C. 0.4 2.7V 5.0V 5.5V 0.3 2 DNL Error (LSb) INL Error (LSb) 0.2 1 0 -1 -2 0.1 0.0 -0.1 2.7V 5.0V 5.5V -0.2 -3 -0.3 0 128 256 384 512 640 768 896 1024 0 128 Volatile DAC Register Code 384 512 640 768 896 1024 Volatile DAC Register Code FIGURE 2-56: INL vs. Code (code = 25 to 1000) and VDD (2.7V, 5V, 5.5V) (MCP4716). VREF1:VREF0 = 10, G = 1, VREF = VDD/2, Temp = +25°C. 1.0 256 FIGURE 2-59: DNL vs. Code (code = 25 to 1000) and VDD (2.7V, 5V, 5.5V) (MCP4716). VREF1:VREF0 = 10, G = 1, VREF = VDD/2, Temp = +25°C. 0.30 2.7V 5.0V 5.5V 0.25 0.20 0.15 DNL Error (LSb) INL Error (LSb) 0.5 0.0 0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.5 -0.20 2.7V 5.0V 5.5V -0.25 -1.0 -0.30 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-57: INL vs. Code (code = 6 to 250) and VDD (2.7V, 5V, 5.5V) (MCP4706). VREF1:VREF0 = 10, G = 1, VREF = VDD/2, Temp = +25°C. DS22272C-page 24 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-60: DNL vs. Code (code = 6 to 250) and VDD (2.7V, 5V, 5.5V) (MCP4706). VREF1:VREF0 = 10, G = 1, VREF = VDD/2, Temp = +25°C. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. 16 0.5 2.7V 5.0V 5.5V 0.4 0.3 0.2 8 DNL Error (LSb) INL Error (LSb) 12 4 0 0.1 0.0 -0.1 -0.2 -0.3 -4 2.7V 5.0V 5.5V -0.4 -8 -0.5 0 1024 2048 3072 0 4096 1024 Volatile DAC Register Code FIGURE 2-61: INL vs. Code (code = 100 to 4000) and VDD (2.7V, 5V, 5.5V) (MCP4726). VREF1:VREF0 = 11, G = 1, VREF = VDD/2, Temp = +25°C. 3 2048 3072 4096 Volatile DAC Register Code FIGURE 2-64: DNL vs. Code (code = 100 to 4000) and VDD (2.7V, 5V, 5.5V) (MCP4726). VREF1:VREF0 = 11, G = 1, VREF = VDD/2, Temp = +25°C. 0.4 2.7V 5.0V 5.5V 0.3 2 DNL Error (LSb) INL Error (LSb) 0.2 1 0 -1 -2 0.1 0.0 -0.1 2.7V 5.0V 5.5V -0.2 -3 -0.3 0 128 256 384 512 640 768 896 1024 0 128 256 Volatile DAC Register Code 384 512 640 768 896 1024 Volatile DAC Register Code FIGURE 2-62: INL vs. Code (code = 25 to 1000) and VDD (2.7V, 5V, 5.5V) (MCP4716). VREF1:VREF0 = 11, G = 1, VREF = VDD/2, Temp = +25°C. FIGURE 2-65: DNL vs. Code (code = 25 to 1000) and VDD (2.7V, 5V, 5.5V) (MCP4716). VREF1:VREF0 = 11, G = 1, VREF = VDD/2, Temp = +25°C. 0.30 1.0 2.7V 5.0V 5.5V 0.25 0.20 0.15 DNL Error (LSb) INL Error (LSb) 0.5 0.0 -0.5 0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 2.7V 5.0V 5.5V -0.25 -1.0 -0.30 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-63: INL vs. Code (code = 6 to 250) and VDD (2.7V, 5V, 5.5V) (MCP4706). VREF1:VREF0 = 11, G = 1, VREF = VDD/2, Temp = +25°C. © 2011-2012 Microchip Technology Inc. 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-66: DNL vs. Code (code = 6 to 250) and VDD (2.7V, 5V, 5.5V) (MCP4706). VREF1:VREF0 = 11, G = 1, VREF = VDD/2, Temp = +25°C. DS22272C-page 25 MCP4706/4716/4726 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. 1.0 16 1V 2V 3V 4V 5V 2V 5V 3V 0.5 8 DNL Error (LSb) INL Error (LSb) 12 1V 4V 4 0 0.0 -0.5 -4 -8 -1.0 0 1024 2048 3072 0 4096 1024 Volatile DAC Register Code FIGURE 2-67: INL vs. Code (code = 100 to 4000) and VREF (MCP4726). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. 0.5 1V 2V 3V 4V 5V 1V 4V 0.4 4096 2V 5V 3V 0.3 0.2 2 DNL Error (LSb) INL Error (LSb) 3072 FIGURE 2-70: DNL vs. Code (code = 100 to 4000) and VREF (MCP4726). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. 4 3 2048 Volatile DAC Register Code 1 0 0.1 0.0 -0.1 -0.2 -0.3 -1 -0.4 -0.5 -2 0 128 256 384 512 640 768 896 0 1024 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-68: INL vs. Code (code = 25 to 1000) and VREF (MCP4716). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. FIGURE 2-71: DNL vs. Code (code = 25 to 1000) and VREF (MCP4716). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. 1.0 0.5 1V 4V 0.4 2V 5V 3V 0.3 0.5 DNL Error (LSb) INL Error (LSb) 0.2 0.0 -0.5 1V 2V 3V 4V 5V 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -1.0 0 0.1 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-69: INL vs. Code (code = 6 to 250) and VREF (MCP4706). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. DS22272C-page 26 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-72: DNL vs. Code (code = 6 to 250) and VREF (MCP4706). VDD = 5V, VREF1:VREF0 = 10, G = 0, VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. 1.0 16 1V 2V 3V 4V 5V 2V 5V 3V 0.5 8 DNL Error (LSb) INL Error (LSb) 12 1V 4V 4 0 0.0 -0.5 -4 -8 -1.0 0 1024 2048 3072 0 4096 1024 Volatile DAC Register Code FIGURE 2-73: INL vs. Code (code = 100 to 4000) and VREF (MCP4726). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. 0.5 1V 2V 3V 4V 5V 1V 4V 0.4 4096 2V 5V 3V 0.3 0.2 2 DNL Error (LSb) INL Error (LSb) 3072 FIGURE 2-76: DNL vs. Code (code = 100 to 4000) and VREF (MCP4726). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. 4 3 2048 Volatile DAC Register Code 1 0 0.1 0.0 -0.1 -0.2 -0.3 -1 -0.4 -0.5 -2 0 128 256 384 512 640 768 896 0 1024 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-74: INL vs. Code (code = 25 to 1000) and VREF (MCP4716). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. FIGURE 2-77: DNL vs. Code (code = 25 to 1000) and VREF (MCP4716). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. 1.0 0.5 1V 4V 0.4 2V 5V 3V 0.3 0.5 DNL Error (LSb) INL Error (LSb) 0.2 0.0 -0.5 1V 2V 3V 4V 5V 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -1.0 0 0.1 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-75: INL vs. Code (code = 6 to 250) and VREF (MCP4706). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. © 2011-2012 Microchip Technology Inc. 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code FIGURE 2-78: DNL vs. Code (code = 6 to 250) and VREF (MCP4706). VDD = 5V, VREF1:VREF0 = 11, G = 0, VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. DS22272C-page 27 MCP4706/4716/4726 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. -20.0 2.7V 5.0V 5.5V -22.0 Output Error (LSb) -22.0 Output Error (LSb) -20.0 2.7V 5.0V 5.5V -24.0 -26.0 -28.0 -30.0 -24.0 -26.0 -28.0 -30.0 -32.0 -32.0 -34.0 -34.0 -36.0 -36.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 FIGURE 2-79: Output Error vs. Temperature (MCP4726). VDD = 2.7V and 5V, VREF1:VREF0 = 00, Code = 4000. Output Error (LSb) Output Error (LSb) 80 100 120 2.7V 5.0V 5.5V 2.7V 5.0V 5.5V -5.0 -6.0 -5.0 -6.0 -7.0 -7.0 -8.0 -8.0 -40 -20 0 20 40 60 80 100 -40 120 -20 0 20 FIGURE 2-80: Output Error vs. Temperature (MCP4716). VDD = 2.7V and 5V, VREF1:VREF0 = 00, Code = 1000. 60 80 100 120 FIGURE 2-83: Output Error vs. Temperature (MCP4716). VDD = 2.7V and 5V, VREF1:VREF0 = 10, G = 0, VREF = VDD, Code = 1000. -0.4 -0.4 40 Temperature (°C) Temperature (°C) 2.7V 5.0V 5.5V 2.7V 5.0V 5.5V -0.6 Output Error (LSb) Output Error (LSb) 60 FIGURE 2-82: Output Error vs. Temperature (MCP4726). VDD = 2.7V and 5V, VREF1:VREF0 = 10, G = 0, VREF = VDD, Code = 4000. -4.0 -4.0 40 Temperature (°C) Temperature (°C) -0.8 -1.0 -0.6 -0.8 -1.0 -1.2 -1.2 -1.4 -1.4 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-81: Output Error vs. Temperature (MCP4706). VDD = 2.7V and 5V, VREF1:VREF0 = 00, Code = 250. DS22272C-page 28 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-84: Output Error vs. Temperature (MCP4706). VDD = 2.7V and 5V, VREF1:VREF0 = 10, G = 0, VREF = VDD, Code = 250. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. -20.0 2.7V 5.0V 5.5V Output Error (LSb) -22.0 -24.0 -26.0 -28.0 -30.0 -32.0 -34.0 -36.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-85: Output Error vs. Temperature (MCP4726). VDD = 2.7V and 5V, VREF1:VREF0 = 11, G = 0, VREF = VDD, Code = 4000. Output Error (LSb) -4.0 2.7V 5.0V 5.5V -5.0 -6.0 -7.0 -8.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-86: Output Error vs. Temperature (MCP4716). VDD = 2.7V and 5V, VREF1:VREF0 = 11, G = 0, VREF = VDD, Code = 1000. -0.4 2.7V 5.0V 5.5V Output Error (LSb) -0.6 -0.8 -1.0 -1.2 -1.4 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-87: Output Error vs. Temperature (MCP4706). VDD = 2.7V and 5V, VREF1:VREF0 = 11, G = 0, VREF = VDD, Code = 250. © 2011-2012 Microchip Technology Inc. DS22272C-page 29 MCP4706/4716/4726 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. 250 500 2.7V 3.3V 4.5V 5.0V 5.5V 225 2.7V 3.3V 4.5V 5.0V 5.5V 400 IPowerDown (nA) IDD (uA) 200 175 150 300 200 100 125 100 0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-88: IDD vs. Temperature. VDD = 2.7V and 5V, VREF1:VREF0 = 00. FIGURE 2-91: Power-down Current vs. Temperature. VDD = 2.7V, 3.3V, 4.5V, 5.0V and 5.5V, PD1:PD0 = 11. 250 2.7V 3.3V 4.5V 5.0V 5.5V 225 IDD (uA) 200 175 150 125 100 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-89: IDD vs. Temperature. VDD = 2.7V and 5V, VREF1:VREF0 = 10, G = 0, VREF = VDD. 250 2.7V 3.3V 4.5V 5.0V 5.5V 225 IDD (uA) 200 175 150 125 100 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-90: IDD vs. Temperature. VDD = 2.7V and 5V, VREF1:VREF0 = 11, G = 0, VREF = VDD. DS22272C-page 30 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. 70 6 Code = FFFh 2.7V 5.0V 5.5V 5 VOUT (V) VIH (% VDD) 65 60 4 3 2 55 1 0 50 -40 -20 0 20 40 60 80 100 0 120 Temperature (°C) FIGURE 2-92: VIH Threshold of SDA/SCL Inputs vs. Temperature and VDD. 1000 2000 3000 4000 Load Resistance (RL) (:) FIGURE 2-94: VDD = 5.0V. 50 5000 VOUT vs. Resistive Load. 6 Code = FFFh 2.7V 5.0V 5.5V Code = 000h 5 45 VOUT (V) VIL (% VDD) 4 40 3 2 35 1 0 30 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-93: VIL Threshold of SDA/SCL Inputs vs. Temperature and VDD. © 2011-2012 Microchip Technology Inc. 0 3 6 9 ISOURCE/SINK (mA) 12 15 FIGURE 2-95: VOUT vs. Source/Sink Current. VDD = 5.0V. DS22272C-page 31 MCP4706/4716/4726 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF. FIGURE 2-96: Full-Scale Settling Time (000h to FFFh) (MCP4726). FIGURE 2-98: Half-Scale Settling Time (400h to C00h) (MCP4726). FIGURE 2-97: Full-Scale Settling Time (FFFh to 000h) (MCP4726). FIGURE 2-99: Half-Scale Settling Time (C00h to 400h) (MCP4726). FIGURE 2-100: Exiting Power-Down Mode (MCP4726, Volatile DAC Register = FFFh). DS22272C-page 32 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 3.0 PIN DESCRIPTIONS An overview of the pin functions are described in Section 3.1 “Analog Output Voltage Pin (VOUT)” through Section 3.7 “Exposed Pad (EP)”. The descriptions of the pins are listed in Table 3-1. TABLE 3-1: SOT-23 MCP47X6 PINOUT DESCRIPTION DFN Symbol I/O Buffer Type Standard Function 6L 6L 1 6 VOUT A Analog 2 5 VSS — P Ground reference pin for all circuitries on the device Supply Voltage Pin Buffered analog voltage output pin 3 4 VDD — P 4 3 SDA I/O ST I2C™ Serial Data Pin 5 2 SCL I ST I2C Serial Clock Pin 6 1 VREF A Analog — 7 EP — — Legend: Note 1: A = Analog pins O = Digital output P = Power Voltage Reference Input Pin Exposed Pad (Note 1) I = Digital input (high Z) I/O = Input / Output The DFN package has a contact on the bottom of the package. This contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device’s VSS pin. © 2011-2012 Microchip Technology Inc. DS22272C-page 33 MCP4706/4716/4726 3.1 Analog Output Voltage Pin (VOUT) 3.5 Serial Clock Pin (SCL) In Normal mode, the DC impedance of the output pin is about 1Ω. In Power-Down mode, the output pin is internally connected to a known pull-down resistor of 1 kΩ, 125 kΩ, or 640 kΩ. The power-down selection bits settings are shown in Table 4-2. SCL is the serial clock pin of the I2C interface. The MCP47X6 devices act only as a slave and the SCL pin accepts only external serial clocks. The input data from the master device is shifted into the SDA pin on the rising edges of the SCL clock and output from the device occurs at the falling edges of the SCL clock. The SCL pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SCL pin. Refer to Section 5.0 “I2C Serial Interface” for more details about I2C serial interface communication. 3.2 3.6 VOUT is the DAC analog output pin. The DAC output has an output amplifier. VOUT can swing from approximately 0V to approximately VDD. The full-scale range of the DAC output is from VSS to G * VRL, where G is the gain selection option (1x or 2x). Positive Power Supply Input (VDD) VDD is the positive supply voltage input pin. The input supply voltage is relative to VSS. Voltage Reference Pin (VREF) This pin is used for the external voltage reference input. The user can select VDD voltage or the VREF pin voltage as the reference resistor ladder’s voltage reference. The power supply at the VDD pin should be as clean as possible for a good DAC performance. It is recommended to use an appropriate bypass capacitor of about 0.1 µF (ceramic) to ground. An additional 10 µF capacitor (tantalum) in parallel is also recommended to further attenuate high-frequency noise present in application boards. When the VREF pin signal is selected, there is an option for this voltage to be buffered or unbuffered. This is offered in cases where the reference voltage does not have the current capability not to drop its voltage when connected to the internal resistor ladder circuit. 3.3 When the VDD is selected as reference voltage, this pin is disconnected from the internal circuit. Ground (VSS) The VSS pin is the device ground reference. The user must connect the VSS pin to a ground plane through a low-impedance connection. If an analog ground path is available in the application Printed Circuit Board (PCB), it is highly recommended that the VSS pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. 3.4 Serial Data Pin (SDA) SDA is the serial data pin of the I2C interface. The SDA pin is used to write or read the DAC registers and Configuration bits. The SDA pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SDA pin. Except for Start and Stop conditions, the data on the SDA pin must be stable during the high period of the clock. The high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. Refer to Section 5.0 “I2C Serial Interface” for more details of I2C serial interface communication. DS22272C-page 34 See Section 4.2 “DAC’s (Resistor Ladder) Reference Voltage” and Table 4-4 for more details on the Configuration bits. 3.7 Exposed Pad (EP) This pad is conductively connected to the device's substrate. This pad should be tied to the same potential as the VSS pin (or left unconnected). This pad could be used to assist as a heat sink for the device when connected to a PCB heat sink. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 4.0 GENERAL DESCRIPTION 4.1 The MCP4706, MCP4716, and MCP4726 devices are single channel voltage output 8-bit, 10-bit, and 12-bit DAC devices with nonvolatile memory (EEPROM) and an I2C serial interface. This family will be referred to as MCP47X6. The devices use a resistor ladder architecture. The resistor ladder DAC is driven from a software selectable voltage reference source. The source can be either the device’s internal VDD or the external VREF pin voltage. The DAC output is buffered with a low power and precision output amplifier (op amp). This output amplifier provides a rail-to-rail output with low offset voltage and low noise. The gain of the output buffer is software configurable. This device also has user programmable nonvolatile memory (EEPROM), which allows the user to save the desired POR/BOR value of the DAC register and device Configuration bits. The devices use a two-wire I2C serial communication interface and operate with a single supply voltage from 2.7V to 5.5V. Power-On Reset/Brown-Out Reset (POR/BOR) The internal Power-on Reset (POR)/Brown-out Reset (BOR) circuit monitors the power supply voltage (VDD) during operation. This circuit ensures correct device start-up at system power-up and power-down events. VRAM is the RAM retention voltage and is always lower than the POR trip point voltage. POR occurs as the voltage is rising (typically from 0V), while BOR occurs as the voltage is falling (typically from VDD(MIN) or higher). When the rising VDD voltage crosses the VPOR trip point, the following occurs: • Nonvolatile DAC register value latched into volatile DAC register • Nonvolatile Configuration bit values latched into volatile Configuration bits • POR Status bit is set (“1”) • The Reset delay timer starts; when timer times out (tPORD), the I2C interface is operational. The analog output (VOUT) state will be determined by the state of the volatile Configuration bits and the DAC register. This is called a POR Reset (event). When the falling VDD voltage crosses the VPOR trip point, the following occurs: • Device is forced into a power-down state (PD1:PD0 = 11). Analog circuitry is turned off. • Volatile DAC register is forced to 000h • Volatile Configuration bits VREF1, VREF0 and G are forced to ‘0’ Figure 4-1 illustrates the conditions for power-up and power-down events under typical conditions. Volatile memory POR starts Reset Delay Timer. retains data value When timer times out, I2C™ interface can operate (if VDD >= VDD(MIN)) Volatile memory becomes corrupted VDD(MIN) VPOR VBOR TPORD (60 µs max.) VRAM Normal Operation Device in unknown state Device in POR state EEPROM data latched into volatile Configuration bits and DAC register. POR Reset forced active POR Status bit is set (“1”) FIGURE 4-1: Below minimum operating voltage Device Device in in power unknown down state state BOR Reset, volatile DAC Register = 000h volatile VREF1:VREF0 = 00 volatile G = 0 volatile PD1:PD0 = 11 Power-on Reset Operation. © 2011-2012 Microchip Technology Inc. DS22272C-page 35 MCP4706/4716/4726 4.2 DAC’s (Resistor Ladder) Reference Voltage The device can be configured to use one of three voltage sources for the resistor ladder’s reference voltage (VRL) (see Figure 4-2). These are: 1. 2. 3. VDD pin voltage VREF pin voltage internally buffered VREF pin voltage unbuffered The selection of the voltage is specified with the volatile VREF1:VREF0 Configuration bits (see Table 4-4). There are nonvolatile and volatile VREF1:VREF0 Configuration bits. On a POR/BOR event, the state of the nonvolatile VREF1:VREF0 Configuration bits are latched into the volatile VREF1:VREF0 Configuration bits. When the user selects the VDD as reference, the VREF pin voltage is not connected to the resistor ladder. If the VREF pin is selected, then select between the Buffered or Unbuffered mode. In Unbuffered mode, the VREF pin voltage may be from VSS to VDD. Note: In Unbuffered mode, the voltage source should have a low output impedance. If the voltage source has a high output impedance, then the voltage on the VREF’s pin would be lower than expected. The resistor ladder has a typical impedance of 210 kΩ and a typical capacitance of 29 pF. 4.3 The resistor ladder is a digital potentiometer with the B Terminal internally grounded and the A terminal connected to the selected reference voltage (see Figure 4-3). The volatile DAC register controls the wiper position. The wiper voltage (VW) is proportional to the DAC register value divided by the number of resistor elements (RS) in the ladder (256, 1024, or 4096) related to the VRL voltage. Note: Any variation or noises on the reference source can directly affect the DAC output. The reference voltage needs to be as clean as possible for accurate DAC performance. The maximum wiper position is 2n - 1, while the number of resistors in the resistor ladder is 2n. This means that when the DAC register is at full scale, there is one resistor element (RS) between the wiper and the VRL voltage. The resistor ladder (RRL) has a typical impedance of approximately 210 kΩ. This resistor ladder resistance (RRL) may vary from device to device up to ±20%. Since this is a voltage divider configuration, the actual RRL resistance does not effect the output given a fixed voltage at VRL. If the unbuffered VREF pin is used as the VRL voltage source, this voltage source should have a low output impedance. When the DAC is powered down, the resistor ladder is disconnected from the selected reference voltage. PD1:PD0 In Buffered mode, the VREF pin voltage may be from 0.01V to VDD-0.04V. The input buffer (amplifier) provides low offset voltage, low noise, and a very high input impedance, with only minor limitations on the input range and frequency response. DAC Register 2n - 1 RS(2n - 1) RRL 2n - 2 RS(2n - 2) VW 1 RS(1) VDD 0 VRL Buffer FIGURE 4-2: Resistor Ladder Reference Voltage Selection Block Diagram. VW = DAC Register Value * VRL # Resistors in Resistor Ladder Where: # Resistors in Resistor Ladder = 256 (MCP4706) 1024 (MCP4716) 4096 (MCP4726) FIGURE 4-3: DS22272C-page 36 VRL RS(2n) VREF1:VREF0 VREF Reference Selection Note: Resistor Ladder Resistor Ladder. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 4.4 Output Buffer/VOUT Operation The DAC output is buffered with a low power and precision output amplifier (op amp). Figure 4-4 shows a block diagram. This amplifier provides a rail-to-rail output with low offset voltage and low noise. The user can select the output gain of the output amplifier. Gain options are: a) b) Gain of 1, with either VDD or VREF pin used as reference voltage Gain of 2, only when VREF pin is used as reference voltage. The VREF pin voltage should be limited to VDD/2. The amplifier’s output can drive the resistive and high capacitive loads without oscillation. The amplifier provides a maximum load current which is enough for most programmable voltage reference applications. Refer to Section 1.0 “Electrical Characteristics” for the specifications of the output amplifier. Note: The load resistance must stay higher than 5 kΩ for the stable and expected analog output to meet electrical specifications. In any of the three Power-Down modes, the op amp is powered down and its output becomes a highimpedance to the VOUT pin. VW FIGURE 4-4: Diagram. 4.4.1 VOUT Output Buffer Block PROGRAMMABLE GAIN The amplifier’s gain is controlled by the Gain (G) Configuration bit (See Table 4-4) and the VRL reference selection. When the VRL reference selection is the device’s VDD voltage, the G bit is ignored and a gain of 1 is used. The volatile G bit value can be modified by: • • • • OUTPUT VOLTAGE The volatile DAC register’s value controls the analog VOUT voltage, along with the device’s five Configuration bits. The volatile DAC register’s value is unsigned binary. The formula for the output voltage is given in Equation 4-1. Table 4-1 shows examples of volatile DAC register values and the corresponding theoretical VOUT voltage for the MCP47X6 devices. Note: When Gain = 2 (VRL = VREF), if VREF > VDD/2, the VOUT voltage will be limited to VDD. So if VREF = VDD, then the VOUT voltage will not change for volatile DAC register values mid-scale and greater, since the op amp is at its full scale output. EQUATION 4-1: VOUT = CALCULATING OUTPUT VOLTAGE (VOUT) VRL * DAC Register Value * Gain # Resistors in Resistor Ladder # Resistors in Resistor Ladder = 4096 (MCP4726) 1024 (MCP4716) 256 (MCP4706) The DAC register value will be latched on the falling edge of the Acknowledge pulse of the Write command’s last byte. Then the VOUT voltage will start driving to the new value. Gain (1x or 2x) (G = 0 or 1) Op Amp 4.4.2 The following events update the analog voltage output (VOUT): • Power-on Reset or General Call Reset command: Output is updated with EEPROM data. • Falling edge of the Acknowledge pulse of the last Write command byte. 4.4.2.1 Resolution/Step Voltage The Step voltage is dependent on the device resolution and the output voltage range. One LSb is defined as the ideal voltage difference between two successive codes. The step voltage can easily be calculated by using Equation 4-1 where the DAC register value is equal to 1. POR event BOR event I2C Write commands I2C General Call Reset command © 2011-2012 Microchip Technology Inc. DS22272C-page 37 MCP4706/4716/4726 4.4.3 OUTPUT SLEW RATE Figure 4-5 shows an example of the slew rate of the VOUT pin. The slew rate can be affected by the characteristics of the circuit connected to the VOUT pin. VOUT(B) Wiper = A Wiper = B Time Slew Rate = FIGURE 4-5: 4.4.4 | VOUT(B) - VOUT(A) | ΔT VOUT pin Slew Rate. SMALL CAPACITIVE LOAD With a small capacitive load, the output buffer’s current is not affected by the capacitive load (CL). However, the VOUT pin’s voltage is not a step transition from one output value (wiper code value) to the next output value. The change of the VOUT voltage is limited by the output buffer’s characteristics, so the VOUT pin voltage will have a slope from the old voltage to the new voltage. This slope is fixed for the output buffer, and is referred to as the buffer slew rate (SRBUF). 4.4.5 DRIVING RESISTIVE AND CAPACITIVE LOADS The VOUT pin can drive up to 100 pF of capacitive load in parallel with a 5 kΩ resistive load (to meet electrical specifications). Figure 2-94 shows the VOUT vs. Resistive Load. VOUT drops slowly as the load resistance decreases after about 3.5 kΩ. It is recommended to use a load with RL greater than 5 kΩ. VOUT VOUT(A) 4.4.6 Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response with overshoot and ringing in the step response. That is, since the VOUT pin’s voltage does not quickly follow the buffer’s input voltage (due to the large capacitive load), the output buffer will overshoot the desired target voltage. Once the driver detects this overshoot, it compensates by forcing it to a voltage below the target. This causes voltage ringing on the VOUT pin. So, when driving large capacitive loads with the output buffer, a small series resistor (RISO) at the output (see Figure 4-6) improves the output buffer’s stability (feedback loop’s phase margin) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. LARGE CAPACITIVE LOAD With a larger capacitive load, the slew rate is determined by two factors: VW • The output buffer’s short circuit current (ISC) • The VOUT pin’s external load IOUT cannot exceed the output buffer’s short circuit current (ISC) which fixes the output buffer slew rate (SRBUF). The voltage on the capacitive load (CL), VCL, changes at a rate proportional to IOUT, which fixes a capacitive load slew rate (SRCL). So the VCL voltage slew rate is limited to the slower of the output buffer’s internally set slew rate (SRBUF) and the capacitive load slew rate (SRCL). Op Amp VCL VOUT RISO RL CL FIGURE 4-6: Circuit to Stabilize Output Buffer for Large Capacitive Loads (CL). The RISO resistor value for your circuit needs to be selected. The resulting frequency response peaking and step response overshoot for this RISO resistor value should be verified on the bench. Modify the RISO’s resistance value until the output characteristics meet your requirements. A method to evaluate the system’s performance is to inject a step voltage on the VREF pin and observe the VOUT pin’s characteristics. Note: DS22272C-page 38 Additional insight into circuit design for driving capacitive loads can be found in AN884 “Driving Capacitive Loads With Op Amps” (DS00884). © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 TABLE 4-1: Device DAC INPUT CODE VS. ANALOG OUTPUT (VOUT) (VDD = 5.0V) Volatile DAC Register Value LSb VRL 5.0V 1111 1111 1111 0111 1111 1111 MCP4726 (12-bit) 0011 1111 1111 0000 0000 0000 11 1111 1111 01 1111 1111 MCP4716 (10-bit) 00 1111 1111 00 0000 0000 1111 1111 0111 1111 MCP4706 (8-bit) 0011 1111 0000 0000 Note 1: 2: 3: 4: Gain Selection (1) VOUT (4) Equation uV (2) 5.0V/4096 1,220.7 1x VRL * (4095/4096) * 1 4.998779 1x VRL * (4095/4096) * 1 2.499390 2x(3) VRL * (4095/4096) * 2) 4.998779 1x VRL * (2047/4096) * 1) 2.498779 2.5V 2.5V/4096 610.4 5.0V 5.0V/4096 1,220.7 2.5V 2.5V/4096 610.4 5.0V 5.0V/4096 1,220.7 2.5V 2.5V/4096 610.4 5.0V 5.0V/4096 1,220.7 2.5V 2.5V/4096 610.4 5.0V 5.0V/1024 4,882.8 2.5V 2.5V/1024 2,441.4 5.0V 5.0V/1024 4,882.8 2.5V 2.5V/1024 2,441.4 5.0V 5.0V/1024 4,882.8 2.5V 2.5V/1024 2,441.4 5.0V 5.0V/1024 4,882.8 2.5V 2.5V/1024 2,441.4 5.0V 5.0V/256 19,531.3 2.5V 2.5V/256 9,765.6 5.0V 5.0V/256 19,531.3 2.5V 2.5V/256 9,765.6 5.0V 5.0V/256 19,531.3 2.5V 2.5V/256 9,765.6 5.0V 5.0V/256 19,531.3 2.5V 2.5V/256 9,765.6 Equation V 1x VRL * (2047/4096) * 1) 1.249390 2x(3) VRL * (2047/4096) * 2) 2.498779 1x VRL * (1023/4096) * 1) 1.248779 1x VRL * (1023/4096) * 1) 0.624390 2x(3) VRL * (1023/4096) * 2) 1.248779 1x VRL * (0/4096) * 1) 0 1x VRL * (0/4096) * 1) 0 2x(3) VRL * (0/4096) * 2) 0 1x VRL * (1023/1024) * 1 4.995117 1x VRL * (1023/1024) * 1 2.497559 2x(3) VRL * (1023/1024) * 2 4.995117 1x VRL * (511/1024) * 1 2.495117 1x VRL * (511/1024) * 1 1.247559 2x(3) VRL * (511/1024) * 2 2.495117 1x VRL * (255/1024) * 1 1.245117 1x VRL * (255/1024) * 1 0.622559 2x(3) VRL * (255/1024) * 2 1.245117 1x VRL * (0/1024) * 1 0 1x VRL * (0/1024) * 1 0 2x(3) VRL * (0/1024) * 1 0 1x VRL * (255/256) * 1 4.980469 1x VRL * (255/256) * 1 2.490234 2x(3) VRL * (255/256) * 2 4.980469 1x VRL * (127/256) * 1 2.480469 1x VRL * (127/256) * 1 1.240234 2x(3) VRL * (127/256) * 2 2.480469 1x VRL * (63/256) * 1 1.230469 1x VRL * (63/256) * 1 0.615234 2x(3) VRL * (63/256) * 2 1.230469 1x VRL * (0/256) * 1 0 1x VRL * (0/256) * 1 0 2x(3) VRL * (0/256) * 2 0 VRL is the resistor ladder’s reference voltage. It is independent of VREF1:VREF0 selection. Gain selection of 2x requires voltage reference source to come from VREF pin and requires VREF pin voltage ≤ VDD / 2. Requires G = 1, VREF1:VREF0 = 10 or ‘11’, and VRL ≤ VDD/2. These theoretical calculations do not take into account the Offset and Gain errors. © 2011-2012 Microchip Technology Inc. DS22272C-page 39 MCP4706/4716/4726 Power-Down Operation Gain (1x or 2x) (Gx = 0 or 1) To allow the application to conserve power when the DAC operation is not required, three Power-Down modes are available. The Power-Down Configuration bits (PD1:PD0) control the power-down operation (Figure 4-7). All Power-Down modes do the following: VW Depending on the selected Power-Down mode, the following will occur: FIGURE 4-7: Diagram. • VOUT pin is switched to one of three resistive pulldowns (See Table 4-2) - 640kΩ (typical) - 125kΩ (typical) - 1kΩ (typical) 4.5.1 There is a delay (TPDE) between the PD1:PD0 bits changing from ‘00’ to either ‘01’, ‘10’, or ‘11’ and the op amp no longer driving the VOUT output and the pulldown resistors are sinking current. In any of the Power-Down modes, where the VOUT pin is not externally connected (sinking or sourcing current), the power-down current will typically be 60 nA (see Section 1.0 “Electrical Characteristics”). Section 6.0 “MCP47X6 I2C Commands” describes the I2C commands for writing the power-down bits. The commands that can update the volatile PD1:PD0 bits are: • • • • • • Write Volatile DAC Register Write Volatile Memory Write All Memory Write Volatile Configuration Bits General Call Reset General Call Wake-up Note: The I2C serial interface circuit is not affected by the Power-Down mode. This circuit remains active in order to receive any command that might come from the I2C master device. TABLE 4-2: POWER-DOWN BITS AND OUTPUT RESISTIVE LOAD PD1 PD0 Function 0 0 Normal operation 0 1 1 kΩ resistor to ground 1 0 125 kΩ resistor to ground 1 1 640 kΩ resistor to ground DS22272C-page 40 640 kΩ PD1:PD0 1 kΩ • Turn off most of its internal circuits (op amp, resistor ladder, ...) • Op amp output becomes high-impedance to the VOUT pin • Disconnects resistor ladder from reference voltage (VRL) • Retains the value of the volatile DAC register and Configuration bits, and the nonvolatile (EEPROM) DAC register and Configuration bits VOUT Op Amp 125 kΩ 4.5 Op Amp to VOUT Pin Block EXITING POWER-DOWN When the device exits the Power-Down mode, the following occurs: • Disabled circuits (op amp, resistor ladder, ...) are turned on • Resistor ladder is connected to selected reference voltage (VRL) • Selected pull-down resistor is disconnected • The VOUT output will be driven to the voltage represented by the volatile DAC register’s value and Configuration bits The VOUT output signal will require time as these circuits are powered up and the output voltage is driven to the specified value as determined by the volatile DAC register and Configuration bits. Note: Since the op amp and resistor ladder were powered off (0V), the op amp’s input voltage (VW) can be considered 0V. There is a delay (TPDD) between the PD1:PD0 bits updated to ‘00’ and the op amp driving the VOUT output. The op amp’s settling time (from 0V) needs to be taken into account to ensure the VOUT voltage reflects the selected value. The following events will change the PD1:PD0 bits to ‘00’ and therefore exit the Power-Down mode. These are: • Any I2C Write command for where the PD1:PD0 bits are ‘00’ • I2C General Call Wake-up Command • I2C General Call Reset Command (if nonvolatile PD1:PD0 bits are ‘00’) © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 4.6 Device Resets 4.7 Device Resets can be grouped into two types: Resets due to change in voltage (POR/BOR Reset), and Resets caused by the system master (such as a microcontroller). The MCP47X6 devices have both volatile and nonvolatile (EEPROM) memory. Figure 4-8 shows the volatile and nonvolatile memory and their interaction due to a POR event. After a device Reset, and when VDD ≥ VDD(MIN), the device memory may be written or read. 4.6.1 There are five Configuration bits in both the volatile and nonvolatile memory, the DAC registers in both the volatile and nonvolatile memory, and two volatile Status bits. The DAC registers (volatile and nonvolatile) will be either 12-bits (MCP4726), 10-bits (MCP4716), or 8-bits (MCP4706) wide. POR/BOR RESET OPERATION The POR and BOR trip points are at the same voltage, and are determined if the VDD voltage is rising or falling (see Figure 4-1). What occurs is different, depending if the Reset is a POR or BOR Reset. When the device is first powered up, it automatically uploads the EEPROM memory values to the volatile memory. The volatile memory determines the analog output (VOUT) pin voltage. After the device is powered up, the user can update the device memory. POR Reset (VDD Rising) On a POR Reset, the nonvolatile memory values (DAC register and Configuration bits) are latched into the volatile memory. This configures the analog output (VOUT) circuitry. A Reset delay timer also starts. During this delay time, the I2C interface will not accept commands. The I2C interface is how this memory is read and written. Refer to Section 5.0 “I2C Serial Interface” and Section 6.0 “MCP47X6 I2C Commands” for more details on the reading and writing the device’s memory. When the nonvolatile memory is written (using the I2C Write All Memory command), the volatile memory is written with the same values. The device starts writing the EEPROM cell at the Acknowledge pulse of the EEPROM Write command. BOR Reset (VDD Falling) On a BOR Reset, the device is forced into a powerdown state. The volatile PD1:PD0 bits are forced to ‘11’ and all other volatile memory forced to ‘0’. The I2C interface will not accept commands. 4.6.2 DAC Registers, Configuration Bits, and Status Bits Table 4-3 shows the operation of the device Status bits, Table 4-4 shows the operation of the device Configuration bits, and Table 4-5 shows the factory default value of a POR/BOR event for the device Configuration bits. RESET COMMANDS When the MCP47X6 is in the valid operating voltage, the I2C General Call Reset command will force a Reset event. This is similar to the POR Reset, except that the Reset delay timer is not started. There are two Status bits. These are only in volatile memory and give indication on the status of the device. The POR bit indicates if the device VDD is above or below the POR trip point. During normal operation, this bit should be ‘1’. The RDY/BSY bit indicates if an EEPROM write cycle is in progress. While the RDY/BSY bit is low (during the EEPROM writing), all commands are ignored, except for the Read command. In the case where the I2C interface bus does not seem to be responsive, the technique shown in Section 8.9 “Software I2C Interface Reset Sequence” can be used to force the I2C interface to be reset. DAC Register Value (1) Config Bits VREF1 VREF0 PD1 PD0 DMAX G D1 D0 POR Event Status Bits (2) VREF1 VREF0 PD1 PD0 G RDY/BSY POR N.V. Memory DMAX D1 D0 Vol. Memory Note 1: The DMAX value depends on the device. For the MCP4706: DMAX = D7, MCP4716: DMAX = D9, and the MCP4726: DMAX = D11. 2: Status bits are read-only. FIGURE 4-8: DAC Memory and POR Interaction. © 2011-2012 Microchip Technology Inc. DS22272C-page 41 MCP4706/4716/4726 TABLE 4-3: STATUS BITS OPERATION Name Function This bit indicates the state of the EEPROM program memory 1 = EEPROM is not in a programming cycle 0 = EEPROM is in a programming cycle RDY/BSY POR Power-on Reset Status Indicator (flag) 1 = Device is powered on with VDD > VPOR. Ensure that VDD is above VDD(MIN) to ensure proper operation. 0 = Device is in powered off state. If this value is read, VDD < VDD(MIN) < VPOR. Unreliable device operation should be expected. TABLE 4-4: CONFIGURATION BITS Name Function VREF1:VREF0 Resistor Ladder Voltage Reference (VRL) Selection bits 0x = VDD (Unbuffered) 10 = VREF pin (Unbuffered) 11 = VREF pin (Buffered) PD1:PD0 Power-Down Selection bits When the DAC is powered down, most of the internal circuits are powered off and the op amp is disconnected from the VOUT pin. 00 = Not Powered Down (Normal operation) 01 = Powered Down – VOUT is loaded with 1 kΩ resistor to ground. 10 = Powered Down – VOUT is loaded with 100 kΩ resistor to ground. 11 = Powered Down – VOUT is loaded with 500 kΩ resistor to ground. Note: G See Table 4-2 and Figure 4-7 for more details. Gain Selection bit 0 = 1x (gain of 1) 1 = 2x (gain of 2). Not applicable when VDD is used as VRL Note: TABLE 4-5: If VREF = VDD, the device uses a gain of 1 only, regardless of the gain selection bit (G) setting. CONFIGURATION BIT VALUES AFTER POR/BOR EVENT R/W R/W R/W R/W R/W Comment Bit Name VREF1 VREF0 PD1 PD0 G POR Event 0(1) 0(1) 0(1) 0(1) 0(1) When VDD transitions from VDD < VPOR to VDD > VPOR BOR Event 0 0 1 1 0 When VDD transitions from VDD > VBOR to VDD < VBOR Note 1: Default configuration when the device is shipped to customer. The POR/BOR value may be modified by writing the corresponding nonvolatile Configuration bit. REGISTER 4-1: Bit Name POR/BOR Event Note 1: 2: DAC REGISTER BITS R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W —(2) —(2) —(2) —(2) D7 D6 D5 D4 D3 D2 D1 —(2) —(2) D9 D8 D7 D6 D5 D4 D3 D2 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 (1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0 R/W Comment D0 MCP4706 D1 D0 MCP4716 D1 D0 MCP4726 Default configuration when the device is shipped to customer. The POR/BOR value may be modified by writing the corresponding nonvolatile Configuration bit. This device does not implement this bit, so there is no corresponding POR/BOR value. DS22272C-page 42 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 I2C SERIAL INTERFACE 5.0 The MCP47X6 devices support the I2C serial protocol. The MCP47X6 I2C’s module operates in Slave mode (does not generate the serial clock). 5.1 5.2 Signal Descriptions The I2C interface uses up to two pins (signals). These are: • SDA (Serial Data) • SCL (Serial Clock) Overview 2 This I C interface is a two-wire interface. Figure 5-1 shows a typical I2C interface connection. The I2C interface specifies different communication bit rates. These are referred to as Standard, Fast or HighSpeed modes. The MCP47X6 supports these three modes. The bit rates of these modes are: • Standard mode: bit rates up to 100 kbit/s • Fast mode: bit rates up to 400 kbit/s • High-Speed mode (HS mode): bit rates up to 3.4 Mbit/s A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access and generates the Start and Stop conditions. The MCP47X6 device works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. Communication is initiated by the master (microcontroller) which sends the Start bit, followed by the slave address byte. The first byte transmitted is always the slave address byte, which contains the device code, the address bits, and the R/W bit. 5.2.1 SERIAL DATA (SDA) The Serial Data (SDA) signal is the data signal of the device. The value on this pin is latched on the rising edge of the SCL signal when the signal is an input. With the exception of the Start and Stop conditions, the high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. During the high period of the clock, the SDA pin’s value (high or low) must be stable. Changes in the SDA pin’s value while the SCL pin is High will be interpreted as a Start or a Stop condition. 5.2.2 SERIAL CLOCK (SCL) The Serial Clock (SCL) signal is the clock signal of the device. The rising edge of the SCL signal latches the value on the SDA pin. The MCP47X6 will not stretch the clock signal (SCL) since memory read access occurs fast enough. Depending on the clock rate mode, the interface will display different characteristics. Typical I2C™ Interface Connections MCP4XXX Host Controller SCL SCL SDA SDA FIGURE 5-1: Typical I2C Interface. The I2C serial protocol only defines the field types, field lengths, timings, etc. of a frame. The frame content defines the behavior of the device. For details on the frame content (commands/data) refer to Section 6.0 “MCP47X6 I2C Commands”. Refer to the NXP I2C document for more details on the I2C specifications. © 2011-2012 Microchip Technology Inc. DS22272C-page 43 MCP4706/4716/4726 5.3 I2C Operation 5.3.1.3 The MCP47X6’s I2C module is compatible with the NXP I2C specification. The following lists some of the module’s features: • 7-bit slave addressing • Supports three clock rate modes: - Standard mode, clock rates up to 100 kHz - Fast mode, clock rates up to 400 kHz - High-speed mode (HS mode), clock rates up to 3.4 MHz • Support multi-master applications • General call addressing (Reset and Wake-Up commands) The I2C 10-bit Addressing mode is not supported. The NXP I2C specification only defines the field types, field lengths, timings, etc. of a frame. The frame content defines the behavior of the device. The frame content for the MCP47X6 is defined in Section 6.0 “MCP47X6 I2C Commands”. 5.3.1 I2C BIT STATES AND SEQUENCE Figure 5-8 shows the I2C transfer sequence. The serial clock is generated by the master. The following definitions are used for the bit states: The Start bit (see Figure 5-2) indicates the beginning of a data transfer sequence. The Start bit is defined as the SDA signal falling when the SCL signal is “High”. 1st Bit 2nd Bit SCL SCL FIGURE 5-4: FIGURE 5-2: Start Bit. Data Bit The SDA signal may change state while the SCL signal is Low. While the SCL signal is High, the SDA signal MUST be stable (see Figure 5-3). SDA 1st Bit D0 A 8 9 Acknowledge Waveform. Not A (A) Response The A bit has the SDA signal high. Table 5-1 shows some of the conditions where the slave device will issue a Not A (A). If an error condition occurs (such as an A instead of A), then a Start bit must be issued to reset the command state machine. MCP47X6 A/A RESPONSES Acknowledge Bit Response General Call A Slave Address valid A Slave Address not valid A Communication during EEPROM write cycle A Bus Collision S 5.3.1.2 SDA Event Start Bit SDA The A bit (see Figure 5-4) is typically a response from the receiving device to the transmitting device. Depending on the context of the transfer sequence, the A bit may indicate different things. Typically, the slave device will supply an A response after the Start bit and 8 “data” bits have been received. An A bit has the SDA signal low. TABLE 5-1: • Start bit (S) • Data bit • Acknowledge (A) bit (driven low) / No Acknowledge (A) bit (not driven low) • Repeated Start bit (Sr) • Stop bit (P) 5.3.1.1 Acknowledge (A) Bit N/A Comment After device has received address and command, and valid conditions for EEPROM write I2C module Resets, or a “Don’t Care” if the collision occurs on the Master’s “Start bit” 2nd Bit SCL Data Bit FIGURE 5-3: DS22272C-page 44 Data Bit. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 5.3.1.4 5.3.1.5 Repeated Start Bit The Repeated Start bit (see Figure 5-5) indicates the current master device wishes to continue communicating with the current slave device without releasing the I2C bus. The Repeated Start condition is the same as the Start condition, except that the Repeated Start bit follows a Start bit (with the Data bits + A bit) and not a Stop bit. Stop Bit The Stop bit (see Figure 5-6) Indicates the end of the I2C Data Transfer Sequence. The Stop bit is defined as the SDA signal rising when the SCL signal is “High”. A Stop bit resets the I2C interface of all MCP47X6 devices. SDA A / A The Start bit is the beginning of a data transfer sequence and is defined as the SDA signal falling when the SCL signal is “High”. SCL P Note 1: A bus collision during the Repeated Start condition occurs if: FIGURE 5-6: Transmit Mode. • SDA is sampled low when SCL goes from low to high. 5.3.2 • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". Stop Condition Receive or CLOCK STRETCHING “Clock Stretching” is something that the receiving Device can do, to allow additional time to “respond” to the “data” that has been received. The MCP47X6 will not stretch the clock signal (SCL) since memory read access occurs fast enough. 1st Bit SDA 5.3.3 If any part of the I2C transmission does not meet the command format, it is aborted. This can be intentionally accomplished with a Start or Stop condition. This is done so that noisy transmissions (usually an extra Start or Stop condition) are aborted before they corrupt the device. SCL Sr = Repeated Start FIGURE 5-5: Waveform. ABORTING A TRANSMISSION Repeat Start Condition SDA SCL S FIGURE 5-7: 1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit A/A P Typical 8-Bit I2C Waveform Format. SDA SCL Start Condition FIGURE 5-8: Data allowed to change Data or A valid Stop Condition I2C Data States and Bit Sequence. © 2011-2012 Microchip Technology Inc. DS22272C-page 45 MCP4706/4716/4726 5.3.4 SLOPE CONTROL TABLE 5-2: I2C ADDRESS/ORDER CODE The MCP47X6 implements slope control on the SDA output. 7-bit I2C™ Device Order Code Address As the device transitions from HS mode to FS mode, the slope control parameter will change from the HS specification to the FS specification. ‘1100000’ For Fast (FS) and High-Speed (HS) modes, the device has a spike suppression and a Schmidt Trigger at SDA and SCL inputs. ‘1100001’ ‘1100010’ 5.3.5 DEVICE ADDRESSING The address byte is the first byte received following the Start condition from the master device. The MCP47X6’s slave address consists of a 4-bit fixed code (‘1100’) and a 3-bit code that is user specified when the device is ordered. This allows up to eight MCP47X6 devices on a single I2C bus. Figure 5-9 shows the I2C slave address byte format, which contains the seven address bits and a read/write (R/W) bit. Table 5-2 shows the eight I2C slave address options and their respective device order code. ‘1100011’ ‘1100100’ ‘1100101’ ‘1100110’ ‘1100111’ Acknowledge bit Note 1: Start bit Read/Write bit R/W Slave Address ACK Address Byte 2: Comment MCP47x6A0-E/xx MCP47x6A0T-E/xx Tape and Reel MCP47x6A1-E/xx MCP47x6A1T-E/xx Tape and Reel MCP47x6A2-E/xx MCP47x6A2T-E/xx Tape and Reel MCP47x6A3-E/xx MCP47x6A3T-E/xx Tape and Reel MCP47x6A4-E/xx MCP47x6A4T-E/xx Tape and Reel MCP47x6A5-E/xx MCP47x6A5T-E/xx Tape and Reel MCP47x6A6-E/xx MCP47x6A6T-E/xx Tape and Reel MCP47x6A7-E/xx MCP47x6A7T-E/xx Tape and Reel The sample center will generally stock I2C address ‘1100000’, other addresses may be available. ‘xx’ in the order code is the device package code (CH for SOT-23 and MAY for DFN) Slave Address (7-bits) Fixed 1 1 User Specified 0 0 A2 A1 A0 Note: Address Bits (A2:A0) specified at time of device order, see Table 5-2. FIGURE 5-9: I2C Control Byte. DS22272C-page 46 Slave Address Bits in the © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 5.3.6 HS MODE After switching to the High-Speed mode, the next transferred byte is the I2C control byte, which specifies the device to communicate with, and any number of data bytes plus acknowledgements. The master device can then either issue a Repeated Start bit to address a different device (at High-Speed) or a Stop bit to return to Fast/Standard bus speed. After the Stop bit, any other master device (in a multi-master system) can arbitrate for the I2C bus. 2 The I C specification requires that a High-Speed mode device must be ‘activated’ to operate in High-Speed (3.4 Mbit/s) mode. This is done by the master sending a special address byte following the Start bit. This byte is referred to as the High-Speed Master Mode Code (HSMMC). The MCP47X6 device does not acknowledge this byte. However, upon receiving this command, the device switches to HS mode. The device can now communicate at up to 3.4 Mbit/s on SDA and SCL lines. The device will switch out of the HS mode on the next Stop condition. See Figure 5-10 for illustration of HS mode command sequence. For more information on the HS mode, or other I2C modes, please refer to the NXP I2C specification. The master code is sent as follows: 1. 2. 3. 5.3.6.1 Start condition (S) High-Speed Master Mode Code (0000 1XXX), The XXX bits are unique to the High-Speed (HS) mode master. No Acknowledge (A) Slope Control The slope control on the SDA output is different between the Fast/Standard Speed and the High-Speed clock modes of the interface. 5.3.6.2 Pulse Gobbler The pulse gobbler on the SCL pin is automatically adjusted to suppress spikes < 10 ns during HS mode. F/S-mode HS mode S ‘0 0 0 0 1 X X X’b P A Sr ‘Slave Address’ R/W A HS Select Byte Control Byte “Data” Command/Data Byte(s) S = Start bit Sr = Repeated Start bit A = Acknowledge bit A = Not Acknowledge bit R/W = Read/Write bit P = Stop bit (Stop condition terminates HS mode) FIGURE 5-10: A/A F/S mode HS mode continues Sr ‘Slave Address’ R/W A Control Byte HS Mode Sequence. © 2011-2012 Microchip Technology Inc. DS22272C-page 47 MCP4706/4716/4726 5.3.7 GENERAL CALL The MCP47X6 has two General Call commands. The function of these commands are: The General Call is a method that the “master” device can communicate with all other “slave” devices. In a multi-master application, the other master devices are operating in Slave mode. The General Call address has two documented formats. These are shown in Figure 5-11. • Reset the device(s) (Software Reset) • Wake-Up the device(s) For details on the operation of the MCP47X6’s General Call commands, see Section 6.6 “I2C General Call Commands”. Note: Only one General Call command per issue of the General Call control byte. Any additional General Call commands are ignored and Not Acknowledged. Second Byte S 0 0 0 0 0 0 0 0 General Call Address A x x x x X x x 0 A P “7-bit Command” Reserved 7-bit Commands (By I2C Specification – NXP specification # UM10204, Rev. 03 19 June 2007) ‘0000 011’b - Reset and write programmable part of slave address by hardware ‘0000 010’b - Write programmable part of slave address by hardware ‘0000 000’b - NOT Allowed The Following is a “Hardware General Call” Format Second Byte S 0 0 0 0 0 0 0 0 General Call Address FIGURE 5-11: DS22272C-page 48 A x x x x X x x 1 “Master Address” n occurrences of (Data + A) A x x x x X x x X A P This indicates a “Hardware General Call” General Call Formats. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 MCP47X6 I2C COMMANDS 6.0 TABLE 6-1: The I2C protocol does not specify how commands are formatted, so this section specifies the MCP47X6’s I2C command formats and operation. Operation Write Volatile Memory Command The supported commands are shown in Table 6-2. Many of these commands allow for continuous operation. This means that the I2C master does not generate a Stop bit but repeats the required data/clocks. This allows faster updates since the overhead of the I2C control byte is removed. Table 6-1 shows the supported commands and the required number of bit clocks for both single and continuous commands. 0 X 1 0 38 27n + 11 Read Command (12 and 10-bit DAC Register) (2) Single Read Command (8-bit DAC Register) (2) Single 6.0.1 Continuous Continuous Continuous 38 27n + 11 20 9n + 11 65 54n + 11 47 36n + 11 “n” indicates the number of times the command operation is to be repeated. This command is useful to determine when an EEPROM programming cycle has completed (RDY/BSY Status bit) ABORTING A TRANSMISSION A Restart or Stop condition in an expected data bit position will abort the current command sequence and data will not be written to the MCP47X6. MCP47X6 SUPPORTED COMMANDS Command Name Writes Volatile Memory? Config. Write Volatile DAC Register Command (Note 2) 0 Single 2: The General Call commands utilize the I specification reserved General Call command address and command codes. 0 Continuous Write Volatile Configuration Bits Command Note 1: 2C C0 18n + 11 Single Continuous The Read command is strictly determined by the R/W bit = 1. There are two formats of the command, one for 12-bit and 10-bit devices and a second for 8-bit devices. C1 29 Write All Memory Command Single Write commands, determined by the R/W bit = 0, use up to three command codes bits (C2:C0) to determine the write’s operation. C2 Mode Write Volatile DAC Register Single Command (2) Continuous • Write memory • Read memory • General Call commands Command Code (Note 1) # of Bit Clocks (1) Command The commands can be grouped into the following categories: TABLE 6-2: I2C COMMANDS - NUMBER OF CLOCKS Write Volatile Memory Writes EEPROM Memory? DAC Config. DAC Command during EEPROM Write Cycle? PD1:PD0 only Yes No No No Yes Yes No No No Comment Writes volatile power-down bits so can also be used to exit a power-down state. Command 0 1 1 Write All Memory Command Yes Yes Yes Yes No 1 0 0 Write Volatile Configuration Bits Command Yes No No No No N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 1 0 1 1 1 0 1 1 1 Reserved Read Command N/A Note 1: 2: 3: General Call Reset General Call Wake-up N/A Reserved (Note 3) Reserved (Note 3) Yes Determined by R/W bit in I2C™ Control byte N/A No N/A No Determined by General Call command byte after the I2C General Call address. These bits are the MSb of the 2nd byte in the I2C Write command. See Figure 6-1 to Figure 6-4. X = Don’t Care bit. This command format does not use C0 bit. Device operation is not specified. © 2011-2012 Microchip Technology Inc. DS22272C-page 49 MCP4706/4716/4726 6.1 Write Volatile DAC Register (C2:C0 = 00x) This command is used to update the volatile DAC register value and the two Power-down Configuration bits (PD1:PD0). This command is typically used for a quick update of the analog output by modifying the minimum parameters. The EEPROM values are not affected by this command. Figure 6-1 shows an example of the command format, where a Stop bit completes the command. After this ACK bit, the I2C master should generate a Stop bit or the I2C master can repeat the 2nd (2 command bits + 2 power-down bits + 4 data bits (b11:b08)) and the 3rd byte (8 data bits (b07:b00)). Repeating the 2nd and 3rd bytes allows a continuous command where the volatile DAC register can be updated without the communication overhead of the device addressing byte (1st byte). The device updates the VOUT at the falling edge of the Acknowledge pulse of the 3rd byte. The volatile DAC register and Power-down Configuration bits are updated with the written date at the completion of the ACK bit (falling edge of SCL). Read/Write bit (Write) ACK bit (3) Start bit S SDA ACK bit (3) R/W A 1 1 0 0 A2 A1 A0 0 0 ACK bit (3) A 0 0 PD1 PD0 b11 b10 b09 b08 0 Stop bit A b07 b06 b05 b04 b03 b02 b01 b00 P 0 SCL Device Addressing Command Power Data bits (4 bits) bits Down bits Data bits (8 bits) Note 1 Note 2 Data bits (12 bits) b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 MCP4726 MCP4716 MCP4706 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X X X X X D07 D06 D05 D04 D03 D02 D01 D00 Note 1: The device updates VOUT at the falling edge of the SCL at the end of this ACK pulse. 2: The 2nd-3rd bytes can be repeated after the 3rd byte by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. Legend: X = don’t care D11:D00 = 12-bit data for MCP4726 device D09:D00 = 10-bit data for MCP4716 device D07:D00 = 8-bit data for MCP4706 device FIGURE 6-1: DS22272C-page 50 Write Volatile DAC Register Command. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 6.2 Write Volatile Memory (C2:C0 = 010) This Write command is used to update the volatile DAC register value and Configuration bits. The EEPROM is not affected by this command. Figure 6-2 shows an example of this Write command. The volatile DAC register and Configuration bits are updated with the written date at the completion of the ACK bit (falling edge of SCL). After this ACK bit, the I2C master should generate a Stop bit or the I2C master can repeat the 2nd (3 command bits + 5 Configuration bits), and the 3rd byte (8 data bits (b15:b08)), and the 4th byte (8 data bits (b07:b00)). Repeating the 2nd through 4th bytes allows a continuous command where the volatile DAC register and Configuration bits can be updated without the communication overhead of the device addressing byte (1st byte). Read/Write bit (Write) ACK bit (3) Start bit S SDA R/W A 1 1 0 A2 A1 A0 0 0 0 ACK bit (3) VREF1 0 1 0 A VREF0 PD1 PD0 ACK bit (3) G 0 A b15 b14 b13 b12 b11 b10 b09 b08 0 SCL Device Addressing Command Ref. Power- Gain Voltage Down bit bits Select bits bits Data bits (8 bits) (3rd byte) ACK bit (3) Stop bit A b07 b06 b05 b04 b03 b02 b01 b00 P 0 Data bits (8 bits) (4th byte) Data bits (16 bits) (3rd + 4th bytes) b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 MCP4726 MCP4716 MCP4706 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X D07 D06 D05 D04 D03 D02 D01 D00 X X X X X X X X X X X X X Note 1 Note 2 X X X Note 1: The device updates VOUT at the falling edge of the SCL at the end of this ACK pulse. 2: The 2nd-4th bytes can be repeated after the 4th byte by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. Legend: X = don’t care D11:D00 = 12-bit data for MCP4726 device D09:D00 = 10-bit data for MCP4716 device D07:D00 = 8-bit data for MCP4706 device FIGURE 6-2: Write Volatile Memory Command. © 2011-2012 Microchip Technology Inc. DS22272C-page 51 MCP4706/4716/4726 6.3 Write All Memory (C2:C0 = 011) Note: This Write command is used to update the volatile and nonvolatile (EEPROM) DAC register value and Configuration bits. Figure 6-3 shows an example of this Write command. • VOUT update: At the falling edge of the Acknowledge pulse of the 4th byte. • EEPROM update: At the falling edge of the Acknowledge pulse of the 4th byte. RDY/BSY bit toggles to “low” and back to “high” after the EEPROM write is completed. The state of the RDY/BSY bit can be monitored by a Read command. Write commands which only update volatile memory (C2:C0 = 00x or ‘010’) can be issued. Read commands and the General Call commands may not be issued. The DAC register and Power-down Configuration bits (volatile and EEPROM) are updated with the written date at the completion of the ACK bit (falling edge of SCL). The EEPROM memory requires time (TWC) for the values to be written. Another Write All Memory command should not be issued until the EEPROM write is complete. Read/Write bit (Write) ACK bit (3) Start bit S SDA R/W A 1 1 0 A2 A1 A0 0 0 0 ACK bit (3) VREF1 0 1 1 A VREF0 PD1 PD0 ACK bit (3) G 0 A b15 b14 b13 b12 b11 b10 b09 b08 0 SCL Device Addressing Command Ref. Power- Gain bits Voltage Down bit Select bits bits Data bits (8 bits) (3rd byte) ACK bit (3) Stop bit A b07 b06 b05 b04 b03 b02 b01 b00 P 0 Data bits (8 bits) (4th byte) Data bits (16 bits) (3rd + 4th bytes) b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 MCP4726 MCP4716 MCP4706 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X D07 D06 D05 D04 D03 D02 D01 D00 X X X X X X X X X X X X X Note 1 Note 2 X X X Note 1: The device updates VOUT at the falling edge of the SCL at the end of this ACK pulse. 2: The 2nd-4th bytes can be repeated after the 4th byte by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. Legend: X = don’t care D11:D00 = 12-bit data for MCP4726 device D09:D00 = 10-bit data for MCP4716 device D07:D00 = 8-bit data for MCP4706 device FIGURE 6-3: DS22272C-page 52 Write All Memory Command. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 6.4 Write Volatile Configuration Bits (C2:C0 = 100) This Write command is used to update the volatile Configuration register bits only. This command is a quick method to modify the configuration of the DAC, such as the selection of the resistor ladder reference voltage, the op amp gain, and the power-down state. Figure 6-4 shows an example of this Write command. Read/Write bit (Write) ACK bit (3) Start bit S SDA ACK bit (3) R/W A 1 1 0 0 A2 A1 A0 0 0 VREF1 1 0 0 A VREF0 PD1 PD0 G Stop bit P 0 SCL Device Addressing Command bits Configuration bits Note 1 Note 2 Note 1: The device updates VOUT at the falling edge of the SCL at the end of this ACK pulse. 2: The 2nd byte can be repeated after the 2nd by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. FIGURE 6-4: Write Volatile Configuration Bits Command. © 2011-2012 Microchip Technology Inc. DS22272C-page 53 MCP4706/4716/4726 6.5 READ COMMAND This command reads all the device memory. This includes the volatile and nonvolatile (EEPROM) DAC register values and Configuration bits, and the volatile status bits. This command is executed when the I2C control byte’s Read/Write bit is a ‘1’ (read). This command has two different formats based on the resolution of the device. The 12-bit and 10-bit devices use the format in Figure 6-5, while the 8-bit device uses the format in Figure 6-6. The 2nd byte (Configuration bits) indicates the current condition of the device operation. The RDY/BSY bit indicates EEPROM writing status. Read/Write bit (Read) ACK bit (2) Start bit S R/W A 1 SDA 1 0 0 A2 A1 A0 1 0 SCL Device Addressing ACK bit (3) VREF1 RDY POR 0 Vol. Status bits A VREF0 PD1 PD0 G 0 b15 b14 b13 b12 b11 b10 b09 b08 ACK bit (3) VREF1 Vol. Status bits 1 PD1 PD0 G NV Configuration bits A 0 0 b07 b06 b05 b04 b03 b02 b01 b00 ACK/NACK bit (4) Stop bit A b15 b14 b13 b12 b11 b10 b09 b08 A/N 0 NV Data bits (8 bits) (6th byte) b07 b06 b05 b04 b03 b02 b01 b00 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 0 0 P 0/1 NV Data bits (8 bits) (7th byte) Data bits (16 bits) (3rd + 4th bytes, and 6th + 7th bytes) b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 MCP4726 MCP4716 0 Vol. Data bits (8 bits) (4th byte) ACK bit (3) A VREF0 ACK bit (3) A Vol. Data bits (8 bits) (3rd byte) Vol. Configuration bits RDY POR ACK bit (3) 0 0 0 0 0 0 Note 1 0 0 Note 1: The 2nd-7th bytes can be repeated after the 7th byte by continued clocking before issuing Stop bit. 2: ACK bit generated by MCP47X6. 3: ACK bit generated by I2C Master. 4: ACK/NACK bit generated by I2C Master. Legend: D11:D00 = 12-bit data for MCP4726 device D09:D00 = 10-bit data for MCP4716 device FIGURE 6-5: DS22272C-page 54 Read Command Format for 12-bit DAC (MCP4726) and 10-bit DAC (MCP4716). © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 Read/Write bit (Read) ACK bit (2) Start bit S SDA ACK bit (3) R/W A 1 1 0 0 A2 A1 A0 1 0 VREF1 RDY POR 0 ACK bit (3) A VREF0 PD1 PD0 G 0 A b07 b06 b05 b04 b03 b02 b01 b00 0 SCL Device Addressing Vol. Status bits Vol. Configuration bits Vol. Data bits (8 bits) (3rd byte) ACK/NACK bit (4) Stop bit ACK bit (3) VREF1 RDY POR 1 Vol. Status bits A VREF0 PD1 PD0 NV Configuration bits G 0 A/N b07 b06 b05 b04 b03 b02 b01 b00 NV Data bits (8 bits) (5th byte) Data bits (8 bits) (3rd and 5th bytes) b07 b06 b05 b04 b03 b02 b01 b00 MCP4706 P 0/1 Note 1 D07 D06 D05 D04 D03 D02 D01 D00 Note 1: The 2nd-5th bytes can be repeated after the 5th byte by continued clocking before issuing Stop bit. 2: ACK bit generated by MCP47X6. 3: ACK bit generated by I2C™ master. 4: ACK/NACK bit generated by I2C™ master. Legend: D07:D00 = 8-bit data for MCP4706 device FIGURE 6-6: Read Command Format for 8-bit DAC (MCP4706). © 2011-2012 Microchip Technology Inc. DS22272C-page 55 MCP4706/4716/4726 6.6 I2C General Call Commands 6.6.1 GENERAL CALL RESET The device performs General Call Reset if the second byte is “00000110” (06h). At the acknowledgement of this byte, the device will abort the current conversion and perform the following tasks: The device acknowledges the General Call Address command (0x00 in the first byte). The meaning of the general call address is always specified in the second byte. The I2C specification does not allow “00000000” (00h) in the second byte. Please refer to the Phillips I2C document for more details on the General Call specifications. • Internal Reset similar to a Power-on Reset (POR). The contents of the EEPROM are loaded into the DAC registers and analog output is available immediately. • This is a similar event to the POR. The VOUT will be available immediately, but after a short time delay following the Acknowledgement pulse. The VOUT value is determined by the EEPROM contents. The MCP47X6 devices support the following I2C general calls: • General Call Reset • General Call Wake-Up This command allows multiple MCP47X6 devices to be reset synchronously. Read/Write bit (Write) ACK bit (3) Start bit S R/W A 0 SDA ACK bit (3) 0 0 0 0 0 0 0 0 A 0 0 0 0 0 1 1 0 Stop bit P 0 SCL General Call Address General Call Reset Command Note 1 Note 2 Note 1: At the falling edge of the SCL at the end of this ACK pulse a Reset occurs (start-up timer starts and DAC register latched). 2: The 2nd byte can be repeated after the 2nd by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. FIGURE 6-7: DS22272C-page 56 General Call Reset Command. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 6.6.2 GENERAL CALL WAKE-UP This command does not adhere to the I2C specification where if the LSb of the 2nd byte is a ‘1’, it is a ‘Hardware General Call’ (see the NXP I2C Specification). Note: If the second byte is “00001001” (09h), the device forces the volatile power-down bits to ‘00’. The nonvolatile (EEPROM) power-down bit values are not affected by this command. This command allows multiple MCP47X6 devices to wake-up synchronously. Read/Write bit (Write) ACK bit (3) Start bit S SDA ACK bit (3) R/W A 0 0 0 0 0 0 0 0 0 A 0 0 0 0 1 0 0 1 Stop bit P 0 SCL General Call Address General Call Wake-Up Command Note 1 Note 2 Note 1: At the falling edge of the SCL, at the end of this ACK pulse, the volatile PD1:PD0 bits are forced to ‘00’. 2: The 2nd byte can be repeated after the 2nd by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. FIGURE 6-8: General Call Wake-Up Command. © 2011-2012 Microchip Technology Inc. DS22272C-page 57 MCP4706/4716/4726 NOTES: DS22272C-page 58 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 7.0 TERMINOLOGY 7.1 Resolution The resolution is the number of DAC output states that divide the full-scale range. For the 12-bit DAC, the resolution is 212, meaning the DAC code ranges from 0 to 4095. 7.2 For a given output voltage range, which is typically the voltage between the Full-Scale voltage and the ZeroScale voltage (VOUT(FS) - VOUT(ZS)), it is divided by the resolution of the device (Equation 7-1). EQUATION 7-1: VLSb = LSb VOLTAGE CALCULATION VOUT(FS) - VOUT(ZS) 2N - 1 2N = 4096 (MCP4726) 1024 (MCP4716) 256 (MCP4706) The Zero-Scale error (see Figure 7-4) is the difference between the ideal and measured VOUT voltage with the volatile DAC register equal to 000h. The Zero-Scale error is the same as the Offset error for this case (volatile DAC register = 000h). EQUATION 7-3: ZSE = ZERO-SCALE ERROR VOUT(@ZS) VLSb Where: FSE is expressed in LSb VOUT(@ZS) is the VOUT voltage when the DAC register code is at Zero-scale. VLSb is the delta voltage of one DAC register code step (such as code 000h to code 001h). 7.6 Offset Error The Offset error (see Figure 7-1) is the deviation from zero voltage output when the volatile DAC register value = 000h (zero scale voltage). This error affects all codes by the same amount. The Offset error can be calibrated by software in application circuits. Monotonicity Normally this is thought of as the VOUT voltage never decreasing, as the DAC register code is continuously incremented by 1 code step (LSb). 7.4 Zero-Scale Error (ZSE) Least Significant bit (LSb) Normally this is thought of as the ideal voltage difference between two successive codes. This bit has the smallest value or weight of all bits in the register. 7.3 7.5 Actual Transfer Function Analog Output Full-Scale Error (FSE) The Full-Scale error (see Figure 7-4) is the sum of Offset error plus Gain error. It is the difference between the ideal and measured DAC output voltage with all bits set to one (DAC input code = FFFh for 12-bit DAC). EQUATION 7-2: FSE = Ideal Transfer Function Offset Error (ZSE) 0 FIGURE 7-1: DAC Input Code Offset Error Example. FULL-SCALE ERROR VOUT(@FS) - VIDEAL(@FS) VLSb Where: FSE is expressed in LSb VOUT(@FS) is the VOUT voltage when the DAC register code is at Full-scale. VIDEAL(@FS) is the ideal output voltage when the DAC register code is at Full-scale. VLSb is the delta voltage of one DAC register code step (such as code 000h to code 001h). © 2011-2012 Microchip Technology Inc. DS22272C-page 59 MCP4706/4716/4726 7.7 Integral Nonlinearity (INL) The Integral Nonlinearity (INL) error is the maximum deviation of an actual transfer function from an ideal transfer function (straight line). In the MCP47X6, INL is calculated using two end points (zero and full scale). INL can be expressed as a percentage of full scale range (FSR) or in a fraction of an LSb. INL is also called relative accuracy. Equation 7-4 shows how to calculate the INL error in LSb and Figure 7-2 shows an example of INL accuracy. EQUATION 7-4: Where: INL is expressed in LSb. = Code*LSb VIdeal = Differential Nonlinearity (DNL) The Differential Nonlinearity (DNL) error (see Figure 7-3) is the measure of step size between codes in actual transfer function. The ideal step size between codes is 1 LSb. A DNL error of zero would imply that every code is exactly 1 LSb wide. If the DNL error is less than 1 LSb, the DAC ensures monotonic output and no missing codes. The DNL error between any two adjacent codes is calculated as follows: EQUATION 7-5: INL ERROR ( V OUT – V Ideal ) INL = --------------------------------------LSb VOUT 7.8 The output voltage measured with a given DAC input code DNL ERROR ΔV OUT – LSb DNL = ---------------------------------LSb Where: DNL is expressed in LSb. ΔVOUT = The measured DAC output voltage difference between two adjacent input codes 7 7 DNL = 0.5 LSb 6 INL = < -1 LSb 6 5 INL = - 1 LSb 5 Analog 4 Output (LSb) 3 DNL = 2 LSb Analog 4 Output (LSb) 3 INL = 0.5 LSb 2 2 1 1 0 000 001 010 0 000 001 010 011 100 101 110 111 DAC Input Code Ideal Transfer Function Actual Transfer Function Ideal Transfer Function Actual Transfer Function FIGURE 7-2: DS22272C-page 60 011 100 101 110 111 DAC Input Code FIGURE 7-3: DNL Accuracy Example. INL Accuracy Example. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 7.9 Gain Error 7.10 The Gain error (see Figure 7-4) is the difference between the actual full-scale output voltage from the ideal output voltage of the DAC transfer curve. The Gain error is calculated after nullifying the Offset error, or Full-Scale error minus the Offset error. The Gain error indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The Gain error is usually expressed as percent of full-scale range (% of FSR) or in LSb. In the MCP4706/4716/4726, the Gain error is not calibrated at the factory and most of the Gain error is contributed by the output buffer (op amp) saturation near the code range beyond 4000d. For the applications that need the Gain error specification less than 1% maximum, the user may consider using the DAC code range between 100d and 4000d instead of using full code range (code 0 to 4095d). The DAC output of the code range between 100d and 4000d is much more linear than full-scale range (0 to 4095d). The Gain error can be calibrated out by software in the application. Actual Transfer Function Full-Scale Error Gain Error Analog The Gain error drift is the variation in Gain error due to a change in ambient temperature. The Gain error drift is typically expressed in ppm/oC. 7.11 Actual Transfer Function after Offset Error is removed Zero-Scale Error 0 FIGURE 7-4: Error Example. Ideal Transfer Function DAC Input Code Offset Error Drift The Offset error drift is the variation in Offset error due to a change in ambient temperature. The Offset error drift is typically expressed in ppm/oC. 7.12 Settling Time The Settling time is the time delay required for the VOUT voltage to settle into its new output value. This time is measured from the start of code transition, to when the VOUT voltage is within the specified accuracy. In the MCP47X6, the settling time is a measure of the time delay until the VOUT voltage reaches within 0.5 LSb of its final value, when the volatile DAC register changes from 400h to C00h. 7.13 Major-Code Transition Glitch Major-code transition glitch is the impulse energy injected into the DAC analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-Sec, and is measured when the digital code is changed by 1 LSb at the major carry transition (Example: 011...111 to 100... 000, or 100... 000 to 011 ... 111). 7.14 Output Gain Error Drift Digital Feedthrough The digital feedthrough is the glitch that appears at the analog output caused by coupling from the digital input pins of the device. The area of the glitch is expressed in nV-Sec, and is measured with a full scale change (Example: all 0s to all 1s and vice versa) on the digital input pins. The digital feedthrough is measured when the DAC is not being written to the output register. Gain Error and Full-Scale 7.15 Power-Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. The VOUT is measured while the VDD is varied +/- 10%, and expressed in dB or µV/V. © 2011-2012 Microchip Technology Inc. DS22272C-page 61 MCP4706/4716/4726 NOTES: DS22272C-page 62 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 TYPICAL APPLICATIONS The MCP47X6 family of devices are general purpose, single channel voltage output DACs for various applications where a precision operation with low-power and nonvolatile EEPROM memory is needed. Since the devices include a nonvolatile EEPROM memory, the user can utilize these devices for applications that require the output to return to the previous set-up value on subsequent power-ups. 8.1.1 The user can test the presence of the device on the I2C bus line using a simple I2C command. This test can be achieved by checking an acknowledge response from the device after sending a Read or Write command. Figure 8-1 shows an example with a Read command. The steps are: a) b) Applications generally suited for the devices are: • • • • Set Point or Offset Trimming Sensor Calibration Portable Instrumentation (Battery Powered) Motor Control 8.1 Connecting to I2C BUS using Pull-Up Resistors The SCL and SDA pins of the MCP47X6 devices are open-drain configurations. These pins require a pull-up resistor as shown in Figure 8-2. The pull-up resistor values (R1 and R2) for SCL and SDA pins depend on the operating speed (standard, fast, and high speed) and loading capacitance of the I2C bus line. A higher value of the pull-up resistor consumes less power, but increases the signal transition time (higher RC time constant) on the bus line. Therefore, it can limit the bus operating speed. The lower resistor value, on the other hand, consumes higher power, but allows higher operating speed. If the bus line has higher capacitance due to long metal traces or multiple device connections to the bus line, a smaller pull-up resistor is needed to compensate the long RC time constant. The pull-up resistor is typically chosen between 1 kΩ and 10 kΩ ranges for Standard and Fast modes, and less than 1 kΩ for High-Speed mode. © 2011-2012 Microchip Technology Inc. DEVICE CONNECTION TEST c) Set the R/W bit “High” in the device’s address byte. Check the ACK bit of the address byte. If the device acknowledges (ACK = 0) the command, then the device is connected, otherwise it is not connected. Send Stop bit. Address Byte SCL 1 2 SDA 1 1 0 Start Bit 3 4 5 6 7 8 1 A2 A1 A0 1 9 ACK 8.0 Stop Bit Device Code Address bits R/W Device Response FIGURE 8-1: I2C Bus Connection Test. DS22272C-page 63 MCP4706/4716/4726 Power Supply Considerations VDD The power source should be as clean as possible. The power supply to the device is also used for the DAC voltage reference internally if the internal VDD is selected as the resistor ladder’s reference voltage (VREF1:VREF0 = 00 or 01). Analog C3 Output VOUT 1 VSS VDD 2 3 MCP47X6 Any noise induced on the VDD line can affect the DAC performance. Typical applications will require a bypass capacitor in order to filter out high-frequency noise on the VDD line. The noise can be induced onto the power supply’s traces or as a result of changes on the DAC output. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-2 shows an example of using two bypass capacitors (a 10 µF tantalum capacitor and a 0.1 µF ceramic capacitor) in parallel on the VDD line. These capacitors should be placed as close to the VDD pin as possible (within 4 mm). If the application circuit has separate digital and analog power supplies, the VDD and VSS pins of the device should reside on the analog plane. Optional 6 VREF 5 4 R1 R2 SCL To MCU SDA C1 C2 (a) Circuit when VDD is selected as reference (Note: VDD is connected to the reference circuit internally.) VDD Optional Optional Analog C3 Output VOUT 1 VSS 2 VDD 3 MCP47X6 8.2 VREF C4 C5 6 VREF 5 4 SCL R1 R2 To MCU SDA C1 C2 (b) Circuit when external reference is used. R1 and R2 are I2C™ pull-up resistors: R1 and R2: 5 kΩ - 10 kΩ for fSCL = 100 kHz to 400 kHz ~700Ω for fSCL = 3.4 MHz C1: 0.1 µF capacitor Ceramic C2: 10 µF capacitor Tantalum C3: ~ 0.1 µF Optional to reduce noise in VOUT pin. C4: 0.1 µF capacitor Ceramic C5: 10 µF capacitor Tantalum Note: Pin assignment is opposite in DFN-6 package. FIGURE 8-2: Example MCP47X6 Circuit with SOT-23 package. DS22272C-page 64 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 8.3 Application Examples The MCP47X6 devices are rail-to-rail output DACs designed to operate with a VDD range of 2.7V to 5.5V. The internal output op amplifier is robust enough to drive common, small-signal loads directly, thus eliminating the cost and size of external buffers for most applications. The user can use gain of 1 or 2 of the output op amplifier by setting the Configuration register bits. Also, the user can use internal VDD as the reference or use external reference. Various user options and easy-to-use features make the devices suitable for various modern DAC applications. Application examples include: • • • • • • • • • • Decreasing Output Step Size Building a “Window” DAC Bipolar Operation Selectable Gain and Offset Bipolar Voltage Output Designing a Double-Precision DAC Building Programmable Current Source Serial Interface Communication Times Software I2C Interface Reset Sequence Power Supply Considerations Layout Considerations 8.3.1 DC SET POINT OR CALIBRATION A common application for the devices is a digitally-controlled set point and/or calibration of variable parameters, such as sensor offset or slope. For example, the MCP4726 provides 4096 output steps. If voltage reference is 4.096V, the LSb size is 1 mV. If a smaller output step size is desired, a lower external voltage reference is needed. 8.3.1.1 Decreasing Output Step Size If the application is calibrating the bias voltage of a diode or transistor, a bias voltage range of 0.8V may be desired with about 200 µV resolution per step. Two common methods to achieve small step size are using lower VREF pin voltage or using a voltage divider on the DAC’s output. Using an external voltage reference (VREF) is an option, if the external reference is available with the desired output voltage range. However, occasionally, when using a low-voltage reference voltage, the noise floor causes a SNR error that is intolerable. Using a voltage divider method is another option, and provides some advantages when external voltage reference needs to be very low, or when the desired output voltage is not available. In this case, a larger value reference voltage is used, while two resistors scale the output range down to the precise desired level. Figure 8-3 illustrates this concept. A bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the DAC and the induced noise from the environment. VDD Optional VREF VDD RSENSE VCC+ R1 MCP47X6 VTRIP Comp. VO C1 R2 I2C™ VOUT VCC– 2-wire FIGURE 8-3: Example Circuit Of Set Point or Threshold Calibration. EQUATION 8-1: VOUT AND VTRIP CALCULATIONS VOUT = VREF • G • DAC Register Value 2N ⎛ R2 ⎞ V trip = V OUT ⎜ --------------------⎟ ⎝ R 1 + R 2⎠ © 2011-2012 Microchip Technology Inc. DS22272C-page 65 MCP4706/4716/4726 8.3.1.2 Building a “Window” DAC 8.4 When calibrating a set point or threshold of a sensor, typically only a small portion of the DAC output range is utilized. If the LSb size is adequate enough to meet the application’s accuracy needs, the unused range is sacrificed without consequences. If greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. If the threshold is not near VREF, 2 • VREF, or VSS, then creating a “window” around the threshold has several advantages. One simple method to create this “window” is to use a voltage divider network with a pull-up and pull-down resistor. Figure 8-4 and Figure 8-6 illustrate this concept. Bipolar Operation Bipolar operation is achievable by utilizing an external operational amplifier. This configuration is desirable due to the wide variety and availability of op amps. This allows a general purpose DAC, with its cost and availability advantages, to meet almost any desired output voltage range, power and noise performance. Figure 8-5 illustrates a simple bipolar voltage source configuration. R1 and R2 allow the gain to be selected, while R3 and R4 shift the DAC's output to a selected offset. Note that R4 can be tied to VDD, instead of VSS, if a higher offset is desired. Optional VREF VDD VCC+ Optional VREF VDD VCC+ RSENSE MCP47X6 VCC+ R1 MCP47X6 R3 R3 VTRIP Comp. VOUT I2C™ 2-wire C1 R2 VOA+ VOUT C1 R4 VO VO I2C™ VCC– 2-wire VCC– R2 VIN R1 VCC– FIGURE 8-4: DAC. Single-Supply “Window” FIGURE 8-5: Digitally-Controlled Bipolar Voltage Source Example Circuit. EQUATION 8-2: VOUT AND VTRIP CALCULATIONS EQUATION 8-3: VOUT = VREF • G • DAC Register Value VOUT = VREF • G • 2N V OUT R23 + V 23 R1 V TRIP = --------------------------------------------R 1 + R23 Thevenin Equivalent VOUT, VOA+, AND VO CALCULATIONS VOA+ = R2R3 R23 = ------------------R2 + R3 DAC Register Value VOUT • R4 R3 + R4 VO = VOA+ • ( 1 + ( VCC+ R2 ) + ( V CC- R 3 ) V23 = -----------------------------------------------------R 2 + R3 2N R2 R1 ) - VDD • ( R2 R1 ) R1 VOUT VTRIP R23 V23 DS22272C-page 66 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 8.5 Selectable Gain and Offset Bipolar Voltage Output In some applications, precision digital control of the output range is desirable. Figure 8-6 illustrates how to use the DAC devices to achieve this in a bipolar or single-supply application. This circuit is typically used for linearizing a sensor whose slope and offset varies. The equation to design a bipolar “window” DAC would be utilized if R3, R4 and R5 are populated. 8.5.1 BIPOLAR DAC EXAMPLE USING MCP4726 Optional VCC+ Optional VREF VDD R5 MCP4726 I2C™ 2-wire Since 212 = 4096, 12-bit resolution is desired. Step 3: The amplifier gain (R2/R1), multiplied by full-scale VOUT (4.096V), must be equal to the desired minimum output to achieve bipolar operation. Since any gain can be realized by choosing resistor values (R1+R2), the VREF value must be selected first. If a VREF of 4.096V is used, solve for the amplifier’s gain by setting the DAC to 0, knowing that the output needs to be -2.05V. The equation can be simplified to: – R2 – 2.05 --------- = ----------------R1 4.096V R2 VIN R1 C1 = 0.1 µF FIGURE 8-6: Bipolar Voltage Source with Selectable Gain and Offset. EQUATION 8-4: VOUT, VOA+, AND VO CALCULATIONS VOUT = VREF • G • VOA+ = DAC Register Value R4 2 2.05V + ( 0.5 ⋅ 4.096V ) ------------------------ = ------------------------------------------------------- = --( R3 + R 4 ) 1.5 ⋅ 4.096V 3 If R4 = 20 kΩ, then R3 = 10 kΩ 2N VOUT • R4 + VCC- • R5 R3 + R4 R2 1 ------ = --R1 2 Step 4: Next, solve for R3 and R4 by setting the DAC to 4096, knowing that the output needs to be +2.05V. VCC– VCC– VO = VOA+ • ( 1 + If R1 = 20 kΩ and R2 = 10 kΩ, the gain will be 0.5. VOUT C1 R4 Step 1: Calculate the range: +2.05V – (-2.05V) = 4.1V. 4.1V/1 mV = 4100 VOA+ VO An output step size of 1 mV, with an output range of ±2.05V, is desired for a particular application. Step 2: Calculate the resolution needed: VCC+ R3 R2 R1 ) - VIN • ( Offset Adjust EQUATION 8-5: Thevenin Equivalent R2 R1 ) Gain Adjust BIPOLAR “WINDOW” DAC USING R4 AND R5 V CC+ R 4 + VCC- R5 V 45 = --------------------------------------------R 4 + R5 VOUT R 45 + V 45 R 3 VIN+ = --------------------------------------------R3 + R 45 R4R5 R45 = ------------------R4 + R5 R2 R2 V O = V IN+ ⎛⎝ 1 + ------⎞⎠ – V A ⎛⎝ ------⎞⎠ R1 R1 Offset Adjust Gain Adjust © 2011-2012 Microchip Technology Inc. DS22272C-page 67 MCP4706/4716/4726 8.6 Designing a Double-Precision DAC 8.7 Building Programmable Current Source Figure 8-7 shows an example design of a single-supply voltage output capable of up to 24-bit resolution. This requires two 12-bit DACs. This design is simply a voltage divider with a buffered output. Figure 8-8 shows an example of building a programmable current source using a voltage follower. The current sensor resistor is used to convert the DAC voltage output into a digitally-selectable current source. As an example, if a similar application to the one developed in Section 8.5.1 “Bipolar DAC Example Using MCP4726” required a resolution of 1 µV instead of 1 mV, and a range of 0V to 4.1V, then 12-bit resolution would not be adequate. The smaller RSENSE is, the less power dissipated across it. However, this also reduces the resolution that the current can be controlled. Step 1: Calculate the resolution needed: VDD (or VREF) Optional 4.1V/1 µV = 4.1 x 106. Since 222 = 4.2 x 106, 22-bit resolution is desired. Since DNL = ±0.75 LSb, this design can be attempted with the 12-bit DAC. Step 2: Since DACB’s VOUTB has a resolution of 1 mV, its output only needs to be “pulled” 1/1000 to meet the 1 µV target. Dividing VOUTA by 1000 would allow the application to compensate for DACB’s DNL error. Step 3: If R2 is 100Ω, then R1 needs to be 100 kΩ. Step 4: The resulting transfer function is shown in the equation of Example 8-6. VREF VDD Load VCC+ VOUT IL MCP47X6 Ib VCC– I2C™ 2-wire IL Ib = ---- RSENSE β V OUT β I L = --------------- × ------------R sense β + 1 where β = Common-Emitter Current Gain. Optional VDD VREF MCP4726 (A) FIGURE 8-8: Source. VOA R1 I2C™ 2-wire Digitally-Controlled Current VCC+ VOUT Optional VREF VDD 0.1 µF R2 MCP4726 (B) VCC– VOB I2C™ 2-wire FIGURE 8-7: Simple Double Precision DAC using MCP4726. EQUATION 8-6: VOUT = VOUT CALCULATION VOA * R2 + VOB * R1 R1 + R2 Where: VOA = (VREF * G * DAC A Register Value)/4096 VOB = (VREF * G * DAC B Register Value)/4096 G = Selected Op Amp Gain DS22272C-page 68 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 8.8 Serial Interface Communication Times Table 8-1 shows time/frequency of the supported operations of the I2C serial interface for the different serial interface operational frequencies. This, along with the VOUT output performance (such as slew rate), would be used to determine your application’s volatile DAC register update rate. TABLE 8-1: SERIAL INTERFACE TIMES / FREQUENCIES Command Code C2 C1 C0 Function # of Serial Interface Bits Writes Volatile Memory? Writes EEPROM Memory? Config. DAC Config. DAC (2) 100 kHz 400k Hz 3.4 MHz 100 kHz 400 kHz 3.4 MHz Yes(1) Yes No No 29 290 72.5 8.5 3.4 13.8 117.2 Command Time (uS) Command Frequency (kHz) 0 0 X Write Volatile DAC 0 1 0 Write Volatile Memory Yes Yes No No 38 380 95 11.2 2.6 10.5 89.5 0 1 1 Write All Memory Yes Yes Yes Yes 38 380 95 11.2 2.6 10.5 89.5 1 0 0 Write NV Configuration Bits Yes No No No 20 200 50 5.9 5.0 20.0 170.0 Read N/A N/A N/A N/A 77 750 187.5 22.1 1.3 5.3 45.3 N/A Note 1: 2: Only the volatile PD1:PD0 bits of the Configuration bits are written. Includes the Start or Stop bits. © 2011-2012 Microchip Technology Inc. DS22272C-page 69 MCP4706/4716/4726 Software I2C Interface Reset Sequence 8.9 Note: This technique is documented in AN1028. At times, it may become necessary to perform a Software Reset Sequence to ensure the MCP47X6 device is in a correct and known I2C interface state. This technique only resets the I2C state machine. This is useful if the MCP47X6 device powers up in an incorrect state (due to excessive bus noise, etc), or if the master device is reset during communication. Figure 8-9 shows the communication sequence to software reset the device. S ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Start bit S P Nine bits of ‘1’ Start bit Stop bit FIGURE 8-9: Format. Software Reset Sequence The 1st Start bit will cause the device to reset from a state in which it is expecting to receive data from the master device. In this mode, the device is monitoring the data bus in Receive mode and can detect if the Start bit forces an internal Reset. DS22272C-page 70 The nine bits of ‘1’ are used to force a Reset of those devices that could not be reset by the previous Start bit. This occurs only if the MCP47X6 is driving an A bit on the I2C bus, or is in Output mode (from a Read command) and is driving a data bit of ‘0’ onto the I2C bus. In both of these cases, the previous Start bit could not be generated due to the MCP47X6 holding the bus low. By sending out nine ‘1’ bits, it is ensured that the device will see an A bit (the master device does not drive the I2C bus low to acknowledge the data sent by the MCP47X6), which also forces the MCP47X6 to reset. The 2nd Start bit is sent to address the rare possibility of an erroneous write. This could occur if the master device was reset while sending a Write command to the MCP47X6, AND then as the master device returns to normal operation and issues a Start condition, while the MCP47X6 is issuing an acknowledge. In this case, if the 2nd Start bit is not sent (and the Stop bit was sent) the MCP47X6 could initiate a write cycle. Note: The potential for this erroneous write ONLY occurs if the master device is reset while sending a Write command to the MCP47X6. The Stop bit terminates the current I2C bus activity. The MCP47X6 waits to detect the next Start condition. This sequence does not effect any other I2C devices which may be on the bus, as they should disregard this as an invalid command. © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 8.10.2 • Power Supply Considerations • Layout Considerations 8.10.1 The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-10 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 µF. This capacitor should be placed as close (within 4 mm) to the device power pin (VDD) as possible. The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, VDD and VSS should reside on the analog plane. VDD 0.1 µF VDD 0.1 µF Noise Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP47X6’s performance. Careful board layout minimizes these effects and increases the Signal-to-Noise Ratio (SNR). Multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. Separate digital and analog ground planes are recommended. In this case, the VSS pin and the ground pins of the VDD capacitors should be terminated to the analog ground plane. Note: Breadboards and wire-wrapped boards are not recommended. 8.10.2.2 PCB Area Requirements In some applications, PCB area is a criteria for device selection. Table 8-2 shows the typical package dimensions and area for the different package options. The table also shows the relative area factor compared to the smallest area. For space critical applications, the DFN package would be the suggested package. PACKAGE FOOTPRINT (1) SCL SDA PIC® Microcontroller TABLE 8-2: MCP47X6 VOUT • Noise • PCB Area Requirements 8.10.2.1 POWER SUPPLY CONSIDERATIONS VREF Several layout considerations may be applicable to your application. These may include: Package Package Footprint Relative Area In the design of a system with the MCP4706/4716/4726 devices, the following considerations should be taken into account: LAYOUT CONSIDERATIONS Area (mm2) Design Considerations Pins 8.10 CH 2.90 2.70 7.83 1.96 MAY 2.00 2.00 4.00 1 Dimensions (mm) Type Code Length Width 6 6 SOT-23 DFN Note 1: Does not include recommended land pattern dimensions. Dimensions are typical values. VSS FIGURE 8-10: Connections. VSS Typical Microcontroller © 2011-2012 Microchip Technology Inc. DS22272C-page 71 MCP4706/4716/4726 NOTES: DS22272C-page 72 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 9.0 DEVELOPMENT SUPPORT Development support can be classified into two groups. These are: • Development Tools • Technical Documentation 9.1 Development Tools Several development tools are available to assist in your design and evaluation of the MCP47X6 devices. The currently available tools are shown in Table 9-1. These boards may be purchased directly from the Microchip web site at www.microchip.com. 9.1.1 Explorer 16 MCP47X6 PICtail™ Plus Development Board Daughter Board inserted into PICtail™ Connector MCP47X6 PICtail™ PLUS DAUGHTER BOARD The MCP47X6 PICtail™ Plus Daughter Board (order number: ADM00317) is available from Microchip Technology Inc. This board works with Microchip’s PICkit™ Serial Analyzer and PIC® Explorer 16 Development Board. The firmware example is also available for the Explorer 16 Development Board with PIC24FJ128. FIGURE 9-1: MCP47X6 PICtail™ Plus Daughter Board with PIC® Explorer 16 Development Board. MCP47X6 PICtail™ Plus Daughter Board Figure 9-1 shows the MCP47X6 PICtail™ Plus Daughter Board being used with a PIC® Explorer 16 Development Board (order number: ADM00317), while Figure 9-2 shows the MCP47X6 PICtail™ Plus Daughter Board being used with a PICkit™ Serial Analyzer. The PICkit™ Serial Analyzer allows the user to quickly evaluate the DAC operation. Refer to the “MCP47X6 PICtail™ Plus Daughter Board User’s Guide” (DS51932) for detailed descriptions on operating the daughter board. Refer to www.microchip.com for further information on this product and related material for the users. FIGURE 9-2: MCP47X6 PICtail™ Plus Daughter Board with PICkit™ Serial Analyzer. TABLE 9-1: DEVELOPMENT TOOLS Board Name Part # SC70-6 and SOT-23-6/8 to DIP-8 Evaluation Board SC70EV MCP47X6 PICtail™ Plus Daughter Board Evaluation ADM00317 Board(1, 2) Supported Devices MCP4706, MCP4716, MCP4726 MCP47X6 Note 1: Requires a PICDEM™ Demo board. See the User’s Guide for additional information and requirements. 2: Requires a PICkit™ Serial Analyzer. See the User’s Guide for additional information and requirements. © 2011-2012 Microchip Technology Inc. DS22272C-page 73 MCP4706/4716/4726 9.2 Technical Documentation Several additional technical documents are available to assist you in your design and development. These technical documents include Application Notes, Technical Briefs, and Design Guides. Table 9-2 shows some of these documents. TABLE 9-2: Application Note Number TECHNICAL DOCUMENTATION Title Literature # AN1326 Using the MCP4728 12-Bit DAC for LDMOS Amplifier Bias Control Applications DS01326 — Signal Chain Design Guide DS21825 — Analog Solutions for Automotive Applications Design Guide DS01005 DS22272C-page 74 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 6-Lead SOT-23 Example XXNN DC25 PIN 1 PIN 1 Address Option Code MCP4706A0T-E/CH MCP4716A0T-E/CH MCP4726A0T-E/CH A0 (00) DBNN DFNN DKNN A1 (01) DCNN DGNN DLNN A2 (10) DDNN DHNN DMNN A3 (11) DENN DJNN DPNN 6-Lead DFN (2x2x0.9 mm) Example AAB 256 Address Option Code MCP4706A0T-E/MAY MCP4716A0T-E/MAY A0 (00) AAA AAE AAP MCP4726A0T-E/MAY A1 (01) AAB AAF AAQ A2 (10) AAC AAG AAR A3 (11) AAD AAH AAS Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011-2012 Microchip Technology Inc. DS22272C-page 75 MCP4706/4716/4726 /$ !$%$ 0".!1 !!$ 20 &$$"$ $$ ,33... 3 0 b 4 N E E1 PIN 1 ID BY LASER MARK 1 2 3 e e1 D A A2 c φ L A1 L1 4$! !5 $! 6% 9&2! 55## 6 6 67 8 2$ )*+ 7%$!"5"2$ *+ 7-:$ ; ""200!! < ; ) $"&& ; ) 7-="$ # ; ""20="$ # ; < 7-5$ ; /$5$ 5 ; /$ $ 5 ) ; < /$ > ; > 5"0!! < ; 5"="$ 9 ; ) !!"#"$%" "&! $%!!"&! $%!!!$'" !"$ #() *+, *! !$'$-%!..$%$$! !" . +<* DS22272C-page 76 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011-2012 Microchip Technology Inc. DS22272C-page 77 MCP4706/4716/4726 DS22272C-page 78 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 © 2011-2012 Microchip Technology Inc. DS22272C-page 79 MCP4706/4716/4726 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22272C-page 80 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 APPENDIX A: REVISION HISTORY Revision C (April 2012) The following is the list of modifications: 1. 2. 3. 4. 5. Updated the layout of the Absolute Maximum Rating page. Added three new sections, Section 4.4.3 “Output Slew Rate”, Section 4.4.4 “Small Capacitive Load” and Section 4.4.5 “Large Capacitive Load”. Enhanced former Section 4.4.3 (now Section 4.4.6 “Driving Resistive and capacitive Loads”). Updated the descriptive information related to the ACK bit in FIGURE 6-5: “Read Command Format for 12-bit DAC (MCP4726) and 10-bit DAC (MCP4716).” Corrected DFN package code and drawings to MAY code (from MA code). Both MA and MAY have the same dimensions/footprint. Revision B (September 2011) The following is the list of modifications: 1. 2. Updated references to graphics and equations in the text. Updated notes in FIGURE 6-6: “Read Command Format for 8-bit DAC (MCP4706).” Revision A (February 2011) • Original Release of this Document. © 2011-2012 Microchip Technology Inc. DS22272C-page 81 MCP4706/4716/4726 NOTES: DS22272C-page 82 © 2011-2012 Microchip Technology Inc. MCP4706/4716/4726 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. X PART NO. XX Device Address Options Device: X Tape and Temperature Reel Range /XX Package MCP4706: Single Channel 8-Bit DAC with EEPROM Memory MCP4716: Single Channel 10-Bit DAC with EEPROM Memory MCP4726: Single Channel 12-Bit DAC with EEPROM Memory A0 = “1100000” I2C Address. Devices ordered from the Microchip Sample center will have this address. A1 = “1100001” I2C Address. A2 = “1100010” I2C Address. A3 = “1100011” I2C Address. A4 = “1100100” I2C Address. A5 = “1100101” I2C Address. A6 = “1100110” I2C Address. A7 = “1100111” I2C Address. Tape and Reel: T = Tape and Reel Temperature Range: E = -40°C to +125°C Package: CH = Plastic Small Outline Transistor (SOT-23-6), 6-lead MAY= Plastic Dual Flat, No Lead Package (2x2 DFN), 6-lead Address Options: © 2011-2012 Microchip Technology Inc. Examples: a) MCP4706A0T-E/CH: 8-bit VOUT resolution, I2C Address “1100000”, Tape and Reel, Extended Temp., 6LD SOT-23 pkg. b) MCP4706A6T-E/CH: 8-bit VOUT resolution, I2C Address “1100110”, Tape and Reel, Extended Temp., 6LD SOT-23 pkg. c) MCP4706A0T-E/MAY: 8-bit VOUT resolution, I2C Address “1100000”, Tape and Reel, Extended Temp., 6LD DFN pkg. d) MCP4706A6T-E/MAY: 8-bit VOUT resolution, I2C Address “1100110”, Tape and Reel, Extended Temp., 6LD DFN pkg. a) MCP4716A0T-E/CH: 10-bit VOUT resolution, I2C Address “1100000”, Tape and Reel, Extended Temp., 6LD SOT-23 pkg. b) MCP4716A6T-E/CH: 10-bit VOUT resolution, I2C Address “1100110”, Tape and Reel, Extended Temp., 6LD SOT-23 pkg. c) MCP4716A0T-E/MAY: 10-bit VOUT resolution, I2C Address “1100000”, Tape and Reel, Extended Temp., 6LD DFN pkg. d) MCP4716A6T-E/MAY: 10-bit VOUT resolution, I2C Address “1100110”, Tape and Reel, Extended Temp., 6LD DFN pkg. a) MCP4726A0T-E/CH: 12-bit VOUT resolution, I2C Address “1100000”, Tape and Reel, Extended Temp., 6LD SOT-23 pkg. b) MCP4726A6T-E/CH: 12-bit VOUT resolution, I2C Address “1100110”, Tape and Reel, Extended Temp., 6LD SOT-23 pkg. c) MCP4726A0T-E/MAY: 12-bit VOUT resolution, I2C Address “1100000”, Tape and Reel, Extended Temp., 6LD DFN pkg. d) MCP4726A6T-E/MAY: 12-bit VOUT resolution, I2C Address “1100110”, Tape and Reel, Extended Temp., 6LD DFN pkg. DS22272C-page 83 MCP4706/4716/4726 NOTES: DS22272C-page 84 © 2011-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-161-8 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == © 2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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