IDT 23S09T

IDT23S09T
2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
COMMERCIAL TEMPERATURE RANGE
IDT23S09T
2.5V ZERO DELAY
CLOCK BUFFER, SPREAD
SPECTRUM COMPATIBLE
FEATURES:
DESCRIPTION:
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five and one bank of
four outputs
• Separate output enable for each output bank
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• No external RC network required
• Operates at 2.5V VDD
• Spread spectrum compatible
• Available in SOIC package
The IDT23S09T is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT23S09T is a 16-pin version of the IDT23S05T. The IDT23S09T
accepts one reference input, and drives two banks of four low skew clocks.
All parts have on-chip PLLs which lock to an input clock on the REF pin.
The PLL feedback is on-chip and is obtained from the CLKOUT pad. In
the absence of an input clock, the IDT23S09T enters power down, and
the outputs are tri-stated. In this mode, the device will draw less than 12µA.
FUNCTIONAL BLOCK DIAGRAM
16
1
2
PLL
CLKOUT
CLKA1
REF
3
CLKA2
14
CLKA3
15
S2
S1
CLKA4
8
9
Control
Logic
6
7
10
11
CLKB1
CLKB2
CLKB3
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
MAY 2010
1
c
2003 Integrated Device Technology, Inc.
DSC 6396/8
IDT23S09T
2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
REF
1
16
CLKOUT
CLKA1
2
15
CLKA4
CLKA2
3
14
CLKA3
VDD
4
13
VDD
GND
5
12
GND
CLKB1
6
Unit
Supply Voltage Range
Rating
–0.5 to +4.6
V
VI (2)
Input Voltage Range (REF)
–0.5 to +5.5
V
VI
Input Voltage Range
–0.5 to
V
(except REF)
Input Clamp Current
–50
mA
IO (VO = 0 to VDD)
Continuous Output Current
±50
mA
VDD or GND
Continuous Current
±100
mA
TA = 55°C
Maximum Power Dissipation
0.7
W
–65 to +150
°C
0 to +70
°C
CLKB4
CLKB3
TSTG
Storage Temperature Range
S1
Operating
Commercial Temperature
Temperature
Range
CLKB2
7
10
S2
8
9
(in still air)
(3)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
APPLICATIONS:
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
PIN DESCRIPTION
Pin Name
REF
(1)
CLKA1(2)
CLKA2
Pin Number
Type
Functional Description
1
IN
Input reference clock, 3.3V tolerant input
2
Out
Output clock for bank A
Output clock for bank A
3
Out
VDD
4, 13
PWR
GND
(2)
2.5V Supply
5, 12
GND
CLKB1(2)
6
Out
Output clock for bank B
CLKB2(2)
7
Out
Output clock for bank B
S2(3)
8
IN
Select input Bit 2
S1
Ground
9
IN
Select input Bit 1
CLKB3(2)
10
Out
Output clock for bank B
CLKB4(2)
11
Out
Output clock for bank B
CLKA3(2)
14
Out
Output clock for bank A
CLKA4
15
Out
Output clock for bank A
16
Out
Output clock, internal feedback on this pin
(3)
(2)
CLKOUT(2)
VDD+0.5
IIK (VI < 0)
11
SOIC
TOP VIEW
•
•
•
•
•
Max.
VDD
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
2
IDT23S09T
2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLE(1)
S2
S1
CLKA
CLKB
CLKOUT (2)
Output Source
PLL Shut Down
L
L
Tri-State
Tri-State
Driven
PLL
N
L
H
Driven
Tri-State
Driven
PLL
N
H
L
Driven
Driven
Driven
REF
Y
H
H
Driven
Driven
Driven
PLL
N
NOTES:
1. H = HIGH Voltage Level.
L = LOW Voltage Level
2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max.
Unit
VIL
Input LOW Voltage Level
—
0.7
V
VIH
Input HIGH Voltage Level
1.7
—
V
IIL
Input LOW Current
VIN = 0V
—
50
µA
IIH
Input HIGH Current
VIN = VDD
—
100
µA
VOL
Output LOW Voltage
Standard Drive, IOL = 8mA
—
0.3
V
VOH
Output HIGH Voltage
Standard Drive, IOH = -8mA
2
—
V
IDD_PD
Power Down Current
REF = 0MHz (S2 = S1 = H)
—
12
µA
Supply Current
Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND
—
32
mA
IDD
OPERATING CONDITIONS
Symbol
Parameter
Min.
Max.
Unit
2.3
2.7
V
Operating Temperature (Ambient Temperature)
0
70
°C
CL
Load Capacitance 10MHz - 133MHz
—
15
pF
CIN
Input Capacitance
—
7
pF
VDD
Supply Voltage
TA
SWITCHING CHARACTERISTICS
Symbol
t1
(1,2)
Parameter
Conditions
Min.
Typ.
Max.
Unit
Output Frequency
15pF Load
10
—
133
MHz
Duty Cycle = t2 ÷ t1
Measured at VDD/2, FOUT = 66.66MHz
40
50
60
%
t3
Rise Time
Measured between 0.7V and 1.7V
—
—
2.5
ns
t4
Fall Time
Measured between 0.7V and 1.7V
—
—
2.5
ns
All outputs equally loaded
—
—
250
ps
—
0
±350
ps
t5
Output to Output Skew
t6A
Delay, REF Rising Edge to CLKOUT Rising Edge(2) Measured at VDD/2
t6B
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2 in PLL bypass mode
1
5
8.7
ns
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
0
700
ps
tJ
Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
—
—
200
ps
PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
—
1
ms
tLOCK
(2)
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
3
IDT23S09T
2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
COMMERCIAL TEMPERATURE RANGE
ZERO DELAY AND SKEW CONTROL
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative
loading can affect and adjust the input/output delay.
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive
load equal to that on the other outputs in order to obtain true zero I/O Delay. For zero output-to-output skew, all outputs must be loaded equally.
SPREAD SPECTRUM COMPATIBLE
Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter
off the Spread Spectrum feature of the reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature
through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.
4
IDT23S09T
2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUIT
VDD
0.1 F
OUTPUTS
CLKOUT
CLOAD
VDD
0.1 F
GND
GND
Test Circuit for All Parameters
SWITCHING WAVEFORMS
t1
Output
t2
VDD/2
VDD/2
VDD/2
VDD/2
VDD/2
Output
t5
Output to Output Skew
Duty Cycle Timing
Output
0.7V
t3
1.7V 1.7V
0.7V
2.5V
VDD/2
REF
0V
t4
VDD/2
Output
t6
Input to Output Propagation Delay
All Outputs Rise/Fall Time
CLKOUT
Device 1
CLKOUT
Device 2
VDD/2
t7
VDD/2
Device to Device Skew
5
IDT23S09T
2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XXXXX
Device Type
XX
Package
X
Process
Blank
Commercial (0oC to +70oC)
DC
DCG
Small Outline
SOIC - Green
23S09T-1
2.5V Zero Delay Clock Buffer, Spread Spectrum Compatible
Part / Order Number
Shipping Packaging
Package
23S09T-1DCG
23S09T-1DCG8
Tubes
Tape and Reel
16-pin SOIC
16-pin SOIC
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
6
Temperature
0° to +70° C
0° to +70° C
for Tech Support:
clockhelp@idt.com