MF10 MF10 Universal Monolithic Dual Switched Capacitor Filter Literature Number: SNOS547B MF10 Universal Monolithic Dual Switched Capacitor Filter General Description The MF10 consists of 2 independent and extremely easy to use, general purpose CMOS active filter building blocks. Each block, together with an external clock and 3 to 4 resistors, can produce various 2nd order functions. Each building block has 3 output pins. One of the outputs can be configured to perform either an allpass, highpass or a notch function; the remaining 2 output pins perform lowpass and bandpass functions. The center frequency of the lowpass and bandpass 2nd order functions can be either directly dependent on the clock frequency, or they can depend on both clock frequency and external resistor ratios. The center frequency of the notch and allpass functions is directly dependent on the clock frequency, while the highpass center frequency depends on both resistor ratio and clock. Up to 4th order functions can be performed by cascading the two 2nd order building blocks of the MF10; higher than 4th order functions can be obtained by cascading MF10 packages. Any of the classical filter configurations (such as Butterworth, Bessel, Cauer and Chebyshev) can be formed. For pin-compatible device with improved performance refer to LMF100 datasheet. Features n Easy to use n Clock to center frequency ratio accuracy ± 0.6% n Filter cutoff frequency stability directly dependent on external clock quality n Low sensitivity to external component variation n Separate highpass (or notch or allpass), bandpass, lowpass outputs n fO x Q range up to 200 kHz n Operation up to 30 kHz n 20-pin 0.3" wide Dual-In-Line package n 20-pin Surface Mount (SO) wide-body package System Block Diagram 01039901 Package in 20 pin molded wide body surface mount and 20 pin molded DIP. © 2001 National Semiconductor Corporation DS010399 www.national.com MF10 Universal Monolithic Dual Switched Capacitor Filter May 2001 MF10 Absolute Maximum Ratings SO Package: (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V+ − V−) 215˚C Infrared (15 Sec.) 220˚C See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” (Appendix D) for other methods of soldering surface mount devices. 14V V+ + 0.3V Voltage at Any Pin Vapor Phase (60 Sec.) V− − 0.3V Input Current at Any Pin (Note 2) Operating Ratings (Note 1) 5 mA Package Input Current (Note 2) 20 mA Power Dissipation (Note 3) Storage Temperature 150˚C ESD Susceptability (Note 11) 2000V Soldering Information N Package: 10 sec 260˚C TMIN ≤ TA ≤ TMAX Temperature Range 500 mW MF10ACN, MF10CCN 0˚C ≤ TA ≤ 70˚C MF10CCWM 0˚C ≤ TA ≤ 70˚C Electrical Characteristics V+ = +5.00V and V− = −5.00V unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25˚C. MF10ACN, MF10CCN, MF10CCWM Symbol Parameter Conditions V+ − V− Supply Voltage IS Maximum Supply Clock Applied to Pins 10 & 11 Current No Input Signal Typical Tested Design (Note 8) Limit Limit (Note 9) (Note 10) Min Max fO x Q < 200 kHz 12 V 14 V 12 mA 0.2 Hz kHz Center Frequency Range Max 30 20 fCLK Clock Frequency Min 5.0 10 Hz Range Max 1.5 1.0 MHz 50:1 Clock to Center Frequency Ratio Deviation MF10A 100:1 Clock to Center Frequency Ratio Deviation MF10A fCLK/fO MF10C MF10C Q = 10 Mode 1 Q = 10 Mode 1 0.1 9 fO fCLK/fO Min 8 Units Vpin12 = 5V fCLK = 250 KHz ± 0.2 ± 0.6 ± 0.6 % ± 0.2 ± 1.5 ± 1.5 % Vpin12 = 0V fCLK = 500 kHz ± 0.2 ± 0.6 ± 0.6 % ± 0.2 ± 1.5 ± 1.5 % Clock Feedthrough Q = 10 Mode 1 Q Error (MAX) Q = 10 Vpin12 = 5V (Note 4) Mode 1 fCLK = 250 kHz 10 Vpin12 = 0V mV ±2 ±6 ±6 % ±2 ±6 ±6 % 0 ± 5.0 ± 0.2 ± 20 ± 0.2 ± 20 mV −150 −185 −185 mV fCLK = 500 kHz HOLP DC Lowpass Gain VOS1 DC Offset Voltage (Note 5) VOS2 DC Offset Voltage www.national.com Mode 1 R1 = R2 = 10k Min Vpin12 = +5V 2 SA/B = V+ dB (Continued) V+ = +5.00V and V− = −5.00V unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25˚C. MF10ACN, MF10CCN, MF10CCWM Symbol Parameter (Note 5) VOS3 DC Offset Voltage (Note 5) VOS2 Conditions Max (fCLK/fO = 50) Min Vpin12 = +5V Max (fCLK/fO = 50) Min Vpin12 = +5V Max (fCLK/fO = 50) DC Offset Voltage Vpin12 = 0V (Note 5) (fCLK/fO = 100) Vpin12 = 0V Typical Tested Design (Note 8) Limit Limit (Note 9) (Note 10) −85 −85 SA/B = V− −70 All Modes −70 Units mV −100 −100 −20 −20 mV SA/B = V+ −300 mV SA/B = V− −140 mV All Modes −140 mV (fCLK/fO = 100) VOS3 VOUT DC Offset Voltage Vpin12 = 0V (Note 5) (fCLK/fO = 100) Minimum Output BP, LP Pins RL = 5k Voltage Swing N/AP/HP Pin RL = 3.5k GBW Op Amp Gain BW Product SR Op Amp Slew Rate Dynamic Range(Note 6) ± 4.25 ± 4.25 Vpin12 = +5V (fCLK/fO = 50) Vpin12 = 0V (fCLK/fO = 100) ISC ± 3.8 ± 3.8 ± 3.8 ± 3.8 V V 2.5 MHz 7 V/µs 83 dB 80 dB Maximum Output Short Source 20 mA Circuit Current (Note 7) Sink 3.0 mA Logic Input Characteristics Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25˚C MF10ACN, MF10CCN, MF10CCWM Parameter Conditions Typical (Note 8) CMOS Clock Input Voltage Min Logical “1” Tested Design Units Limit Limit (Note 9) (Note 10) V+ = +5V, V− = −5V, +3.0 +3.0 V V Max Logical “0” VLSh = 0V −3.0 −3.0 Min Logical “1” V+ = +10V, V− = 0V, +8.0 +8.0 V Max Logical “0” VLSh = +5V +2.0 +2.0 V TTL Clock Min Logical “1” V+ = +5V, V− = −5V, +2.0 +2.0 V Input Voltage Max Logical “0” VLSh = 0V +0.8 +0.8 V 3 www.national.com MF10 Electrical Characteristics MF10 Logic Input Characteristics (Continued) Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25˚C MF10ACN, MF10CCN, MF10CCWM Parameter Conditions Typical Tested Design (Note 8) Limit Limit (Note 9) (Note 10) Units Min Logical “1” V+ = +10V, V− = 0V, +2.0 +2.0 V Max Logical “0” VLSh = 0V +0.8 +0.8 V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V− or VIN > V+) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJMAX = 125˚C, and the typical junction-to-ambient thermal resistance of the MF10ACN/CCN when board mounted is 55˚C/W. For the MF10AJ/CCJ, this number increases to 95˚C/W and for the MF10ACWM/CCWM this number is 66˚C/W. Note 4: The accuracy of the Q value is a function of the center frequency (fO). This is illustrated in the curves under the heading “Typical Performance Characteristics”. Note 5: VOS1, VOS2, and VOS3 refer to the internal offsets as discussed in the Applications Information Section 3.4. Note 6: For ± 5V supplies the dynamic range is referenced to 2.82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 µV rms for the MF10 with a 50:1 CLK ratio and 280 µV rms for the MF10 with a 100:1 CLK ratio. Note 7: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions. Note 8: Typicals are at 25˚C and represent most likely parametric norm. Note 9: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Note 11: Human body model, 100 pF discharged through a 1.5 kΩ resistor. www.national.com 4 MF10 Typical Performance Characteristics Positive Output Voltage Swing vs. Load Resistance (N/AP/HP Output) Power Supply Current vs. Power Supply Voltage 01039935 01039934 Negative Output Voltage Swing vs. Load Resistance (N/AP/HP Output) Negative Output Swing vs. Temperature 01039936 01039937 Positive Output Swing vs. Temperature Crosstalk vs. Clock Frequency 01039939 01039938 5 www.national.com MF10 Typical Performance Characteristics (Continued) Q Deviation vs. Temperature Q Deviation vs. Temperature 01039941 01039940 Q Deviation vs. Clock Frequency Q Deviation vs. Clock Frequency 01039942 01039943 fCLK/fO Deviation vs. Temperature fCLK/fO Deviation vs. Temperature 01039944 www.national.com 01039945 6 MF10 Typical Performance Characteristics (Continued) fCLK/fO Deviation vs. Clock Frequency fCLK/fO Deviation vs. Clock Frequency 01039946 01039947 Deviation of fCLK/fO vs. Nominal Q Deviation of fCLK/fO vs. Nominal Q 01039948 01039949 7 www.national.com MF10 Pin Descriptions LP(1,20), BP(2,19), N/AP/HP(3,18) The second order lowpass, bandpass and notch/allpass/highpass outputs. These outputs can typically sink 1.5 mA and source 3 mA. Each output typically swings to within 1V of each supply. INV(4,17) The inverting input of the summing op-amp of each filter. These are high impedance inputs, but the non-inverting input is internally tied to AGND, making INVA and INVB behave like summing junctions (low impedance, current inputs). S1(5,16) S1 is a signal input pin used in the allpass filter configurations (see modes 4 and 5). The pin should be driven with a source impedance of less than 1 kΩ. If S1 is not driven with a signal it should be tied to AGND (mid-supply). SA/B(6) This pin activates a switch that connects one of the inputs of each filter’s second summer to either AGND (SA/B tied to V−) or to the lowpass (LP) output (SA/B tied to V+). This offers the flexibility needed for configuring the filter in its various modes of operation. VA+(7),VD+(8) Analog positive supply and digital positive supply. These pins are internally connected through the IC substrate and therefore VA+ and VD+ should be derived from the same power supply source. They have been brought out separately so they can be bypassed by separate capacitors, if desired. They can be externally tied together and bypassed by a single capacitor. VA−(14), VD−(13) Analog and digital negative supplies. The same comments as for VA+ and VD+ apply here. LSh(9) Level shift pin; it accommodates various clock levels with dual or single supply operation. With dual ± 5V supplies, the MF10 can be driven with CMOS clock levels ( ± 5V) and the LSh pin should be tied to the system ground. If the same supplies as above are used CLKA(10), 50/100/CL(12) AGND(15) but only TTL clock levels, derived from 0V to +5V supply, are available, the LSh pin should be tied to the system ground. For single supply operation (0V and +10V) the VA−, VD−pins should be connected to the system ground, the AGND pin should be biased at +5V and the LSh pin should also be tied to the system ground for TTL clock levels. LSh should be biased at +5V for CMOS clock levels in 10V single-supply applications. CLKB(11) Clock inputs for each switched capacitor filter building block. They should both be of the same level (TTL or CMOS). The level shift (LSh) pin description discusses how to accommodate their levels. The duty cycle of the clock should be close to 50% especially when clock frequencies above 200 kHz are used. This allows the maximum time for the internal op-amps to settle, which yields optimum filter operation. By tying this pin high a 50:1 clock-to-filter-center-frequency ratio is obtained. Tying this pin at mid-supplies (i.e. analog ground with dual supplies) allows the filter to operate at a 100:1 clock-to-center-frequency ratio. When the pin is tied low (i.e., negative supply with dual supplies), a simple current limiting circuit is triggered to limit the overall supply current down to about 2.5 mA. The filtering action is then aborted. This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to mid-supply for single supply operation. For a further discussion of mid-supply biasing techniques see the Applications Information (Section 3.2). For optimum filter performance a “clean” ground must be provided. 1.0 Definition of Terms the −3 dB bandwidth of the 2nd order bandpass filter (Figure 1). The value of Q determines the shape of the 2nd order filter responses as shown in Figure 6. QZ: the quality factor of the second order complex zero pair, if any. QZ is related to the allpass characteristic, which is written: fCLK: the frequency of the external clock signal applied to pin 10 or 11. fO: center frequency of the second order function complex pole pair. fO is measured at the bandpass outputs of the MF10, and is the frequency of maximum bandpass gain. (Figure 1) fnotch: the frequency of minimum (ideally zero) gain at the notch outputs. fz: the center frequency of the second order complex zero pair, if any. If fz is different from fO and if QZ is high, it can be observed as the frequency of a notch at the allpass output. (Figure 10) Q: “quality factor” of the 2nd order filter. Q is measured at the bandpass outputs of the MF10 and is equal to fO divided by www.national.com where QZ = Q for an all-pass response. HOBP: the gain (in V/V) of the bandpass output at f = fO. 8 below the center frequency (Figure 4). When the low-frequency gain differs from the high-frequency gain, as in modes 2 and 3a (Figure 11 and Figure 8), the two quantities below are used in place of HON. HON1: the gain (in V/V) of the notch output as f → 0 Hz. (Continued) HOLP: the gain (in V/V) of the lowpass output as f → 0 Hz (Figure 2). HOHP: the gain (in V/V) of the highpass output as f → fCLK/2 (Figure 3). HON: the gain (in V/V) of the notch output as f → 0 Hz and as f → fCLK/2, when the notch filter has equal gain above and HON2: the gain (in V/V) of the notch output as f → fCLK/2. 01039905 (a) 01039906 (b) 01039956 FIGURE 1. 2nd-Order Bandpass Response 9 www.national.com MF10 1.0 Definition of Terms MF10 1.0 Definition of Terms (Continued) 01039907 (a) 01039908 (b) 01039957 FIGURE 2. 2nd-Order Low-Pass Response www.national.com 10 MF10 1.0 Definition of Terms (Continued) 01039909 (a) 01039910 (b) 01039958 FIGURE 3. 2nd-Order High-Pass Response 11 www.national.com MF10 1.0 Definition of Terms (Continued) 01039911 (a) 01039912 (b) 01039960 FIGURE 4. 2nd-Order Notch Response www.national.com 12 MF10 1.0 Definition of Terms (Continued) 01039913 (a) 01039914 (b) 01039961 FIGURE 5. 2nd-Order All-Pass Response 13 www.national.com MF10 1.0 Definition of Terms (Continued) (a) Bandpass (b) Low Pass 01039950 (c) High-Pass 01039952 01039951 (d) Notch (e) All-Pass 01039954 01039953 FIGURE 6. Response of various 2nd-order filters as a function of Q. Gains and center frequencies are normalized to unity. 2.0 Modes of Operation The MF10 is a switched capacitor (sampled data) filter. To fully describe its transfer functions, a time domain approach is appropriate. Since this is cumbersome, and since the MF10 closely approximates continuous filters, the following discussion is based on the well known frequency domain. Each MF10 can produce a full 2nd order function. See Table 1 for a summary of the characteristics of the various modes. MODE 1: Notch 1, Bandpass, Lowpass Outputs: fnotch = fO (See Figure 7) = quality factor of the complex pole pair BW = the −3 dB bandwidth of the bandpass output. Circuit dynamics: fO = center frequency of the complex pole pair MODE 1a: Non-Inverting BP, LP (See Figure 8) fnotch = center frequency of the imaginary zero pair = fO. Note: VIN should be driven from a low impedance ( < 1 kΩ) source. www.national.com 14 MF10 2.0 Modes of Operation (Continued) 01039916 FIGURE 7. MODE 1 01039917 FIGURE 8. MODE 1a MODE 2: Notch 2, Bandpass, Lowpass: fnotch < fO (See Figure 9) MODE 3: Highpass, Bandpass, Lowpass Outputs (See Figure 10) 15 www.national.com MF10 2.0 Modes of Operation (Continued) 01039918 FIGURE 9. MODE 2 01039919 *In Mode 3, the feedback loop is closed around the input summing amplifier; the finite GBW product of this op amp causes a slight Q enhancement. If this is a problem, connect a small capacitor (10 pF − 100 pF) across R4 to provide some phase lead. FIGURE 10. MODE 3 www.national.com 16 MODE 4: Allpass, Bandpass, Lowpass Outputs(See Figure 12) (Continued) MODE 3a: HP, BP, LP and Notch with External Op Amp (See Figure 11) *Due to the sampled data nature of the filter, a slight mismatch of fz and fO occurs causing a 0.4 dB peaking around fO of the allpass filter amplitude response (which theoretically should be a straight line). If this is unacceptable, Mode 5 is recommended. 01039920 FIGURE 11. MODE 3a 17 www.national.com MF10 2.0 Modes of Operation MF10 2.0 Modes of Operation (Continued) 01039921 FIGURE 12. MODE 4 MODE 6a: Single Pole, HP, LP Filter (See Figure 14) MODE 5: Numerator Complex Zeros, BP, LP (See Figure 13) MODE 6b: Single Pole LP Filter (Inverting and Non-Inverting) (See Figure 15) 01039922 FIGURE 13. MODE 5 www.national.com 18 MF10 2.0 Modes of Operation (Continued) 01039923 FIGURE 14. MODE 6a 01039924 FIGURE 15. MODE 6b TABLE 1. Summary of Modes. Realizable filter types (e.g. low-pass) denoted by asterisks. Unless otherwise noted, gains of various filter outputs are inverting and adjustable by resistor ratios. Mode 1 BP * LP HP * N AP Number of * Adjustable Resistors fCLK/fO 3 No 2 No (2) 1a HOBP1 = −Q May need input buffer. HOLP + 1 HOBP2 = +1 Poor dynamics for high Q. * * * * * * * * 4 * * * 3 5 * * * 4 2 Notes * 3 Yes (above fCLK/50 or fCLK/100) 3 3a 4 Yes Universal State-Variable 7 Yes As above, but also includes Filter. Best general-purpose mode. * resistor-tuneable notch. No Gives Allpass response with HOAP = −1 and HOLP = −2. Gives flatter allpass response than above if R1 = R2 = 0.02R4. 6a 6b * * 3 Single pole. 2 Single pole. 19 www.national.com MF10 3.0 Applications Information The MF10 is a general-purpose dual second-order state variable filter whose center frequency is proportional to the frequency of the square wave applied to the clock input (fCLK). By connecting pin 12 to the appropriate DC voltage, the filter center frequency fO can be made equal to either fCLK/100 or fCLK/50. fO can be very accurately set (within ± 6%) by using a crystal clock oscillator, or can be easily varied over a wide frequency range by adjusting the clock frequency. If desired, the fCLK/fO ratio can be altered by external resistors as in Figures 9, 10, 11, 13, 14, 15. The filter Q and gain are determined by external resistors. All of the five second-order filter types can be built using either section of the MF10. These are illustrated in Figure 1 through Figure 5 along with their transfer functions and some related equations. Figure 6 shows the effect of Q on the shapes of these curves. When filter orders greater than two are desired, two or more MF10 sections can be cascaded. externally. From Table 1, we see that Mode 3 can be used to produce a low-pass filter with resistor-adjustable center frequency. In most filter designs involving multiple second-order stages, it is best to place the stages with lower Q values ahead of stages with higher Q, especially when the higher Q is greater than 0.707. This is due to the higher relative gain at the center frequency of a higher-Q stage. Placing a stage with lower Q ahead of a higher-Q stage will provide some attenuation at the center frequency and thus help avoid clipping of signals near this frequency. For this example, stage A has the lower Q (0.785) so it will be placed ahead of the other stage. For the first section, we begin the design by choosing a convenient value for the input resistance: R1A = 20k. The absolute value of the passband gain HOLPA is made equal to 1 by choosing R4A such that: R4A = −HOLPAR1A = R1A = 20k. If the 50/100/CL pin is connected to mid-supply for nominal 100:1 clock-to-center-frequency ratio, we find R2A by: 3.1 DESIGN EXAMPLE In order to design a second-order filter section using the MF10, we must define the necessary values of three parameters: f0, the filter section’s center frequency; H0, the passband gain; and the filter’s Q. These are determined by the characteristics required of the filter being designed. As an example, let’s assume that a system requires a fourth-order Chebyshev low-pass filter with 1 dB ripple, unity gain at DC, and 1000 Hz cutoff frequency. As the system order is four, it is realizable using both second-order sections of an MF10. Many filter design texts include tables that list the characteristics (fO and Q) of each of the second-order filter sections needed to synthesize a given higher-order filter. For the Chebyshev filter defined above, such a table yields the following characteristics: f0A = 529 Hz QA = 0.785 f0B = 993 Hz QB = 3.559 The resistors for the second section are found in a similar fashion: For unity gain at DC, we also specify: H0A = 1 H0B = 1 The desired clock-to-cutoff-frequency ratio for the overall filter of this example is 100 and a 100 kHz clock signal is available. Note that the required center frequencies for the two second-order sections will not be obtainable with clock-to-center-frequency ratios of 50 or 100. It will be necessary to adjust www.national.com The complete circuit is shown in Figure 16 for split ± 5V power supplies. Supply bypass capacitors are highly recommended. 20 MF10 3.0 Applications Information (Continued) 01039925 FIGURE 16. Fourth-Order Chebyshev Low-Pass Filter from Example in 3.1. ± 5V Power Supply. 0V–5V TTL or −5V ± 5V CMOS Logic Levels. 01039926 FIGURE 17. Fourth-Order Chebyshev Low-Pass Filter from Example in 3.1. Single +10V Power Supply. 0V–5V TTL Logic Levels. Input Signals Should be Referred to Half-Supply or Applied through a Coupling Capacitor. 21 www.national.com MF10 3.0 Applications Information (Continued) 01039927 (a) Resistive Divider with Decoupling Capacitor 01039928 (b) Voltage Regulator 01039929 (c) Operational Amplifier with Divider FIGURE 18. Three Ways of Generating V+/2 for Single-Supply Operation www.national.com 22 MF10 3.0 Applications Information Vos1 = opamp offset = ± 5 mV (Continued) 3.2 SINGLE SUPPLY OPERATION The MF10 can also operate with a single-ended power supply. Figure 17 shows the example filter with a single-ended power supply. VA+ and VD+ are again connected to the positive power supply (8V to 14V), and VA− and VD− are connected to ground. The AGND pin must be tied to V+/2 for single supply operation. This half-supply point should be very “clean”, as any noise appearing on it will be treated as an input to the filter. It can be derived from the supply voltage with a pair of resistors and a bypass capacitor (Figure 18a), or a low-impedance half-supply voltage can be made using a three-terminal voltage regulator or an operational amplifier (Figure 18b and Figure 18c). The passive resistor divider with a bypass capacitor is sufficient for many applications, provided that the time constant is long enough to reject any power supply noise. It is also important that the half-supply reference present a low impedance to the clock frequency, so at very low clock frequencies the regulator or op-amp approaches may be preferable because they will require smaller capacitors to filter the clock frequency. The main power supply voltage should be clean (preferably regulated) and bypassed with 0.1 µF. Vos2 = −150 mV @ 50:1: −300 mV @ 100:1 Vos3 = −70 mV @ 50:1: −140 mV @ 100:1 When SA/B is tied to V−, Vos2 will approximately halve. The DC offset at the BP output is equal to the input offset of the lowpass integrator (Vos3). The offsets at the other outputs depend on the mode of operation and the resistor ratios, as described in the following expressions. 3.3 DYNAMIC CONSIDERATIONS The maximum signal handling capability of the MF10, like that of any active filter, is limited by the power supply voltages used. The amplifiers in the MF10 are able to swing to within about 1V of the supplies, so the input signals must be kept small enough that none of the outputs will exceed these limits. If the MF10 is operating on ± 5V, for example, the outputs will clip at about 8 Vp–p. The maximum input voltage multiplied by the filter gain should therefore be less than 8 Vp–p. Note that if the filter Q is high, the gain at the lowpass or highpass outputs will be much greater than the nominal filter gain (Figure 6). As an example, a lowpass filter with a Q of 10 will have a 20 dB peak in its amplitude response at fO. If the nominal gain of the filter HOLP is equal to 1, the gain at fO will be 10. The maximum input signal at fO must therefore be less than 800 mVp–p when the circuit is operated on ± 5V supplies. Also note that one output can have a reasonable small voltage on it while another is saturated. This is most likely for a circuit such as the notch in Mode 1 (Figure 7). The notch output will be very small at fO, so it might appear safe to apply a large signal to the input. However, the bandpass will have its maximum gain at fO and can clip if overdriven. If one output clips, the performance at the other outputs will be degraded, so avoid overdriving any filter section, even ones whose outputs are not being directly used. Accompanying Figure 7 through Figure 15 are equations labeled “circuit dynamics”, which relate the Q and the gains at the various outputs. These should be consulted to determine peak circuit gains and maximum allowable signals for a given application. 3.4 OFFSET VOLTAGE The MF10’s switched capacitor integrators have a higher equivalent input offset voltage than would be found in a typical continuous-time active filter integrator. Figure 19 shows an equivalent circuit of the MF10 from which the output DC offsets can be calculated. Typical values for these offsets with SA/B tied to V+ are: 23 www.national.com MF10 3.0 Applications Information (Continued) 01039930 FIGURE 19. MF10 Offset Voltage Sources 01039931 FIGURE 20. Method for Trimming VOS For most applications, the outputs are AC coupled and DC offsets are not bothersome unless large signals are applied www.national.com to the filter input. However, larger offset voltages will cause clipping to occur at lower AC signal levels, and clipping at 24 can be reduced or eliminated by limiting the input signal spectrum to less than fs/2. This may in some cases require the use of a bandwidth-limiting filter ahead of the MF10 to limit the input spectrum. However, since the clock frequency is much higher than the center frequency, this will often not be necessary. (Continued) any of the outputs will cause gain nonlinearities and will change fO and Q. When operating in Mode 3, offsets can become excessively large if R2 and R4 are used to make fCLK/fO significantly higher than the nominal value, especially if Q is also high. An extreme example is a bandpass filter having unity gain, a Q of 20, and fCLK/fO = 250 with pin 12 tied to ground (100:1 nominal). R4/R2 will therefore be equal to 6.25 and the offset voltage at the lowpass output will be about +1V. Where necessary, the offset voltage can be adjusted by using the circuit of Figure 20. This allows adjustment of VOS1, which will have varying effects on the different outputs as described in the above equations. Some outputs cannot be adjusted this way in some modes, however (VOS(BP) in modes 1a and 3, for example). Another characteristic of sampled-data circuits is that the output signal changes amplitude once every sampling period, resulting in “steps” in the output voltage which occur at the clock rate (Figure 21). If necessary, these can be “smoothed” with a simple R–C low-pass filter at the MF10 output. The ratio of fCLK to fC (normally either 50:1 or 100:1) will also affect performance. A ratio of 100:1 will reduce any aliasing problems and is usually recommended for wideband input signals. In noise sensitive applications, however, a ratio of 50:1 may be better as it will result in 3 dB lower output noise. The 50:1 ratio also results in lower DC offset voltages, as discussed in Section 3.4. The accuracy of the fCLK/fO ratio is dependent on the value of Q. This is illustrated in the curves under the heading “Typical Performance Characteristics”. As Q is changed, the true value of the ratio changes as well. Unless the Q is low, the error in fCLK/fO will be small. If the error is too large for a specific application, use a mode that allows adjustment of the ratio with external resistors. It should also be noted that the product of Q and fOshould be limited to 300 kHz when fO < 5 kHz, and to 200 kHz for fO > 5 kHz. 3.5 SAMPLED DATA SYSTEM CONSIDERATIONS The MF10 is a sampled data filter, and as such, differs in many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect on signals at frequencies greater than one-half the sampling frequency. (The MF10’s sampling frequency is the same as its clock frequency.) If a signal with a frequency greater than one-half the sampling frequency is applied to the input of a sampled data system, it will be “reflected” to a frequency less than one-half the sampling frequency. Thus, an input signal whose frequency is fs/2 + 100 Hz will cause the system to respond as though the input frequency was fs/2 − 100 Hz. This phenomenon is known as “aliasing”, and 01039932 FIGURE 21. The Sampled-Data Output Waveform 25 www.national.com MF10 3.0 Applications Information MF10 3.0 Applications Information (Continued) Connection Diagram Surface Mount and Dual-In-Line Package 01039904 Top View Order Number MF10CCWM See NS Package Number M20B Order Number MF10ACN or MF10CCN See NS Package Number N20A www.national.com 26 MF10 Physical Dimensions inches (millimeters) unless otherwise noted Molded Package (Small Outline) (M) Order Number MF10ACWM or MF10CCWM NS Package Number M20B 20-Lead Molded Dual-In-Line Package (N) Order Number MF10ACN or MF10CCN NS Package Number N20A 27 www.national.com MF10 Universal Monolithic Dual Switched Capacitor Filter Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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