STL8N80K5 N-channel 800 V, 0.80 Ω typ., 4.5 A Zener-protected SuperMESH™ 5 Power MOSFET in a PowerFLAT™ 5x6 VHV package Datasheet − production data Features Order code VDS RDS(on)max. ID STL8N80K5 800 V 0.95 Ω 4.5 A • Outstanding RDS(on)*area 1 • Worldwide best FOM (figure of merit) 2 • Ultra low gate charge 3 4 • 100% avalanche tested PowerFLAT™ 5x6 VHV • Zener protected Applications • Switching applications Figure 1. Internal schematic diagram D(5, 6, 7, 8) 8 7 5 6 G(4) 1 S(1, 2, 3) 2 3 4 Description This N-channel Zener-protected Power MOSFET is designed using ST's revolutionary avalancherugged very high voltage SuperMESH™ 5 technology, based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance, and ultra-low gate charge for applications which require superior power density and high efficiency. Top View AM15540v1 Table 1. Device summary Order code Marking Package Packaging STL8N80K5 8N80K5 PowerFLAT™ 5x6 VHV Tape and reel November 2013 This is information on a product in full production. DocID024079 Rev 3 1/17 www.st.com 17 Contents STL8N80K5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/17 .............................................. 9 DocID024079 Rev 3 STL8N80K5 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit Gate-source voltage ± 30 V ID (1) Drain current (continuous) at TC = 25 °C 4.5 A ID (1) Drain current (continuous) at TC = 100 °C 3 A 18 A Total dissipation at TC = 25 °C 42 W IAR(3) Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) 2 A EAS(4) Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 114 mJ Peak diode recovery voltage slope 4.5 V/ns MOSFET dv/dt ruggedness 50 V/ns VGS IDM (1),(2) Drain current (pulsed) PTOT(1) dv/dt (5) dv/dt (6) Tstg Tj Storage temperature °C - 55 to 150 Max. operating junction temperature °C 1. The value is rated according to Rthj-case and limited by package. 2. Pulse width limited by safe operating area. 3. Pulse width limited by Tjmax 4. Starting Tj=25 °C, ID=IAR, VDD=50 V 5. ISD ≤ 4.5 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS 6. VDS ≤ 640 V Table 3. Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 3 °C/W Rthj-amb(1) Thermal resistance junction-amb max 59 °C/W 1. When mounted on 1inch² FR-4 board, 2 oz Cu. DocID024079 Rev 3 3/17 Electrical characteristics 2 STL8N80K5 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage (VGS = 0) Test conditions ID = 1 mA IDSS VDS = 800 V Zero gate voltage drain current (VGS = 0) VDS = 800 V, TC=125 °C IGSS Gate-body leakage current (VDS = 0) Min. Typ. Max. Unit 800 V 1 µA 50 µA ± 10 µA 4 5 V 0.80 0.95 Ω Min. Typ. Max. Unit - 450 - pF - 50 - pF - 1 - pF - 57 - pF - 24 - pF f = 1 MHz, ID=0 - 6 - Ω VDD = 640 V, ID = 6 A, VGS = 10 V (see Figure 16) - 16.5 - nC - 3.2 - nC - 11 - nC VGS = ± 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on) Static drain-source onVGS = 10 V, ID = 3 A resistance 3 Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Equivalent capacitance time related Co(er)(2) Equivalent capacitance energy related RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 VDS = 0 to 640 V, VGS = 0 1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 2. Coss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/17 DocID024079 Rev 3 STL8N80K5 Electrical characteristics Table 6. Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time VDD = 400 V, ID = 3 A, RG = 4.7 W, VGS = 10 V (see Figure 15), (see Figure 20) Rise time Turn-off delay time Fall time Min. Typ. Max Unit - 12 - ns - 14 - ns - 32 - ns - 20 - ns Min. Typ. Table 7. Source drain diode Symbol ISD ISDM VSD(1) trr Parameter Test conditions Max. Unit Source-drain current - 4.5 A Source-drain current (pulsed) - 18 A - 1.5 V ISD = 6 A, VGS = 0 Forward on voltage Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 6 A, di/dt = 100 A/µs VDD = 60 V (see Figure 17) ISD = 6 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 17) - 300 ns - 3 µC - 20 A - 415 ns - 3.8 µC - 18 A Min Typ. Max Unit 30 - - V 1. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol Parameter Test conditions V(BR)GSO Gate-source breakdown voltage IGS= ± 1mA, ID=0 The built-in back-to-back Zener diodes have been specifically designed to enhance not only the device's ESD capability, but also to make them capable of safely absorbing any voltage transients that may occasionally be applied from gate to source. In this respect, the Zener voltage is appropriate to achieve efficient and cost-effective protection of device integrity. The integrated Zener diodes thus eliminate the need for external components. DocID024079 Rev 3 5/17 Electrical characteristics 2.1 STL8N80K5 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM15762v1 ID (A) ZthPowerFlat_5x6_27 K δ=0.5 0.2 10 10µs s ai re n) s a DS(o i th R in ax n io y m t b a er ed Op mit Li 1 0.02 1ms 10ms Tj=150°C Tc=25°C Single pulse 10 0.01 pcb 10 -2 Single pulse 10 -3 10 -5 0.01 1 0.05 100µs 0.1 0.1 0.1 10 -1 VDS(V) 100 Figure 4. Output characteristics 10 -4 10 -3 10 0 10 -2 10 -1 10 1 tp(s) Figure 5. Transfer characteristics AM15633v1 ID (A) AM15634v1 ID (A) VGS=10, 11V 12 VDS=20V 12 9V 10 10 8 8 8V 6 6 4 4 7V 2 2 6V 0 0 4 8 12 16 0 VDS(V) Figure 6. Gate charge vs gate-source voltage VGS (V) VDS AM15635v1 VDS VDD=640V ID=6A 12 (V) 600 10 500 8 400 6 300 4 200 2 100 5 6 7 8 9 10 VGS(V) Figure 7. Static drain-source on-resistance AM15636v1 RDS(on) (Ω) VGS=10V 1.6 1.2 0.8 0.4 0 0 6/17 4 8 12 16 0 Qg(nC) DocID024079 Rev 3 0 1 2 3 4 5 6 ID(A) STL8N80K5 Electrical characteristics Figure 8. Capacitance variations Figure 9. Output capacitance stored energy AM15637v1 C (pF) AM15638v1 Eoss (µJ) 1000 6 Ciss 100 4 Coss 2 10 Crss 1 0.1 1 100 10 Figure 10. Normalized gate threshold voltage vs. temperature AM15639v1 VGS(th) (norm) 0 0 VDS(V) ID=100µA VDS=VGS 200 400 600 VDS(V) Figure 11. Normalized on-resistance vs. temperature AM15640v1 RDS(on) (norm) VGS=10V ID=3 A 2.4 1 2 1.6 0.8 1.2 0.6 0.8 0.4 -50 50 0 TJ(°C) 100 Figure 12. Drain-source diode forward characteristics AM15641v1 VSD (V) TJ=-50°C 0.4 -50 0 TJ(°C) AM15642v1 VDS (norm) ID = 1mA 1.06 TJ=25°C 0.8 100 Figure 13. Normalized VDS vs. temperature 1.1 0.9 50 1.02 0.7 0.98 TJ=150°C 0.6 0.5 1 0.94 0.9 2 3 4 5 ISD(A) DocID024079 Rev 3 -50 0 50 100 TJ(°C) 7/17 Electrical characteristics STL8N80K5 Figure 14. Maximum avalanche energy vs. starting TJ AM15643v1 EAS (mJ) VDD=50V ID=2A 100 80 60 40 20 0 0 8/17 40 80 120 TJ(°C) DocID024079 Rev 3 STL8N80K5 3 Test circuits Test circuits Figure 15. Switching times test circuit for resistive load Figure 16. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 17. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 18. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 0 DocID024079 Rev 3 10% AM01473v1 9/17 Package mechanical data 4 STL8N80K5 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/17 DocID024079 Rev 3 STL8N80K5 Package mechanical data Table 9. PowerFLAT™ 5x6 VHV mechanical data mm. DIM min. typ. max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 D 5.00 5.20 5.40 E 5.95 6.15 6.35 D2 4.30 4.40 4.50 E2 2.40 2.50 2.60 e 0.50 1.27 L 0.50 0.55 0.60 K 2.60 2.70 2.80 aaa 0.15 bbb 0.15 ccc 0.10 eee 0.10 DocID024079 Rev 3 11/17 Package mechanical data STL8N80K5 Figure 21. PowerFLAT™ 5x6 VHV Bottom view Side view Top view 8368144_REV_B 12/17 DocID024079 Rev 3 STL8N80K5 Package mechanical data Figure 22. PowerFLAT™ 5x6 VHV (dimensions are in mm) 8368144_REV_B_footprint DocID024079 Rev 3 13/17 Packaging mechanical data 5 STL8N80K5 Packaging mechanical data Figure 23. PowerFLAT™ 5x6 tape P0 4.0±0.1 (II) P2 2.0±0.1 (I) T (0.30 ±0.05) E1 1.75±0.1 Y 0. 20 Do Ø1.55±0.05 W(12.00±0.3) F(5.50±0.1)(III) R Bo (5.30±0.1) C L EF D1 Ø1.5 MIN. REF .R0 .50 Y P1(8.00±0.1) Ao(6.30±0.1) Ko (1.20±0.1) SECTION Y-Y (I) Measured from centerline of sprocket hole to centerline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ± 0.20 . Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centerline of sprocket hole to centerline of pocket. 8234350_Tape_rev_C Figure 24. PowerFLAT™ 5x6 package orientation in carrier tape. Pin 1 identification 14/17 DocID024079 Rev 3 STL8N80K5 Packaging mechanical data Figure 25. PowerFLAT™ 5x6 reel R0.60 W3 11.9/15.4 PART NO. 1.90 2.50 R25.00 ØN 178(±2.0) ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES W2 18.4 (max) A 330 (+0/-4.0) 4.00 2.50 77 ESD LOGO W1 12.4 (+2/-0) 06 PS ØA 128 2.20 R1.10 Ø21.2 All dimensions are in millimeters 13.00 CORE DETAIL 8234350_Reel_rev_C DocID024079 Rev 3 15/17 Revision history 6 STL8N80K5 Revision history Table 10. Document revision history 16/17 Date Revision Changes 18-Dec-2012 1 First release. 22-Apr-2013 2 – Deleted: VDS, drain current (continuous) at Tamb = 25 °C and Tamb = 100 °C, total dissipation at Tamb = 25 °C in Table 2 – Modified: PTOT, IAR and EAS values in Table 2 – Added: MOSFET dv/dt ruggedness parameter and note 6 in Table 2 – Modified: values in Table 3, RDS(on) typ in Table 4, the entire typical values in Table 5, 6 and 7 – Inserted: Section 2.1: Electrical characteristics (curves) 19-Nov-2013 3 – Modified: Figure 3, 15, 16, 17 and 18 – Minor text changes DocID024079 Rev 3 STL8N80K5 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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