STD3PK50Z P-channel 500 V, 3 Ω typ., 2.8 A Zener-protected SuperMESH™ Power MOSFET in a DPAK package Datasheet — production data Features Order code VDSS RDS(on)max STD3PK50Z 500 V < 4Ω ■ Gate charge minimized ■ Extremely high dv/dt capability ■ 100% avalanche tested ■ Very low intrinsic capacitance ■ Improved ESD capability ID PTOT 2.8 A 70 W TAB 3 1 DPAK Applications ■ Switching applications Figure 1. Description Internal schematic diagram or TAB This device is a P-channel Zener-protected Power MOSFET developed using STMicroelectronics’ SuperMESH™ technology, achieved through optimization of ST’s well established strip-based PowerMESH™ layout. In addition to a significant reduction in on-resistance, this device is designed to ensure a high level of dv/dt capability for the most demanding applications. AM11279v1 Table 1. Device summary Order code Marking Package Packaging STD3PK50Z 3PK50Z DPAK Tape and reel Note: For the P-channel Power MOSFETs actual polarity of voltages and current has to be reversed. August 2012 This is information on a product in full production. Doc ID 18280 Rev 2 1/15 www.st.com 15 Contents STD3PK50Z Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 ............................................... 8 Doc ID 18280 Rev 2 STD3PK50Z 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain source voltage 500 V VGS Gate- source voltage ± 30 V ID Drain current (continuous) at TC = 25 °C 2.8 A ID Drain current (continuous) at TC = 100 °C 1.8 A Drain current (pulsed) 11 A Total dissipation at TC = 25 °C 85 W IAR Max current during repetitive or single pulse avalanche (pulse width limited by Tjmax ) 2.8 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID=IAS, VDD= 50 V) 200 mJ Peak diode recovery voltage slope 40 V/ns ESD Gate-source human body model (R = 1,5 k, C = 100 pF) 3 kV Tj Tstg Operating junction temperature Storage temperature - 55 to 150 °C Value Unit IDM (1) PTOT dv/dt (2) 1. Pulse width limited by safe operating area. 2. ISD ≤ 2.8 A, di/dt ≤ 200 A/µs, VPeak ≤V(BR)DSS Table 3. Symbol Note: Thermal data Parameter Rthj-case Thermal resistance junction-case max 1.47 °C/W Rthj-pcb Thermal resistance junction-pcb max 50 °C/W For the P-channel Power MOSFETs actual polarity of voltages and current has to be reversed. Doc ID 18280 Rev 2 3/15 Electrical characteristics 2 STD3PK50Z Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4. Symbol On/off states Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown voltage ID = 1 mA, VGS= 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = 500 V, VDS = 500 V,Tc=125 °C 1 100 µA µA IGSS Gate body leakage current (VDS = 0) VGS = ± 25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 3.75 4.5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID= 1.4 A 3 4 Ω Typ. Max. Unit V(BR)DSS Table 5. Symbol 500 3 V Dynamic Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions Min. 530 VDS =50 V, f=1 MHz, VGS=0 - 50 pF - 25 Co(tr)(1) Equivalent capacitance time related Co(er)(2) Equivalent capacitance energy related RG Intrinsic gate resistance f = 1MHz open drain Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 400 V, ID = 2.8 A VGS =10 V (see Figure 14) pF pF - 32 - pF - 23 - pF - 4.7 - Ω - 29 4.3 15 - nC nC nC VGS = 0, VDS = 0 to 400 V 1. Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 2. energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS Note: 4/15 For the P-channel Power MOSFETs actual polarity of voltages and current has to be reversed. Doc ID 18280 Rev 2 STD3PK50Z Electrical characteristics Table 6. Switching times Symbol Parameter td(on) tr td(off) tf Table 7. Symbol ISD ISDM VSD(1) trr Qrr IRRM trr Qrr IRRM 1. Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 250 V, ID = 1.4 A, RG=4.7 Ω, VGS=10 V (see Figure 13) - 16 15 46 26 - ns ns ns ns Test conditions Min. Typ. Max. Unit - 2.8 11.2 mA A 1.5 V Source drain diode Parameter Source-drain current Source-drain current (pulsed) Forward on voltage ISD= 2.8 A, VGS=0 - Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 2.8 A, VDD= 60 V di/dt = 100 A/µs, (see Figure 15) - 220 1600 14 ns nC A Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 2.8 A,VDD= 60 V di/dt=100 A/µs, Tj=150 °C (see Figure 15) - 280 2100 15 ns nC A Min. Typ. Pulsed: pulse duration = 300µs, duty cycle 1.5% Table 8. Symbol BVGSO Gate-source Zener diode Parameter Test conditions Gate-source breakdown voltage Igs ± 1mA, (open drain) 30 Max. - Unit V The built-in back- to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. Note: For the P-channel Power MOSFETs actual polarity of voltages and current has to be reversed. Doc ID 18280 Rev 2 5/15 Electrical characteristics STD3PK50Z 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 5. Transfer characteristics AM11259v1 ID (A) Tj=150°C Tc=25°C Single pulse 10 a DS (o Op Lim era ite tion d by in th m is ax a r R e n) is 100µs 1 0.1 0.1 Figure 4. 1ms 10ms 10 1 100 VDS(V) Output characteristics AM11260v1 ID (A) 7 AM11261v1 ID (A) 4.5 VGS=10V 7V 6 VDS=15V 4.0 3.5 5 6V 2.0 3 1.5 2 5V 1 0 0 Figure 6. 3.0 2.5 4 1.0 0.5 5 10 15 20 25 Normalized BVDSS vs temperature AM11262v1 BVDSS 0 0 VDS(V) (norm) Figure 7. 2 4 6 8 10 VGS(V) Static drain-source on-resistance AM11263v1 RDS(on) (Ω) VGS=10V ID=1mA 3.3 1.10 3.2 3.1 1.05 3.0 1.00 2.9 2.8 0.95 2.7 0.90 2.5 0.5 2.6 -50 -25 6/15 0 25 50 75 100 125 TJ(°C) Doc ID 18280 Rev 2 1.0 1.5 2.0 2.5 3.0 ID(A) STD3PK50Z Figure 8. Electrical characteristics Gate charge vs gate-source voltage Figure 9. AM11264v1 VGS (V) VDS (V) VDD=400V ID=2.8A VDS 12 Capacitance variations AM11265v1 C (pF) 400 350 10 1000 Ciss 300 8 250 6 200 100 150 4 100 2 Coss Crss 10 50 0 0 5 10 15 20 30 25 Figure 10. Normalized gate threshold voltage vs temperature AM11266v1 VGS(th) (norm) 1 100 10 VDS(V) Figure 11. Normalized on-resistance vs temperature AM11267v1 RDS(on) ID=1.4A VGS=10V (norm) ID=100µA 1.10 1 0.1 0 Qg(nC) 2.5 1.00 2.0 1.5 0.90 1.0 0.80 0.5 0.70 -75 25 -25 75 125 TJ(°C) 0 -75 -25 25 75 125 TJ(°C) Figure 12. Maximum avalanche energy vs starting Tj AM11268v1 EAS (mJ) ID=2.8 A VDD=50 V 200 180 160 140 120 100 80 60 40 20 0 0 20 40 60 80 100 120 140 TJ(°C) Doc ID 18280 Rev 2 7/15 Test circuits 3 STD3PK50Z Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit AM11255v1 Figure 15. Test circuit for diode recovery behavior AM11257v1 8/15 Doc ID 18280 Rev 2 AM11256v1 STD3PK50Z 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Doc ID 18280 Rev 2 9/15 Package mechanical data Table 9. STD3PK50Z DPAK (TO-252) mechanical data mm Dim. Min. Typ. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 E 5.10 6.40 6.60 E1 4.70 e 2.28 e1 4.40 4.60 H 9.35 10.10 L 1 1.50 L1 2.80 L2 0.80 L4 0.60 1 R V2 10/15 Max. 0.20 0° 8° Doc ID 18280 Rev 2 STD3PK50Z Package mechanical data Figure 16. DPAK (TO-252) drawing 0068772_H Figure 17. DPAK footprint(a) 6.7 1.8 3 1.6 2.3 6.7 2.3 1.6 AM08850v1 a. All dimensions are in millimeters Doc ID 18280 Rev 2 11/15 Packaging mechanical data 5 STD3PK50Z Packaging mechanical data Table 10. DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 12/15 Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 Doc ID 18280 Rev 2 18.4 22.4 STD3PK50Z Packaging mechanical data Figure 18. Tape for DPAK (TO-252) 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 W K0 B0 For machine ref. only including draft and radii concentric around B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 Figure 19. Reel for DPAK (TO-252) T REEL DIMENSIONS 40mm min. Access hole At sl ot location B D C N A Full radius Tape slot in core for tape start 25 mm min. width G measured at hub AM08851v2 Doc ID 18280 Rev 2 13/15 Revision history 6 STD3PK50Z Revision history Table 11. 14/15 Document revision history Date Revision Changes 26-Nov-2010 1 First release. 31-Aug-2012 2 Document status promoted from preliminary data to production data. Minor text changes on the cover page. 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