TC74HC123AP/AF
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74HC123AP,TC74HC123AF
Dual Retriggerable Monostable Multivibrator
The TC74HC123A is a high speed CMOS MONOSTABLE
MULTIVIBRATOR fabricated with silicon gate C2MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
There are two trigger inputs, A input (negative edge), and B
input (positive edge). These inputs are valid for a slow rise/fall
time signal (tr = tf = 1 s) as they are schmitt trigger inputs. This
device may also be triggered by using CLR input (positive
edge).
After triggering, the output stays in a MONOSTABLE state for
a time period determined by the external resistor and capacitor
(Rx, Cx ). A low level at the CLR input breaks this state. In the
MONOSTABLE state, if a new trigger is applied, it extends the
MONOSTABLE period (retrigger mode).
Limits for Cx and Rx are:
External capacitor, Cx: No limit
External resistor, Rx: VCC = 2.0 V more than 5 kΩ
VCC ≥ 3.0 V more than 1 kΩ
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
TC74HC123AP
TC74HC123AF
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
Features (Note)
•
High speed: tpd = 25 ns (typ.) at VCC = 5 V
•
Low power dissipation
Standby state: ICC = 4 μA (max) at Ta = 25°C
Active state: ICC = 700 μA (max) at Ta = 25°C
•
High noise immunity: VNIH = VNIL = 28% VCC (min)
•
Output drive capability: 10 LSTTL loads
•
•
Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
∼ tpHL
Balanced propagation delays: tpLH −
•
Wide operating voltage range: VCC (opr) = 2 to 6 V
•
Pin and function compatible with 74LS123
: 1.00 g (typ.)
: 0.18 g (typ.)
Note:
In the case of using only one circuit, CLR should be tied to GND, Rx/Cx･Cx･Q･ Q should be tied to
OPEN, the other inputs should be tied to VCC or GND.
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Pin Assignment
IEC Logic Symbol
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Block Diagram (Note 1)(Note 2)
Note 1: Cx, Rx, Dx are external
capacitor, resistor, and diode, respectively.
Note 2: External clamping diode, Dx;
The external capacitor is charged to VCC level in the wait state, i.e. when no trigger is applied.
If the supply voltage is turned off, Cx is discharges mainly through the internal (parasitic) diode. If Cx is
sufficiently large and VCC drops rapidly, there will be some possibility of damaging the IC through in rush
current or latch-up. If the capacitance of the supply voltage filter is large enough and VCC drops slowly, the
in rush current is automatically limited and damage to the IC is avoided.
The maximum value of forward current through the parasitic diode is ±20 mA.
In the case of a large Cx, the limit of fall time of the supply voltage is determined as follows:
tf ≥ (VCC − 0.7) Cx/20 mA
(tf is the time between the supply voltage turn off and the supply voltage reaching 0.4 VCC.)
In the event a system does not satisfy the above condition, an external clamping diode (Dx) is needed to
protect the IC from in rush current.
Truth Table
Inputs
Outputs
CLR
H
H
X
L
H
L
H
Inhibit
H
X
H
L
H
Inhibit
L
Q
Function
B
A
Q
Output Enable
H
L
H
X
X
Output Enable
Output Enable
L
L
H
Inhibit
X: Don’t care
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System Diagram
VCC
QP
RX/CX
CX
Vref
L
C2
C1
Vref
H
QN
VCC
D R
Q
CK
Q
F/F
A
B
Q
Q
CLR
Timing Chart
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Functional Description
(1)
(2)
(3)
(4)
Stand-by state
The external capacitor (Cx) is fully charged to VCC in the stand-by state. That means, before
triggering, the QP and QN transistors which are connected to the Rx/Cx node are in the off state. Two
comparators that relate to the timing of the output pulse, and two reference voltage supplies turn off.
The total supply current is only leakage current.
Trigger operation
Trigger operation is effective in any of the following three cases. First, the condition where the A
input is low, and the B input has a rising signal; second, where the B input is high, and the A input
has a falling signal; and third, where the A input is low and the B input is high, and the CLR
input has a rising signal.
After a trigger becomes effective, comparators C1 and C2 start operating, and QN is turned on. The
external capacitor discharges through QN. The voltage level at the Rx/Cx node drops. If the Rx/Cx
voltage level falls to the internal reference voltage Vref L, the output of C1 becomes low. The flip-flop
is then reset and QN turns off. At that moment C1 stops but C2 continues operating.
After QN turns off, the voltage at the Rx/Cx node starts rising at a rate determined by the time
constant of external capacitor Cx and resistor Rx.
Upon triggering, output Q becomes high, following some delay time of the internal F/F and gates. It
stays high even if the voltage of Rx/Cx changes from falling to rising. When Rx/Cx reaches the
internal reference voltage Vref H, the output of C2 becomes low, the output Q goes low and C2 stops
its operation. That means, after triggering, when the voltage level of the Rx/Cx node reaches Vref H,
the IC returns to its MONOSTABLE state.
With large values of Cx and Rx, and ignoring the discharge time of the capacitor and internal
delays of the IC, the width of the output pulse, tw (OUT), is as follows:
tw (OUT) = 1.0 Cx Rx
Retrigger operation
When a new trigger is applied to either input A or B while in the MONOSTABLE state, it is
effective only if the IC is charging Cx. The voltage level of the Rx/Cx node then falls to Vref L level
again. Therefore the Q output stays high if the next trigger comes in before the time period set by Cx
and Rx.
If the new trigger is very close to previous trigger, such as an occurrence during the discharge cycle,
it will have no effect.
The minimum time for a trigger to be effective 2nd trigger, trr (Min.), depends on VCC and Cx.
Reset operation
In normal operation, the CLR input is held high. If CLR is low, a trigger has no effect because
the Q output is held low and the trigger control F/F is reset. Also, QP turns on and Cx is charged
rapidly to VCC.
This means if CLR is set low, the IC goes into a wait state.
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Absolute Maximum Ratings (Note 1)
Characteristics
Symbol
Rating
Unit
Supply voltage range
VCC
−0.5 to 7
V
DC input voltage
VIN
−0.5 to VCC + 0.5
V
VOUT
−0.5 to VCC + 0.5
V
Input diode current
IIK
±20
mA
Output diode current
IOK
±20
mA
DC output current
IOUT
±25
mA
DC VCC/ground current
ICC
±50
mA
Power dissipation
PD
500 (DIP) (Note 2)/180 (SOP)
mW
Storage temperature
Tstg
−65 to 150
°C
DC output voltage
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C shall be
applied until 300 mW.
Operating Ranges (Note 1)
Characteristics
Symbol
Rating
Unit
Supply voltage
VCC
2 to 6
V
Input voltage
VIN
0 to VCC
V
VOUT
0 to VCC
V
Topr
−40 to 85
°C
Output voltage
Operating temperature
Input rise and fall time
( CLR only)
0 to 1000 (VCC = 2.0 V)
tr, tf
0 to 500 (VCC = 4.5 V)
ns
0 to 400 (VCC = 6.0 V)
External capacitor
Cx
External resistor
Rx
No limitation
(Note 2)
≥5 k (VCC = 2.0 V) (Note 2)
≥1 k (VCC ≥ 3.0 V) (Note 2)
F
Ω
Note 1: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
Note 2: The maximum allowable values of Cx and Rx are a function of leakage of capacitor Cx, the leakage of
TC74HC123A, and leakage due to board layout and surface resistance.
Susceptibility to externally induced noise signals may occur for Rx > 1 MΩ.
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Electrical Characteristics
DC Characteristics
Characteristics
High-level input
voltage
Low-level input
voltage
High-level output
voltage
VOH
Low-level output
voltage
Min
Typ.
Max
Min
Max
2.0
1.50
⎯
⎯
1.50
⎯
4.5
3.15
⎯
⎯
3.15
⎯
6.0
4.20
⎯
⎯
4.20
⎯
2.0
⎯
⎯
0.50
⎯
0.50
4.5
⎯
⎯
1.35
⎯
1.35
6.0
⎯
⎯
1.80
⎯
1.80
2.0
1.9
2.0
⎯
1.9
⎯
IOH = −20 μA
4.5
4.4
4.5
⎯
4.4
⎯
6.0
5.9
6.0
⎯
5.9
⎯
IOH = −4 mA
4.5
4.18
4.31
⎯
4.13
⎯
IOH = −5.2 mA
6.0
5.68
5.80
⎯
5.63
⎯
2.0
⎯
0.0
0.1
⎯
0.1
4.5
⎯
0.0
0.1
⎯
0.1
6.0
⎯
0.0
0.1
⎯
0.1
IOL = 4 mA
4.5
⎯
0.17
0.26
⎯
0.33
IOL = 5.2 mA
6.0
⎯
0.18
0.26
⎯
0.33
⎯
VIL
VIN
= VIH or VIL
IOL = 20 μA
VOL
(Q, Q )
Ta = −40 to 85°C
VCC (V)
⎯
VIH
(Q, Q )
Ta = 25°C
Test Condition
Symbol
VIN
= VIH or VIL
Unit
V
V
V
V
Input leakage
current
IIN
VIN = VCC or GND
6.0
⎯
⎯
±0.1
⎯
±1.0
μA
Rx/Cx terminal
off-state current
IIN
VIN = VCC or GND
6.0
⎯
⎯
±0.1
⎯
±1.0
μA
Quiescent supply
current
ICC
VIN = VCC or GND
6.0
⎯
⎯
4.0
⎯
40.0
μA
2.0
⎯
45
200
⎯
260
μA
4.5
⎯
400
500
⎯
650
μA
6.0
⎯
0.7
1.0
⎯
1.3
mA
Active-state supply
current
(Note)
Note:
ICC
VIN = VCC or GND
Rx/Cx = 0.5 VCC
Per circuit
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Timing Requirements (input: tr = tf = 6 ns)
Characteristics
Minimum pulse width
Minimum clear width
Symbol
tW (L)
⎯
tW (H)
⎯
tW (L)
Rx = 1 kΩ
Cx = 100 pF
Minimum retrigger time
Ta = 25°C
Test Condition
Ta =
−40 to
85°C
VCC (V)
Typ.
Limit
Limit
2.0
⎯
75
95
4.5
⎯
15
19
6.0
⎯
13
16
2.0
⎯
75
95
4.5
⎯
15
19
6.0
⎯
13
16
2.0
325
⎯
⎯
4.5
108
⎯
⎯
Unit
ns
ns
ns
6.0
78
⎯
⎯
2.0
5.0
⎯
⎯
4.5
1.4
⎯
⎯
6.0
1.2
⎯
⎯
Test Condition
Min
Typ.
Max
Unit
⎯
⎯
4
8
ns
⎯
⎯
25
36
ns
⎯
⎯
26
41
ns
⎯
⎯
16
27
ns
trr
Rx = 1 kΩ
Cx = 0.01 μF
μs
AC Characteristics (CL = 15 pF, VCC = 5 V, Ta = 25°C, input: tr = tf = 6 ns)
Characteristics
Output transition time
Symbol
tTLH
tTHL
Propagation delay time
tpLH
( A , B-Q, Q )
tpHL
Propagation delay time
tpLH
( CLR TRIGGER-Q, Q )
tpHL
Propagation delay time
tpLH
( CLR -Q, Q )
tpHL
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AC Characteristics (CL = 50 pF, input: tr = tf = 6 ns)
Ta = 25°C
Test Condition
Characteristics
Output transition time
Symbol
( A , B-Q, Q )
tpHL
Propagation delay
time
tpLH
Max
Min
Max
2.0
⎯
30
75
⎯
95
4.5
⎯
8
15
⎯
19
6.0
⎯
7
13
⎯
16
2.0
⎯
102
210
⎯
265
4.5
⎯
29
42
⎯
53
6.0
⎯
22
36
⎯
45
2.0
⎯
102
235
⎯
295
4.5
⎯
31
47
⎯
59
6.0
⎯
23
40
⎯
50
2.0
⎯
68
160
⎯
200
4.5
⎯
20
32
⎯
40
6.0
⎯
16
27
⎯
34
Cx = 28 pF
2.0
⎯
700
2000
⎯
2500
Rx = 6 kΩ (VCC = 2 V)
4.5
⎯
250
400
⎯
500
Rx = 2 kΩ (VCC = 4.5 V, 6 V)
6.0
⎯
210
340
⎯
425
2.0
90
110
130
90
130
4.5
95
105
115
95
115
6.0
95
105
115
95
115
2.0
0.9
1.0
1.2
0.9
1.2
4.5
0.9
1.0
1.1
0.9
1.1
6.0
0.9
1.0
1.1
0.9
1.1
⎯
⎯
⎯
tpHL
Propagation delay
time
tpLH
( CLR -Q, Q )
tpHL
Output pulse width
Typ.
tTHL
tpLH
( CLR TRIGGER-Q,
Q)
Min
tTLH
Propagation delay
time
twOUT
⎯
Cx = 0.01 μF
Rx = 10 kΩ
Cx = 0.1 μF
Rx = 10 kΩ
Output pulse width
error between circuits
Ta = −40 to 85°C
VCC
(V)
Unit
ns
ns
ns
ns
ns
μs
ms
ΔtwOUT
⎯
⎯
±1
⎯
⎯
⎯
%
Input capacitance
CIN
⎯
⎯
5
10
⎯
10
pF
Power dissipation
capacitance
CPD
⎯
⎯
162
⎯
⎯
⎯
pF
(in same package )
Note:
(Note)
CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD･VCC･fIN + ICC’･duty/100 + ICC/2 (per circuit)
(ICC’: active supply current)
(duty. %)
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Output Pulse Width Constant K – Supply Voltage (typical)
tWOUT – Cx Characteristics (typ.)
trr – VCC Characteristics (typ.)
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Package Dimensions
Weight: 1.00 g (typ.)
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Package Dimensions
Weight: 0.18 g (typ.)
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TC74HC123AP/AF
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