GA100JT12-227 Normally – OFF Silicon Carbide Junction Transistor Features Package RoHS Compliant 175 °C Maximum Operating Temperature Gate Oxide Free SiC Switch Exceptional Safe Operating Area Integrated SiC Schottky Rectifier Excellent Gain Linearity Temperature Independent Switching Performance Low Output Capacitance Positive Temperature Coefficient of RDS,ON Suitable for Connecting an Anti-parallel Diode = 1200 V RDS(ON) = 10 mΩ ID (Tc = 25°C) = 160 A ID (Tc = 115°C) = 100 A hFE (Tc = 25°C) = 100 D S D Pin D - Drain Pin S - Source Pin GR - Gate Return Pin G - Gate G GR G GR S SOT-227 Advantages Applications Compatible with Si MOSFET/IGBT Gate Drive ICs > 20 µs Short-Circuit Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input Signal Distortion High Amplifier Bandwidth Reduced cooling requirements Reduced system size VDS Please note: The Source and Gate Return pins are not exchangeable. Their exchange might lead to malfunction. Down Hole Oil Drilling, Geothermal Instrumentation Hybrid Electric Vehicles (HEV) Solar Inverters Switched-Mode Power Supply (SMPS) Power Factor Correction (PFC) Induction Heating Uninterruptible Power Supply (UPS) Motor Drives Table of Contents Section I: Absolute Maximum Ratings ...........................................................................................................1 Section II: Static Electrical Characteristics ....................................................................................................2 Section III: Dynamic Electrical Characteristics .............................................................................................2 Section IV: Figures ...........................................................................................................................................3 Section V: Driving the GA100JT12-227 ..........................................................................................................6 Section VI: Package Dimensions ................................................................................................................. 10 Section VII: SPICE Model Parameters ......................................................................................................... 11 Section I: Absolute Maximum Ratings Parameter Drain – Source Voltage Continuous Drain Current Continuous Drain Current Continuous Gate Current Continuous Gate Return Current Symbol VDS ID ID IG IGR Turn-Off Safe Operating Area RBSOA Short Circuit Safe Operating Area SCSOA Reverse Gate – Source Voltage Reverse Drain – Source Voltage Power Dissipation Operating and storage temperature Sept 2015 VSG VSD Ptot Tstg Conditions VGS = 0 V TC = 25°C TC = 115°C TVJ = 175 oC, Clamped Inductive Load TVJ = 175 oC, IG = 1 A, VDS = 800 V, Non Repetitive TC = 25 °C / 115 °C, tp > 100 ms Value 1200 160 100 7 7 ID,max = 100 @ VDS ≤ VDSmax Unit V A A A A Fig. 12 Fig. 12 A Fig. 14 >20 µs 30 25 535 / 214 -55 to 175 V V W °C http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Notes Fig. 11 Pg 1 of 10 GA100JT12-227 Mechanical Properties Symbol Conditions Min. Mounting Torque Terminal Connection Torque Weight Case Color Dimensions Md Value Typical 1.5 1.3 Unit Notes Max. 1.5 29 Black 38 x 25.4 x 12 Nm Nm g mm Section II: Static Electrical Characteristics Parameter Symbol Conditions Drain – Source On Resistance RDS(ON) ID = 100 A, Tj = 25 °C ID = 100 A, Tj = 150 °C ID = 100 A, Tj = 175 °C Gate – Source Saturation Voltage VGS,SAT ID = 100 A, ID/IG = 40, Tj = 25 °C ID = 100 A, ID/IG = 30, Tj = 175 °C hFE VDS = 8 V, ID = 100 A, Tj = 25 °C VDS = 8 V, ID = 100 A, Tj = 125 °C VDS = 8 V, ID = 100 A, Tj = 175 °C Drain Leakage Current IDSS VDS = 1200 V, VGS = 0 V, Tj = 25 °C VDS = 1200 V, VGS = 0 V, Tj = 150 °C VDS = 1200 V, VGS = 0 V, Tj = 175 °C Gate Leakage Current ISG VSG = 20 V, Tj = 25 °C Min. Value Typical Max. Unit Notes mΩ Fig. 4 V Fig. 7 – Fig. 5 μA Fig. 8 A: On State DC Current Gain 10 18 21 3.42 3.23 100 65 58 105 B: Off State 5 5 10 40 nA C: Thermal Thermal resistance, junction - case RthJC 0.28 °C/W Fig. 16 Unit Notes 14.4 248 102 nF pF µJ Fig. 9 Fig. 9 Fig. 10 462 pF Section III: Dynamic Electrical Characteristics Parameter Symbol Conditions Ciss Crss/Coss EOSS VGS = 0 V, VDS = 800 V, f = 1 MHz VDS = 800 V, f = 1 MHz VGS = 0 V, VDS = 800 V, f = 1 MHz Min. Value Typical Max. A: Capacitance and Gate Charge Input Capacitance Reverse Transfer/Output Capacitance Output Capacitance Stored Energy Effective Output Capacitance, time related Effective Output Capacitance, energy related Gate-Source Charge Gate-Drain Charge Gate Charge - Total B: SJT Switching Characteristics Internal Gate Resistance – zero bias Internal Gate Resistance – ON Turn On Delay Time Fall Time, VDS Turn Off Delay Time Rise Time, VDS Turn-On Energy Per Pulse Turn-Off Energy Per Pulse Total Switching Energy 1 Coss,tr ID = constant, VGS = 0 V, VDS = 0…800 V Coss,er VGS = 0 V, VDS = 0…800 V 320 pF QGS QGD QG VGS = -5…3 V VGS = 0 V, VDS = 0…800 V 110 368 478 nC nC nC 0.58 Ω 0.09 50 120 160 100 1300 1050 2350 Ω ns ns ns ns µJ µJ µJ 1 RG(INT-ZERO) RG(INT-ON) td(on) tf td(off) tr Eon Eoff Etot f = 1 MHz, VAC = 50 mV, VDS = 0 V, VGS = 0 V, Tj = 175 ºC VGS > 2.5 V, VDS = 0 V, Tj = 175 ºC Tj = 25 ºC, VDS = 750 V, ID = 60 A, Inductive Load Refer to Section V for additional driving information. Tj = 25 ºC, VDS = 750 V, ID = 60 A, Inductive Load Refer to Section V. – All times are relative to the Drain-Source Voltage VDS Sept 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 2 of 10 GA100JT12-227 Section IV: Figures A: Static Characteristics Figure 1: Typical Output Characteristics at 25 °C Figure 2: Typical Output Characteristics at 150 °C Figure 3: Typical Output Characteristics at 175 °C Figure 4: On-Resistance vs. Gate Current Figure 5: DC Current Gain and Normalized On-Resistance vs. Temperature Figure 6: DC Current Gain vs. Drain Current Sept 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 3 of 10 GA100JT12-227 Figure 7: Typical Gate – Source Saturation Voltage Figure 8: Typical Blocking Characteristics B: Dynamic Characteristics Figure 9: Input, Output, and Reverse Transfer Capacitance Figure 10: Energy Stored in Output Capacitance C: Current and Power Derating Figure 11: Power Derating Curve Sept 2015 Figure 12: Drain Current Derating vs. Temperature http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 4 of 10 GA100JT12-227 Figure 13: Forward Bias Safe Operating Area at Tc= 25 oC Figure 14: Turn-Off Safe Operating Area Figure 15: Transient Thermal Impedance Figure 16: Drain Current Derating vs. Pulse Width Sept 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 5 of 10 GA100JT12-227 Section V: Driving the GA100JT12-227 Drive Topology TTL Logic Constant Current High Speed – Boost Capacitor High Speed – Boost Inductor Proportional Pulsed Power Gate Drive Power Consumption High Medium Medium Low Lowest Medium Switching Frequency Low Medium High High High N/A Application Emphasis Availability Wide Temperature Range Wide Temperature Range Fast Switching Ultra Fast Switching Wide Drain Current Range Pulse Power Coming Soon Coming Soon Production Coming Soon Coming Soon Coming Soon A: Static TTL Logic Driving The GA100JT12-227 may be driven using direct (5 V) TTL logic after current amplification. The (amplified) current level of the supply must meet or exceed the steady state gate current (I G,steady) required to operate the GA100JT12-227. The power level of the supply can be estimated from the target duty cycle of the particular application. IG,steady is dependent on the anticipated drain current ID through the SJT and the DC current gain hFE, it may be calculated from the following equation. An accurate value of the hFE may be read from Figure 6. 5V SiC SJT TTL Gate Signal D G 5/0V TTL i/p IG,steady S Figure 17: TTL Gate Drive Schematic B: High Speed Driving The SJT is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 18 which features a positive current peak during turn-on, a negative current peak during turn-off, and continuous gate current to remain on. Figure 18: An idealized gate current waveform for fast switching of an SJT. An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, QG, for turn-on is supplied by a burst of high gate current, IG,on, until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. Sept 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 6 of 10 GA100JT12-227 Ideally, IG,on should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the steady onstate. In practice, the rise time of the I G,on pulse is affected by the parasitic inductances, Lpar in the device package and drive circuit. A voltage developed across the parasitic inductance in the source path, L s, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The voltage applied to the gate pin should be maintained high enough, above the VGS,sat (see Figure 7) level to counter these effects. A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. While satisfactory turn off can be achieved with V GS = 0 V, a negative gate voltage VGS may be used in order to speed up the turn-off transition. Two high-speed drive topologies for the SiC SJTs are presented below. B:1: High Speed, Low Loss Drive with Boost Capacitor, GA15IDDJT22-FR4 The GA100JT12-227 may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology. In which a gate resistor, a gate capacitor and multiple voltage levels are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while in on-state. A point-of-load evaluation gate drive board (GA15IDDJT22-FR4) utilizing this topology is commercially available for low-side driving, its datasheet provides additional details about this drive topology. GA15IDDJT22-FR4 Gate Driver Board FOD3182 Signal Isolator IXDN609 Gate Drive IC Gate Signal CG AO4629 MOSFET Totem Pole IXDF604 Gate Drive IC IG G D Gate SiC SJT S RG +12 V DC/DC Converters +15 V +5 V -8.7 V Figure 19: The GA15IDDJT22-FR4 Two Voltage Source gate driver. The GA15IDDJT22-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective gate resistance3 of RG = 0.70 Ω. It may be necessary for the user to reduce RG1 and RG2 under high drain current conditions for effective operation of the GA100JT12-227 in order to increase its output gate current. For the GA100JT12-227, RG must be reduced for ID ≥ ~60 A for safe operation with the GA15IDDJT22-FR4. Please referrer to the GA15IDDJT22-FR4 datasheet for additional information. 3 – RG = (1/RG1 +1/RG2)-1 Sept 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 7 of 10 GA100JT12-227 B:2: High Speed, Low Loss Drive with Boost Inductor A High Speed, Low-Loss Driver with Boost Inductor is also capable of driving the GA100JT12-227 at high-speed. It utilizes a gate drive inductor instead of a capacitor to provide the high-current gate current pulses IG,on and IG,off. During operation, inductor L is charged to a specified IG,on current value then made to discharge IL into the SJT gate pin using logic control of S 1, S2, S3, and S4, as shown in Figure 20. After turn on, while the device remains on the necessary steady state gate current IG,steady is supplied from source VCC through RG. Please refer to the article “A current-source concept for fast and efficient driving of silicon carbide transistors” by Dr. Jacek Rąbkowski for additional information on this driving topology.4 VCC S1 VCC S2 L VEE S3 SiC SJT D G RG S S4 VEE Figure 20: Simplified Inductive Pulsed Drive Topology C: Proportional Gate Current Driving For applications in which the GA100JT12-227 will operate over a wide range of drain current conditions, it may be beneficial to drive the device using a proportional gate drive topology to optimize gate drive power consumption. A proportional gate driver relies on instantaneous drain current ID feedback to vary the steady state gate current IG,steady supplied to the GA100JT12-227 C:1: Voltage Controlled Proportional Driver The voltage controlled proportional driver relies on a gate drive IC to detect the GA100JT12-227 drain-source voltage VDS during on-state to sense ID. The gate drive IC will then increase or decrease IG,steady in response to ID. This allows IG,steady, and thus the gate drive power consumption, to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A high voltage diode connected between the drain and sense protects the IC from high-voltage when the driver and GA100JT12-227 are in off-state. A simplified version of this topology is shown in Figure 22, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ HV Diode Sense Gate Signal Proportional Gate Current Driver Signal Output D G IG,steady SiC SJT S Figure 21: Simplified Voltage Controlled Proportional Driver 4 – Archives of Electrical Engineering. Volume 62, Issue 2, Pages 333–343, ISSN (Print) 0004-0746, DOI: 10.2478/aee-2013-0026, June 2013 Sept 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 8 of 10 GA100JT12-227 C:2: Current Controlled Proportional Driver The current controlled proportional driver relies on a low-loss transformer in the drain or source path to provide feedback ID of the GA100JT12227 during on-state to supply IG,steady into the device gate. IG,steady will then increase or decrease in response to ID at a fixed forced current gain which is set be the turns ratio of the transformer, hforce = ID / IG = N2 / N1. GA100JT12-227 is initially tuned-on using a gate current pulse supplied into an RC drive circuit to allow ID current to begin flowing. This topology allows IG,steady, and thus the gate drive power consumption, to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A simplified version of this topology is shown in Figure 22, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/. N2 SiC SJT Gate Signal D G S N3 N1 N2 Figure 22: Simplified Current Controlled Proportional Driver Sept 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 9 of 10 GA100JT12-227 Section VI: Package Dimensions SOT-227 PACKAGE OUTLINE 0.472 (11.9) 0.480 (12.19) 1.240 (31.5) 1.255 (31.88) 0.310 (7.87) 0.322 (8.18) R 3.97 0.372 (9.45) 0.378 (9.60) 0.108 (2.74) 0.124 (3.15) Ø 0.163 (4.14) 0.169 (4.29) 1.049 (26.6) 1.059 (26.90) 0.163 (4.14) 0.169 (4.29) 0.990 (25.1) 1.000 (25.40) 0.495 (12.5) 0.506 (12.85) 0.172 (4.37) 0.186 (4.72) 0.191 (4.85) 0.080 (2.03) 0.084 (2.13) 0.234 (5.94) M4 0.165 (4.19) 0.169 (4.29) 0.164 (4.16) 0.174 (4.42) 0.030 (0.76) 0.033 (0.84) 0.588 (14.9) 0.594 (15.09) 1.186 (30.1) 1.192 (30.28) 1.494 (37.9) 1.504 (38.20) NOTE 1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER. 2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS Revision History Date 2015/09/16 2015/05/29 Revision 1 0 Comments Updated Characteristics Initial release Supersedes Published by GeneSiC Semiconductor, Inc. 43670 Trade Center Place Suite 155 Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. Sept 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 10 of 10 GA100JT12-227 Section VII: SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website (http://www.genesicsemi.com/images/products_sic/sjt/GA100JT12-227_SPICE.pdf) into LTSPICE (version 4) software for simulation of the GA100JT12-227. * MODEL OF GeneSiC Semiconductor Inc. * $Revision: 1.0 $ * $Date: 29-MAY-2015 $ * * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * * COPYRIGHT (C) 2015 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. * * * Start of GA100JT12-227 SPICE Model * .SUBCKT GA100JT12 DRAIN GATE SOURCE QA DRAIN GATE SOURCE GA100JT12_Q QB DRAIN GATE SOURCE GA100JT12_Q * .model GA100JT12_Q NPN + IS 9.833E-48 ISE 1.073E-26 EG 3.23 + BF 110 BR 0.55 IKF 9000 + NF 1 NE 2 RB 0.95 + RE 0.005 RC 0.014 CJC 2.398E-9 + VJC 2.8346 MJC 0.4846 CJE 6.026E-09 + VJE 3.1791 MJE 0.5295 XTI 3 + XTB -1.5 TRC1 9.0E-03 MFG GeneSiC_Semi + IRB 0.005 RBM 0.073 .ENDS * * End of GA100JT12-227 SPICE Model Sept 2015 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 1 of 1