[AK4120] AK4120 Sample Rate Converter with Mixer and Volume AK4120 8kHz 32kHz,44.1kHz,48kHz 48kHz 96kHz ( ) (FSI): 8kHz 48kHz (FSO): 32kHz,44.1kHz,48kHz,96kHz : FSO/FSI=0.667 6 THD+N : –113dB at 1kHz input I/F : 20 20/16 I2S 256fs/512fs µP I/F: 3 , I2C 2.7 to 3.6V I2C SDTI1 ILRCK1 I2S PDN VDD Input#1 Audio I/F Sample Rate Converter VSS Volume#1 TEST IBICK1 IMCLK1 OMCLK IMCLK2 SDTI2 ILRCK2 Input#2 Audio I/F Volume#2 Output Audio I/F IBICK2 SDTO OLRCK OBICK μ P I/F I2MODE CAD0 CSN/CAD1 CCLK/SCL CDTI/SDA MS0134-J-01 OMODE 2008/06 -1- [AK4120] ■ AK4120VF AKD4120 −40 ∼ +85°C AK4120 24pin VSOP (0.65mm pitch) ■ IMCLK1 1 24 IMCLK2 SDTI1 2 23 SDTI2 IBICK1 3 22 IBICK2 ILRCK1 4 21 ILRCK2 TEST 5 20 I2MODE I2S 6 19 VDD I2C 7 18 VSS CAD0 8 17 OMODE CSN/CAD1 9 16 OMCLK CCLK/SCL 10 15 SDTO CDTI/SDA 11 14 OBICK PDN 12 13 OLRCK Top View MS0134-J-01 2008/06 -2- [AK4120] No. 1 2 3 IMCLK1 SDTI1 IBICK1 I/O I I I Input#1 Input#1 Input#1 4 ILRCK1 I Input#1 5 TEST I 6 I2S I 7 I2C I 8 CAD0 CSN CAD1 CCLK SCL CDTI SDA 9 10 11 Function VSS PDN 13 14 OLRCK OBICK 15 SDTO O 16 OMCLK I 17 OMODE I 18 19 VSS VDD I I 0 3 20 I2MODE I 21 22 23 24 ILRCK2 IBICK2 SDTI2 IMCLK2 I/O I/O I I I2C 1 3 I2C 3 I2C & “L” I I/O I/O , “H”: I2C “L”: 3 I I I I I I I/O 12 , “H”: I2S “L”: Output Output Output Output “L”: , “H”: , “H”: , 3.3V Input#2 “L”: Input#2 Input#2 Input#2 Input#2 MS0134-J-01 2008/06 -3- [AK4120] (VSS=0V; Note 1) Parameter Power Supplies Input Current , Any Pin Except Supplies Input Voltage Ambient Temperature (Power applied) Storage Temperature Note 1: : Symbol min max Units VDD IIN VIN -0.3 -0.3 4.6 ±10 VDD+0.3 V mA V Ta Tstg -40 -65 85 150 °C °C (VSS=0V; Note 2) Parameter Power Supply Symbol min typ max Units VDD 2.7 3.3 3.6 V Note 2: : SRC (Ta=-40∼ 85°C; VDD = 2.7∼3.6V; data = 20bit; measurement bandwidth = 20Hz~ FSO/2; unless otherwise specified.) Parameter Symbol min typ max Units Resolution 20 Bits Input Sample Rate (Note 3) FSI 8 48 kHz Output Sample Rate (Note 4) FSO 32 96 kHz Dynamic Range (Input= 1kHz, -60dBFS, Note 5) FSO/FSI=44.1kHz/48kHz 115 dB FSO/FSI=48kHz/44.1kHz 116 dB FSO/FSI=32kHz/48kHz 114 dB FSO/FSI=96kHz/32kHz 119 dB Worst Case (FSO/FSI=32kHz/44.1kHz ) 112 dB Dynamic Range (Input= 1kHz, -60dBFS, A-weighted, Note 5) FSO/FSI=44.1kHz/48kHz 117 dB THD+N (Input= 1kHz, 0dBFS, Note 5) FSO/FSI=44.1kHz/48kHz -112 dB FSO/FSI=48kHz/44.1kHz -113 dB FSO/FSI=32kHz/48kHz -111 dB FSO/FSI=96kHz/32kHz -111 dB Worst Case (FSO/FSI=48kHz/8kHz) -103 dB Ratio between Input and Output Sample Rate (FSO/FSI, Note 6, Note 7) 0.667 6 FSO/FSI Note 3. Path Mode0 Input#2 FSI=32kHz~96kHz Math Mode2 3 FSI=8kHz~96kHz Note 4. Path Mode2 3 min=8kHz Note 5. Rohde & Schwarz UPD04 Rejection Filter= wide 8192point FFT 1 2 Note 6. 0.667 FSI 48kHz FSO 32kHz FSO/FSI Note 7. 6 FSI 8kHz FSO 48kHz MS0134-J-01 2008/06 -4- [AK4120] 1. Input Sample Rate (FSI) vs. THD+N (FSO=48kHz) 2. Input Frequency vs. THD+N (FSI=44.1kHz, FSO=48kHz) MS0134-J-01 2008/06 -5- [AK4120] (Ta =-40∼ 85°C; VDD = 2.7∼3.6V; FSO=FSI=fs) Parameter Symbol min Typ PB SB PR SA GD 0 0.5417fs Max Units 0.4583fs kHz kHz dB dB 1/fs Digital Filter Passband (Note 8) Stopband Passband Ripple Stopband Attenuation Group Delay Note 8. fs Note 9. LRCK -0.001dB (Note 8) (Note 9) ± 0.01 97 - 56.5 L,R - LRCK ( L,R 20Bit, 20,16Bit ) min typ Max Units 8.5 - mA 20 100 0.3xVDD mA mA μA V V DC (Ta=-40∼ 85°C; VDD=2.7~3.6V) Parameter Power Supply Current Normal operation: (PDN = “H”, Path Mode 0) FSI=FSO=48kHz at Slave Mode (I2MODE= OMODE = “L”): VDD=3.3V FSI=48kHz,FSO=96kHz at Master Mode (I2MODE=OMODE= “H”) : VDD=3.3V : VDD=3.6V Power down: PDN = “L” (Note 10) High-Level Input Voltage Low-Level Input Voltage Symbol VIH VIL 0.7xVDD - 10.2 11.5 10 - High-Level Output Voltage (Iout=-400μA) Low-Level Output Voltage (Except SDA pin: Iout=400μA); ( SDA pin: Iout= 3mA) Input Leakage Current Note 10. VOH VDD-0.4 - - V - - 0.4 0.4 ± 10 V V μA VOL VOL Iin VSS MS0134-J-01 2008/06 -6- [AK4120] (Ta=-40∼ 85°C; VDD=2.7~3.6V; CL=20pF) Parameter Master Clock Input (IMCLK1) Frequency Duty Cycle (at FSI > 33kHz) Duty Cycle (at FSI ≤ 33kHz) Master Clock Input (IMCLK2) Frequency Duty Cycle (at FSI > 33kHz) Duty Cycle (at FSI ≤ 33kHz) Master Clock Input (OMCLK) Frequency (Note 11) Duty Cycle (at FSI > 33kHz) Duty Cycle (at FSI ≤ 33kHz) L/R clock for Input data #1 (ILRCK1) Frequency Duty Cycle L/R clock for Input data #2 (ILRCK2) Frequency (Note 12) Duty Cycle Slave Mode Master Mode L/R clock for Output data (OLRCK) Frequency (Note 13) Duty Cycle Slave Mode Master Mode Audio Interface Timing (Note 14) Input#1 at Path Mode 0 and 2 Input#2 (Slave Mode) at Path Mode 1 BICK Period BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “↑” (Note 15) BICK “↑” to LRCK Edge (Note 15) SDTI1-2, Hold Time from BICK “↑” SDTI1-2, Setup Time to BICK “↑” Input#2 (Slave Mode) at Path Mode 0 and 3 BICK Period BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “↑” (Note 15) BICK “↑” to LRCK Edge (Note 15) SDTI2, Hold Time from BICK “↑” SDTI2, Setup Time to BICK “↑” Output (Slave Mode) OBICK Period OBICK Pulse Width Low OBICK Pulse Width High OLRCK Edge to OBICK “↑” (Note 15) OBICK “↑” to OLRCK Edge (Note 15) OLRCK to SDTO (MSB) OBICK “↓” to SDTO MS0134-J-01 Symbol min fCLK dCLK dCLK typ max Units 2.048 40 28 24.576 60 72 MHz % % fCLK dCLK dCLK 2.048 40 28 24.576 60 72 MHz % % fCLK dCLK dCLK 8.192 40 28 24.576 60 72 MHz % % fs Duty 8 48 48 52 kHz % fs Duty Duty 8 48 96 52 kHz % % fs Duty Duty 32 48 96 52 kHz % % tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 325 130 130 45 45 40 25 ns ns ns ns ns ns ns tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 162 65 65 45 45 40 25 ns ns ns ns ns ns ns tBCK tBCKL tBCKH tBLR tLRB tLRS tBSD 162 65 65 45 45 ns ns ns ns ns ns ns 50 50 50 50 50 40 40 2008/06 -7- [AK4120] Parameter Symbol min typ Audio Interface Timing Input#2(Master Mode) at Path Mode 1 BICK Frequency fBCK 64fs BICK Duty dBCK 50 BICK “↓” to LRCK tMBLR −25 BICK “↓” to SDTO tBSD −25 SDTI2 Hold Time from BICK “↑” tSDH 50 SDTI2 Setup Time to BICK “↑” tSDS 50 Input#2 (Master Mode) at Path Mode0 and 3 Output (Master Mode) fBCK 64fs BICK Frequency dBCK 50 BICK Duty tMBLR −20 BICK “↓” to LRCK tBSD −20 BICK “↓” to SDTO tSDH 40 SDTI2 Hold Time from BICK “↑” tSDS 25 SDTI2 Setup Time to BICK “↑” Note 11. Path Mode2 Path Mode3 min=2.048MHz Note 12. Path Mode 1 max=48kHz Note 13. Path Mode2 Path Mode3 min=8kHz Note 14. BICK IBICK1, IBICK2, OBICK LRCK L/R ILRCK1, ILRCK2, OLRCK Note 15. LRCK BICK MS0134-J-01 max Units 25 40 Hz % ns ns ns ns 20 30 Hz % ns ns ns ns 2008/06 -8- [AK4120] Parameter Control Interface Timing (3-wire Serial mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” Control Interface Timing (I2C® Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 16) SDA Setup Time to SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Maximum Pulse Width of Spike Noise Suppressed by Input Filter Power-down & Reset Timing PDN Pulse Width (Note 17) Symbol min tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 40 40 150 50 50 fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP 4.7 4.0 4.7 4.0 4.7 0 0.25 4.0 tPD 150 typ max Units ns ns ns ns ns ns ns ns 100 1.0 0.3 30 kHz μs μs μs μs μs μs μs μs μs μs ns ns Note 16. 300ns SCL Note 17. PDN “L” Note 18. I2C Philips Semiconductors MS0134-J-01 2008/06 -9- [AK4120] ■ 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD 70%VDD SDTO 30%VDD tSDS tSDH VIH SDTI VIL Audio Interface Timing at Slave Mode Note: MCLK BICK LRCK SDTI IMCLK1, IMCLK2,OCLK IBICK1,IBICK2,OBICK ILRCK1,ILRCK2,OLRCK SDTI1,SDTI2 MS0134-J-01 2008/06 - 10 - [AK4120] LRCK 50%VDD tMBLR dBCK 50%VDD BICK tBSD 50%VDD SDTO tSDS tSDH VIH VIL SDTI Audio Interface Timing at Master Mode VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS C1 CDTI tCDH C0 R/W VIH A4 VIL WRITE Command Input Timing (3-wire Serial mode) tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 D0 VIH VIL WRITE Data Input Timing (3-wire Serial mode) MS0134-J-01 2008/06 - 11 - [AK4120] VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Start I2C Bus mode Timing tPD VIH PDN VIL tPDV 70%VDD SDTO 30%VDD Power-down & Reset Timing MS0134-J-01 2008/06 - 12 - [AK4120] ■ AK4120 (Input#1 1 Path Mode 0 1 02H PATH1-0 “00” Input#2) 4 PATH1-0 bit Input#1 Input# IMCLK1 Volume#2 Volume#2 1 “01” OMCLK Volume#1 Volume Input#1 Input#2 4 IMCLK2 OMCLK Volume#1 2 “10” Input#1 SRC Volume#2 3 “11” Input#2 SRC Volume#2 5 6 1. Path Mode Note: Path Mode PW bit (PW bit= “0”) MS0134-J-01 2008/06 - 13 - [AK4120] I2C SDTI1 ILRCK1 I2S PDN VDD Input#1 Audio I/F Sample Rate Converter VSS Volume#1 TEST IBICK1 IMCLK1 OMCLK IMCLK2 SDTI2 ILRCK2 Input#2 Audio I/F Output Audio I/F Volume#2 IBICK2 SDTO OLRCK OBICK μ P I/F I2MODE CAD0 CSN/CAD1 CCLK/SCL CDTI/SDA 3. Path Mode I2C OMODE (Input#1 SRC + Mixer) I2S PDN VDD SDTI1 Sample Rate Converter ILRCK1 VSS Volume#1 TEST IBICK1 IMCLK1 OMCLK IMCLK2 SDTI2 ILRCK2 Input#2 Audio I/F Output Audio I/F IBICK2 SDTO OLRCK OBICK μ P I/F I2MODE CAD0 CSN/CAD1 CCLK/SCL CDTI/SDA OMODE 4. Path Mode1(Input#2 SRC) MS0134-J-01 2008/06 - 14 - [AK4120] I2C SDTI1 ILRCK1 I2S PDN VDD Input#1 Audio I/F VSS TEST IBICK1 IMCLK1 OMCLK IMCLK2 SDTI2 ILRCK2 Output Audio I/F Volume#2 IBICK2 SDTO OLRCK OBICK μ P I/F I2MODE CAD0 CSN/CAD1 CCLK/SCL CDTI/SDA 5. Path Mode2(Input#1 I2C I2S OMODE ) PDN VDD SDTI1 VSS ILRCK1 TEST IBICK1 IMCLK1 OMCLK IMCLK2 SDTI2 ILRCK2 Input#2 Audio I/F Output Audio I/F Volume#2 IBICK2 SDTO OLRCK OBICK μ P I/F I2MODE CAD0 CSN/CAD1 CCLK/SCL CDTI/SDA 6. Path Mode3(Input#2 MS0134-J-01 OMODE ) 2008/06 - 15 - [AK4120] ■ Path Mode I2MODE 3,4Input#1 PDN pin= “H” OMODE Path Mode 0 1 2 3 Synchronizing Group A SDTI1 SDTI2 SDTI1, SDTO SDTI2, SDTO Path Mode 0 1 2 3 ILRCK1, IBICK1 Input (Not used) Input (Not used) Path Mode 0 1 2 3 Input#2 3, 4 SRC Active Active (Not used) (Not used) 2. Clock Synchronizing Group B SDTI2, SDTO SDTO - IMCLK1 IMCLK2 Input (Not used) (Not used) Input Input (Not used) (Not used) (Not used) 3. Master Clock ILRCK2, IBICK2 I2MODE = “L” I2MODE = “H” (Not used) Output Input Output (Not used) (Not used) (Not used) Output (Not used) SDTI1 SDTI2 SDTI1 OMCLK Input Input (Not used) Input OLRC, OBICK OMODE= “L” OMODE= “H” Output Input Output Input Output (Not used) Output Input 4. LRCK/BICK (1) Path Mode 0 IMCLK1 OMCLK IMCLK1 ILRCK1 STDI2 OLRCK OBICK OLRCK IBICK2 OLRCK OBICK Input#2 (2) Path Mode 1 IMCLK2 OMCLK Input#2 Output IMCLK2 ILRCK2 OMCLK OLRCK (3) Path Mode 2 IMCLK1 ILRCK1 OLRCK OBICK pin OLRCK SDTO ILRCK1 IBICK1 ILRCK1 IBICK1 OBICK (4) Path Mode 3 OMCLK OLRCK OLRCK OMCLK ILRCK2 Input#2 ILRCK2 SDTI2 OLRCK1 OBICK1 Input#2 OBICK IBICK2 ILRCK2 IBICK2 pin MS0134-J-01 2008/06 - 16 - [AK4120] IMCLK1,IMCLK2 OMCLK 01H IMCKS1, IMCKS2, OMCKS bit LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96kHz MCLK (MHz) 256fs 8.1920 11.2896 12.2880 22.5792 24.5760 5. 512fs 16.384 22.5792 24.576 N/A N/A (256fs/512fs) 512fs 48kHz BICK (MHz) 64fs 2.0480 2.8224 3.0720 5.6448 6.1440 ■ AK4120 Path Mode1 Volume#2 (Volume#1 Volume#2) Input#1 Input#2 SRC Path Mode0 Input#2 SRC Path Mode3 Input#2 –83.25dB 12dB 0.75 dB 3-6H MS0134-J-01 Volume#1 Path Mode0 Path Mode 2 Input#1 2008/06 - 17 - [AK4120] ■ 4 MSB 2’s I2S DIFI11 DIFI10 0 0 0 1 1 0 1 1 X X 6. SDTI1 SDTI1 20bit, MSB justified 20bit, I2S 20bit, LSB justified 16bit, LSB justified 20bit, I2S LRCK H/L L/H H/L H/L L/H (X: Don’t care) L L L L H DIFI21 DIFI20 0 0 0 1 1 0 1 1 X X 7. SDTI2 SDTI2 20bit, MSB justified 20bit, I2S 20bit, LSB justified 16bit, LSB justified 20bit, I2S LRCK H/L L/H H/L H/L L/H (X: Don’t care) L L L L H DIFO1 DIFO0 0 0 0 1 1 0 1 1 X X 8. SDTO SDTO 20bit, MSB justified 20bit, I2S 20bit, LSB justified 16bit, LSB justified 20bit, I2S LRCK H/L L/H H/L H/L L/H (X: Don’t care) L L L L H I2S I2S Note: 6 00H D5-D0 bit I2S pin SDTO BICK PW bit 8 SDTI BICK Default Default Default (PW bit= “0”) MS0134-J-01 2008/06 - 18 - [AK4120] LRCK 0 1 12 13 14 15 16 31 0 1 12 13 14 15 16 31 0 1 0 1 BICK (64fs) SDTI 16bit Don’t care 15 0 Don’t care 15 0 Don’t care 15 0 15 0 15:MSB, 0:LSB SDTI 20bit 19 Don’t care 18 17 16 19 18 16 17 19:MSB, 0:LSB Lch Data Rch Data 7. 16bit/20bit LSB justified LRCK 0 1 2 18 19 20 30 31 0 1 2 18 19 20 30 31 BICK (64fs) SDTI 19 18 1 0 Don’t care 19 18 1 0 Don’t care 19 18 0 1 20:MSB, 0:LSB Lch Data Rch Data 8. 20bit MSB justified LRCK 0 1 2 3 19 20 21 31 0 1 2 3 19 20 21 31 BICK (64fs) SDTI 19 18 1 0 Don’t care 19 18 1 0 Don’t care 19 19:MSB, 0:LSB Lch Data 9. 20bit I Rch Data 2 S MS0134-J-01 2008/06 - 19 - [AK4120] ■ AK4120 CAD0 pin, CAD1 pin “1” 2 I2C mode CAD0 pin PDN pin * PDN pin= “L” * AK4120 “L” I2C (1) 3 (I2C = “L”) 3 I/F pin: CSN, CCLK, CDTI I/F address(2bits), Read/Write(1bit), Register address(MSB first, 5bits), Control data(MSB first, 8bits) CCLK CSN CCLK 5MHz(max) Chip CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 1 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (C1:1,C0:CAD0) Read/Write (Fixed to “1” : Write only) Register Address Control Data 10. 3 Note: 00H I/F 06H MS0134-J-01 2008/06 - 20 - [AK4120] (2) I2C(I2C= “H”) AK4120I 2C(max:100kHz) (max:400kHz) (2)-1. WRITE I2C (Start Condition) ( 17) 8 (R/WN) IC CAD1-0 pin AK4120 (Acknowledge) SDA( R/WN bit “1” 2 “0”( MSB first( (Stop Condition) “L” “H”( 11IC “H” SCL SDA “H” “L” 7 5 “00100” 12) ( 2 18) R/W bit “0” () 13) 3 14) AK4120 8 MSB first 3 8 SCL “H”SDA 17) AK4120 1 “06H” “00H” “00H”~ “06H” “07H” “H” SCL SDA ) SDA “H” “L” “L” S T A R T SDA S ( SCL “H” S T O P R/WN= “0” Slave Address Sub Address(n) A C K 11. I 0 19) 0 Data(n) Data(n+x) Data(n+1) A C K A C K A C K A C K P A C K 2 C 1 0 0 CAD1 CAD0 R/WN A3 A2 A1 A0 D3 D2 D1 D0 (CAD1, CAD0 ) 12. 1 0 0 0 A4 13. D7 D6 2 D5 D4 14. 3 MS0134-J-01 2008/06 - 21 - [AK4120] (2)-2. READ R/WN bit “1” AK4120 READ “06H” “00H” “00H” ~ “06H” H AK4120 2 READ (2)-2-1. AK4120 (READ “n+1” AK4120 WRITE ) “n” READ (R/WN bit= “1”) 1 READ S T A R T SDA S S T O P R/WN= “1” Slave Address Data(n) A C K Data(n+1) A C K Data(n+x) Data(n+2) A C K A C K A C K P A C K 15. CURRENT ADDRESS READ (2)-3-2. READ (R/WN bit= “1”) WRITE WRITE (R/WN bit= “0”) AK4120 READ (R/WN bit= “1”) AK4120 1 READ S T A R T SDA S S T A R T R/WN= “0” Sub Address(n) Slave Address A C K S A C K S T O P R/WN= “1” Slave Address Data(n) A C K Data(n+x) Data(n+1) A C K A C K A C K P A C K 16. RANDOM ADDRESS READ MS0134-J-01 2008/06 - 22 - [AK4120] SDA SCL S P start condition stop condition 17. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION 2 C 18. I SDA SCL data line stable; data valid 19. I Note: 00H 06H 00H Read change of data allowed 2 C Write 06H MS0134-J-01 2008/06 - 23 - [AK4120] ■ AK4120 (PDN) ON PDN pin “L” “L” Power Down 3, 4 SRC Power Down 2*ILRCK1 2*ILRCK2 2053*OLRCK “L” ■ Volume ZTM1-0(01H) (01H: ZELM bit= “0”) L/R 01H:ZELM bit= “1” Volume (3) (1) (2) 20. (1) (2) (3) ZTM1-0 MS0134-J-01 2008/06 - 24 - [AK4120] ■ Addr 00H 01H 02H 03H 04H 05H 06H Register Name Control 1 Control 2 Control 3 Lch Volume#1 Control Rch Volume#1 Control Lch Volume#2 Control Lch Volume#2 Control : PDN pin “L” 00H 06H D7 PW D6 D5 D4 D3 D2 D1 D0 Default 0 DIFO1 DIFO0 DIFI21 0 0 GAIN3 GAIN3 GAIN3 GAIN3 DIFI20 DIFI11 DIFI10 OMCKS IMCKS2 IMCKS1 0 GAIN2 GAIN2 GAIN2 GAIN2 PATH1 GAIN1 GAIN1 GAIN1 GAIN1 PATH0 GAIN0 GAIN0 GAIN0 GAIN0 80H 20H 00H 10H 10H 10H 10H 0 ZELM ZTM1 ZTM0 MUTE2R MUTE2L MUTE1R MUTE1L 0 0 0 0 GAIN6 GAIN6 GAIN6 GAIN6 GAIN5 GAIN5 GAIN5 GAIN5 GAIN4 GAIN4 GAIN4 GAIN4 Read Write ■ Addr 00H Register Name Control 1 Default D7 PW D6 D5 D4 D3 D2 D1 D0 0 DIFO1 DIFO0 DIFI21 DIFI20 DIFI11 DIFI10 0 0 0 0 0 0 0 D4 ZTM0 0 D3 D2 D1 D0 0 OMCKS IMCKS2 IMCKS1 0 0 0 0 DIFI11-0: Input#1( DIFI21-0: Input#2( DIFO1-0: Output( PW : 0: 6 ) 7 ) 8 ) 1: (default) Addr 01H Register Name Control 2 Default IMCKS1: D7 0 0 D6 ZELM 0 D5 ZTM1 1 (IMCLK1) 0: 256fs 1: 512fs IMCKS2: (IMCLK2) 0: 256fs 1: 512fs OMCKS: (OMCLK) 0: 256fs 1: 512fs Note: PW bit=“0” MS0134-J-01 2008/06 - 25 - [AK4120] ZTM1-0 Enable(ZELM bit= “0”) Volume ZTM1 ZTM0 0 0 1 1 0 1 0 1 L/R 48kHz 10.7ms 21.4ms 42.7ms 85.4ms 513/fs 1025/fs 2049/fs 4097/fs 44.1kHz 11.6ms 23.2ms 46.5ms 92.9ms 32kHz 16.0ms 32.0ms 64.0ms 128.0ms Default () 9. ZELM: Volume 0: Enable (Default) 1: Disable Volume “1” Volume “0” Addr 02H Register Name Control 3 Default Path2-0: Path Mode( Mute1L : 0: 1: Mute1R : 0: 1: Mute2L : 0: 1: Mute2R : 0: 1: 1 Volume#1 Lch Volume#1 Rch Volume#2 Lch Volume#2 Rch L/R D7 D6 D5 D4 D3 D2 D1 D0 MUTE2R MUTE2L MUTE1R MUTE1L 0 0 PATH1 PATH0 0 0 0 0 0 0 0 0 3 6 ) MS0134-J-01 2008/06 - 26 - [AK4120] Addr 03H 04H 05H 06H Register Name Lch Volume#1 Control Rch Volume#1 Control Lch Volume#2 Control Rch Volume#2 Control Default D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 GAIN6 GAIN6 GAIN6 GAIN6 GAIN5 GAIN5 GAIN5 GAIN5 GAIN4 GAIN4 GAIN4 GAIN4 GAIN3 GAIN3 GAIN3 GAIN3 GAIN2 GAIN2 GAIN2 GAIN2 GAIN1 GAIN1 GAIN1 GAIN1 GAIN0 GAIN0 GAIN0 GAIN0 0 0 0 1 0 0 0 0 GAIN6-0 : . ∼12dB(Step 0.75dB) : -83.25dB GAIN6-0 00H 01H 02H : 9H 10H 11H : 7DH 7EH 7FH Volume Level 12dB 11.25dB 10.5dB : 0.75dB 0dB -0.75dB : -81.75 -82.50 -83.25 10. Default Note: |Gain error| < 0.3dB, |Step error| < 0.1dB. MS0134-J-01 2008/06 - 27 - [AK4120] 21 AKD4120 :VDD=3.3V, 3-wire serial control mode, Chip Address = “10” Path Mode 0, Input#2 and Output are slave mode Digital Audio Source (DIR) IMCLK2 24 SDTI1 SDTI2 23 3 IBICK1 IBICK2 22 4 ILRCK1 ILRCK2 21 5 TEST I2MODE 20 6 I2S VDD 19 7 I2C VSS 18 8 CAD0 OMODE 17 9 CSN/CAD1 OMCLK 16 10 CCLK/SCL SDTO 15 11 CDTI/SDA OBICK 14 12 PDN OLRCK 13 1 IMCLK1 2 AK4120 Top View uP ADC Analog Input 3.3V Supply 0.1u Audio DSP 21. MS0134-J-01 2008/06 - 28 - [AK4120] 24pin VSOP (Unit: mm) 1.25±0.2 *7.8±0.15 13 A 7.6±0.2 *5.6±0.2 24 12 1 0.22±0.1 0.65 0.15±0.05 0.1±0.1 0.5±0.2 Detail A Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° ■ : : : ( ) MS0134-J-01 2008/06 - 29 - [AK4120] AKM AK4120VF AAXXXX Contents of AAXXXX AA: Lot# XXXX: Date Code Date (YY/MM/DD) 02/01 08/06/27 Revision 00 01 Reason Page Contents 9 Note 17 • • • • • • MS0134-J-01 2008/06 - 30 -