5 4 3 DVDD_33V DVDD_33V DVDD_18V GP4 GP3 GP2 C1 220uF C2 0.1uF DVDD_33V C4 0.1uF C5 0.1uF C6 0.1uF 3 2 1 TEST2 C8 0.1uF C9 0.1uF C10 0.1uF C11 220uF C12 0.1uF C13 0.1uF EECK 3 2 1 EEDO R37 R38 R39 47k 47k 47k TXD2_1 TXD2_0 Port 2 mode J17 J16 0 0 MII mode 1 0 reverse MII mode 1 0 RMII mode 1 1 RGMII mode TXD2_2 (J6)---Port 2 in force mode MDC (J7)Polarity of IRQ 0:IRQ pin high actice 1:IRQ pin low actice TXE (J11) 0:Port 2 disable 1:Port 1 disable CRS2 COL2 RXER2 RXC2 RXDV2 RXD2_3 RXD2_2 RXD2_1 RXD2_0 TEST2 TX1+ TX1- AVDD_18V 1 DVDD_33V TXD2_3 GP6 GP5 J3 1 J4 1 J5 1 2 JUMPER 2 JUMPER 2 JUMPER R5 IO16 IOWAIT TXD2_0 TXD2_1 J16 1 J17 1 2 JUMPER 2 JUMPER R6 R36 4.7k 4.7k TXD2_2 J6 1 2 JUMPER R33 4.7k MDC J7 1 2 JUMPER R10 4.7k TXE2 J8 1 2 JUMPER R11 4.7k EECS 1.4k/1% R2 HEADER_3 RX1+ RX1- R34 4.7k 4.7k/NC Mount R34 use SCLK as system clock NC:use internal system clock DVDD_18V DVDD_33V AVDD_18V U3 C17 0.1uF C19 0.1uF C20 0.1uF C21 220uF C22 0.1uF C23 0.1uF VCNTL VREF C25 0.1uF X1 X2 DVDD_33V L1 AVDD_33V F.B/120/SO805 2SB1386 VCNTL B E Q1 C DVDD_18V L2 AVDD_18V F.B/120/SO805 J15 C15 0.1uF B L3 1 TEST_POINT F.B/120/SO805 J91 R40 2 JUMPER 75k DVDD_33V BWLED1 BWLED2 BWLED3 BWLED4 C31 BWLED5 BWLED6 BWLED7 U4 1 2 3 4 EECK EEDO EEDI CS VCC SK DC DI ORG DO GND 8 7 6 5 0.1uF 93LC46 DM9016 for uP Interface TXC2 TXE2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TXC2 TXE2 VCC3 TXD2_0 TXD2_1 TXD2_2 TXD2_3 DVDD18 MDIO MDC GND PWRST# EECS EECK EEDO EEDI DVDD33 (GP3_7) SD31 (GP3_6) SD30 GND (GP3_5) SD29 (GP3_4) SD28 (GP3_3) SD27 (GP3_2) SD26 DVDD33 (GP3_1) SD25 (GP3_0) SD24 (GP2_7) SD23 (GP2_6) SD22 GND (GP2_5) SD21 (GP2_4) SD20 TXD2_0 TXD2_1 TXD2_2 TXD2_3 MDIO MDC PWRST# EECS EECK EEDO EEDI TX0+ TX0RX0+ RX0TX1+ TX1RX1+ RX1- BWLED[0..7] BWLED4 BWLED5 BWLED6 BWLED7 SD29 SD28 SD27 SD26 MII Interface SD25 SD24 SD23 SD22 RXD2_0 RXD2_1 RXD2_2 RXD2_3 RXDV2 RXC2 CRS2 COL2 RXER2 B RXD2_[0..3] SD21 SD20 RXD2_[0..3] RXDV2 RXC2 CRS2 COL2 RXER2 TXD2_[0..3] MDIO R35 4.7k TXD2_[0..3] TXD2_0 TXD2_1 TXD2_2 TXD2_3 TXE2 TXC2 TXE2 TXC2 X2 X1 2 3 U10 MDIO MDC Y1 10uF SD16 SD17 SD18 SD19 SD14 SD15 SD12 SD13 RESET_IC_(AP1701DW) SD10 SD11 C32 SD4 SD5 SD6 SD7 SD8 SD9 25MHz/49US C29 C30 22pF 22pF CMD CS# IOW# A PWRST# IOR# IRQ SD0 SD1 SD2 SD3 10k 1 2 3 4 5 6 7 GP0 GP1 GP2 GP3 GP4 GP5 GP6 4 3 A MDIO MDC Davicom Semiconductor Inc. J14 Title 3 Port Switch + uP Interface Chip HEADER_7 Size B Date: 5 C LNK0_LED SPD0_LED FDX0_LED LNK1_LED SPD1_LED FDX1_LED 2 D1 1N4148 1 R12 1 C A PWRST# CMD CS# IOW# IOR# IRQ IO16 IOWAIT WOL BWLED[0..7] BWLED0 BWLED1 BWLED2 BWLED3 SD31 SD30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DVDD_33V D LNK0_LED SPD0_LED FDX0_LED LNK1_LED SPD1_LED FDX1_LED 3 DVDD_33V VCNTL VREF AVDD33 DVDD33 X1 X2 GND LNK1_LED SPD1_LED FDX1_LED LNK0_LED SPD0_LED FDX0_LED WOL GP6 GP5 GP4 GP3 GP2 SCLK GP1 GP0 BWLED0 DVDD18 BWLED1 BWLED2 BWLED3 BWLED4 GND BWLED5 BWLED6 BWLED7 SD[00..31] SD16 SD17 SD18 SD19 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31 TX0+ TX0RX0+ RX0TX1+ TX1RX1+ RX1- CMD CS# IOW# DVDD33 IOR# IRQ SD0 SD1 SD2 SD3 GND SD4 SD5 SD6 SD7 SD8 SD9 DVDD33 SD10 SD11 GND SD12 SD13 DVDD18 SD14 SD15 GND SD16 (GP2_0) SD17 (GP2_1) SD18 (GP2_2) SD19 (GP2_3) DVDD33 C27 0.1uF LNK1_LED SPD1_LED FDX1_LED LNK0_LED SPD0_LED FDX0_LED WOL GP6 GP5 GP4 GP3 GP2 SCLK GP1 GP0 BWLED0 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 SD[00..31] SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 TP / LED Interface BGRESG BGRES AVDD33 RX0RX0+ AGND AGND TX0TX0+ AVDD18 AVDD33 RX1RX1+ AGND AGND TX1TX1+ AVDD18 TEST3 TEST2 TEST1 DVDD33 RXD2_0 RXD2_1 RXD2_2 RXD2_3 RXDV2 GND RXC2 RXER2 COL2 CRS2 C16 220uF uP Interface PWRST# CMD CS# IOW# IOR# IRQ IO16 IOWAIT WOL 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AVDD_33V 16-Bit 32-Bit 8-Bit Reserved Port 2 force mode GP2: 0:100M status 1:10M status GP3: 0:full duplex status 1:half duplex status GP4: 0:link status 1:not link status TX0+ TX0- J12 1:2-Port 0:3-Port AVDD_33V EECS GP4 GP3 GP2 RX0+ RX0- J12 1.2 Short 3-Port Mode 2.3 Short 2-Port Mode J13 EECK EEDO 0 0 0 1 1 0 1 1 J13 4.7k R3 HEADER_3 C C14 0.1uF 4.7k 4.7k 4.7k DVDD_33V J12 D C7 0.1uF R7 R8 R9 2 TXD2_3 ISA pin control J3 0:GP5/6 as normal general purpose pins 1:GP5 as IO16 GP6 as IOWAIT in used ISA bus only 2 Document Number Rev 1.0 DM9016_EVB_BOARD Wednesday, March 18, 2009 Sheet 1 1 of 3 4 U5 AP1117-3.3V OUT O IN OUT RXDV2 RXC2 CRS2 COL2 RXER2 TXE2 MDC CRS2 COL2 TXD2_3 TXD2_2 TXD2_1 TXD2_0 TXE2 TXC2 C IOW# IOR# IO16 RXER2 RXC2 RXDV2 RXD2_0 RXD2_1 RXD2_2 RXD2_3 MDC MDIO IOWAIT CS# CMD IRQ PWRST# B 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 SD16 SD17 SD18 SD19 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31 WOL SD[00..31] 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DVDD_5V DVDD_5V DGND 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 MDIO MDC HEADER_20X2 HEADER_16X2 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 JP2 J11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PWRST# CMD CS# IOW# IOR# IRQ IO16 IOWAIT WOL HEADER_16 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 PWRST# CMD CS# IOW# IOR# IRQ IO16 IOWAIT WOL HEADER_16X2 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 JP1 JP4 TXE2 TXC2 SD[00..31] SD16 SD17 SD18 SD19 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31 A C34 0.1uF TXD2_[0..3] uP Interface B C33 220uF DVDD_5V MDIO MDC SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 D 4 DVDD_33V DVDD_33V DVDD_33V DGND DGND DGND DVDD_5V DVDD_5V TXD2_0 TXD2_1 TXD2_2 TXD2_3 TXE2 TXC2 C RXD2_[0..3] I TXD2_[0..3] 1 DVDD_33V G D RXD2_0 RXD2_1 RXD2_2 RXD2_3 RXDV2 RXC2 CRS2 COL2 RXER2 DVDD_5V GND RXD2_[0..3] 2 RXD2_0 RXD2_1 RXD2_2 RXD2_3 CRS2 COL2 RXDV2 RXER2 RXC2 TXC2 TXD2_0 TXD2_1 TXD2_2 TXD2_3 MDIO MII Interface 3 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 5 A Davicom Semiconductor Inc. Title 3 Port Switch + uP Interface Chip Size A Date: 5 4 3 Document Number Rev 1.0 DM9016_EVB_BOARD Wednesday, March 18, 2009 2 Sheet 2 of 1 3 5 4 3 TP / LED Interface U6 TX0TX0+ RX+ NC RXMCT NC TX+ NC TX- JP3 RJ-45_LED 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 MAGCOM_HS9024 R13 R14 49.9/1% R15 R16 49.9/1% 49.9/1% C36 0.1uF BWLED[0..7] D 49.9/1% LED1+ LED1- RX0+ RDNC RD+ NC CT TDNC TD+ 14 13 1 2 3 4 5 6 7 8 LED2+ LED2- RX0- LNK0_LED SPD0_LED FDX0_LED LNK1_LED SPD1_LED FDX1_LED BWLED[0..7] BWLED0 BWLED1 BWLED2 BWLED3 AVDD_18V TX0+ TX0RX0+ RX0TX1+ TX1RX1+ RX1- LNK0_LED SPD0_LED FDX0_LED LNK1_LED SPD1_LED FDX1_LED 1 16 15 D TX0+ TX0RX0+ RX0TX1+ TX1RX1+ RX1- 2 R17 R18 R19 75/1% 75/1% 75/1% C35 C37 0.1uF C38 0.1uF BWLED4 BWLED5 BWLED6 BWLED7 0.01uF/2KV RJ45_SPD RJ45_LINK R20 R21 512 512 U2A 74HC04 C C SPD0_LED 1 2 U2B LNK0_LED 3 4 DVDD_33V R22 330 LNK0_LED SPD0_LED FDX0_LED C D3 C D2 LEDA C D4 LEDA C D6 C D5 LEDA C D7 LEDA LEDA 4 3 2 1 5 6 7 8 74HC04 AVDD_18V R23 330 LNK1_LED SPD1_LED FDX1_LED LEDA 4 3 2 1 RX1- 1 2 3 4 5 6 7 8 RX1+ TX1TX1+ DVDD_33V C D11 C D8 LEDA C D10 LEDA LEDA LEDA 4 3 2 1 R24 5 6 7 8 49.9/1% R32 330 BWLED3 BWLED2 BWLED1 BWLED0 C D13 C D15 C D12 LEDA C D14 LEDA LEDA LEDA 4 3 2 1 5 6 7 8 R25 R26 49.9/1% 49.9/1% 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 B C40 0.1uF R29 R30 R31 75/1% 75/1% 75/1% C39 49.9/1% C41 0.1uF C42 0.1uF 0.01uF/2KV C43 A Davicom Semiconductor Inc. 0.1uF Title C44 3 Port Switch + uP Interface Chip Size A 0.1uF Date: 4 RXNC RX+ MCT NC TXNC TX+ R27 A 5 RDNC RD+ NC CT TDNC TD+ MAGCOM_HS9016 R28 330 C D9 JP4 RJ-45 U7 5 6 7 8 B BWLED7 BWLED6 BWLED5 BWLED4 MAGCOM HS-9016, HS-9024 DELTA LFE8563-DC, LFE8563T-DC 3 Document Number Rev 1.0 DM9016_EVB_BOARD Wednesday, March 18, 2009 2 Sheet 3 of 1 3