IMP16C550

IMP16C550
Data Communications
Universal Asynchronous
Receiver/Transmitter
(UART)with 16-BYTE FIFO's
Key Features
•
5V Operation
•
Full duplex asynchronous receiver and transmitter
•
Easily interfaces to most popular microprocessors
Independently controlled transmitter, receiver,
line status, and data set interrupts
•
Programmable baud rate generator allows
division of any input clock by 1 to (216-1) and
generates the internal 16 x clock
•
Independent receiver clock input
•
MODEM control functions (CTS, RTS, DSR,
DTR, RI,and DCD)
40-PIN DIP
1
Fully prioritized interrupt systems controls
•
16 byte FIFO for reduced CPU overhead
44-PIN PLCC
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N.C.
D4
D3
D2
D1
D0
VCC
RI •
CD •
DSR •
CTS •
N.C.
48
47
46
45
44
43
42
41
40
39
38
37
1
36
N.C.
D5
2
35
RESET
D6
3
34
OP1 •
D7
4
33
DTR •
RCLK
5
32
RTS •
N.C.
6
31
OP2 •
RX
7
30
INT
TX
8
29
RXRDY •
CS0
9
28
A0
IMP16C550
21
22
23
N.C.
DDIS •
TXRDY •
24
20
IOR
AS
19
IOR •
N.C.
18
25
GND
12
17
A2
BAUDOUT •
IOW
A1
26
16
27
11
-IOW
10
15
CS1
CS2 •
XTAL2
IMP16C550
N.C.
13
7
8
9
10
11
12
13
14
15
16
17
MR
OUT1•
DTR•
RTS•
OUT2•
NC
INTRPT
RXRDY•
A0
A1
A2
14
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2•
BAUDOUT•
39
38
37
36
35
34
33
32
31
30
29
N.C.
6
5
4
3
2
1
44
43
42
41
40
D4
D3
D2
D1
D0
NC
VCC
RI•
DCD•
DSR•
CTS•
Pin Configuration
18
19
20
21
22
23
24
25
26
27
28
VCC
RI•
DCD•
DSR•
CTS•
MR
OUT1•
DTR•
RTS•
OUT2•
INTRPT
RXRDY•
A0
A1
A2
ADS•
TXRDY•
DDIS
DISTR
DISTR•
•
The UART performs serial to parallel conversion on
data characters received from a peripheral device or a
MODEM, and parallel-to-serial conversions on data characters received from the CPU. The CPU can read the complete
status of the UART at any time during the functional operation.
Status information reported includes the type and condition of
the transfer operation being performed by the UART, as well
as any error conditions (party, overrun, framing, or break
detect).
XTAL1
XTAL2
DOSTR•
DOSTR
VSS
NC
DISTR•
DISTR
DDIS
TXRDY•
ADS•
I
M
P
1
6
C
5
5
0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Internal diagnostic capabilities:
The IMP16C550 Universal Asynchronous Receiver
Transmitter (UART) is a CMOS-VLSI communication
device in a single package.
False start bit detection
Complete status reporting capabilities
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
•
General Description
Fully programmable serial interface
characteristics:
- 5, 6, 7, or 8 bit characters
- Even, odd, or no-parity bit generation and
detection
- 1, 1.5, or 2 stop bit generation
- Baud generation (DC to 56k baud)
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
SIN
SOUT
CS0
CS1
CS2•
BAUDOUT•
XTAL1
XTAL2
DOSTR•
VSS
Line break generation and detection
- Break, parity overrun, and framing error simulation
•
•
•
•
- Loopback controls for communications link fault
isolation
Adds or deletes standard asynchronous
communication bits (start, stop, and parity) to or
from a serial data stream
•
Tri-State® TTL drive capabilities for bidirectional data bus and control bus
XTAL1
•
•
48-PIN TQFP
Daily Silver IMP
IMP16C550
Description
The IMP16C550 is an enhanced version of the
IMP16C450 Universal Asynchronous Receiver/
Transmitter (UART). The improved specifications
existing
with
interface
easy
ensure
microprocessors systems with DMA controller.
Functionally identical to the IMP16C450 on power
up (in Character Mode) the IMP16C550 can be
configured into an alternate mode(FIFO mode) to
relieve the CPU of excessive software overhead
due to interrupts.
In FIFO mode, internal FIFO’s are activated
allowing 16 bytes (plus 3 bits of error data per byte
in the RCVR FIFO) to be stored in both receive
and transmit modes. All the logic is on chip to
minimize system overhead and maximize system
efficiency. Two FIFO control pins have been added
to allow signaling of DMA transfers.
The UART performs serial-to-parallel conversion
on data characters received from a peripheral
device or a MODEM, and parallel-to-serial
conversion on data characters received from the
CPU. The CPU can read the complete status of
the UART at any time during the functional
operation. Status information reported includes
the type and condition of the transfer operations
being performed by the UART, as well as any error
conditions (parity, overrun, framing, or break
interrupt).
The UART includes a programmable baud rate
generator that is capable of dividing the timing
reference clock input by divisors of 1 to (216-1),
and producing a 16x clock to drive the internal
transmitter logic. Provisions are also included to
use this 16x clock to drive the receive logic. The
UART has complete MODEM-control capability,
and a processor interrupts system. Interrupts can
be programmed to the user’s requirements,
minimizing the computing required to handle the
communications link. UART is designed to work
either in a polled or an interrupt driven
environment selected by software.
The UART is fabricated using IMP’s advanced
double metal CMOS process.
ADDRESS BUS
DATA BUS
PARALLEL I/O
INTERFACE
SYSTEM
PROCESSOR
DATA BUS
BUFFER
RECEIVER
SECTION
A0
A1
A2
CONTROL BUS
INTERRUPT
SELECT AND
CONTROL
LOGIC
INTERRUPT
ENABLE AND
CONTROL
TRANSMITTER
SECTION
MODEM
CONTROL AND
STATUS LOGIC
SERIAL DATA
IN
TO/FROM
PERIPHERAL
MODEM OR
DATA SET
SERIAL DATA
OUT
MODEM CONTROL
FUNCTIONS
TO/FROM MODEM
OR DATA SET
MEMO"RY
FIGURE 1 – IMP16C550 General System Configuration
2
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IMP16C550
INTERNAL
DATA BUS
(1-8)
D7-D0
DATA
BUS
BUFFER
RECEIVER
BUFFER
REGISTER
RECEIVER
SHIFT
REGISTER
LINE
CONTROL
REGISTER
RECEIVER
TIMING
&
CONTROL
(10)
SIN
(9)
RCLK
(15)
BAUDO
UT
28
A0
27
DIVISOR
LATCH(LS)
A1
26
A2
12
CS0
DIVISOR
LATCH(MS)
13
CS1
14
BAUD
GENERATOR
CS2*
TRANSMITTEF
TIMING
&
CONTROL
25
ADS*
35
MR*
SELECT
AND
CONTROL
LOGIC
22
DISTR
21
DISTR*
LINE
STATUS
REGISTER
19
DOSTR
18
DOSTR*
TRANSMITTER
SHIFT
REGISTER
FIFO
23
DDIS
24
(11)
SOUT
TXRDY*
16
MODEM
CONTROL
REGISTER
XTAL1
17
XTAL2
29
RXRDY*
(40)
+5V
SUPPLY (20)
GND
POWER
MODEM
CONTROL
LOGIC
MODEM
STATUS
REGISTER
INTERRUPT
ENABLE
REGISTER
INTERRUPT
CONTROL
LOGIC
(32)
(36)
(33)
(37)
(38)
(39)
(34)
(31)
(30)
RTS
CTS
DTR
DSR
DCD
R1
OUT1
OUT2
INTRPT
INTERRUPT
ID
REGISTER
FIFO
CONTROL
REGISTER
FIGURE 2 – IMP16C550 Block Diagram
3
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IMP16C550
IOR
DISTR
RECEIVER ENABLE
IOW
DOSTR
IMP16C550A
MICROCOMPUTE
R
SYSTEM
DATA
BUS
8-BIT BUS
TRANSCEIVER
DATA BUS
DRIVER DISABLE
D7-D0
DDIS
FIGURE 3-Typical Interface for a high-capacity data bus
A0
A1
A2
80286
MICROPR
OCESSOR A3-A23
DATA PORT
D7-D0
8237A-5
CLK
80284
CLOCK
GENERATOR
AND DRIVER
RESET
CS0
CS1
CS2
ADDRESS
DECODE
DataDMA
port
CONTROLLEF
DB0
D7-D0
DB1
DB2
8228/8238 DB3
SYSTEM DB4
DB5
CONTROLL
DB6
ER
DB7
IOR
IOW
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DISTR
DOSTR
TXRDY
RXRDY
MR VSS
XTAL1
XTAL2
BAUDOUT
RCLK
DTR
RTS
IMP16C550A
D7-D0
RESET
A0
A1
A2
OUT1
OUT2
RS-232
Interface
R1
RLSD
DSR
CTS
SOUT
SIN
INTRPT
DDIS
DISTR
DOSTR
ADS
VCC
+5V
FIGURE4-Typical 16 -Bit Microprocessor/RS-232 Terminal Interface using the FIFO UART
4
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IMP16C550
Pin Description
Note: In the following descriptions, a low represents a logic 0 and a high represents logic 1.
Mnemonic
CS0,CS1
CS2*
Pin
Type
IN
DISTR*
DISTR
5
PIN # for
40-DIP/
44-PLCC
Description
12:14/14:16
Chip Select pins: When CS0 and CS1 are high and CS2* is low, the chip is
selected. This enables communication between the UART and CPU. The
positive edge of an active Address Strobe signal latches the decoded chip select
signals, completing chip selection. If ADS* is always low, valid chip selects
should stabilize according to the tCSW parameter.
23,24/25,26
Data In strobe: When DISTR is high or DISTR* is low while the chip is selected,
the CPU can read status information or data from the selected UART register.
Note: Only an active DISTR or DISTR* input is required to transfer data from the
UART during a read operation. Therefore, tie either the DISTR input
permanently low or the DISTR* input permanently high, when it is not used.
DOSTR*
DOSTR
IN
18,19/20,21
ADS*
IN
25/28
A2,A1, A0
IN
26:28/29:31
Data Out strobe: When DOSTR is high or DOSTR* is low while the chip is
selected, the CPU can write control words or data into the selected UART
register.
Note: Only an active DOSTR or DOSTR* input is required to transfer data to the
UART during a write operation. Therefore, tie either the DISTR input
permanently low or the DOSTR* input permanently high, when it is not used.
Address Strobe: The positive edge of an active Address Strobe signal (ADS*)
latches the Register Select pins (A0, A1, A2) and chip Selects signal (CS0, CS1,
CS2*).
Note: An Active ADS* input is required when the Register Selects (A0, A1, A2)
signals are not stable for the duration of a read or write operation. If not required,
tie the ADS* input permanently low.
Register select pins: Address signals connected to these 3 inputs select a
UART register for the CPU to read from or write to during data transfer. A table of
register and their address is shown below. Note that the state of the Diver Latch
Access Bit (DLAB), which is the most significant bit of the line control register,
affects the selection of certain UART registers. The DLAB must be set high by
the system software to access the Baud Generator Divisor Latches.
REGISTER ADDRESS
DLAB A2 A1 A0 Register
0
0 0 0 Receiver Buffer Register (read)
0
0 0 0 Transmitter Holding Register (write)
0
0 0 0 Interrupt Enable Register
x
0 1 0 Interrupt Identification Register (read)
x
0 1 0 FIFO Control Register (write)
x
0 1 1 Line Control Register
x
1 0 0 MODEM Control Register
x
1 0 1 Line Status Register
x
1 1 0 MODEM Status Register
x
1 1 1 Scratch Pad Register
1
0 0 0 Divisor Latch Register (Least significant byte)
1
0 0 1 Divisor Latch Register (Most significant byte)
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IMP16C550
Mnemonic
PIN # for
40-DIP/
44-PLCC
Description
Master Reset: When this input is high, it clears all the registers (except the
Register Buffer, Transmitter Holding and Divisor Latches), and the control logic
of the UART. The states of various output signals (SOUT, INTR, OUT1*, OUT2*,
RTS*, DTR*) are affected by an active MR input (Refer to Table 1).this input is
buffered with a TTL-compatible Schmitt Trigger with 0.5V typical hysteresis.
MR
IN
35/39
RCLK
IN
9/10
Receiver Clock: This input is the 16 x baud rate clock for the receiver section of
the chip.
SIN
IN
10/11
Serial Input: Serial data input from communication link such as peripheral
device, MODEM or data set.
CTS*
IN
36/40
DSR*
RLSD*
RI*
Mnemonic
6
Pin
Type
IN
IN
IN
Pin
Type
37/41
38/42
39/43
PIN # for
40-DIP/
Clear to send: When low, this pin indicates that the MODEM or data set is ready
to exchange data. The CTS* signal is a MODEM status input whose conditions
can be tested by the CPU reading bit 4 (CTS) of the MODEM Status Register. Bit
4 is the complement of the CTS* signal. Bit 0 (DCTS) of the MODEM Status
Register indicates whether the CTS* input has changed state since the previous
reading of the modem Status Register, CTS* has no effect on the Transmitter.
Note: Whenever the CTS bit of the MODEM Status Register changes state, an
interrupt is generated if the MODEM Status interrupt is enabled.
Data Set Ready: When low, this pin indicates that the MODEM or data set is
ready to establish the communications link with the UART. The DSR* signal is a
MODEM status input whose condition can be tested by the CPU reading bit 5
(DSR) of the MODEM Status Register. Bit 5 is the complement of the DSR
signal. Bit 1 (DDSR) of the MODEM Status Register indicates whether the DSR*
input has changed state since the previous reading of the MOEM status
Register. DSR* has no the transmitter.
Note: whenever the DSR bit of the MODM Status Register changes state, an
interrupt is generates if the MODEM Status Interrupt is enabled.
Receiver Line Signal Detect: When low, this pin indicates that the data carrier
has been detected by the MODEM or data set. The DCD* signal is a MODEM
status input whose condition can be tested by the CPU reading bit 7 (RLSD) of
the MODEM Status Register. Bit 7 is the complement of the RLSD* signal. Bit
3(DRLSD) of the MODEM Status Register indicates whether the RLSD* input
has changed state since the previous reading of the MODEM Status Register.
DCD* has no effect on the receiver.
Note: whenever the DCD bit of the MODEM Status Register changes state, an
interrupt is generated if the MODEM Status interrupt is enabled.
Ring indicator: When low, this pin indicates that a telephone ringing signal has
been received by the MODEM or data set. The RI* signal is a MODEM status
input whose condition can be tested by the CPU reading bit 6 (RI) of the
MODEM Status Register. Bit 6 is the complement of the RI* signal. Bit 2(TERI) of
the MODEM Status Register indicates whether the RI* input signal has changed
from a low to a high state since the previous reading of the MODEM Status
Register.
Note: Whenever the RI bit of the MODEM Status Register changes from a low to
a high state, an interrupt is generated if the MODEM Status Interrupt is enabled.
Description
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IMP16C550
Mnemonic
Pin
Type
PIN # for
40-DIP/
44-PLCC
Description
VCC
IN
40/44
+5V supply
VSS
IN
20/22
Ground
DTR*
OUT
33/37
Data Terminal Ready: When low, this informs the MODEM or data set that the
UART is ready to establish a communication link. The DTR output signal can be
set to an active low by programming bit 0(DTR) of the MODEM Control Register
to a 1. A Master Reset operation sets this signal to its inactive (high) state. Loop
mode operation holds this signal in its inactive state.
RTS*
OUT
32/36
Request To Send: When low, this informs the MODEM or data set that the
UART is ready to exchange data. The RTS output signal can be set to an active
low by programming bit 1 (RTS) of the MODEM Control Register to a 1. A
Master Reset operation sets this signal to its inactive (high) state. Loop
operation holds this signal in its inactive state.
OUT1*
OUT
34/38
Output 1: This user-designated output can be set to an active low by
programming bit 3 (OUT2) of the MODEM Control Register to a 1. A Master
Reset operation sets this signal to its inactive (high) state. Loop mode operation
holds this signal in its inactive state.
OUT2*
OUT
31/35
Output 2: This user-designated output can be set to an active low by
programming bit 3 (out2) of the MODEM Control Register to a 1. A master Reset
operation sets this signal to its inactive (high) state. Loop mode operation holds
this signal in its inactive state.
TXRDY*
OUT
24/27
Transmitter Ready pin: Transmitter DMA signaling is available through this pin.
When operating in the FIFO mode. One of two types of DMA signaling can be
selected via FCR3. When operating as in the Ei16c450 Mode, only DMA mode
0 is allowed. Mode 0 supports single transfer DMA where a transfer is made
between CPU bus cycles. Mode 1 support multi-transfer DMA where multiple
transfers are made continuously until the XMIT FIFO has been filled.
TXRDY Mode 0: In the Ei16c450 Mode (FCR3=0) or in the FIFO Mode
(FCR0=1, FCR3=0) there are no characters in the XMIT FIFO or XMIT holding
register, the TXRDY pin will bee low active. Once it is activated the TXRDY pin
will go inactive after the first character is loaded into the XMIT FIFO or holding
register.
TXTDY Mode 1: In the FIFO Mode (FCR0=1, FCR3=1) there is at least one
unfilled position in the XMIT FIFO, it will to low active. This pin will become
inactive when the XMIT FIFO is completely full.
RXRDY*
7
OUT
29/32
Receiver Ready pin: Receiver DMA signaling is available through this pin.
When operating in the FIFO mode, one of two types of DMA signaling can be
selected via FCR3. When operating as in the Ei16c450 Mode, only DMA mode
0 is allowed. Mode 0 supports single transfer DMA where a transfer is mode
between CPU bus cycles. Mode 1 support multi-transfer DMA where multiple
transfers are made continuously until the RCVR FIFO has been emptied.
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IMP16C550
Mnemonic
Pin
Type
PIN # for
40-DIP/
44-PLCC
Description
RXRDY Mode 0: When in the IMP16c450 Mode (FCR0=0) or in the FIFO
Mode (FCR0=1, FCR3=0) there is at least 1 character in the RCVR
FIFO or RCVR holding register, the RXRDY pin will be low active. Once
it is activated the RXRDY pin will go inactive when there are no more
characters in the FIFO or holding register.
RXRDY Mode 1: In the FIFO Mode (FCR0=1, FCR3=1) the trigger level
or the timeout has been reached, the RXRDY pin will to low active, Once
it is activated it will to inactive when there are no more characters in the
FIFO or holding register.
8
DDIS
OUT
23/26
Driver Disable: This goes low whenever the CPU is reading data or
status from the UART, It can be used to disable or control the direction of
a data bus transceiver between the CPU and the UART.
BAUDOUT*
OUT
15/17
Baud Out Clock: This is the 16 x clock signal from the transmitter section
of the UART. The clock rate is equal to the main reference oscillator
frequency divided by the specified divisor in the baud Rate Generator
Divisor Latches. The BAUDOUT* may also be used for the receiver
section by tying this output to the RCLK input of the chip.
INTRPT
OUT
30/33
Interrupt: This pin goes high whenever any one of the following interrupt
types has an active high condition and is enabled via the IER: Receiver
Error Flag; Received Data Available; Timeout (FIFO Mode only);
Transmitter Holding register Empty; and MODEM STATUS. The
INTRPT signal is reset low upon the appropriate interrupt service or a
Master Reset operation.
SOUT
OUT
11/13
Serial Output: Composite serial data output to the communications link
(peripheral, MODEM or data set). The SOUT signal is set to the Marking
(logic 1) state upon a Master Reset operation.
D0-D7
I/O
1:8/2:9
Data Bus D0-D7: This 3-state bus provides bi-directional
communications between the UART and the CPU. Data, control words,
and status information are transferred via the D0-D7 Data Bus.
XTAL1
XTAL2
IN,
OUT
16/18
External Clock Input/Output: These two pins connect the main timing
reference (crystal or signal clock) to the UART. See Figure 5 for circuit
connection diagram.
NC
NA
-/1,12,23,34
Pins not connected.
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IMP16C550
UART Operational Description
MASTER RESET
A high level input on MR pin resets UART and forces internal register and output pins as shown in Table 1.
TABLE 1-RESET Configuration of Registers and Output Signals
9
Register/Signal
Reset Control
Reset State
Receiver buffer
Register
First word Received
Undefined Data
Transmitter Holding
Register
Writing into the Transmitter
Holding Register
Undefined Data
Interrupt Enable
Register
Master Reset
All bits low-bits(4-7) are
permanently low
Interrupt Identification
Register
Master Reset
Bit 0 is forced high and Bit (1-3), 6, 7
are forced low-bits 4 and 5 are
permanently low
Line Control Register
Master Reset
All bits low
Modem Control Register
Master reset
All bits low-bits(5-7) are
permanently low
Line Status Register
Master Reset
All bits low – except bit 5, 6 which
are high
Modem Status Register
Master Reset MODEM Signal
inputs
Bits(0-3) low
Bits(4-7 follow input signals
Divisor Latch
(low order byte)
Writing 00(H) into the Latch
Undefined Data
Divisor Latch
(high order byte)
Writing 00(H) into the Latch
Undefined Data
SOUT
Master Reset
High
BAUDOUT*
Writing into either Divisor
Latch
Low
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IMP16C550
TABLE 1-Reset Control of Registers and Pin out Signals (continued)
Register/Signal
Reset Control
Reset State
DDIS
According to CS0, CS1, CS2*,
DISTR, DISTR*
According to CS0, CS1, CS2,
DISTR, DISTR*
INTRPT (RCVR ERRS)
Master Reset/Read LSR
Low
INTRPT(RCVR DATA READY)
Master Reset /Read LSR
Low
INTRJPT(THRE)
Master Reset /Read IIR/Write THR
Low
OUT2*
Master Reset
High
OUT1*
Master Reset
High
RTS*
Master Reset
High
DTR*
Master Reset
High
RCVR FIFO
Master Reset
Undefined data
XMIT FIFO
Master Reset
Undefined data
FIFO CONTROL
Master Reset
All bits low {(0-3), 6, 7 forced
and 4, 5 permanent}
Data bus (D0-D7)
According to CS0, CS1, CS2*, DISTR,
According to CS0, CS1, CS2*,
DISTR, DISTR*, DOSTR, DOSTR*
DISTR*, DOSTR, DOSTR*
10
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IMP16C550
Internal Register Description
The system programmer has access to any of the registers as summarized in Table II.
Table II-Accessible IMP16C550 Registers
0 DLAB =0
2
2
3
Receiver
Buffer
Register
(Read
Only)
RBR
Transmitter
Holding
Register
(Write Only)
Interrupt
Enable
Register
Interrupt
Identification
Register
(Read only)
FIFO Control
Register
(Write only)
Line control
Register
THR
IER
IIR
FCR
LCR
0
Data Bit 0
Data Bit 0
Enable
Received
Data-Register
Interrupt
(ERBFI)
“0”if
interrupt
Pending
FIFO Enable
(FEWO)
Word Length
Select bit 0
(WLSO)
1
Data Bit 1
Data Bit 1
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
Interrupt
ID bit 0
(IIDB0)
Receiver
FIFO
Reset
(RFR)
Word Length
Select bit 1
(WLS1)
2
Data Bit 2
Data Bit 2
Interrupt
ID bit 1
(IIDB1)
Data Bit 3
Data Bit 3
Transmitter
FIFO
Reset
(TFR)
DMA
Mode
Select
(DMS)
Number
Stoop Bits
(STB)
3
4
Data Bit 4
Data Bit 4
Enable
Received
Line- Status
(ERLSI)
Enable
MODEM
Status
interrupt
(EDSSI)
0
0
Reserved
5
Data Bit 5
Data Bit 5
0
0
Reserved
6
Data Bit 6
Data Bit 6
0
7
Data Bit 7
Data Bit 7
0
FIFO
Enable*
(FE)
FIFO
Enable*
(FE)
RCVR FIFO
Trigger level
(LSB)
RCVR FIFO
Trigger-level(MS
B)
Even Parity
Select(EPS)
Stick Parity
(STP)
Set Break
Control
Bit
No.
11
Register Address
0 DLAB =0
1 DLAB=0
Interrupt
ID bit 2
(IIDB 2)
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Parity
Enable
(PEN)
Divisor Latch
Access bit
(DLAB)
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IMP16C550
TABLE II-Accessible IMP16C550 Registers (continued)
Bit
No.
0
1
Register Address
4
5
Line Status
MODEM
Register
Control
(Read Only)
Register
MCR
LSR
Data
Data
Ready
Terminal
(DR)
Ready
(DTR)
Request to Overrun
Error
Send
(OE)
(RTS)
2
Out 1
Parity
Error
(PE)
3
Out 2
Framing
Error
(FE)
4
Loop
5
0
6
0
7
0
Break
Interrupt
(BI)
Transmitter
Holding
Register
Empty
(THRE)
Transmitter
Empty
(TEMT)
Error in
RCVR
FIFO(*)
(EIRF)
6
MODEM
Status
Register
MSR
Delta
Clear to
Send
(DCTS)
Delta
Data Set
Ready
(DDSR)
Trailing
Edge Ring
Indicator
(TERI)
Delta
Receive
Line Signal
Detect
(DRLSD)
Clear to
Send
(CTS)
Data Set
Ready
(DSR)
7
Scratch
Pad
Register
SCR
Bit 0
0 DLAB=0
Divisor
Latch
(LSB)
DLL
Bit 0
1 DLAB=1
Divisor
Latch
(MSB)
DLM
Bit 8
Bit 1
Bit 1
Bit 9
Bit 2
Bit 2
Bit 10
Bit 3
Bit 3
Bit 11
Bit 4
Bit 4
Bit 12
Bit 5
Bit 5
Bit 13
Ring
Indicator
(RI)
Receive
Line Signal
Detect
Bit 6
Bit 6
Bit 14
Bit 7
Bit 7
Bit 15
(*)These bits are read 0 in Character Mode.
12
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Line Control Register
The system programmer specifies the format of the
asynchronous data communications exchange and
sets the Divisor Latch Access bit via the Line Control
Register (LCR). The programmer can also read the
contents of the Line Control Register. The read
capability simplifies system programming and
eliminates the need for separate storage in system
memory of the line characteristics.
Bits 0 and 1: These two bits specify the number of
bits in each transmitted or received serial character.
The encoding of bits 0 and 1 is as follows:
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Character Length
5 Bits
6 Bits
7 Bits
8 Bits
1. Load an all 0s, pad character, in response to
THRE.
2. Set Break after the next THRE.
3. Wait for the transmitter to be idle, (TEMT=1), and
clear break when normal transmission has to be
restored.
During the break, the Transmitter can be used as a
character timer to accurately establish the break
duration.
Bit 2: This bit specifies the number of Stoop bits
transmitted and received in each serial character. If
bit 2 is logic 0, one Stop bit is generated in the
transmitted data. If bit 2 is logic 1 when a 5-bit word
length is selected via bits 0 and 1, one and a half Stop
bits are generated. If bit 2 is logic 1 when either a 6-,
7-, or 8-bit word length is selected, 2 Stop bits are
generated. The Receiver checks the first Stop-bit
only, regardless of the number of Stop bits selected.
Bit 7: This bit is the Divisor Latch Access Bit (DLAB).
It must be set high (logic 1) to access the Divisor
Latches of the Baud Rate Generator during a Read
or Write operation. Is must be set low (logic 0) to
access the receiver Buffer, the Transmitter Holding
Register, or the Interrupt Enable Register.
Bit 3: This bit is the Parity Enable bit. When bit 3 is a
logic 1, a Parity bit is generated (transmit data) or
checked (receive data) between the last data word bit
and Stop bit of the serial data. (The Parity bit is used
to produce an even or odd number of 1s when the
data word bits and the Parity bit are summed).
The UART contains a programmable Baud
Generator that is capable of taking any clock input
from DC TO 8. 0 MHz and dividing it by any divisor
from 1 to 216-1. The output frequency of the Baud
Generator is 16x the Baud rate. Two 8-bit latches
store the divisor in a 16-bit binary format. These
Divisor Latches must be loaded during initialization to
ensure proper operation of the Baud Rate generator.
Upon loading either of the Divisor Latches, a 16-bit
Baud counter is immediately loaded. This prevents
long counts on initial load.
Bit 4: This bit is he Even Parity Selects bit. When bit
3 is logic 1 and bit 4 is logic 0, an odd number of logic
1s is transmitted or checked in the data word bits and
parity bit. When bit 3 is logic 1 and bit 4 is logic 1, an
even number of logic 1s is transmitted or checked in
the data word bits and Parity bit.
Bit 5: This bit is the Stick Parity bit. When bits 3 and
5 are logic 1 the parity bit is transmitted and detected
by the receiver in the opposite state indicated by bit 4.
If bit 5 is zero, Stick parity is disabled.
Bit 6: This bit is the Break Control bit. It causes a
break condition to be transmitted to the receiving
13
UART. When bit 6 is set to a logic 1, the serial output
(SOUT) is forced to the Spacing (logic 0) state and
remains there until bit 6 is set to a logic 0. This bit
acts only on SOUT pin and has no effect on
transmitter logic. This feature enables the CPU to
alert a terminal in a computer communications
system. If the following sequence is followed, no
erroneous characters will be transmitted because of
break.
Programmable Baud Rate Generator
Table III, IV and V illustrate the use of the Baud Rate
Generator with three different driving frequencies.
Table III references to a 1. 8430 MHz clock, table IV
to a 3. 070 MHz and table V to an 8 MHz clock. For
baud rates of 38400 and below, the error obtained is
minimal. The accuracy of the desired baud rate is
dependent on the crystal frequency chosen. Using a
divisor of zero is not recommended. In no case
should the data rate be greater than 512K baud.
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14
TABLE III-Baud Rates Using 1. 8432 MHz clock
Divisor Used
Desired
to generate
Baud
16 x clock
Rate
2304
50
1536
75
1047
110
857
134. 5
768
150
384
300
192
600
96
1200
64
1800
58
2000
48
2400
32
3600
24
4800
16
7200
12
9600
6
19200
3
38400
2(*)
56000
Percent Error
Difference Between
Desired and Actual
0. 026
0. 058
0. 690
2. 860
TABLE IV-Baud Rates Using 3.072 MHz clock
Divisor Used
Desired
to generate
Baud
16 x clock
Rate
3840
50
2560
75
1745
110
1428
134. 5
1280
150
640
300
320
600
160
1200
107
1800
96
2000
80
2400
53
3600
40
4800
27
7200
20
9600
10
19200
5
38400
3(*)
56000
Percent Error
Difference Between
Desired and Actual
0. 026
0. 034
0. 312
0. 628
1. 230
14. 285
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Table V-Baud Rate using 8. 0 MHz Clock
Divisor Used
Desired
to generate
Baud
16 x clock
Rate
10000
50
6667
75
4545
110
3717
134. 5
3333
150
1667
300
833
600
417
1200
277
1800
250
2000
208
2400
139
3600
104
4800
69
7200
52
9600
26
19200
13
38400
9
56000
4
128000
2(*)
256000
Percent Error
Difference Between
Desired and Actual
0. 005
0. 010
0. 013
0. 010
0. 020
0. 040
0. 080
0. 080
1. 160
0. 080
1. 160
0. 644
1. 160
1. 160
1. 160
0. 790
2. 344
2. 344
(*) Smallest allowable divisor when using corresponding crystal.
Line Status Register
This register provides status information to the CPU
concerning the data transfer. Table II shows the
contents of the Line Status Register. Description of
each bit follows:
Bit 0: This bit is the receiver Data Ready (RDR)
indicator. Bit 0 is set to a logic 1 whenever a
complete incoming character has been received and
transferred into the Receiver Buffer Register of the
FIFO. Bit 0 is reset to a logic 0 by reading all of the
data in thee Receiver Buffer Register (for character
mode) or the RCVR FIFO (for FIFO mode).
Bit 1: This bit is the Overrun Error (OE) indicator. Bit
1 indicates that data in the Receiver buffer Register
was not read by the CPU before the next character
was transferred into the Receiver Buffer Register,
there by destroying the previous character. The OE
indicator is set to logic 1 upon detection of an overrun
condition and reset whenever the CPU reads the
contents of the Line Status Register. If the FIFO
mode data continues to fill the FIFO beyond the
trigger level, an overrun error will occur only after the
FIFO is full and the next character has been
15
completely received in the shift register. An OE is
indicated as soon as it happens. The character in the
shift register is overwritten, but nothing will be
transferred to the FIFO.
BIT 2: This bit is the Parity Error (PE) indicator. Bit 2
indicates that the received data character doses not
have the correct even or odd parity, as selected by
the even-parity -select bit. The PE is set to logic 2
upon detection of a parity error and is reset to logic 0
whenever the CPU reads the contents of the Line
Status Register. In the FIFO mode this error is
associated with the particular character in the FIFO
and revealed to the CPU when the associated
character is at the top of the FIFO.
Bit 3: This bit is the Framing Error (FE) indicator. Bit
3 indicates that the received character did not have a
valid Stop bit. Bit 3 is set to logic 1 whenever the Stop
bit following the last data bit or parity bit is detected
as a logic 0 bit (Spacing level). The FE indicator is
reset whenever the CPU reads the contents of the
Line status Register. In the FIFO mode this error is
associated with the particular character in the FIFO it
applies to. This error is revealed to the CPU when its
associated character is at the top to the FIFOT. The
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UART will resynchronize after a Framing Error.
if there are no subsequent errors in the FIFO.
Bit 4: This bit is the Break interrupt (BI) indicator. Bit
4 is set to a logic 1 whenever the received data input
is held in the spacing (logic 0) state for longer than a
full word transmission time (that is, the total time of
Start bit + data bits + Parity + Stop bits ). The BI
indicator is reset whenever the CPU reads the
contents of the Lines Status Register. When in FIFO
mode, BI is associated to the particular character in
the FIFO, and this bit is set when the associated
character is at the top of the FIFO. When a break
occurs, only one zero character is loaded into the
FIFO. The next character transferred is enable after
SIN goes to the marking state (logic 1) and receives
the next valid start bit.
Note: The line Status Register is intended for read
operations only, Writing to this register is not
recommended.
Note: Bits 1 through 4 are the error conditions that
produce a Receiver Line Status interrupt whenever
any of the corresponding conditions are detected and
the interrupt is enabled.
Information indicating that a prioritized interrupt is
pending and source of that interrupt is stored in the
interrupt identification Register. Register IIR, when
addressed during chip select time, freezes the
highest priority interrupt pending and no other
interrupts are acknowledged until the particular
interrupt is serviced by the CPU. Its contents are
indicated in Table VI and are described below:
Bit 5: This bit is the Transmitter Holding Register
empty (THRE) indicator. Bit 5 indicates that the
UART is ready to accept a new character for
transmission. In addition, this bit causes the UART to
issue an interrupt to the CPU when the Transmit
Holding Register Empty Interrupt enable is set high.
The THRE bit is set to logic 1 when a character is
transferred from the Transmitter Holding Register
into the Transmitter Shift Register. The bit is reset or
logic 0 concurrently with the loading of the
Transmitter Holding Register by the CPU. In the
FIFO mode, this bit will be set when XMIT FIFO is
empty, and cleared when as least one character is
written to XMIT FIFO.
16
Interrupt Identification Register
In order to provide minimum software overhead
during data character transfers, the UART prioritizes
interrupts into four levels, The four levels of interrupt
conditions are as follows: Receiver Line Status
(priority 1), Received Data Ready (priority 2),
Transmitter Holding Register Empty (priority 3), and
MODEM Status (priority 4).
Bit 0: This bit can be used in a prioritized or polled
environment to indicate whether an interrupt is
pending. When bit 0 is logic 0, an interrupt is pending
and the IIR contents may be used as a pointer to the
appropriate interrupt service routine. When bit 0 is
logic 1, no interrupt is pending and polling (if used)
continues.
Bit 1, 2: These two bits of the IIR are used to identify
the highest priority interrupt pending (see Table VI).
Bit 6: This bit is the Transmitter Empty (TEMT)
indicator. Bit 6 is set to a logic 1 whenever the
Transmitter Holding Register (THR) and the
Transmitter Shift Register (TSR) are both empty. It is
reset to logic 0 whenever either the THR or the TSR
contains a data character. In the FIFO mode this bit
is set to 1 whenever the transmitter FIFO and shift
register are both empty.
Bit 3: In the Character Mode this bit is 0. In the FIFO
Mode this bit is set along with bit 2 when a timeout
interrupt is pending.
Bit 7: In the Character Mode, this bit (LSR7) is a 0. In
the FIFO mode it is set when there is a least one
parity error, framing error or break indication in the
FIFO. LSR7 is cleared when the CPU reads the LSR,
Interrupt Enable Register
Bit 4, 5: These two bits of the IIR are always logic 0.
Bit 6, 7: These two bits, when set, indicate that the
device is in FIFO Mode, i.e. when FCR0=1.
This 8-bit register enables the four interrupt sources
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TABLEL VI-Interrupt Control Functions
Interrupt Identification Register
Interrupt Set and Reset Functions
Bit 3
Bit 2
Bit 1 Bit 0
Priority
Interrupt
Interrupt Source
Level
Type
None
None
1
0
0
0
17
Interrupt
Reset Control
-
0
1
1
0
Highest
Receiver
Line Status
Overrun Error
or Parity Error
or Framing Error
or Break Interrupt
reading the
Line Status
Register
0
1
0
0
Second
Received Data
Available
Receiver Data
Available
or
trigger Level
Reached
Reading the
Receiver Buffer
Register or the
FIFO Drops
below the
trigger Level
1
1
0
0
Second
Character
timeout
Identification
No characters
have been input
to or removed
from the RCVR
FIFO during the
last 4 character
times, and there
is at least one
character in it
during this time
Reading the
Receiver Buffer
register
0
0
1
0
Third
Transmitter
Holding
Register
Empty
Transmitter
Holding
Register
Empty
Reading the IIR
Register (if
source of
interrupt) or
Writing into the
Transmitter
Holding Register
0
0
0
0
Fourth
MODEM
Status
Clear to send
or Data Set ready
or Ring Indicator
or Received Line
Signal Detect
Reading the
MODEM status
Register
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of the UART to separately activate the chip Interrupt
(INTRPT)OUTPUT signal.
Each interrupt can
individually activate the interrupt (INTRPT) output
signal. Its contents are indicated in Table 3-2 and are
described below. It is possible to totally disable the
interrupt system by resetting bits 0 through 3 of the
interrupt Enable (IER). Similarly, setting bits of the
Bit 0: This bit enables the Received Data Available
interrupt (and timeout interrupts in the FIFO mode)
when set to logic 1.
Bit 1: This bit enables the Transmitter Holding
Register Empty Interrupt when set to logic 1.
IER register to logic 1 enables the selected
interrupt(s). Disabling an interrupt prevents it from
being indicated as active in the IIR and from
activating the INTRPT output signal. All other system
functions operate in their normal manner, including
the setting of the Line Status and MODE Status
registers.
mode 1 (see description of RXRDY and TXRDY
pins).
Bit 4, 5: FCR4 and FCR5 are reserved for future use.
Bit 6, 7: FCR6 and FCR7 are used to set the trigger
level for the RCVR FIFO interrupt as follows:
Bit 2: This bit enables the Receiver Line Status
Interrupt when set to logic 1.
Bit 3: This bit enables the MODEM Status Interrupt
when set to logic 1.
7
6
0
0
1
1
0
1
0
1
RCVR FIFO Trigger
Level (in bytes)
01
04
08
14
Bit 4-7: These four bits are always logic 0.
MODEM Control Register
Scratch Pad Register
This 8-bit Read/Write Register does not control the
UART in anyway. It is intended as a scratch pad
register to be used by the programmer to hold
general purpose data temporarily.
FIFO Control Register
This write only register is located at the same
address as the IIR (read only). This register is used
to enable FIFO Mode, clear FIFO’s set the RCVR
FIFO trigger levels, and select the mode of DMA
signaling.
Bit 0: Writing a 1 to this bit enables both the XMIT and
RCVR FIFO’s. When changing from FIFO Mode to
Character Mode and vice versa, data is not
automatically cleared from the FIFO’s. This bit must
be a 1 when writing to other FCR bits or they will not
be programmed.
Bit 1: Writing a 1 to FCR1 will reset the receiver FIFO
counters to 0, and then self clear this bit to. The shift
register is not cleared.
Bit 2: Functions the same as bit 1. Except for XMIT
FIFO counters.
Bit 3: If FCR0=1, setting FCR3 to a 1 will cause the
RXRDY and TXRDY pins to change from mode 0 to
18
This 8-bit register controls the interface with the
MODEM or data set (or a peripheral device emulating
a MODEM). The contents of the MODEM control
Register are indicated in Table II and are described
below:
Bit 0: This bit controls the Data Terminal Ready (DTR)
output. When bit 0 is set to logic 1, the DTR output is
forced to logic 0. When bit 0 is reset to logic 0, the
DTR output is forced to logic 1.
Note: The DTR output of the UART may be applied to
an EIA inverting line driver (such as the DS1488) to
obtain the proper polarity input at the succeeding
MODEM OR data set.
Bit 1: This bit controls the Request to Send (RTS*)
output. Bit 1 affects the RTS output in a manner
identical to that described above for bit 0.
Bit 2: This bit controls the Output 1 (OUT1*) signal,
which is an auxiliary user-designated output. Bit 2
affects the OUT1 output in a manner identical to that
described above for bit 0.
Bit 3: This bit controls the Output 2 (OUT2*) signal,
which is an auxiliary user-designated output. Bit 3
affects the OUT2* output in a manner identical to that
described above for bit 0.
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Bit 4: This bit provides a local loopback feature for
diagnostic testing of the UART. When bit 4 is set to
logic 1, the following occur: the transmitter Serial
Output (SOUT) is set to a logic 1 (high) state; the
receiver Serial Input (SIN) is disconnected; the
output of the Transmitter Shift Register is "looped
back" into the Receiver Shift Register input: the four
MODEM Control inputs (CTS*, DSR*, RLSD* and RI*)
are disconnected, and the MIDEM Control output
pins (RTS*, DTR*, OUT2* and OUT1*) are forced to
their inactive state (high). In the diagnostic mode,
data that is transmitted is immediately received. This
feature allows the processor to verify the
transmit-and receive-data paths of the UART.
In the diagnostic mode, the receiver and transmitter
interrupt are fully operational, The MODEM control
Interrupts are also operational. The MODEM control
Interrupts are also operational, but the sources of
interrupts are now the lower four bits of the MODEM
Control Register instead of the four MODEM control
inputs. The interrupts are still controlled by the
interrupt Enable Register.
Bit 5-7: These bits are permanently set to logic 0.
(TREI) detector. Bit 2 indicates that the RI input to
the chip has changed from a low to high state since
the last time it was read by the CPU.
Bit 3: This bit is the Delta Received Line Signal
Detector (DRLSD) indicator. Bit 3 when set to logic 1,
indicates that the RLSD input to the chip has
changed state since the last time it was read by the
CPU.
Note: Whenever bit 0, 1, 2, or 3 is set to logic 1, a
MODEM Status Interrupt is generated, if bit 3 (EDSSI)
of the interrupt enable register is set.
Bit 4: This bit is the complement of the Clear to Send
(CTS*) input. This bit is equivalent to bit RTS of the
MODEM control register, if bit 4 of the MCR is set to
(loop mode).
Bit 5: This bit is the complement of the Data Set
Ready (DSR) input. This bit is equivalent to bit DTR
of the MODEM control register, if bit 4 of the MCR is
set to 1(loop mode).
Bit 6: This bit is the complement of the Ring Indicator
(RI) input. This bit is equivalent to bit OUT1 of the
MODEM control register, if bit 4 the MCR is set to 1
(loop mode).
MODEM Status Register
This 8-bit register provides the current state of the
control lines from the MODEM or data set (or a
peripheral device emulating a modem) to the CPU. In
addition to this current-state information, four bits of
the MODEM Status Register provide change
information. These bits are set to logic 1 whenever a
control input from the MODEM changes state. They
are reset to logic 0 whenever the CPU reads the
MODEM Status Register.
The contents of the MODEM Status Register are
indicated in Table II and described below:
Bit 7: This bit is the complement of the Received Line
Signal Detect (RLSD) input. This bits equivalent to
bit OUT2 of the MODEM control register, if bit 4 of the
MCR is set to 1 (loop mode).
FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are
enabled (FCR0=1, IER0=1) RCVR interrupts will
occur as follows:
A.
The receive data available interrupt will be
issued to the CPU when the FIFO has reached
its programmed trigger level; it will be cleared as
soon as the FIFO drops below its programmed
trigger level.
B.
The IIR receive data available indication also
occurs when the FIFO trigger level is reached,
and like the interrupt, it is cleared when the FIFO
drops below the trigger level.
Bit 0: This bit is the delta Clear to Send (DCTS)
indicator. Bit 0 when set to logic 1, indicates that the
CTS input to the chip has changed state since the
last time this bit was cleared to logic 0 by reading this
bit by the CPU.
Bit 1: This bit is the Delta Data Set Ready (DDSR)
indicator, Bit 1 when set to logic 1, indicates that the
DSR input to the chip has changed state since the
last time it was read by the CPU.
Bit 2: This bit is the Trailing Edge of Rin Indicator
19
C. The receiver line status interrupt (IIR=06), as
before, has higher priority than the received data
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changing FCR0 will be immediate, if it is
enabled.
available (IIR=04) interrupt.
D. The data ready bit (LSR bit 0) is set as soon as a
character is transferred from the shift register to
the RCVR FIFO. It is reset when the FIFO is
empty.
When RCVR FIFO and receiver interrupts are
enabled, RCVR FIFO timeout interrupts will occur as
follows:
A.
A FIFO timeout interrupt will occur, if the
following conditions exists:
-at least one character is in the RCVR FIFO.
- the most recent serial character received was
longer than 4 continuous character times ago
(if 2 stop bits are programmed the second one
is included in this time delay ).
-the most recent CPU read of the FIFO was
longer than 4 continuous character times ago.
This will cause a maximum character received to
interrupt issued delay of 160 ms at 300 BAUD with a
12 bit character.
B.
character times are calculated by using the
RCLK input for a clock signal (this makes the
delay proportional to the baud rate).
C. When a timeout interrupt has occurred, it is
cleared and the timer is reset when the CPU
reads one character form the RCVR FIFO.
D. When a timeout interrupt has not occurred the
timeout timer is reset after a new character is
received or after the CPU reads the RCVR FIFO.
When the XMIT FIFO and transmitter interrupts are
enabled (FCR0=1, IER1=1), XMIT interrupts will
occur as follows:
20
A.
The transmitter holding register interrupt (02)
occurs when the XMIT FIFO is empty; it is
cleared as soon as the transmitter holding
register is written to (1 to 16 characters may be
written to this XMIT FIFO while servicing this
interrupt) or the IIR is read.
B.
The transmitter FIFO empty indications will be
delayed 1 character time minus the last stop bit
time whenever the following occurs: THRE=1
and there have not been at least tow bytes at the
same time in the transmit FIFO, since the last
THRE=1, The first transmitter interrupt after
Character timeout and RCVR FIFO trigger level
interrupts have the same priority as the current
received data available interrupt; XMIT FIFO empty
has the same priority as the current transmitter
holding register empty interrupt.
FIFO Polled Mode Operation
With FCR0=1 RESETTING IER1, IER2, IERR3 or all
to zero puts the UART in the RCVR and XMITTER
are controlled separately either one or both can be in
the polled mode of operation.
In this mode the users program will check RCVR and
XMITTED status via the LSR. As stated previously:
LSR0 will be set as long as there is one byte in the
RCVR FIFO.
LSR1 to LSR4 will specify which error(s) has
occurred. Character error status is handled the same
way as when in the interrupt mode, the IIR is not
affected since IER2=0.
LSR5 will indicate when the XMIT FIFO is empty.
LSR6 will indicate that both the XMIT FIFO and shift
register is empty.
LSR7 will indicate whether there are any errors in the
RCVR FIFO.
There is no trigger level reached or timeout condition
indicated in the FIFO Polled Mode. However, the
RCVR and XMIT FIFO’s are still fully capable of
holding characters.
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AC, DC TIMING SPECIFICATION
If Military/Aerospace specified devices are required.
contact Factory for availability and specifications.
Note: Maximum rating indicate limits beyond which
permanent damage may occur.
Continuous
operation at these limits is not intended and should
be limited to those conditions specified under DC
electrical characteristics.
Absolute Maximum Ratings
0
0
Temperature Under Bias
0 c to +70 c
0
0
Storage or Output Voltage –65 c to + 150 c
All Input or Output Voltages
0
0
With Respect to VSS
-0. 5 c to + 7. 0 c
Power Dissipation
1W
DC ELECTRICAL CHARACTERISTICS
0
0
TA=0 C to + 70 c, Vcc=+5V±5%, Vss=0V, unless otherwise specified.
Symbol
Parameter
Conditions
Clock Input Low Voltage
VILX
Clock Input High Voltage
VIHX
Input Low Voltage
VIL
Input High Voltage
VIH
IOL = 2 mA on all (note 1)
Output Low Voltage
VOL
Loh = -1. 0 mA (note 1)
Output High Voltage
VOH
Min
-0. 5V
2. 0
-0. 5V
2. 0
Max
0. 8
Vcc
0. 8
Vcc
0. 4
Units
V
V
V
V
V
V
2. 4
ICC(AV)
Avg. Power Supply
Current(Vcc)
Vcc =5. 25V, f=4MHz
No Loads on outputs
SIN, DSR, DCD
CTS, RI=2. 0V
All other inputs =0. 8V
10
mA
IIL
Input Leakage
Vcc=5. 25V, Vss=0V
All other pins floating
±10
µA
ICL
Clock Leakage
VOUT = 0v, 5. 25v
LOZ
Tri-State® Leakage
VCC=5. 25V, VSS=0V
VOUT =0V, 5. 25V
1) chip deselected
2) WRITE mode, chip selected
VILMR
VIHMR
±10
MR Schmitt VIL
MR Schmitt VIH
±10
µA
µA
2. 0
0. 8
V
V
Typ
15
20
6
10
Max
20
30
10
20
Units
pF
pF
pF
pF
(note 1) Does not apply to XOUT
CAPACITANCE
0
TA=25 C, VCC=VSS=0V
Symbol
Parameter
CXIN
Clock Input Capacitance
CXOUT
Clock Output Capacitance
CIN
Input Capacitance
COUT
Output Capacitance
21
Conditions
Fc =1 MHz
Unmeasured pins
Returned to VSS
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Min
Daily Silver IMP
IMP16C550
DRIVER
EXTERNAL
CLOCK
XIN
XIN
OPTIONAL
DRIVER
OPTIONAL
CLOCK
OUTPUT
RP
C1
CRYSTAL
OSC CLOCK TO
BAUD GENLOGIC
RX2
OSC CLOCK TO
BAUD GEN LOGIC
XOUT
XOUT
C2
FIGURE 5 – Typical Crystal Oscillator Network
CRYSTAL
Rp
RX2
C1
C2
3.1MHz
1MΩ
1.5K
10-30Pf
40-60Pf
1.8mhZ
1MΩ
1.5K
10-30Pf
40-60Pf
External Clock Input(8.0 MHz Max.)
2.4V
tXH
AC Test Points
2.4V
2.0V
Note:1
0.4V
0.8V
0.4V
tXL
2.0V
Note:2
0.8V
Note 1 : Input drive levels are 0.4v (low) and 2.4 (high) for AC tests.
Note 2 : Output compare levels are 0.8v (low) and 2.0v (high) for AC lests.
Reset Timing
MR
tMR
FIGURE 6 – Clock and Reset Timing
22
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IMP16C550
Symbol
txh
Parameter
Duration of External
Clock High Pulse
Min
55
txl
Duration of External
Clock Low Pulse
tMR
Master Reset Pulse Width
Max
Units
nsec
Test Conditions
External Clock
(8. 0 MHz Max)
55
nsec
1TTL Load
(8. 0 MHz Max)
5. 0
µsec
1TTL Load
N
XTAL1
tBLD
tBHD
tHW
BAUDOUT*
(divide by 1)
tBHD
tLW
tBLD
tHW
BAUDOUT*
(divide by 2)
tLW
tBHD
tBLD
tHW
BAUDOUT*
(divide by 3)
tLW
tHW=(n-2)XTAL1 CYCLES
tBHD
tBLD
BAUDOUT*
(divide by N,N>3)
tLW=2XTAL1 CYCLES
FIGURE 7 – Baud Rate Generator Timing
Symbol
N
tBLD
Min
1
tLW
Parameter
Baud Rate Divisor
Baud Output Negative
Edge Delay
Baud Output Positive
Edge Delay
Baud Output Low Time
tHW
Baud Output High Time
tBLD
23
Max
16
(2 -1)
125
Units
Test Conditions
nsec
100pF Load
125
nsec
100pF Load
75
nsec
100
nsec
100pF Load
(fx=8. 0 MHz+2)
100pF Load
(fx=8. 0 MHz+2)
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Daily Silver IMP
IMP16C550
`
tRC
ADS*
A0,A1,A2
AND
CS0,CS1,CS2*
tAW
tACH
tAcs
tACR
VALID
tDIC
DISTR*/DISTR
tDIW
tRC
ACTIVE
ACTIVE
DOSTR*/DOSTR
ACTIVE
tDD
DDIS
tDDD
DATA
DO-D7
tDD
tHZ
valid data
tRC
FIGURE 8 – Read cycle Timing
24
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Daily Silver IMP
IMP16C550
twC
ADS*
A0,A1,A2
AND
CS0,CS1,CS2*
tAW
tACH
tAcs
tACw
VALID
tDOC
DOSTR*/DOSTR
twC
tDoW
ACTIVE
ACTIVE
DISTR*/DISTR
tDs
DATA
D0-D7
ACTIVE
tHZ
VALID DATA
t WC
FIGURE 9 – Write Cycle Timing
25
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Daily Silver IMP
IMP16C550
Symbol
tAW
Parameter
Address Strobe Width
Min
60
tACS
Address and Chip
Select Setup Time
tACH
Address and Chip
Select Setup Time
tDIW
Units
nsec
Test conditions
1 TTL Load
60
nsec
1 TTL Load
0
nsec
1 TTL Load
DISTR /DISTR Strobe Width
125
nsec
1 TTL Load
tRC
Read Cycle Delay
125
nsec
1 TTL Load
RC
Read Cycle(tDIC + tDIW + tRC)
280(no
FIFO)
425
(FIFO)
nsec
1 TTL Load
tDD
DISTR /DISTR to Driver disable Delay
60
nsec
@100 pF Load
tDDD
Delay from DISTR /DISTR to Data
125
nsec
@100 pF Load
tHZ
DISTR /DISTR to floating Data Delay
100
nsec
@100 pF Load
tDOW
*
*
0
*
Max
*
0
DISTR /DISTR Strobe Width
*
100
nsec
1 TTL Load
tWC
Write Cycle Delay
150
nsec
1 TTL Load
WC
Write Cycle (tDoC + tDoW + twC)
280
nsec
1 TTL Load
tDS
Data Setup Time
30
nsec
1 TTL Load
tDH
Data Hold Time
30
nsec
1 TTL Load
tDIC(*)
DISTR /DISTR delay form chip Select or Address
*
30
nsec
1 TTL Load
tDOC(*)
DISTR /DISTR delay from chip Select or address
*
30
nsec
1 TTL Load
tACR(*)
Address and Chip Select Hold time from
*
DISTR /DISTR
20
nsec
1 TTL Load
tACW(*)
Address and Chip Select Hold time from
*
DISTR /DISTR
30
nsec
1 TTL Load
(*) Only applicable when ADS* is tied low
26
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Daily Silver IMP
IMP16C550
DOSTR*/DOSTR(1)
(write MCR)
tMDO
tMDO
RIS8,DTR*
OUT1*,OUT2*
CTS*,DSR*,RLSD*
INTRPT
tSIM
DISTR*/DISTR(2)
(read MSR)
tRIM
tSIM
tRIM
tSIM
RI*
NOTES:
(1)See Write cycle Timing
(2)See Read cycle Timing
FIGURE 10 – Modem Control Timing
27
Symbol
tMDO
Parameter
*
Delay from DOSTR /
DOSTR (WR MCR)
To output
tSIM
tRIM
Min
Max
0. 200
Units
µsec
Test Conditions
100pF Load
Delay to Set Interrupt
From MODEM Input
0. 250
µsec
100pF Load
Delay to Reset Interrupt
*
from DISTR /DISTR (RD MSR)
0. 250
µsec
100pF Load
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IMP16C550
RCLK
tSCD
8 CLKS
SAMPLE CLK
SIN
START
PARITY
DATA BITS(5-8)
STOP
START
SAMPLE CLK
tSINT
RDR
INTERRUPT
tRINT
DISTR*/DISTR(1)
(read RBR)
ACTIVE
tSINT
LSI
INTERRUPT
tRINT
DISTR*/DISTR(1)
(read LSR)
ACTIVE
Note:
(1)See Read Cycle timing
FIGURE 11 – Receiver Timing
Symbol
tSCD
Parameter
Delay from RCLK
To Sample Time
Min
tSINT
Delay from
Stop to Set Interrupt
TrinT
Delay From DISTR /DISTR
(RD RBR or RD LSR) Reset
Interrupt
*
Max
2
Units
µsec
1
RCLK
Cycles
1
µsec
Test Conditions
100pF Load
(*)When receiving the first byte in FIFO mode tSINT will be delayed 3 RCLK cycles, except for a timeout interrupt where tSINT will be
delayed 8 RCLK cycles.
28
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Daily Silver IMP
IMP16C550
SIN
PARITY
START
DATA(5-8)
STOP
SAMPLE CLK
FIFO at or above trigger level
TRIGGER LEVEL
INTERRUPT
(FCR6,7=0,0)
tRINT
tSINT
FIFO below
trigger level
LSI INTERRUPT
tSINT
DISTR*/DISTR
(read LSR)
ACTIVE
DISTR*/DISTR
(read RBR)
ACTIVE
FIGURE 12 – RCVR FIFO Timing for First Byte
SERIAL IN
(SIN)
PARITY
DATA(5-8)
STOP
START
SAMPLE CLK
FIFO at or above trigger level
FIFO TRIGGER
LEVLINTERRUPT
OR TIMEOUT
tSINT
FIFO below
trigger levle
top byte of FIFO
LSI INTERRUPT
tSINT
DISTR*/DISTR
(read LSR)
DISTR*/DISTR
(read RBR)
tRINT
tRINT
ACTIVE
ACTIVE
ACTIVE
previous
byte read
from FIFO
FIGURE 13 – RCVR FIFO Timing after First Byte
(RDR already set)
29
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Daily Silver IMP
IMP16C550
DISTR*/DISTR
(read RBR)
ACTIVE
Note1
SIN
(first byte)
PARITY
STOP
SAMPLE CLK
RXRDY*
tSINT
tRINT
Note 1
FCR0=1:Reading of last byte from FIFO
FCR0=0:Reading RBR
FIGURE 14 – Receiver DMA Timing (FCR0= OR FCR1 and FCR3=0)
Mode 0
DISTR8/DISTR
(read RBR)
ACTIVE
Note1
SIN
(first byte that reaches trigger level)
PARITY
STOP
SAMPLE CLK
RXRDY
tSINT
tRINT
Note 1
Reading of last byte from FIFO
FIGURE 15 – Receiver DMA Timing (FCR0=1 and FCR3=1)
Mode 1
30
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Daily Silver IMP
IMP16C550
SERIAL OUT
(SOUT)
START
DATA(5-8)
PARITY
STOP
tIRS
THRE INTERRUPT
START
tSTI
tHR
tHR
tSI
DOSTR*/DOSTR(1)
(write THR)
tIR
DISTR*/DISTR(2)
(read IIR)
NOTES:
(1)See Write Cycle Timing
(2)See Read Cycle Timing
FIGURE 16 – Transmitter Timing
Symbol
THR
Parameter
*
Delay from DISTR /DISTR (WR THR)
to Reset Interrupt
tIR
Delay DISTR /DISTR(RD
Reset Interrupt(THRE)
tIRS
Delay from Initial INTRPT reset to
transmit Start
0
tSI
Delay from Initial Write to Interrupt
*
IIR)
Min
Max
0. 175
Units
µsec
Test Conditions
100pF Load
0. 250
µsec
100pF Load
16
BADOUT
Cycles
16
32
BADOUT
Cycles
8
8
0
8
0
0. 195
BADOUT
Cycles
(note 1)
BADOUT
Cycles
(note 1)
to
Delay from Stop to Interrupt(THRE)
tSTI
Delay from Start to TXREY Active
tSXA
Delay from Write to TXRDY Inactive
tWXI
µsec
100pF Load
100pF Load
Note 1: This delay will be lengthened by 1 character time minus the last STOP bit time if the transmitter internal circuit is active (see FIFO
Interrupt Mode Operation).
31
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Daily Silver IMP
IMP16C550
DOSTTR*/DOSTR
(write THR)
SOUT
BYTE#1
DATA
TXRDY*
PARITY
empty
STOP
START
empty
not empty
tWXI
tSXA
FIGURE 17 – Transmitter Ready Timing in DMA
(FCR0=0 or FCR0=1 and FCR3=0)
Mode 0
DOSTR*/DOSTR
(write THR)
SOUT
TXRDY*
BYTE#16
PARITY
DATA
FIFO not full
STOP
START
FIFO not full
FIFO full
tWXI
tSXA
FIGURE 18 – Transmitter Ready Timing in DMA
(FCR0=0 or FCR0=1 and FCR3 =0)
Mode 1
32
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Daily Silver IMP
IMP16C550
ORDERING INFORMATION
Part Number
Package
Operating Temperature
IMP16C550-CP40
PDIP 40 pins
0°C to +70°C
IMP16C550-CJ44
PDIP 44 pins
0°C to +70°C
IMP16C550-A48
TQFP 48 pins
LIFE SUPPORT POLICY: IMP’S products are not to be used in life support devices without prior written
authorization.
IMP retains the right to make changes to these specifications at anytime without notice.
Daily Silver IMP Microelectronics Co.,Ltd
7 Keda Road , Hi-Tech Park,
NingBo,Zhejiang, P.R.C.
Post Code : 315040
Tel:(086)-574-87906358
Fax:(086)-574-87908866
e-mail:[email protected]
http://www.ds-imp.com.cn
The IMP logo is a registered trademark of Daily Silver IMP.
All other company and product names are trademarks of their respective owners.
2005 Daily Silver IMP
Revision : A
Issue Date: 08 / 08 / 05
Type: Product