RTCmodule - FPGA & SoC

Optimized for
RTCmodule
Description
Features
The RTCmodule is part of Inicore's IPmodule family. The RTCmodule implements
the standard functionality of a Real Time Clock. With a synchronous system
interface, the module can be integrated in a wide range of systems, from small
CPU to a ARM AMBA system.
• External or internal
reference time
int_req
clk
reset_n
test_mode
• Counts day, month & year
Interrupt
Controller
• Automatic end of month and
leap recognition
Alarm
Register 1/2
Time Keeper
• Counts milliseconds,
seconds, minutes and hours
of day
• 2 alarm interrupts
• Seconds, minutes, hour,
day, month and year overroll interrupts
clk_1ms/clk_1ms_ebl
clk_1s/clk_1s_ebl
CPU bus
• Time & date are counted in
BCD format
UPI
RTCmodule
• Time is in 24-hour format
• Special test mode to
increase test coverage
Figure 1: Block diagram
System Bus Interface (UPI): A fully synchronous single clock cycle bus interface
provides direct access to all local register resources. See the memory map for
detailed description of all registers
• Synchronous bus interfaces
- Zero wait-states
- Supports system bus such
as AMBA APB version 2.0
Time Keeper: Using either the system clock or an external time reference, the
time keeper keeps track of the current time.
• Full synchronous design
Alarm register: Using the alarm register, a preprogrammed system wake-up event
can be programmed allowing the CPU to go into a power-down mode.
Interrupt Controller: The interrupt controller bundles all local interrupt sources
together and provides one interrupt request line to the main system.
Applications
• Industrial control
• System-on-Chip
Utilization and Performance Table Optimized for Actel Devices
Fam ily
Fusion
IGLOO
PA3/E
ProASICPLUS
Axcelerator
SXA
eX
Device
- (speed grade)
AFS250-2
AGL600V5 STD
A3PE600-2
APA450 STD
AX250-1
SX72A-3
EX256
Utilization
s-mod
71
72
78
73
81
83
41
c-mod
686
683
751
804
435
436
72
• Peripheral Logic
Perform ance
RAM
Total
12%
5%
6%
7%
12%
9%
15%
• Embedded Systems
[MHz]
80
59
74
59
79
67
94
INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 www.inicore.com
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About Inicore
addr[3:1]
sel
rwn
data_in[15:0]
data_out[15:0]
int_req
 Easy-to-use IP Cores
clk
reset_n
clk_1s
 System-on-Chip Solutions
clk_1s_ebl
 Consulting Services
clk_1ms
 ASIC to FPGA Migration
clk_1ms_ebl
 Obsolete ASIC Replacements
RTCmodule
Figure 2: Symbol
Interfaces
Pin Name
Type
Description
Global Signals
clk
in
System clock
reset_n
in
Asynchronous system reset, active low
Addr[3:1]
in
Address bus input
data_in[15:0]
in
Data bus input
Local Bus
data_out [15:0]
out
Data bus output
sel
in
Module chip select, active low
rwn
in
Read/write control signal
'0': Write
'1': Read
int_req
out
Interrupt request, active high
External Reference Clock
clk_1s
in
1 Hz reference clock
clk_1s_ebl
in
1 Hz reference clock enable
clk_1ms
in
1 KHz reference clock
clk_1ms_ebl
in
1 KHz reference clock enable
Implementation
All IPmodule cores are designed for system integration. Standard interfaces ease
connecting different cores in a system.
For gate-count optimization, several configurations are available to optimize the
core for the target application:min:
●
●
 FPGA and ASIC Design
number of timer alarms
CPU readback. Configuration value readback can be disabled to
minimize gate count.
Inicore is an experienced system
design house providing FPGA /
ASIC and SoC design services.
The company's expertise in
architecture, intellectual property,
methodology and tool handling
provides a complete design
environment that helps
customers shorten their design
cycle and speed time to market.
Our offering covers feasibility
study, concept analysis,
architecture definition, code
generation and implementation.
When ready, we deliver you a
FPGA or take your design to an
ASIC provider, whatever is more
suitable for your unique solution.
Deliverables
The core is available as Actel
optimized netlist or as RTL
version.
Actel Optimized Netlist:
• Netlist for target FPGA, EDIF,
Verilog and VHDL format
• User Guide
RTL Source Code:
• VHDL or Verilog source code
• Functional verification
testbench
• Synthesis script
• Timing constraints
• User guide
With a separate APB wrapper, the core can be used in ARM subsystems.
© 2009, Inicore Inc, All rights reserved.
All brands or product names mentioned are
the property of their respective holders.
51140.71.01 Jan/2009
INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 www.inicore.com
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