8-Bit Serial-Input Shift Register With Latched 3

TECHNICAL DATA
IN74HC4094A
8-Bit Serial-Input Shift Register
With Latched 3-State Outputs
High-Performance Silicon-Gate CMOS
The IN74HC4094A is identical in pinout to the LS/ALS4094. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of an 8-bit shift register and 8-bit D-type latch
with three-state parallel outputs. Data is shifted serially through the shift
register on the positive going transition of the clock input signal. The
output of the last stage SQH can be used to cascade several devices.
Data on the SQH output is transferred to a second output (SQH’) on the
following negative transition of the clock input signal. The data of each
stage of the shift register is provided with a latch, which latches data on
the negative going transition of the Strobe input signal. When the Strobe
input is held high, data propagates through the latch to a 3-state output
buffer.
This buffer is enabled when Output Enable input is taken high.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC4094AN Plastic
IN74HC4094AD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Clock Output
Enable
PIN 16 =VCC
PIN 8 = GND
Parallel
Outputs
Strobe A
QA
QN
Serial
Outputs
SQH SQH’
L
X
X
Z
Z
Q6
L
X
X
Z
Z
NC SQH
H
L
X NC
NC
Q6
NC
H
H
L
L
QN-1
Q6
NC
H
H
H
H
QN-1
Q6
NC
NC
NC SQH
H
X
NC = No Change
Z = high impedance
X = don’t care
X NC
NC
Rev. 00
IN74HC4094A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
-55
+125
°C
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
Rev. 00
IN74HC4094A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
VIH
Minimum High-Level
Input Voltage
VIL
VOH
Test Conditions
V
25 °C
to
-55°C
≤85
°C
≤125
°C
Unit
VOUT= 0.1 V or VCC-0.1 V
IOUT≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
Maximum Low Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
IOUT ≤ 20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
Minimum High-Level
Output Voltage
VIN=VIH or VIL
IOUT ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VIN= VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
VIN= VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
VOL
Guaranteed Limit
Maximum Low-Level
Output Voltage
VIN=VIH or VIL
IOUT ≤ 20 µA
V
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0
±1.0
µA
IOZ
Maximum ThreeState Leakage
Current
Output in High-Impedance
State
VIN= VIL or VIH
VOUT=VCC or GND
6.0
±0.5
±5.0
±10
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA
6.0
4.0
40
160
µA
Rev. 00
IN74HC4094A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
VCC
Symbol
V
25 °C
to
-55°C
≤85°C
≤125°C
Unit
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
2.0
4.5
6.0
6
30
35
5
25
28
4
20
23
MHz
tPLH, tPHL
Maximum Propagation Delay, Clock to SQH
(Figures 1 and 5)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPLH, tPHL
Maximum Propagation Delay, Clock to QA-QH
(Figures 2 and 5)
2.0
4.5
6.0
195
40
33
245
50
42
295
60
50
ns
tPLZ, tPHZ
Maximum Propagation Delay ,Output Enable to
QA-QH (Figures 3 and 6)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tPZL, tPZH
Maximum Propagation Delay ,Output Enable to
QA-QH (Figures 3 and 6)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
Maximum Input Capacitance
-
10
10
10
pF
Maximum Three-State Output Capacitance
(Output in High-Impedance State), QA-QH
-
15
15
15
pF
fmax
CIN
COUT
CPD
Parameter
Guaranteed Limit
Power Dissipation Capacitance (Per Package)
Typical @25°C,VCC=5.0 V
Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
300
pF
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Symbol
Parameter
Guaranteed Limit
V
25 °C to
-55°C
≤85°C
≤125°C
Unit
tsu
Minimum Setup Time, Serial Data
Input A to Clock (Figure 4)
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
th
Minimum Hold Time, Clock to Data
Input A (Figure 4)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
tw
Minimum Pulse Width, Strobe
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
tr, tf
Rev. 00
IN74HC4094A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Test Circuit
Figure 6. Test Circuit
Rev. 00
IN74HC4094A
EXPANDED LOGIC DIAGRAM
Rev. 00
IN74HC4094A
TIMING DIAGRAM
Rev. 00
IN74HC4094A
N SUFFIX PLASTIC DIP
(MS - 001BB)
A
Dimension, mm
9
16
Symbol
MIN
MAX
A
18.67
19.69
B
6.1
7.11
B
1
8
5.33
C
F
L
C
D
0.36
0.56
F
1.14
1.78
G
2.54
H
7.62
-T- SEATING
PLANE
N
G
K
M
H
D
J
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 012AC)
Dimension, mm
A
16
9
H
B
1
G
P
8
R x 45
C
-TK
D
SEATING
PLANE
J
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
F
M
Symbol
MIN
MAX
A
9.8
10
B
3.8
4
C
1.35
1.75
D
0.33
0.51
F
0.4
1.27
G
1.27
H
5.72
J
0°
8°
K
0.1
0.25
M
0.19
0.25
P
5.8
6.2
R
0.25
0.5
Rev. 00