M15F1G1664A (2R)

ESMT
M15F1G1664A (2R)
DDR III SDRAM
8M x 16 Bit x 8 Banks
DDR III SDRAM
Feature
z
1.5V ± 0.075V (JEDEC Standard Power Supply)
z
Output Driver Impedance Control
z
Programmable CAS Latency: 5, 6, 7, 8, 9,10,11
z
Differential bidirectional data strobe
z
8 Internal memory banks (BA0- BA2)
z
Write Leveling
z
Differential clock input (CK, CK )
z
OCD Calibration
z
POSTED CAS ADDITIVE Programmable Additive
z
Dynamic ODT (Rtt_Nom & Rtt_WR)
Latency (AL): 0, CL-1, CL-2 clock
z
Auto Self-Refresh
z
Programmable Sequential / Interleave Burst Type
z
Self-Refresh Temperature
z
Programmable Burst Length: 4, 8
z
8n-bit prefetch architecture
Ordering Information
Data Rate
Product ID
Max Freq.
VDD
Package
Comments
96 ball BGA
Pb-free
(CL-tRCD-tRP)
M15F1G1664A –ADBG2R
800MHz
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1.5V
DDR3-1600 (10-10-10)
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M15F1G1664A (2R)
Description
The 1Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation. It is internally
configured as an eight bank DRAMs.
The 1Gb chip is organized as 8Mbit x 16 I/Os x 8 bank devices.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized
with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.
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M15F1G1664A (2R)
Pin Configuration – 96 balls BGA Package
< TOP View>
See the balls through the package
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M15F1G1664A (2R)
Input / Output Functional Description
Symbol
Type
CK, CK 
Input
CKE
Input
Function
Clock: CK and CK  are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK .
Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE low provides Precharge Power-Down
and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).
CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become
stable during the power on and initialization sequence, they must be maintained during all
operations (including Selg-Refresh). CKE must be maintained high throughout read and
write accesses. Input buffers, excluding CK, CK , ODT and CKE are disabled during
Power Down. Input buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select: All commands are masked when CS is registered high. CS provides for
CS
Input
external rank selection on systems with multiple memory ranks. CS is considered part of
the command code.
RAS , CAS , WE
Input
Command Inputs: RAS , CAS and WE (along with CS ) define the command being
entered.
DM, (DMU, DML)
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
both edges of DQS.
BA0 - BA2
Input
Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read, Write or
Precharge command is being applied. Bank address also determines which mode register
is to be accessed during a MRS cycle.
Input
Auto-Precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation.
(HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses.
A10 / AP
A0 – A12
Input
A12/ BC
Input
ODT
Input
Address Inputs: Provide the row address for Activate commands and the column address
for Read/Write commands to select one location out of the memory array in the respective
bank. (A10/AP and A12/ BC have additional function as below.) The address inputs also
provide the op-code during Mode Register Set commands.
Burst Chop: A12/ BC is sampled during Read and Write commands to determine if burst
chop (on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped).
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS , and DM. The
ODT pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT.
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Symbol
M15F1G1664A (2R)
Type
Function
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive
RESET
Input
DQ (DQL, DQU)
Input/output
DQS, DQS
(DQSL, DQSL ,
Input/output
DQSU, DQSU )
NC
-
when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC
high and 0.30V for DC low.
Data Inputs/Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge aligned with read data,
centered with write data. DQSL corresponds to the data on DQL0-DQL7; DQSU
corresponds to the data on DQU0-DQU7. The data strobes DQS (DQSL, DQSU) are paired
with differential signals DQS ( DQSL , DQSU ), respectively, to provide differential pair
signaling to the system during both reads and writes. DDR3 SDRAM supports differential
data strobe only and does not support single-ended.
No Connect: No internal electrical connection is present.
VDDQ
Supply
DQ Power Supply: 1.5V ± 0.075V
VDD
Supply
Power Supply: 1.5V ± 0.075V
VSSQ
Supply
DQ Ground
VSS
Supply
Ground
VREFCA
Supply
Reference voltage for CA
VREFDQ
Supply
Reference voltage for DQ
ZQ
Supply
Reference pin for ZQ calibration.
Note: Input only pins (BA0-BA2, A0-A12, RAS , CAS , WE , CS , CKE, ODT, and RESET ) do not supply termination.
DDR3 SDRAM Addressing
Configuration
# of Bank
Bank Address
M15F1G1664A
8
BA0 – BA2
Auto precharge
A10 / AP
BL switch on the fly
A12 / BC
Row Address
A0 – A12
Column Address
A0 – A9
Page size
2KB
Note:
Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is
registered. Page size is per bank, calculated as follows:
Page size = 2 COLBITS * ORG / 8
where
COLBITS = the number of column address bits
ORG = the number of I/O (DQ) bits
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M15F1G1664A (2R)
Simplified State Diagram
Power
Applied
Power
ON
From any
State
Reset
Procedure
MRS, MPR,
Write
Levelizing
Initialization
ZQCL
Self Refresh
SRE
MRS
SRX
RESET
ZQCL
ZQCS
ZQ Calibration
Idle
REF
Refreshing
PDX
ACT
PDE
Precharge
Power
Down
Activating
Active
Power
Down
PDE
PDX
Bank
Active
Write
Read
Read
Write
Read
Writing
Reading
Write
Write A
Automatic
Sequence
Read A
Write A
Read A
Read A
Write A
Command
Sequence
PRE,
PREA
Writing
PRE,
PREA
Reading
PRE,
PREA
Precharging
State Diagram Command Definitions
Abbreviation
ACT
PRE
PREA
MRS
REF
ZQCL
Function
Abbreviation
Function
Abbreviation
Function
Active
Read
RD, RDS4, RDS8
PDE
Enter Power-down
Precharge
Read A
RDA, RDAS4, RDAS8
PDX
Exit Power-down
Precharge All
Write
WR, WRS4, WRS8
SRE
Self-Refresh entry
Mode Register Set
Write A
WRA, WRAS4, WRAS8
SRX
Self-Refresh exit
Refresh
RESET
Start RESET Procedure
MPR
Multi-Purpose Register
ZQ Calibration Long
ZQCS
ZQ Calibration Short
-
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Basic Functionality The DDR3 SDRAM is a high-speed dynamic random access memory internally configured as an eight-bank DRAM. The DDR3
SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n prefetch architecture is combined with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3
SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and two corresponding n-bit wide,
one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and continue for a burst length of
eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an Active command, which
is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select
the bank and row to be activated (BA0-BA2 select the bank; A0-A12 select the row). The address bit registered coincident with
the Read or Write command are used to select the starting column location for the burst operation, determine if the auto
precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined manner. The following sections
provide detailed information covering device reset and initialization, register definition, command descriptions and device operation.
RESET and Initialization Procedure
Power-up Initialization sequence
The Following sequence is required for POWER UP and Initialization
1. Apply power ( RESET is recommended to be maintained below 0.2 x VDD, all other inputs may be undefined). RESET
needs to be maintained for minimum 200μs with stable power. CKE is pulled “Low” anytime before RESET being
de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDDmin must be no greater than 200ms; and
during the ramp, VDD>VDDQ and (VDD-VDDQ) <0.3 Volts.
- VDD and VDDQ are driven from a single power converter output, AND
- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side
and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95V max once power
ramp is finished, AND
- VREF tracks VDDQ/2.
OR
- Apply VDD without any slope reversal before or at the same time as VDDQ.
- Apply VDDQ without any slope reversal before or at the same time as VTT & VREF.
- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side
and must be larger than or equal to VSSQ and VSS on the other side.
2. After RESET is de-asserted, wait for another 500us until CKE become active. During this time, the DRAM will start internal
state initialization; this will be done independently of external clocks.
3. Clock (CK, CK ) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active. Since
CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be meeting. Also a NOP or Deselect command
must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE registered “High” after Reset, CKE
needs to be continuously registered “High” until the initialization sequence is finished, including expiration of tDLLK and tZQinit.
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4. The DDR3 DRAM will keep its on-die termination in high impedance state as long as RESET is asserted. Further, the DRAM
keeps its on-die termination in high impedance state after RESET de-assertion until CKE is registered HIGH. The ODT input
signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal
may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1, the ODT input signal must be statically
held LOW. In all cases, the ODT input signal remains static until the power up initialization sequence is finished, including the
expiration of tDLLK and tZQinit.
5. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command to load
mode register. [tXPR=max (tXS, 5tCK)]
6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to BA0 and
BA2, “High” to BA1)
7. Issue MRS command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to BA2,
“High” to BA0 and BA1)
8. Issue MRS command to load MR1 with all application settings and DLL enabled. (To issue “DLL Enable” command, provide
“Low” to A0, “High” to BA0 and “Low” to BA1 and BA2)
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command, provide “High”
to A8 and “Low” to BA0-BA2)
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
12. The DDR3 SDRAM is now ready for normal operation.
Fig. 1: Reset and Initialization Sequence at Power- on Ramping (Cont’d)
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Reset Procedure at Stable Power (Cont’d)
The following sequence is required for RESET at no power interruption initialization.
1.
Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to be
maintained for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time 10ns).
2.
Follow Power-up Initialization Sequence step 2 to 11.
3.
The Reset sequence is now completed. DDR3 SDRAM is ready for normal operation.
Fig. 2: Reset Procedure at Power Stable Condition Elite Semiconductor Memory Technology Inc
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Register Definition
Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by the
DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. As the
default values of the Mode Registers (MR) are not defined, contents of Mode Registers must be fully initialized and/or re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers can be altered by
re-executing the MRS command during normal operation. When programming the mode registers, even if the user chooses to
modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be redefined when the MRS
command is issued. MRS command and DLL Reset do not affect array contents, which mean these commands can be executed
any time after power-up without affecting the array contents.
The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the
minimum time required between two MRS commands shown as below.
Fig. 3: tMRD Timing
The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except DLL reset, and is
the minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown as the following
figure.
Fig. 4: tMOD Timing Elite Semiconductor Memory Technology Inc
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Programming the Mode Registers (Cont’d)
The mode register contents can be changed using the same command and timing requirements during normal operation as long
as the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed and CKE is
high prior to writing into the mode register. If the RTT_NOM Feature is enabled in the Mode Register prior and/or after an MRS
Command, the ODT Signal must continuously be registered LOW ensuring RTT is in an off State prior to the MRS command. The
ODT Signal may be registered high after tMOD has expired. If the RTT_NOM Feature is disabled in the Mode Register prior and
after an MRS command, the ODT Signal can be registered either LOW or HIGH before, during and after the MRS command. The
mode registers are divided into various fields depending on the functionality and/or modes.
Mode Register MR0
The mode-register MR0 stores data for controlling various operating modes of DDR3 SDRAM. It controls burst length, read burst
type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which include various vendor specific
options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting low on CS , RAS ,
CAS , WE , BA0, BA1, and BA2, while controlling the states of address pins according to the following figure.
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Fig. 5:MR0 Definition
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Burst Length, Type, and Order Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 as
shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length, burst type,
and the starting column address. The burst length is defined by bits A0-A1. Burst lengths options include fix BC4, fixed BL8, and
on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/ BC .
Table 1: Burst Type and Burst Order
Burst
Length
4
Chop
Read
Write
Read
Write
8
Read
Starting
Column
Address
(A2,A1,A0)
Burst type:
Sequential
(decimal)
A3 = 0
Burst type:
Interleaved
(decimal)
A3 = 1
0,0,0
0,1,2,3,T,T,T,T
0,1,2,3,T,T,T,T
0,0,1
0,1,0
0,1,1
1,0,0
1,0,1
1,1,0
1,1,1
0,V,V
1,V,V
0,0,0
0,0,1
0,1,0
0,1,1
1,0,0
1,0,1
1,1,0
1,1,1
V,V,V
1,2,3,0,T,T,T,T
2,3,0,1,T,T,T,T
3,0,1,2,T,T,T,T
4,5,6,7,T,T,T,T
5,6,7,4,T,T,T,T
6,7,4,5,T,T,T,T
7,4,5,6,T,T,T,T
0,1,2,3,X,X,X,X
4,5,6,7,X,X,X,X
0,1,2,3,4,5,6,7
1,2,3,0,5,6,7,4
2,3,0,1,6,7,4,5
3,0,1,2,7,4,5,6
4,5,6,7,0,1,2,3
5,6,7,4,1,2,3,0
6,7,4,5,2,3,0,1
7,4,5,6,3,0,1,2
0,1,2,3,4,5,6,7
1,0,3,2,T,T,T,T
2,3,0,1,T,T,T,T
3,2,1,0,T,T,T,T
4,5,6,7,T,T,T,T
5,4,7,6,T,T,T,T
6,7,4,5,T,T,T,T
7,6,5,4,T,T,T,T
0,1,2,3,X,X,X,X
4,5,6,7,X,X,X,X
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
0,1,2,3,4,5,6,7
Note
1,2,3
1,2,4,5
2
Write
2,4
Note:
1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than
the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length
being selected on-the-fly via A12/ , the internal write operation starts at the same point in time like a burst of 8 write
operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.
2. 0~7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst.
3. T: Output driver for data and strobes are in high impedance.
4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
5. X: Do not Care.
CAS Latency
The CAS Latency is defined by MR0 (bit A2, A4~A6) as shown in the MR0 Definition figure. CAS Latency is the delay, in clock
cycles, between the internal Read command and the availability of the first bit of output data. DDR3 SDRAM does not support
any half clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL); RL = AL + CL.
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Test Mode
The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in the MR0 definition
figure. Programming bit A7 to a ‘1’ places the DDR3 SDRAM into a test mode that is only used by the DRAM manufacturer and
should not be used. No operations or functionality is guaranteed if A7=1.
DLL Reset
The DLL Reset bit is self-clearing, meaning it returns back to the value of ‘0’ after the DLL reset function has been issued. Once
the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is used, tDLLK must be met
before any functions that require the DLL can be used (i.e. Read commands or ODT synchronous operations.)
Write Recovery
The programmed WR value MR0(bits A9, A10, and A11) is used for the auto precharge feature along with tRP to determine tDAL
WR (write recovery for auto-precharge)min in clock cycles is calculated by dividing tWR(ns) by tCK(ns) and rounding up to the
next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to be equal or larger than tWR (min).
Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12=0), or ‘slow-exit’, the DLL
is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be met prior to the
next valid command. When MR0 (A12=1), or ‘fast-exit’, the DLL is maintained after entering precharge power-down and upon
exiting power-down requires tXP to be met prior to the next valid command.
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Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output strength, Rtt_Nom impedance, additive latency,
WRITE leveling enable and Qoff. The Mode Register 1 is written by asserting low on CS , RAS , CAS , WE , high on BA0 and
low on BA1 and BA2, while controlling the states of address pins according to the following figure.
Fig. 6: MR1 Definition
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DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0=0), the DLL is automatically disabled when entering Self-Refresh operation and is automatically re-enable upon exit of Self-Refresh operation. Any time the DLL
is enabled and subsequently reset, tDLLK clock cycles must occur before a Read or synchronous ODT command can be issued
to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may
result in a violation of the tDQSCK, tAON, or tAOF parameters. During tDLLK, CKE must continuously be registered high. DDR3
SDRAM does not require DLL for any Write operation, expect when RTT_WR is enabled and the DLL is required for proper ODT
operation. For more detailed information on DLL Disable operation in DLL-off Mode.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continuously
registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register set
command during DLL-off mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set Rtt_WR, MR2 {A10, A9} = {0,
0}, to disable Dynamic ODT externally.
Output Driver Impedance Control
The output driver impedance of the DDR3 SDRAM device is selected by MR1 (bit A1 and A5) as shown in MR1 definition figure.
ODT Rtt Values
DDR3 SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal termination value
Rtt_Nom is programmable in MR1. A separate value (Rtt_WR) may be programmable in MR2 to enable a unique Rtt value when
ODT is enabled during writes. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled.
Additive Latency (AL)
Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidth in DDR3
SDRAM. In this operation, the DDR3 SDRAM allows a read or write command (either with or without auto-precharge) to be
issued immediately after the active command. The command is held for the time of the Additive Latency (AL) before it is issued
inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL) register settings. Write
Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A summary of the AL register
options are shown as the following table.
Table 2: Additive Latency (AL) Settings
A4
A3
AL
0
0
0, (AL Disable)
0
1
CL-1
1
0
CL-2
1
1
Reserved
Note: AL has a value of CL-1 or CL-2 as per the CL values programmed in the MR0 register.
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Write leveling
For better signal integrity, DDR3 memory module adopted fly by topology for the commands, addresses, control signals, and
clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time
skew between clock and strobe at every DRAM on DIMM. It makes difficult for the Controller to maintain tDQSS, tDSS, and tDSH
specification. Therefore, the controller should support ‘write leveling’ in DDR3 SDRAM to compensate for skew.
Output Disable
The DDR3 SDRAM outputs maybe enable/disabled by MR1 (bit12) as shown in MR1 definition. When this feature is enabled
(A12=1) all output pins (DQs, DQS, DQS , etc.) are disconnected from the device removing any loading of the output drivers.
This feature may be useful when measuring modules power for example. For normal operation A12 should be set to ‘0’.
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Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write latency. The
Mode Register 2 is written by asserting low on CS , RAS , CAS , WE high on BA1 and low on BA0 and BA2, while controlling
the states of address pins according to the following figure.
Fig. 7: MR2 Definition
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CAS Write Latency (CWL)
The CAS Write Latency is defined by MR2 (bits A3-A5) shown in MR2. CAS Write Latency is the delay, in clock cycles, between
the internal Write command and the availability of the first bit of input data. DDR3 DRAM does not support any half clock
latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency (CWL); WL=AL+CWL.
Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT)
DDR3 SDRAM must support Self-Refresh operation at all supported temperatures. Applications requiring Self-Refresh operation
in the Extended Temperature Range must use the ASR function or program the SRT bit appropriately.
Optional in DDR3 SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3
SDRAM devices support the following options or requirements referred to in this material. For more details refer to “Extended
Temperature Usage” on page36. DDR3 SDRAMs must support Self-Refresh operation at all supported temperatures.
Applications requiring Self-Refresh operation in the Extended Temperature Range must use the optional ASR function or
program the SRT bit appropriately.
Dynamic ODT (Rtt_WR)
DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal integrity on
the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command.
MR2 Register locations A9 and A10 configure the Dynamic ODT settings. In Write leveling mode, only RTT_Nom is available. For
details on Dynamic ODT operation, refer to “Dynamic ODT” on page61.
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Mode Register MR3
The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on CS , RAS , CAS ,
WE high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the following figure.
Fig. 8: MR3 Definition
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Multi-Purpose Register (MPR)
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. To enable
the MPR, a Mode Register Set (MRS) command must be issued to MR3 register with bit A2=1. Prior to issuing the MRS
command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any subsequent RD
or RDA commands will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD or RDA commands are
allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0). Power down mode, Self-Refresh
and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET function is supported during MPR
enable mode.
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence.
Fig. 9: MPR Block Diagram
To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1, prior to issuing the
MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any
subsequent RD or RDA commands will be redirected to the Multi Purpose Register. The resulting operation, when a RD or RDA
command is issued, is defined by MR3 bits A[1:0] when the MPR is enabled as shown on page23. When the MPR is enabled,
only RD or RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2 = 0).
Note that in MPR mode RDA has the same functionality as a READ command which means the auto precharge part of RDA is
ignored. Power-Down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode. The
RESET function is supported during MPR enable mode.
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Table 3: MPR MR3 Register Definition
MR3 A[2]
MR3 A[1:0]
MPR
MPR-Loc
Function
Normal operation, no MPR transaction.
0b
don't care (0b or 1b)
All subsequent Reads will come from DRAM array.
All subsequent Write will go to DRAM array.
1b
See the Table 4
Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].
MPR Functional Description
•One bit wide logical interface via all DQ pins during READ operation.
•Register Read:
•DQL[0] and DQU[0] drive information from MPR.
•DQL[7:1] and DQU[7:1] either drive the same information as DQL [0], or they drive 0b.
•Addressing during for Multi Purpose Register reads for all MPR agents:
•BA [2:0]: don’t care
•A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed
•A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst
Chop 4 cases, the burst order is switched on nibble base A [2]=0b, Burst order: 0,1,2,3 *)
A[2]=1b, Burst order: 4,5,6,7 *)
•A[9:3]: don’t care
•A10/AP: don’t care
•A12/ BC : Selects burst chop mode on-the-fly, if enabled within MR0.
•A11, A12... (if available): don’t care
•Regular interface functionality during register reads:
•Support two Burst Ordering which are switched with A2 and A[1:0]=00b.
•Support of read burst chop (MRS and on-the-fly via A12/ BC )
•All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by the DDR3
SDRAM.
•Regular read latencies and AC timings apply.
•DLL must be locked prior to MPR Reads.
NOTE: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
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MPR Register Address Definition
The following table provide an overview of the available data location, how they are addressed by MR3 A[1:0] during a MRS to
MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read.
Table 4: MPR MR3 Register Definition
MR3 A[2]
1b
MR3 A[1:0]
00b
Function
Read Predefined
Burst Length
BL8
Read Address
Burst Order
A[2:0]
and Data Pattern
000b
Pattern for System
Burst order 0,1,2,3,4,5,6,7
Pre-defined Data Pattern
[0,1,0,1,0,1,0,1]
Calibration
BC4
000b
Burst order 0,1,2,3
Pre-defined Data Pattern
[0,1,0,1]
BC4
100b
Burst order 4,5,6,7
Pre-defined Data Pattern
[0,1,0,1]
1b
1b
1b
01b
10b
11b
RFU
RFU
RFU
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
NOTE: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent.
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DDR3 SDRAM Command Description and Operation
Table 5: Command Truth Table
CKE
Function
Abbreviation Previous Current CS RAS CAS WE
Cycle
Cycle
BA0-
A12/ A10/
BA2
BC
A0-9,
NOTES
AP
A11
Mode Register Set
MRS
H
H
L
L
L
L
BA
Refresh
REF
H
H
L
L
L
H
V
V
V
V
Self Refresh Entry
SRE
H
L
L
L
L
H
V
V
V
V
Self Refresh Exit
SRX
L
H
H
X
X
X
X
X
X
X
L
H
H
H
V
V
V
V
Single Bank Precharge
PRE
H
H
L
L
H
L
BA
V
L
V
PREA
H
H
L
L
H
L
V
V
H
V
Bank Activate
ACT
H
H
L
L
H
H
BA
Write (Fixed BL8 or BC4)
WR
H
H
L
H
L
L
BA
V
L
CA
Write (BC4, on the Fly)
WRS4
H
H
L
H
L
L
BA
L
L
CA
Write (BL8, on the Fly)
WRS8
H
H
L
H
L
L
BA
H
L
CA
Write with Auto Precharge (Fixed BL8 or BC4)
WRA
H
H
L
H
L
L
BA
V
H
CA
Write with Auto Precharge (BC4, on the Fly)
WRAS4
H
H
L
H
L
L
BA
L
H
CA
Write with Auto Precharge (BL8, on the Fly)
WRAS8
H
H
L
H
L
L
BA
H
H
CA
RD
H
H
L
H
L
H
BA
V
L
CA
Read (BC4, on the Fly
RDS4
H
H
L
H
L
H
BA
L
L
CA
Read (BL8, on the Fly)
RDS8
H
H
L
H
L
H
BA
H
L
CA
Read with Auto Precharge (Fixed BL8 or BC4)
RDA
H
H
L
H
L
H
BA
V
H
CA
Read with Auto Precharge (BC4, on the Fly)
RDAS4
H
H
L
H
L
H
BA
L
H
CA
Read with Auto Precharge (BL8, on the Fly)
RDAS8
H
H
L
H
L
H
BA
H
H
CA
No Operation
NOP
H
H
L
H
H
H
V
V
V
V
10
Device Deselected
DES
H
H
H
X
X
X
X
X
X
X
11
Power Down Entry
PDE
H
L
L
H
H
H
V
V
V
V
H
X
X
X
X
X
X
X
Power Down Exit
PDX
L
H
L
H
H
H
V
V
V
V
H
X
X
X
X
X
X
X
ZQ Calibration Long
ZQCL
H
H
L
H
H
L
X
X
H
X
ZQ Calibration Short
ZQCS
H
H
L
H
H
L
X
X
L
X
Precharge all Banks
Read (Fixed BL8 or BC4)
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OP Code
7,9,12
7,8,9,12
Row Address (RA)
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M15F1G1664A (2R)
DDR3 SDRAM Command Description and Operation
Command Truth Table (Conti.)
NOTE1. All DDR3 SDRAM commands are defined by states of CS , RAS , CAS , WE and CKE at the rising edge of the clock.
The MSB of BA, RA and CA are device density and configuration dependant.
NOTE2. RESET is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during
any function.
NOTE3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode
Register.
NOTE4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.
NOTE5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS.
NOTE6. The Power-Down Mode does not perform any refresh operation.
NOTE7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self
Refresh.
NOTE8. Self Refresh Exit is asynchronous.
NOTE9. VREF (Both VrefDQ and VrefCA) must be maintained during Self Refresh operation.
NOTE10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait state. The purpose
of the No Operation command (NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands
between operations. A No Operation command will not terminate a pervious operation that is still executing, such as a
burst read or write cycle.
NOTE11. The Deselect command performs the same function as No Operation command.
NOTE12. Refer to the CKE Truth Table for more detail with CKE transition.
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Table 6: CKE Truth Table
CKE
Current State
Command (N)
Previous Cycle Current Cycle
Action (N)
Notes
RAS , CAS , WE , CS
(N-1)
(N)
L
L
X
Maintain Power-Down
14,15
L
H
DESELECT or NOP
Power-Down Exit
11,14
L
L
X
Maintain Self-Refresh
15,16
L
H
DESELECT or NOP
Self-Refresh Exit
8,12,16
Bank(s) Active
H
L
DESELECT or NOP
Active Power-Down Entry
11,13,14
Reading
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Writing
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Precharging
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Refreshing
H
L
DESELECT or NOP
Precharge Power-Down Entry
11
H
L
DESELECT or NOP
Precharge Power-Down Entry
11,13,14,18
H
L
REFRESH
Self-Refresh
9,13,18
Power-Down
Self-Refresh
All Banks Idle
NOTE 1 CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
NOTE 2 Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N.
NOTE 3 COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not
included here.
NOTE 4 All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
NOTE 5 The state of ODT does not affect the states described in this table. The ODT function is not available during
Self-Refresh.
NOTE 6 CKE must be registered with the same value on tCKEmin consecutive positive clock edges. CKE must remain at the
valid input level the entire time it takes to achieve the tCKEmin clocks of registrations. Thus, after any CKE transition,
CKE may not transition from its valid level during the time period of tIS + tCKEmin + tIH.
NOTE 7 DESELECT and NOP are defined in the Command Truth Table.
NOTE 8 On Self-Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS
period. Read or ODT commands may be issued only after tXSDLL is satisfied.
NOTE 9 Self-Refresh modes can only be entered from the All Banks Idle state.
NOTE 10 Must be a legal command as defined in the Command Truth Table.
NOTE 11 Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
NOTE 12 Valid commands for Self-Refresh Exit are NOP and DESELECT only.
NOTE 13 Self-Refresh cannot be entered during Read or Write operations.
NOTE 14 The Power-Down does not perform any refresh operations.
NOTE 15 “X” means “don’t care“(including floating around VREF) in Self-Refresh and Power-Down. It also applies to Address
pins.
NOTE 16 VREF (Both Vref_DQ and Vref_CA) must be maintained during Self-Refresh operation.
NOTE 17 If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power-Down is
entered, otherwise Active Power-Down is entered.
NOTE 18 ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high,
and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as
all Self-Refresh exit and Power-Down Exit parameters are satisfied (tXS, tXP, tXPDLL, etc).
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No Operation (NOP) Command
The No operation (NOP) command is used to instruct the selected DDR3 SDRAM to perform a NOP ( CS low and RAS , CAS ,
and WE high). This prevents unwanted commands from being registered during idle or wait states. Operations already in
progress are not affected.
Deselect Command
The Deselect function ( CS HIGH) prevents new commands from being executed by the DDR3 SDRAM. The DDR3 SDRAM is
effectively deselected. Operations already in progress are not affected.
DLL- Off Mode
DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until A0 bit set
back to “0”. The MR1 A0 bit for DLL control can be switched either during initialization or later.
The DLL-off Mode operations listed below are an optional feature for DDR3. The maximum clock frequency for DLL-off Mode is
specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the refresh interval,
tREFI.
Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write Latency (CWL) in MR2
are supported. The DLL-off mode is only required to support setting of both CL=6 and CWL=6.
DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the data Strobe to Data relationship
(tDQSQ, tQH). Special attention is needed to line up Read data to controller time domain.
Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after the Read command, the
DLL-off mode tDQSCK starts (AL+CL-1) cycles after the read command. Another difference is that tDQSCK may not be small
compared to tCK (it might even be larger than tCK) and the difference between tDQSCKmin and tDQSCKmax is significantly
larger than in DLL-on mode.
The timing relations on DLL-off mode READ operation have shown at the following Timing Diagram (CL=6, BL=8)
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Fig. 10 DLL-off mode READ Timing Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK
CK
CMD
Address
READ
Bank, Col b
RL = AL+CL = 6 (CL=6, AL=0)
DQSdiff_DLL_on
Din
b
DQ_DLL_on
RL(DLL_off) = AL+(CL-1) = 5
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
tDQSCKDLL_diff_min
DQSdiff_DLL_off
DQ_DLL_off
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
Din
b+3
Din
b+4
Din
b+5
Din
b+6
DQSdiff_DLL_off
tDQSCKDLL_diff_max
DQ_DLL_off
Din
b
Din
b+1
Din
b+2
Din
b+7
Note: The tDQSCK is used here for DQS, DQS , and DQ to have a simplified diagram; the DLL_off shift will affect both timings in
the same way and the skew between all DQ, DQS, and DQS signals will still be tDQSQ.
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DLL on/off switching procedure
DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operation until A0 bit set
back to “0”.
DLL “on” to DLL “off” Procedure
To switch from DLL “on” to DLL “off” requires the frequency to be changed during Self-Refresh outlined in the following
procedure:
1.
Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT, must be in
high impedance state before MRS to MR1 to disable the DLL).
2.
Set MR1 Bit A0 to “1” to disable the DLL.
3.
Wait tMOD.
4.
Enter Self Refresh Mode; wait until (tCKSRE) satisfied.
5.
Change frequency, in guidance with “Input Clock Frequency Change” section.
6.
Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
7.
Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from any
MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh mode
was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any MRS command are
satisfied. If both ODT features were disabled in the mode registers when Self Refresh mode was entered, ODT signal can
be registered LOW or HIGH.
8.
Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be
necessary. A ZQCL command may also be issued after tXS).
9.
Wait for tMOD, and then DRAM is ready for next command.
Fig. 11: DLL Switch Sequence from DLL-on to DLL-off
T0
T1
Ta0
Ta1
Tb0
Tc0
Td0
Td1
SRX 6)
NOP
Te 0
Te1
Tf0
CK
CK
tMOD
CMD
1)
MRS 2)
NOP
tCKSRE
SRE 3)
4)
tCKSRX 5)
NOP
tXS
tMOD
MRS 7)
NOP
Valid 8)
tCKESR
CKE
Valid 8)
ODT
Valid 8)
Time
break
Do not
Care
Note:
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
1) Starting with Idle State, RTT in Hi-Z State.
2) Disable DLL by setting MR1 Bit A0 to 1.
3) Enter SR.
4) Change Frequency.
5) Clock must be stable at least tCKSRX.
6) Exit SR.
7) Update Mode registers with DLL off parameters setting.
8) Any valid command.
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DLL “off” to DLL “on” Procedure
To switch from DLL “off” to DLL “on” (with requires frequency change) during Self-Refresh:
1.
Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT) must be in
high impedance state before Self-Refresh mode is entered).
2.
Enter Self Refresh Mode, wait until tCKSRE satisfied.
3.
Change frequency, in guidance with “Input clock frequency change” section.
4.
Wait until a stable is available for at least (tCKSRX) at DRAM inputs.
5.
Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from subsequent
DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh
mode was entered. The ODT signal must continuously be registered LOW until tDLLK timings from subsequent DLL Reset
command is satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was entered, ODT
signal can be registered LOW or HIGH.
6.
Wait tXS, then set MR1 Bit A0 to “0” to enable the DLL.
7.
Wait tMRD, then set MR0 Bit A8 to “1” to start DLL Reset.
8.
Wait tMRD, then set Mode registers with appropriate values (especially an update of CL, CWL, and WR may be necessary.
After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during or after tDLLK).
9.
Wait for tMOD, then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before applying command
requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued.
Fig. 12 DLL Switch Sequence from DLL-off to DLL-on
T0
Ta 0
Ta1
Tb0
Tc0
Tc1
Td0
Te0
Tf1
Tg0
Th0
SRX 5 )
MRS 6)
MRS 7)
MRS 8)
Valid
CK
CK
CMD
1)
NOP
SRE 2)
ODTLoff
+ 1tck
NOP
tCKSRE
3)
tCKSRX 4)
tXS
tMRD
tMRD
tDLLK
CKE
Valid
tCKESR
ODT
Note:
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
1) Starting from Idle State.
2) Enter SR.
3) Change Frequency.
4) Clock must be stable at least tCKSRX.
5) Exit SR.
6) Set DLL-on by MR1 A0="0"
7) Start DLL Reset
8) Any valid command
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Time
break
Do not
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M15F1G1664A (2R)
Input Clock frequency change
Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be “stable” during almost all states of normal
operation. This means once the clock frequency has been set and is to be in the “stable state”, the clock period is not allowed to
deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking) specification.
The input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1)
Self-Refresh mode and (2) Precharge Power-Down mode. Outside of these two modes, it is illegal to change the clock frequency.
For the first condition, once the DDR3 SDRAM has been successfully placed in to Self-Refresh mode and tCKSRE has been
satisfied, the state of the clock becomes a don’t care. Once a don’t care, changing the clock frequency is permissible, provided
the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode of the sole purpose of changing
the clock frequency. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum
operating frequency specified for the particular speed grade.
The second condition is when the DDR3 SDRAM is in Precharge Power-Down mode (either fast exit mode or slow exit mode). If
the RTT_Nom feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal must
continuously be registered LOW ensuring RTT is in an off state. If the RTT_Nom feature was disabled in the mode register prior
to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH
in this case. A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency may change. The DDR3
SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the
particular speed grade. During the input clock frequency change, ODT and CKE must be held at stable LOW levels. Once the
input clock frequency is changed, stable new clocks must be provided to the DRAM tCKSRX before precharge Power Down may
be exited; after Precharge Power Down is exited and tXP has expired, the DLL must be RESET via MRS. Depending on the new
clock frequency additional MRS commands may need to be issued to appropriately set the WR, CL, and CWL with CKE
continuously registered high. During DLL re-lock period, ODT must remain LOW and CKE must remain HIGH. After the DLL lock
time, the DRAM is ready to operate with new clock frequency.
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Fig. 13: Change Frequency during Precharge Power-down
Previous Clock Frequency
T0
T1
T2
New Clock Frequency
Ta0
Tb0
Tc0
Tc1
Td0
Td1
Te0
Te1
NOP
MRS
NOP
Valid
tCKb
tCHb tCLb
tCK
CK
CK
tCH
tCL
tCKSRE
tCKSRX
CKE
tIH
tIS
tIH
tCPDED
tIS
tCKE
Command
NOP
NOP
NOP
NOP
DLL
Reset
Address
tAOFPD/tAOF
Valid
tXP
ODT
tIH
DQS,
DQS
tIS
High-Z
tDLLK
High-Z
DQ
DM
Enter Precharge
Power-Down mode
Frequency
Change
Exit Precharge
Power-Down mode
NOTES:
1.
Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down
2.
tAOFPD and tAOF must be statisfied and outputs High-Z prior to T1; refer to ODT timing section for exact requirements
3.
If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal
must continuously be registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in the mode register
prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or
HIGH in this case.
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M15F1G1664A (2R)
Write Leveling
For better signal integrity, DDR3 memory adopted fly by topology for the commands, addresses, control signals, and clocks. The
fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time skew between
clock and strobe at every DRAM on DIMM. It makes it difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification.
Therefore, the controller should support “write leveling” in DDR3 SDRAM to compensate the skew.
The memory controller can use the “write leveling” feature and feedback from the DDR3 SDRAM to adjust the DQS - DQS to CK
- CK relationship. The memory controller involved in the leveling must have adjustable delay setting on DQS - DQS to align
the rising edge of DQS - DQS with that of the clock at the DRAM pin. DRAM asynchronously feeds back CK - CK , sampled
with the rising edge of DQS - DQS , through the DQ bus. The controller repeatedly delays DQS - DQS until a transition from 0 to
1 is detected. The DQS - DQS delay established though this exercise would ensure tDQSS specification. Besides tDQSS, tDSS,
and tDSH specification also needs to be fulfilled. One way to achieve this is to combine the actual tDQSS in the application with
an appropriate duty cycle and jitter on the DQS - DQS signals. Depending on the actual tDQSS in the application, the actual
values for tDQSL and tDQSH may have to be better than the absolute limits provided in “AC Timing Parameters” section in order
to satisfy tDSS and tDSH specification. A conceptual timing of this scheme is show as below figure.
Fig. 14: Write Leveling Concept
Diff _ CK
Source
Diff _ DQS
Diff _ CK
Destination
Diff _ DQS
DQ
0 or 1
0
0
Push DQS to capture
0 -1 transition
DQ
0 or 1
1
1
DQS/ DQS driven by the controller during leveling mode must be determined by the DRAM based on ranks populated. Similarly,
the DQ bus driven by the DRAM must also be terminated at the controller.
One or more data bits should carry the leveling feedback to the controller across the DRAM configurations x16. On a x16 device,
both byte lanes should be leveled independently. Therefore, a separate feedback mechanism should be able for each byte lane.
The upper data bits should provide the feedback of the upper diff_DQS (diff_UDQS) to clock relationship whereas the lower data
bits would indicate the lower diff_DQS (diff_LDQS) to clock relationship.
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DRAM setting for write leveling and DRAM termination unction in that mode
DRAM enters into Write leveling mode if A7 in MR1 set “High” and after finishing leveling, DRAM exits from write leveling mode if
A7 in MR1 set “Low”. Note that in write leveling mode, only DQS/ DQS terminations are activated and deactivated via ODT pin
not like normal operation.
Table 7: MR setting involved in the leveling procedure
Function
MR1
Enable
Disable
Write leveling enable
A7
1
0
Output buffer mode (Qoff)
A12
0
1
Table 8: DRAM termination function in the leveling mode
ODT pin at DRAM
DQS/ DQS termination
DQs termination
De-asserted
off
off
Asserted
on
off
Note: In write leveling mode with its output buffer disabled (MR1[bit7]=1 with MR1[bit12]=1) all RTT_Nom settings are allowed; in
Write Leveling Mode with its output buffer enabled (MR1[bit7]=1 with MR1[bit12]=0) only RTT_Nom settings of RZQ/2,
RZQ/4, and RZQ/6 are allowed.
Procedure Description
Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. With entering write leveling mode, the DQ
pins are in undefined driving mode. During write leveling mode, only NOP or Deselect commands are allowed, as well as an MRS
command to change Qoff bit (MR1[A12]) and an MRS command to exit write leveling (MR1[A7]). Upon exiting write leveling
mode, the MRS command performing the exit (MR1[A7]=0) may also change MR1 bits of A12-A11, A9, A6-A5, and A2-A1. Since
the controller levels one rank at a time, the output of other rank must be disabled by setting MR1 bit A12 to 1. Controller may
assert ODT after tMOD, time at which DRAM is ready to accept the ODT signal.
Controller may drive DQS low and DQS high after a delay of tWLDQSEN, at which time DRAM has applied on-die termination
on these signals. After tDQSL and tWLMRD controller provides a single DQS, DQS edge which is used by the DRAM to
sample CK – CK driven from controller. tWLMRD (max) timing is controller dependent.
DRAM samples CK - CK status with rising edge of DQS - DQS and provides feedback on all the DQ bits asynchronously after
tWLO timing. Either one or all data bits ("prime DQ bit(s)") provide the leveling feedback. The DRAM's remaining DQ bits are
driven Low statically after the first sampling procedure.There is a DQ output uncertainty of tWLOE defined to allow mismatch on
DQ bits. The tWLOE period is defined from the transition of the earliest DQ bit to the corresponding transition of the latest DQ bit.
There are no read strobes (DQS/ DQS ) needed for these DQs. Controller samples incoming DQ and decides to increment or
decrement DQS – DQS delay setting and launches the next DQS/ DQS pulse after some time, which is controller dependent.
Once a 0 to 1 transition is detected, the controller locks DQS – DQS delay setting and write leveling is achieved for the device.
The following figure describes the timing diagram and parameters for the overall Write leveling procedure.
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Fig. 15: Timing details of Write leveling sequence (DQS - DQS is capturing CK - CK low at T1 and CK CK  high at T2)
T1
tWLS
T2
t WLH
tWLS
t WLH
CK
CK
CMD
M RS
NOP
NOP
NOP
NOP
NO P
N OP
N OP
NOP
N OP
NOP
NOP
tMO D
O DT
t DQSL
tWLDQ SEN
tDQSH
tDQSL
tDQSH
Di ff_ DQ S
tWLMR D
On e Pri me DQ :
tWLO
t WLO
Prime DQ
t WLO
Late
Re ma ini ng
D Qs
Earl y
Re ma ini ng
D Qs
tWLO
All DQs are Prime :
tWLMRD
tWLOE
t WLO
tWLO
Late
Re ma ini ng
D Qs
t WLO E
Earl y
Re ma ini ng
D Qs
tWLO
tWLOE
t WLO
Undefined
Driving Mode
Note:
1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on
one DQ, the remaining DQs must be driven low as shown in above Figure, and maintained at this state
through out the leveling procedure.
2. MRS: Load MR1 to enter write leveling mode
3. NOP: NOP or deselect
4. diff_DQS is the differential data strobe (DQS, ' 4 6 ). Timing reference points are the zero crossings. DQS
is shown with solid line, ' 4 6 is shown with dotted line.
6. DQS/' 4 6 needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for
regular Writes; the max pulse width is system dependent.
Time
break
Do not
Care
Write Leveling Mode Exit
The following sequence describes how Write Leveling Mode should be exited:
1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From now on, DQ pins are in
undefined driving mode, and will remain undefined, until tMOD after the respective MR command (Te1).
2. Drive ODT pin low (tIS must be satisfied) and keep it low (see Tb0).
3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2).
4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be issued after tMRD (Td1).
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Fig. 16: Timing detail of Write Leveling exit
T0
T1
NOP
NOP
T2
Tb0
Ta0
Tc0
Tc1
NOP
NOP
Tc2
Td0
Td1
Te0
Te1
NOP
Valid
NOP
Valid
CK
CK
CMD
NOP
NOP
NOP
MRS
tMOD
MR1
BA
Valid
Valid
tMRD
ODT
tIS
tWLO
RTT_DQS_DQS
tAOFmin
tODTLoff
RTT_Nom
tAOFmax
DQS_DQS
DQ
Result = 1
Time Break
Transitioning
Do not Care
Undefined
Driving Mode
Extended Temperature Usage
DDR3 SDRAM supports the optional extended temperature range of 0°C to +95°C, TC. Thus, the SRT and ASR options must be
used at a minimum. The extended temperature range DRAM must be refreshed externally at 2X (double refresh) anytime the
case temperature is above +85°C (and does not exceed +95°C). The external refreshing requirement is accomplished by
reducing the refresh period from 64ms to 32ms. However, self refresh mode requires either ASR or SRT to support the extended
temperature. Thus either ASR or SRT must be enabled when TC is above +85°C or self refresh cannot be used until the case
temperature is at or below +85°C.
Table 9 summarizes the two extended temperature options and Table 10 summarizes how the two extended temperature options
relate to one another.
Table 9: Mode Register Description
Field
Bits
Description
Auto Self-Refresh (ASR)
When enabled, DDR3 SDRAM automatically provides Self-Refresh power management
ASR
MR2(A6)
functions for all supported operating temperature values. If not enabled, the SRT bit must be
programmed to indicate TOPER during subsequent Self-Refresh operation.
0 = Manual SR Reference (SRT)
1 = ASR enable
Self-Refresh Temperature (SRT) Range
If ASR = 0, the SRT bit must be programmed to indicate TOPER during subsequent Self-Refresh
SRT
MR2(A7)
operation. If ASR = 1, SRT bit must be set to 0.
0 = Normal operating temperature range
1 = Extended operating temperature range
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M15F1G1664A (2R)
Auto Self-Refresh mode - ASR mode
DDR3 SDRAM provides an Auto-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2 bit A6=1 and
MR2 bit A7=0. The DRAM will manage Self-Refresh entry in either the Normal or Extended Temperature Ranges. In this mode,
the DRAM will also manage Self-Refresh power consumption when the DRAM operating temperature changes, lower at low
temperatures and higher at high temperatures. If the ASR option is not supported by DRAM, MR2 bit A6 must set to 0. If the ASR
option is not enabled (MR2 bit A6=0), the SRT bit (MR2 bit A7) must be manually programmed with the operating temperature
range required during Self-Refresh operation. Support of the ASR option does not automatically imply support of the Extended
Temperature Range.
Self-Refresh Temperature Range - SRT
SRT applies to devices supporting Extended Temperature Range only. If ASR=0, the Self-Refresh Temperature (SRT) Range bit
must be programmed to guarantee proper self-refresh operation. If SRT=0, then the DRAM will set an appropriate refresh rate for
Self-Refresh operation in the Normal Temperature Range. If SRT=1, then the DRAM will set an appropriate, potentially different,
refresh rate to allow Self-Refresh operation in either the Normal or Extended Temperature Ranges. The value of the SRT bit can
effect self-refresh power consumption, please refer to IDD table for details.
Table 10: Self-Refresh mode summary
MR2
MR2
A[6]
A[7]
0
0
Allowed Operating
Self-Refresh operation
Temperature Range
for Self-Refresh mode
Self-Refresh rate appropriate for the Normal Temperature Range
Normal (0 ~ 85C)
Self-Refresh appropriate for either the Normal or Extended Temperature Ranges.
0
1
The DRAM must support Extended Temperature Range. The value of the SRT bit
can effect self-refresh power consumption, please refer to the IDD table for details.
1
0
1
0
1
1
ASR enabled (for devices supporting ASR and Normal Temperature Range).
Self-Refresh power consumption is temperature dependent.
Normal and Extended
(0 ~ 95C)
Normal (0 ~ 85C)
ASR enabled (for devices supporting ASR and Extended Temperature Range).
Normal and Extended
Self-Refresh power consumption is temperature dependent.
(0 ~ 95C)
Illegal
ACTIVE Command
The ACTIVE command is used to open (or activate) a row in a particular bank for subsequent access. The value on the BA0-BA2
inputs selects the bank, and the addresses provided on inputs A0-A12 selects the row. These rows remain active (or open) for
accesses until a precharge command is issued to that bank. A PRECHARGE command must be issued before opening a
different row in the same bank.
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PRECHARGE Command
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will
be available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued, except in the
case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not
interrupt the data transfer in the current bank and does not violate any other timing parameters. Once a bank has been
precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A
PRECHARGE command is allowed if there is no open row in that bank (idle bank) or if the previously open row is already in the
process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the
bank.
READ Operation
Read Burst Operation
During a READ or WRITE command DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE
(AUTO PRECHARGE can be enabled or disabled).
A12=0, BC4 (BC4 = burst chop, tCCD=4)
A12=1, BL8
A12 will be used only for burst length control, not a column address.
Fig. 17: Read Burst Operation RL=5 (AL=0, CL=5, BL=8)
T0
T1
T2
T3
NOP
NOP
NOP
T4
T5
T6
NOP
NOP
T7
T8
T9
T10
T145
NOP
NOP
NOP
NOP
CK
CK
CMD
READ
Address
Bank
Col n
NOP
NOP
tRPRE
tRPST
DQS, DQS
Dout
n
DQ
CL=5
RL = AL + CL
Dout
n +1
Dout
n +2
Dout
n +3
Dout
n +4
Dout
n +5
Dout
n +6
Dout
n +7
Fig. 18: READ Burst Operation RL = 9 (AL=4, CL=5, BL=8)
T0
T1
T2
T3
NOP
NOP
NOP
T4
T5
T6
NOP
NOP
T7
T8
T9
T10
T145
NOP
NOP
NOP
NOP
CK
CK
CMD
READ
Address
Bank
Col n
NOP
NOP
AL = 4
tRPRE
DQS, DQS
CL=5
DQ
RL = AL + CL
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Dout
n
Dout
n +1
Dout
n +2
Dout
n +3
Dout
n +4
Dout
n +5
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M15F1G1664A (2R)
READ Timing Definitions
Read timing is shown in the following figure and is applied when the DLL is enabled and locked.
Rising data strobe edge parameters:
tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, CK .
tDQSCK is the actual position of a rising strobe edge relative to CK, CK .
tQSH describes the DQS, DQS differential output high time.
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
tQSL describes the DQS, DQS differential output low time.
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
Fig. 19: Read Timing Definition
C K
C K
tD Q S K , m in
tD Q S K , m a x
R is in g S tr o b e
R e g io n
tD Q S K
R is in g S tr o b e
R e g io n
tQ S H
tQ S L
tD Q S K
D Q S
D Q S
tQ H
tD Q S Q
tQ H
tD Q S Q
A s s o c ia te d
D Q
p in s
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M15F1G1664A (2R)
Read Timing; Clock to Data Strobe relationship
Clock to Data Strobe relationship is shown in the following figure and is applied when the DLL is enabled and locked.
Rising data strobe edge parameters:
tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK and CK .
tDQSCK is the actual position of a rising strobe edge relative to CK and CK .
tQSH describes the data strobe high pulse width.
Falling data strobe edge parameters:
tQSL describes the data strobe low pulse width.
Fig. 20: Clock to Data Strobe Relationship
RL Measured
to this point
CK
CK
tLZ(DQS)min
tDQSCKmin
tQSH
tRPRE
tQSL
tRPST
tHZ(DQS)min
DQS, DQS
Early Strobe
tHZ(DQS)max
tDQSCKmax
tLZ(DQS)max
tRPST
DQS, DQS
Late Strobe
tRPRE
NOTES:
1. Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min) or tDQSCK(max). Instead, rising
strobe edge can vary between tDQSCK(min) and tDQSCK(max).
2.
3.
4.
5.
6.
7.
The DQS, DQS differential output high time is defined by tQSH and the DQS, DQS differential output low time is defined by
tQSL.
Likewise, tLZ(DQS)min and tHZ(DQS)min are not tied to tDQSCKmin (early strobe case) and tLZ(DQS)max and
tHZ(DQS)max are not tied to tDQSCKmax (late strobe case).
The minimum pulse width of read preamble is defined by tRPRE(min).
The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZDSQ(max) on the right
side.
The minimum pulse width of read postamble is defined by tRPST(min).
The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side.
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Read Timing; Data Strobe to Data Relationship
The Data Strobe to Data relationship is shown in the following figure and is applied when the DLL and enabled and locked.
Rising data strobe edge parameters:
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
tDQSQ; both rising/falling edges of DQS, no tAC defined
Fig. 21: Data Strobe to Data Relationship
T0
T1
T2
T3
NOP
NOP
NOP
T4
T5
T6
NOP
NOP
T7
T8
T9
NOP
NOP
CK
CK
CMD
READ
Address
Bank
Col n
NOP
tRPRE
NOP
tDQSQmax
tQH
tRPST
DQS, DQS
tLZ(DQ)min
RL = AL + CL
DQ (Last data valid)
DQ (First data no
longer valid)
tDQSQmin
Dout
n
Dout
n
Dout
n +1
Dout
n +1
tHZ(DQ)min
tQH
Dout
n +2
Dout
n +2
Dout
n +3
Dout
n +3
Dout
n +4
Dout
n +4
Dout
n +5
Dout
n +5
Dout
n +6
Dout
n +6
Dout
n +7
Dout
n +7
All DQ collectively
Valid data
Valid data
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DQ
DQS, DQS
Address
CMD
DQ
DQS, DQS
Address
CMD
CK
CK
Col n
Bank
READ
Col n
Bank
READ
T0
NOP
NOP
T1
tCCD
NOP
tCCD
NOP
T2
RL = 5
RL = 5
NOP
NOP
T3
READ
READ
Col b
Bank
READ
Col b
Bank
READ
T4
tRPRE
tRPRE
NOP
NOP
T5
n
Dout
n
Dout
n +1
Dout
n +1
Dout
NOP
NOP
T6
n +2
Dout
NOP
tRPST
n +3
Dout
n +3
Dout
RL = 5
n +2
Dout
RL = 5
NOP
T7
n +5
Dout
n +6
Dout
n +7
Dout
NOP
T9
tRPRE
NOP
READ (BL4) to READ (BL4)
NOP
READ (BL8) to READ (BL8)
n +4
Dout
NOP
T8
b
Dout
b
Dout
b +1
Dout
b +1
Dout
NOP
NOP
T10
b +2
Dout
b +2
Dout
NOP
b +3
Dout
tRPST
b +3
Dout
NOP
T11
b +4
Dout
b +5
Dout
NOP
NOP
T12
b +6
Dout
b +7
Dout
NOP
tRPST
NOP
T13
ESMT
M15F1G1664A (2R)
Fig. 22: Read to Read (CL=5, AL=0)
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DQ
DQS, DQS
Address
CMD
DQ
DQS, DQS
Address
CMD
CK
CK
Col n
Bank
READ
Col n
Bank
READ
T0
NOP
T3
NOP
T4
tRPRE
NOP
RL = 5
NOP
READ
RL = 5
Col b
Bank
WRITE
tRPRE
READ to Write Command delay = RL +tCCD + 2tCK -WL
NOP
T2
READ to WRITE Command Delay = RL + tCCD/2 + 2tCK - WL
NOP
NOP
T1
NOP
NOP
T5
Dout
n +1
n
n +1
Dout
Dout
n
Dout
NOP
Col b
Bank
n +2
Dout
n +3
Dout
n +5
Dout
n +6
Dout
n +7
Dout
WL = 5
tRPST
NOP
T9
NOP
tWPRE
b
Dout
NOP
READ (BL8) to WRITE (BL8)
n +4
Dout
NOP
T8
READ (BL4) to WRITE (BL4)
NOP
NOP
T7
tRPST
n +3
Dout
WL = 5
n +2
Dout
WRITE
T6
b +1
Dout
b +2
Dout
NOP
NOP
T10
NOP
b +3
Dout
b
Dout
tBL = 4 clocks
tWPST
tWRPRE
NOP
T11
b +1
Dout
NOP
b +2
Dout
NOP
T12
b +3
Dout
NOP
b +4
Dout
NOP
T13
b +5
Dout
NOP
b +6
Dout
NOP
T14
tWTR
tWR
b +7
Dout
NOP
tWPST
NOP
T15
ESMT
M15F1G1664A (2R)
Fig. 23: READ to WRITE (CL=5, AL=0; CWL=5, AL=0)
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DQ
DQS, DQS
Address
CMD
DQ
DQS, DQS
Address
CMD
CK
CK
Col n
Bank
READ
Col n
Bank
READ
T0
NOP
NOP
T1
tCCD
NOP
tCCD
NOP
T2
RL = 5
RL = 5
NOP
NOP
T3
READ
READ
Col b
Bank
READ
Col b
Bank
READ
T4
tRPRE
tRPRE
NOP
NOP
T5
n
Dout
n
Dout
n +1
Dout
n +1
Dout
NOP
NOP
T6
n +2
Dout
NOP
tRPST
n +3
Dout
n +3
Dout
RL = 5
n +2
Dout
RL = 5
NOP
T7
n +5
Dout
n +6
Dout
n +7
Dout
NOP
T9
tRPRE
NOP
READ (BC4) to READ (BL8)
NOP
READ (BL8) to READ (BC4)
n +4
Dout
NOP
T8
b
Dout
b
Dout
b +1
Dout
b +1
Dout
NOP
NOP
T10
b +2
Dout
b +2
Dout
b +3
Dout
b +3
Dout
NOP
tRPST
NOP
T11
b +4
Dout
b +5
Dout
NOP
NOP
T12
b +6
Dout
b +7
Dout
tRPST
NOP
NOP
T13
ESMT
M15F1G1664A (2R)
Fig. 24: READ to READ (CL=5, AL=0)
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DQ
DQS, DQS
Address
CMD
DQ
DQS, DQS
Address
CMD
CK
CK
Col n
Bank
READ
Col n
Bank
READ
T0
NOP
T3
READ
NOP
T4
tRPRE
NOP
RL = 5
NOP
READ
RL = 5
Col b
Bank
WRITE
tRPRE
READ to WRITE Command delay = RL + tCCD +2tCK - WL
NOP
T2
READ to WRITE Command delay = RL + tCCD/2 +2tCK - WL
NOP
NOP
T1
NOP
NOP
T5
n
Dout
n
Dout
n +1
Dout
n +1
Dout
NOP
Col b
Bank
n +2
Dout
NOP
NOP
T7
tRPST
n +3
Dout
n +3
Dout
WL = 5
n +2
Dout
WRITE
T6
n +5
Dout
n +6
Dout
n +7
Dout
WL = 5
tRPST
NOP
T9
tWPRE
b
Dout
NOP
READ (BL4) to WRITE (BL8)
NOP
READ (BL8) to WRITE (BC4)
n +4
Dout
NOP
T8
b +1
Dout
b +2
Dout
NOP
NOP
T10
b +3
Dout
tWPRE
b +4
Dout
NOP
b
Dout
NOP
T11
b +5
Dout
b +1
Dout
b +6
Dout
NOP
b +2
Dout
NOP
T12
b +7
NOP
tWPST
Dout
b +3
Dout
tWPST
NOP
T13
ESMT
M15F1G1664A (2R)
Fig. 25: READ to WRITE (CL=5, AL=0; CWL=5, AL=0)
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M15F1G1664A (2R)
Write Operation
DDR3 Burst Operation
During a READ or WRITE command, DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE
(Auto Precharge can be enabled or disabled).
A12=0, BC4 (BC4 = Burst Chop, tCCD=4)
A12=1, BL8
A12 is used only for burst length control, not as a column address.
WRITE Timing Violations
Motivation
Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure the DRAM
works properly. However, it is desirable for certain minor violations that the DRAM is guaranteed not to “hang up” and errors be
limited to that particular operation.
For the following, it will be assumed that there are no timing violations with regard to the Write command itself (including ODT,
etc.) and that it does satisfy all timing requirements not mentioned below.
Data Setup and Hold Violations
Should the strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges associated with a write burst, then
wrong data might be written to the memory location addressed with the offending WRITE command.
Subsequent reads from that location might result in unpredictable read data, however, the DRAM will work properly otherwise.
Strobe to Strobe and Strobe to Clock Violations
Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements (tDSS, tDSH,
tDQSS) be violated, for any of the strobe edges associated with a Write burst, then wrong data might be written to the memory
location addressed with the offending WRITE command. Subsequent reads from that location might result in unpredictable read
data, however the DRAM will work properly otherwise.
Write Timing Parameters
This drawing is for example only to enumerate the strobe edges that “belong” to a write burst. No actual timing violations are
shown here. For a valid burst all timing parameters for each edge of a burst need to be satisfied (not only for one edge - as
shown).
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ESMT
M15F1G1664A (2R)
Fig. 26: Write Timing Definition
T0
T1
T2
T3
CMD
Write
NOP
NOP
NOP
Address
Bank
Col n
T4
T5
T6
NOP
NOP
T8
T9
Tn
NOP
NOP
NOP
T7
CK
CK
NOP
NOP
tDSH
tDSH
tDSH
tDQSS tDSH
tWPST(min)
tDSS
tWPRE(min)
DQS, DQS
(tDQSS min)
tDQSH
tDQSL
tDQSH
Din
n
DQ
tDQSH
tDSS
tDSS
Din
n +1
tDQSL(min)
tDSS
Din
n +2
Din
n +3
Din
n +4
Din
n +5
Din
n +6
Din
n +7
tDSS
WL = AL + CWL
tWPST(min)
tDSH
tDSH
tDSH
tDSH
tDSS
tWPRE(min)
DQS, DQS
(tDQSS nominal)
tDQSH
tDQSL
tDQSH
Din
n
DQ
Din
n +1
tDQSH
tDSS
tDSS
tDQSL(min)
tDSS
Din
n +2
Din
n +3
Din
n +4
Din
n +5
Din
n +6
Din
n +7
tDSS
tDSH
tDQSS
tDSH
tWPRE(min)
tWPST(min)
tDSH
tDSH
DQS, DQS
(tDQSS max)
tDSS
tDQSH
tDQSL
Din
n
DQ
tDSS
tDSS
tDQSH
Din
n +1
Din
n +2
Din
n +3
Din
n +4
Din
n +5
tDQSH
Din
n +6
tDQSL(min)
Din
n +7
tDSS
tDSS
Note:
1.
BL=8, WL=5 (AL=0, CWL=5). 2.
Din n = data in from column n. 3.
NOP commands are shown for ease of illustration; other command may be valid at these times. 4.
BL8 setting activated by either MR0 [A1:0=00] or MR0 [A1:0=01] and A12 = 1 during WRITE command at T0. 5.
tDQSS must be met at each rising clock edge. Elite Semiconductor Memory Technology Inc
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DQ
DQS, DQS
Address
CMD
DQ
DQS, DQS
Address
CMD
CK
CK
Col n
Bank
WRITE
Col n
Bank
WRITE
T0
NOP
NOP
T1
WL = 5
NOP
T3
WL = 5
NOP
READ
WRITE (BC4) to WRITE (BC4)
tCCD
NOP
WRITE (BL8) to WRITE (BL8)
tCCD
NOP
T2
Col b
Bank
WRITE
Col b
Bank
WRITE
T4
tRPRE
tWPRE
Dout
n +1
n
n +1
Dout
Dout
NOP
n
Dout
NOP
T5
n +2
Dout
NOP
n +2
Dout
NOP
T6
NOP
n +4
Dout
n +3
Dout
WL = 5
tWPST
WL = 5
n +3
Dout
NOP
T7
n +5
Dout
NOP
n +6
Dout
NOP
T8
tWPRE
n +7
Dout
b
Dout
NOP
b
Dout
NOP
T9
b +1
Dout
b +1
Dout
b +2
Dout
NOP
b +2
Dout
NOP
T10
tBL=4
NOP
b +4
Dout
b +3
Dout
tWPST
b +3
Dout
tBL=4
NOP
T11
b +5
Dout
NOP
b +6
Dout
NOP
T12
b +7
Dout
NOP
tWPST
NOP
T13
tWTR
tWR
tWTR
tWR
ESMT
M15F1G1664A (2R)
Fig. 27: WRITE to WRITE (WL=5; CWL=5, AL=0) Publication Date : Sep. 2013
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DQ
DQS, DQS
Address
CMD
DQ
DQS, DQS
Address
CMD
CK
CK
WL = 5
NOP
T3
WL = 5
NOP
tRPRE
tWPRE
NOP
n
Dout
NOP
T5
n +1
Dout
NOP
n +2
Dout
NOP
T6
Dout
NOP
n +4
Dout
WRITE (BC4) to READ (BC4/BL8)
Dout
n +1
Dout
n
n +2
tBL=4
n +3
Dout
tWPST
n +3
Dout
NOP
T7
n +5
Dout
NOP
n +6
Dout
NOP
T8
n +7
Dout
NOP
tWPST
NOP
T9
NOP
NOP
T10
tWTR
NOP
tWTR
NOP
T11
NOP
NOP
T12
READ
Col b
Bank
READ
T13
Bank
NOP
NOP
T4
Col b
NOP
WRITE (BL8) to READ (BC4/BL8)
NOP
T2
Bank
NOP
NOP
T1
Col n
WRITE
Col n
Bank
WRITE
T0
RL=5
RL=5
ESMT
M15F1G1664A (2R)
Fig. 28: WRITE to READ (RL=5, CL=5, AL=0; WL=5, CWL=5, AL=0; BL=4)
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DQ
DQS, DQS
Address
CMD
DQ
DQS, DQS
Address
CMD
CK
CK
Col n
Bank
WRITE
Col n
Bank
WRITE
T0
NOP
NOP
T1
WL = 5
NOP
T3
WL = 5
NOP
READ
WRITE (BC4) to WRITE (BL8)
tCCD
NOP
WRITE (BL8) to WRITE (BC4)
tCCD
NOP
T2
Col b
Bank
WRITE
Col b
Bank
WRITE
T4
tRPRE
tWPRE
Dout
n +1
n
n +1
Dout
Dout
NOP
n
Dout
NOP
T5
n +2
Dout
NOP
n +2
Dout
NOP
T6
NOP
n +4
Dout
n +3
Dout
WL = 5
tWPST
WL = 5
n +3
Dout
NOP
T7
n +5
Dout
NOP
n +6
Dout
NOP
T8
tWPRE
n +7
Dout
b
Dout
NOP
b
Dout
NOP
T9
b +1
Dout
b +1
Dout
b +2
Dout
NOP
b +2
Dout
NOP
T10
b +3
Dout
b +3
Dout
b +3
Dout
tBL=4
NOP
tWPST
tBL=4
NOP
T11
b +4
Dout
b +5
Dout
NOP
NOP
T12
b +6
Dout
b +7
Dout
tWPST
NOP
NOP
T13
tWTR
tWR
tWTR
tWR
ESMT
M15F1G1664A (2R)
Fig. 29: WRITE to WRITE (WL=5, CWL=5, AL=0)
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ESMT
M15F1G1664A (2R)
Refresh Command
The Refresh command (REF) is used during normal operation of the DDR3 SDRAMs. This command is not persistent, so it must
be issued each time a refresh is required. The DDR3 SDRAM requires Refresh cycles at an average periodic interval of tREFI.
When CS , RAS and CAS are held Low and WE High at the rising edge of the clock, the chip enters a Refresh cycle. All
banks of the SDRAM must be precharged and idle for a minimum of the precharge time tRP(min) before the Refresh Command
can be applied. The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care”
during a Refresh command. An internal address counter suppliers the address during the refresh cycle. No control of the external
address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the
precharged (idle) state. A delay between the Refresh Command and the next valid command, except NOP or DES, must be
greater than or equal to the minimum Refresh cycle time tRFC(min) as shown in the following figure.
In general, a Refresh command needs to be issued to the DDR3 SDRAM regularly every tREFI interval. To allow for improved
efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of 8
Refresh commands can be postponed during operation of the DDR3 SDRAM, meaning that at no point in time more than a total
of 8 Refresh commands are allowed to be postponed. In case that 8 Refresh commands are postponed in a row, the resulting
maximum interval between the surrounding Refresh commands is limited to 9 x tREFI. A maximum of 8 additional Refresh
commands can be issued in advance (“pulled in”), with each one reducing the number of regular Refresh commands required
later by one. Note that pulling in more than 8 Refresh commands in advance does not further reduce the number of regular
Refresh commands required later, so that the resulting maximum interval between two surrounding Refresh command is limited
to 9 x tREFI. At any given time, a maximum of 16 REF commands can be issued within 2 x tREFI. Self- Refresh Mode may be
entered with a maximum of eight Refresh commands being postponed. After exiting Self-Refresh Mode with one or more Refresh
commands postponed, additional Refresh commands may be postponed to the extent that the total number of postponed
Refresh commands (before and after the Self-Refresh) will never exceed eight. During Self-Refresh Mode, the number of
postponed or pulled-in REF commands does not change.
Fig. 30: Self-Refresh Entry/Exit Timing
T0
T1
REF
NOP
Ta0
Tb0
Ta1
Tb1
Tb2
Tb3
Valid
Valid
Tc0
Tc1
CK
CK
CMD
NOP
REF
NOP
tRFC
NOP
Valid
Valid
Valid
REF
Valid
tRFC(min)
DRAM must be idle
tREFI (max, 9 x tREFI)
DRAM must be idle
Time Break
Fig. 31: Postponing Refresh Commands (Example)
tR E F I
9 x tR E F I
t
tR E F I
8 R E F - C o m m a n d p o s tp o n e d
Fig. 32: Pulled-in Refresh Commands (Example)
tR E F I
9 x tR E F I
t
tR E F I
8 R E F - C o m m a n d s p u lle d - in
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M15F1G1664A (2R)
Self-Refresh Operation
The Self-Refresh command can be used to retain data in the DDR3 SDRAM, even if the reset of the system is powered down.
When in the Self-Refresh mode, the DDR3 SDRAM retains data without external clocking. The DDR3 SDRAM device has a
built-in timer to accommodate Self-Refresh operation. The Self-Refresh Entry (SRE) Command is defined by having CS , RAS ,
CAS and CKE held low with WE high at the rising edge of the clock.
Before issuing the Self-Refreshing-Entry command, the DDR3 SDRAM must be idle with all bank precharge state with tRP satisfied. ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all
timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.). Also, on-die termination must
be turned off before issuing Self-Refresh-Entry command, by either registering ODT pin low “ODTL + 0.5tCK” prior to the
Self-Refresh Entry command or using MRS to MR1 command. Once the Self-Refresh Entry command is registered, CKE must
be held low to keep the device in Self-Refresh mode. During normal operation (DLL on), MR1 (A0=0), the DLL is automatically
disabled upon entering Self-Refresh and is automatically enabled (including a DLL-RESET) upon exiting Self-Refresh.
When the DDR3 SDRAM has entered Self-Refresh mode, all of the external control signals, except CKE and RESET , are “don’t
care”. For proper Self-Refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ, VREFCA, and
VREFDQ) must be at valid levels. VrefDQ supply may be turned OFF and VREFDQ may take any value between VSS and VDD
during Self Refresh operation, provided that VrefDQ is valid and stable prior to CKE going back high and that first Write operation
or first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self Refresh. The DRAM initiates a minimum of
one Refresh command internally within tCKE period once it enters Self-Refresh mode.
The clock is internally disabled during Self-Refresh operation to save power. The minimum time that the DDR3 SDRAM must
remain in Self-Refresh mode is tCKE. The user may change the external clock frequency or halt the external clock tCKSRE after
Self-Refresh entry is registered; however, the clock must be restarted and stable tCKSRX before the device can exit Self-Refresh
mode.
The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable prior to CKE going back
HIGH. Once a Self-Refresh Exit Command (SRX, combination of CKE going high and either NOP or Deselect on command bus)
is registered, a delay of at least tXS must be satisfied before a valid command not requiring a locked DLL can be issued to the
device to allow for any internal refresh in progress. Before a command that requires a locked DLL can be applied, a delay of at
least tXSDLL must be satisfied. Depending on the system environment and the amount of time spent in Self-Refresh, ZQ
calibration commands may be required to compensate for the voltage and temperature drift as described in “ZQ Calibration
Commands”. To issue ZQ calibration commands, applicable timing requirements must be satisfied.
CKE must remain HIGH for the entire Self-Refresh exit period tXSDLL for proper operation except for Self-Refresh re-entry.
Upon exit from Self-Refresh, the DDR3 SDRAM can be put back into Self-Refresh mode after waiting at least tXS period and
issuing one refresh command (refresh period of tRFC). NOP or deselect commands must be registered on each positive clock
edge during the Self-Refresh exit interval tXS. ODT must be turned off during tXSDLL.
The use of Self-Refresh mode instructs the possibility that an internally times refresh event can be missed when CKE is raised for
exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3 SDRAM requires a minimum of one extra refresh command
before it is put back into Self-Refresh mode.
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M15F1G1664A (2R)
Fig. 33:Self-Refresh Entry/Exit Timing T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Td0
Te0
Tf
Valid
Valid
CK, CK
tCKSRE
tCKSRX
tCPDED
CKE
tCKESR
Valid
ODT
ODTL
CMD
NOP
SRE
NOP
SRX
Note:
1. Only NOP or DES commands
2. Valid commands not requiring a locked DLL
3. Valid commands requiring a locked DLL
Elite Semiconductor Memory Technology Inc
Valid 2)
Valid 3)
Valid
Valid
tXS
tXSDLL
tRF
Enter Self Refresh
NOP 1)
Exit Self Refresh
Do Not
Care
Time
Break
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M15F1G1664A (2R)
Power-Down Modes
Power-Down Entry and Exit
Power-Down is synchronously entered when CKE is registered low (along with NOP or Deselect command). CKE is not allowed
to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or read/write operation are in
progress. CKE is allowed to go low while any of other operation such as row activation, precharge or auto precharge and refresh
are in progress, but power-down IDD spec will not be applied until finishing those operation.
The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If the DLL is not locked
during power-down entry, the DLL must be reset after exiting power-down mode for proper read operation and synchronous ODT
operation. DRAM design provides all AC and DC timing and voltage specification as well proper DLL operation with any CKE
intensive operations as long as DRAM controller complies with DRAM specifications.
During Power-Down, if all banks are closed after any in progress commands are completed, the device will be in precharge
Power-Down mode; if any bank is open after in progress commands are completed, the device will be in active Power-Down
mode.
Entering Power-down deactivates the input and output buffers, excluding CK, CK , ODT, CKE, and RESET . To protect DRAM
internal delay on CKE line to block the input signals, multiple NOP or Deselect commands are needed during the CKE switch off
and cycle(s) after, this timing period are defined as tCPDED. CKE_low will result in deactivation of command and address
receivers after tCPDED has expired.
Table 11: Power-Down Entry Definitions
Status of DRAM
Active
(A Bank or more open)
MRS bit A12
DLL
PD Exit
Don't Care
On
Fast
Relevant Parameters
tXP to any valid command.
tXP to any valid command. Since it is in precharge state,
Precharged
(All Banks Precharged)
0
Off
Slow
commands here will be ACT, AR, MRS/EMRS, PR, or PRA.
tXPDLL to commands who need DLL to operate, such as RD,
RDA, or ODT control line.
Precharged
(All Banks Precharged)
1
On
Fast
tXP to any valid command.
Also the DLL is disabled upon entering precharge power-down (Slow Exit Mode), but the DLL is kept enabled during precharge
power-down (Fast Exit Mode) or active power-down. In power-down mode, CKE low, RESET high, and a stable clock signal
must be maintained at the inputs of the DDR3 SDRAM, and ODT should be in a valid state but all other input signals are “Don’t
care” (If RESET goes low during Power-Down, the DRAM will be out of PD mode and into reset state). CKE low must be
maintain until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device.
The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). CKE high
must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency,
tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined at AC spec table of this datasheet.
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M15F1G1664A (2R)
Fig. 34: Active Power-Down Entry and Exit timing diagram
T0
T1
T2
Ta0
Valid
NO P
NOP
Ta1
Tb0
Tb1
Tc0
NOP
N OP
NO P
Valid
Valid
CK
CK
CM D
NO P
tIS
tPD
tIH
CK E
tIH
tIS
Address
tCK E
Valid
Valid
tCPD ED
tX P
Enter
Power-Down
Exit
Power-Down
D o not
care
Tim e
Break
Timing Diagrams for CKE with PD Entry, PD Exit with Read, READ with Auto Precharge, Write and Write with Auto Precharge,
Activate, Precharge, Refresh, MRS:
Fig. 35: Power-Down Entry after Read and Read with Auto Precharge
T0
T1
Ta0
Ta1
Ta2
WRITE
NOP
NOP
NOP
NOP
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
NOP
NOP
NOP
NOP
NOP
NOP
Tb1
Tb2
Tb3
Tc0
NOP
NOP
Valid
CK
CK
CMD
NOP
tIS
CKE
Address
tCPDED
Bank,
Col n
WL=AL+CWL
WR (1)
tPD
DQS
BL8
Din
b
Din
b+1
Din
b+2
Din
b+3
BC4
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
Start Internal
Precharge
tWRAPDEN
Power-Down
Entry
Do not
care
Time
Break
Fig. 36: Power-Down Entry after Write with Auto Precharge
T0
T1
T a0
T a1
T a2
R D or
RDA
NOP
NOP
NOP
NOP
T a3
T a4
T a5
T a6
NOP
NOP
NOP
NOP
T a7
T a8
Tb0
T b1
NOP
NOP
NOP
V alid
CK
CK
CMD
tIS
CKE
tC P D E D
V alid
tPD
A ddress
V alid
V alid
RL = AL + CL
DQS
BL8
D in
b
D in
b+1
D in
b+2
D in
b+3
BC4
D in
b
D in
b+1
D in
b+2
D in
b+3
D in
b+4
D in
b+5
D in
b+6
D in
b+7
tR D PD E N
P ow er-D ow n
E ntry
D o not
care
T im e
B reak
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Fig. 37: Power-Down Entry after Write
T0
T1
T a0
T a1
T a2
W R IT E
NOP
NOP
NOP
NOP
T a3
T a4
T a5
T a6
T a7
T b0
NOP
NOP
NOP
NOP
NOP
NOP
T b1
Tb2
T c0
CK
CK
CM D
NOP
tIS
CKE
NOP
NOP
tC P D E D
B ank,
Col n
A d d ress
W L =AL+CW L
WR
tP D
DQS
BL8
D in
b
D in
b+1
D in
b+2
D in
b+3
BC4
D in
b
D in
b+1
D in
b+2
D in
b+3
D in
b+4
D in
b+5
D in
b+6
D in
b+7
tW R P D E N
P o w er-D o w n
E n try
D o not
ca re
T im e
B rea k
Fig. 38: Precharge Power-Down (Fast Exit Mode) Entry and Exit
T0
T1
W R IT E
N O P
T2
T a0
T a1
N O P
N O P
Tb0
Tb1
T c0
NO P
NO P
NO P
V a lid
CK
CK
CM D
N O P
N O P
tC P D E D
tC K E
tIS
tIH
C K E
tIS
tP D
tX P
E n te r
P o w e r -D o w n
M ode
E x it
P o w e r -D o w n
M ode
D o not
care
T im e
B reak
Fig. 39: Precharge Power-Down (Slow Exit Mode) Entry and Exit
T0
T1
T2
T a0
T a1
W R IT E
NOP
NOP
NOP
NOP
T b0
Tb1
T c0
Td0
NOP
NOP
V a lid
V a lid
NOP
V a lid
V a lid
CK
CK
CMD
tC P D E D
tC K E
tI S
tI H
CKE
tI S
tX P
tP D
tX P D L L
E n te r
P o w e r -D o w n
M ode
E x it
P o w e r -D o w n
M ode
D o not
care
T im e
B reak
Fig. 40: Refresh Command to Power-Down Entry
T0
T1
T2
T3
T a0
NO P
NO P
T a1
CK
CK
CM D
A d d ress
REF
NO P
V a lid
V a lid
V a lid
tIS
tC P D E D
tP D
C K E
V a lid
tR E F P D E N
D o not
care
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Fig. 41: Active Command to Power-Down Entry
T0
T1
T2
T3
T a0
CMD
A c tiv e
NOP
NOP
NOP
A d d ress
V a lid
T a1
CK
CK
V a lid
V a lid
tC P D E D
tI S
tP D
CKE
V a lid
tA C T P D E N
D o not
care
T im e
B reak
Fig. 42: Precharge/Precharge all Command to Power-Down Entry
T0
T1
T2
T3
Ta0
CMD
PRE
PREA
NOP
NOP
NOP
A d d r e ss
V a lid
T a1
CK
CK
V a lid
V a lid
tC P D E D
tIS
tP D
CKE
V a lid
tP R E P D E N
D o not
care
T im e
B reak
Fig. 43: MRS Command to Power-Down Entry
T0
T1
T a0
T a1
CM D
MRS
NOP
NOP
NOP
A d d ress
V alid
T b0
Tb1
CK
CK
V alid
V alid
tIS
tC P D E D
tP D
CKE
V alid
tM R S P D E N
D o n ot
care
T im e
B reak
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M15F1G1664A (2R)
On-Die Termination (ODT)
ODT (On-Die Termination) is a feature of the DDR3 SDRAM that allows the DRAM to turn on/off termination resistance for each
DQ, DQS, DQS and DM via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel
by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices.
The ODT feature is turned off and not supported in Self-Refresh mode.
A simple functional representation of the DRAM ODT feature is shown as below.
Fig. 44: Functional Representation of ODT
ODT
To other
circuitry
like
RCV, ...
VDDQ/ 2
RTT
Switch
DQ , DQS, DM, TDQS
The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information. The value
of RTT is determined by the settings of Mode Register bits. The ODT pin will be ignored if the Mode Register MR1 and MR2 are
programmed to disable ODT and in self-refresh mode.
ODT Mode Register and ODT Truth Table
The ODT Mode is enabled if either of MR1 {A2, A6, A9} or MR2 {A9, A10} are non-zero. In this case, the value of RTT is
determined by the settings of those bits.
Application: Controller sends WR command together with ODT asserted.
One possible application: The rank that is being written to provides termination.
DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR)
DRAM does not use any write or read command decode information.
Table 12: Termination Truth Table
ODT pin
DRAM Termination State
0
OFF
1
ON, (OFF, if disabled by MR1 {A2, A6, A9} and MR2{A9, A10} in general)
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Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down definition, these
modes are:
z
Any bank active with CKE high
z
Refresh with CKE high
z
Idle mode with CKE high
z
Active power down mode (regardless of MR0 bit A12)
z
Precharge power down mode if DLL is enabled during precharge power down by MR0 bit A12
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continuously
registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register set
command during DLL-off mode.
In synchronous ODT mode, RTT will be turned on ODTLon clock cycles after ODT is sampled high by a rising clock edge and
turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT latency is tied to the write latency
(WL) by: ODTLonn = WL - 2; ODTLoff = WL-2.
ODT Latency and Posted ODT
In synchronous ODT Mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also applies to the ODT signal.
The DRAM internal ODT signal is delayed for a number of clock cycles defined by the Additive Latency (AL) relative to the
external ODT signal. ODTLon = CWL + AL - 2; ODTLoff = CWL + AL - 2. For details, refer to DDR3 SDRAM latency definitions.
Table 13: ODT Latency
Symbol
Parameter
DDR3-1600
Unit
ODTLon
ODT turn on Latency
WL - 2 = CWL + AL - 2
tCK
ODTLoff
ODT turn off Latency
WL - 2 = CWL + AL - 2
tCK
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Timing Parameters
In synchronous ODT mode, the following timing parameters apply: ODTLon, ODTLoff, tAON min/max, tAOF min/max.
Minimum RTT turn-on time (tAON min) is the point in time when the device leaves high impedance and ODT resistance begins to
turn on. Maximum RTT turn-on time (tAON max) is the point in time when the ODT resistance is fully on. Both are measured from
ODTLon.
Minimum RTT turn-off time (tAOF min) is the point in time when the device starts to turn off the ODT resistance. Maximum RTT
turn off time (tAOF max) is the point in time when the on-die termination has reached high impedance. Both are measured from
ODTLoff.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with ODT
high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the write command. ODTH4 and ODTH8 are
measured from ODT registered high to ODT registered low or from the registration of a write command until ODT is registered
low.
Fig. 45: Synchronous ODT Timing Example for AL=3; CWL=5; ODTLon=AL+CWL-2=6;
ODTLoff=AL+CWL-2=6
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T14
T13
T15
CK
CK
CKE
ODT
AL=3
AL=3
tAONmax
CWL - 2
tAONmax
ODTH4, min
ODTLon = CWL + AL -2
tAONmin
tAONmin
ODTLoff = CWL + AL -2
RTT_NOM
DRAM_RTT
Transitioning
Do not care
Fig. 46: Synchronous ODT example with BL=4, WL=7
T0
T1
T2
NOP
NOP
NOP
T3
T4
T5
T6
NOP
NOP
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
CK
NOP
NOP
WRS4
NOP
ODTH4
ODTH4
ODT
ODTH4min
ODTLoff = CWL -2
tAONmin
ODTLoff = WL - 2
tAOFmax
tAONmax
tAOFmax
tAONmax
tAONmin
tAOFmin
tAOFmin
RTT_NOM
DRAM_RTT
ODTLon = CWL -2
ODTLon = CWL -2
Transitioning
Do not care
ODT must be held for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BL=4) or ODTH8 (BL=8) after Write
command (T7). ODTH is measured from ODT first registered high to ODT first registered low, or from registration of Write
command with ODT high to ODT registered low. Note that although ODTH4 is satisfied from ODT registered at T6 ODT must not
go low before T11 as ODTH4 must also be satisfied from the registration of the Write command at T7.
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M15F1G1664A (2R)
ODT during Reads:
As the DDR3 SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock cycle before the
read preamble by driving the ODT pin low appropriately. RTT may not be enabled until the end of the post-amble as shown in the
following figure. DRAM turns on the termination when it stops driving which is determined by tHZ. If DRAM stops driving early (i.e.
tHZ is early), then tAONmin time may apply. If DRAM stops driving late (i.e. tHZ is late), then DRAM complies with tAONmax
timing. Note that ODT may be disabled earlier before the Read and enabled later after the Read than shown in this example.
Fig. 47: ODT must be disabled externally during Reads by driving ODT low. (Example: CL=6; AL=CL-1=5;
RL=AL+CL=11; CWL=5; ODTLon=CWL+AL-2=8; ODTLoff=CWL+AL-2=8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
CK
CMD
Read
Address
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
RL = AL + CL
ODT
ODTLon = CWL + AL - 2
ODTLoff = CWL + AL - 2
tAONmax
tAOFmin
DRAM
ODT
RTT_NOM
RTT
RTT_NOM
tAOFmax
DQSdiff
Din
b
DQ
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
Dynamic ODT
In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of
the DDR3 SDRAM can be changed without issuing an MRS command. This requirement is supported by the “Dynamic ODT”
feature as described as follows:
Functional Description
The Dynamic ODT Mode is enabled if bit (A9) or (A10) of MR2 is set to ‘1’. The function is described as follows:
Two RTT values are available: RTT_Nom and RTT_WR.
z
The value for RTT_Nom is preselected via bits A[9,6,2] in MR1.
z
The value for RTT_WR is preselected via bits A[10,9] in MR2.
During operation without write commands, the termination is controlled as follows:
z
Nominal termination strength RTT_Nom is selected.
z
Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff.
When a Write command (WR, WRA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is enabled, the termination is controlled as follows:
z
A latency ODTLcnw after the write command, termination strength RTT_WR is selected.
z
A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected OTF)
after the write command, termination strength RTT_Nom is selected.
z
Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff.
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M15F1G1664A (2R)
The following table shows latencies and timing parameters which are relevant for the on-die termination control in Dynamic ODT
mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set RTT_WR, MR2[A10,A9 = [0,0],
to disable Dynamic ODT externally.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with ODT
high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the Write command. ODTH4 and ODTH8 are
measured from ODT registered high to ODT registered low or from the registration of Write command until ODT is register low.
Table 14: Latencies and timing parameters relevant for Dynamic ODT
Name and
Description
Abbr.
ODT turn-on Latency
ODTLon
ODT turn-off Latency
ODTLoff
ODT
Latency for
changing from
RTT_Nom
to
RTT_WR
ODT
Latency for
change from
RTT_WR
to
RTT_Nom (BL=4)
ODT
Latency for
change from
RTT_WR
to
RTT_Nom (BL=8)
Minimum ODT high
time
after ODT assertion
Minimum ODT high
time
after Write (BL=4)
Minimum ODT high
time
after Write (BL=8)
RTT change skew
Defined from
Defined to
registering
external
ODT signal high
registering
external
ODT signal low
turning termination
on
turning termination
off
change
RTT
strength from
RTT_Nom
to
RTT_WR
change
RTT
strength from
RTT_WR
to
RTT_Nom
change
RTT
strength from
RTT_WR
to
RTT_Nom
Definition for all DDR3
speed pin
Unit
ODTLon=WL-2
tCK
ODTLoff=WL-2
tCK
ODTLcnw=WL-2
tCK
ODTLcwn4=4+ODTLoff
tCK
ODTLcwn8=6+ODTLoff
tCK(avg)
ODTH4=4
tCK(avg)
ODTH4=4
tCK(avg)
ODTLcnw
registering
external
write command
ODTLcwn4
registering
external
write command
ODTLcwn8
registering
external
write command
ODTH4
registering ODT high
ODT
low
registered
ODTH4
registering write with
ODT high
ODT
low
registered
ODTH8
registering write with
ODT high
ODT register low
ODTH8=6
tCK(avg)
tADC
ODTLcnw
ODTLcwn
RTT valid
tADC(min)=0.3tCK(avg)
tADC(max)=0.7tCK(avg)
tCK(avg)
Note: tAOF,nom and tADC,nom are 0.5tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw, and ODTLcwn)
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ODT Timing Diagrams
Fig. 48: Dynamic ODT: Behavior with ODT being asserted before and after the write
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T 11
T 12
T 13
T 14
T 15
T16
T17
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
CK
NOP
CMD
NOP
NOP
NOP
W R S4
A d d re s s
NOP
NOP
NOP
V alid
ODT
O D T L o ff
ODTH4
O D T L cw n4
tA D C m in
tA O N m in
R TT_W R
tA O N m ax
R TT_N om
tA D C m a x
O D TLon
tA O F m in
tA D C m in
R TT_N om
RTT
tA O F m a x
tA D C m a x
O D T L cnw
ODTH4
D Q S /D Q S
WL
D in
n
DQ
D in
n+1
D in
n+2
D in
n+3
D o not
care
T r a n s itio n in g
Note: Example for BC4 (via MRS or OTF), AL=0, CWL=5. ODTH4 applies to first registering ODT high and to the registration of
the Write command. In this example ODTH4 would be satisfied if ODT went low at T8. (4 clocks after the Write command).
Fig. 49: Dynamic ODT: Behavior without write command, AL=0, CWL=5
T0
T1
T2
T3
T4
Valid
Valid
Valid
Valid
T5
T6
Valid
Valid
T7
T8
T9
T10
T11
Valid
Valid
Valid
Valid
CK
CK
CMD
Valid
Valid
Address
ODTLoff
ODT
ODTH4
ODTLoff
tADCmin
tAONmin
RTT_Nom
RTT
tADCmax
tAONmax
ODTLon
DQS/DQS
DQ
Do not
care
Transitioning
Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered
low at T5 would also be legal.
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Fig. 50: Dynamic ODT: Behavior with ODT pin being asserted together with write command for the duration
of 6 clock cycles T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T 10
T11
NOP
NOP
NOP
NOP
CK
CK
CM D
NOP
W RS8
NOP
NOP
NOP
NOP
NOP
NOP
O D T L cnw
V a lid
A d d re ss
ODT
ODTH8
O D T L o ff
O D TLon
tA O F m in
tA O N m in
R TT_W R
RTT
tA O F m a x
tA O N m a x
O D T L cw n8
D Q S /D Q S
WL
D in
h
DQ
D in
h+1
D in
h+2
D in
h+3
D in
h+4
D in
h+5
D in
h+6
D in
h+7
D o not
care
T r a n sitio n in g
Note: Example for BL8 (via MRS or OTF), AL=0, CWL=5. In this example ODTH8=6 is exactly satisfied.
Fig. 51: Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration
of 6 clock cycles, example for BC4 (via MRS or OTF), AL=0, CWL=5
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T 11
NOP
NOP
NOP
NOP
CK
CK
CM D
A d d ress
O D T Lcnw
NOP
W RS4
NOP
NOP
NOP
NOP
NOP
NOP
V a lid
ODT
ODTH4
tA O N m in
O D T L o ff
tA D C m in
RTT_W R
RTT
tA O F m in
RTT_N om
tA O N m a x
tA O F m a x
tA D C m a x
O D TL on
O D T L cw n4
D Q S /D Q S
WL
DQ
D in
n
D in
n+1
D in
n+2
D in
n+3
D o not
care
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Fig. 52: Dynamic ODT: Behavior with ODT pin being asserted together with write command for the duration
of 4 clock cycles
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
NOP
CK
CK#
CM D
A d d ress
O D T Lcnw
NOP
W RS4
NOP
NOP
NOP
NOP
NOP
NOP
V a li d
ODT
ODTH4
tA O N m in
O D T L o ff
tA O F m i n
RTT_W R
RTT
tA O N m a x
tA O F m a x
O D TL on
O D T L cw n4
D Q S /D Q S
WL
DQ
D in
n
D in
n+1
D in
n+2
D in
n+3
D o not
care
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Asynchronous ODT Mode
Asynchronous ODT mode is selected when DRAM runs in DLLon mode, but DLL is temporarily disabled (i.e. frozen) in precharge
power-down (by MR0 bit A12). Based on the power down mode definitions, this is currently Precharge power down mode if DLL
is disabled during precharge power down by MR0 bit A12.
In asynchronous ODT timing mode, internal ODT command is NOT delayed by Additive Latency (AL) relative to the external ODT
command.
In asynchronous ODT mode, the following timing parameters apply: tAONPD min/max, tAOFPD min/max.
Minimum RTT turn-on time (tAONPD min) is the point in time when the device termination circuit leaves high impedance state
and ODT resistance begins to turn on. Maximum RTT turn on time (tAONPD max) is the point in time when the ODT resistance is
fully on.
tAONPD min and tAONPDmax are measured from ODT being sampled high.
Minimum RTT turn-off time (tAOFPDmin) is the point in time when the devices termination circuit starts to turn off the ODT
resistance. Maximum ODT turn off time (tAOFPDmax) is the point in time when the on-die termination has reached high
impedance. tAOFPD min and tAOFPDmax are measured from ODT being sample low.
Fig. 53: Asynchronous ODT Timings on DDR3 SDRAM with fast ODT transition: AL is ignored.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK
CK#
CKE
tIS
tIH
ODT
tIS
tIH
tAONPDmax
tAOFPDmin
RTT
tAONPDmin
tAOFPDmax
Do not
care
Transitioning
In Precharge Power Down, ODT receiver remains active; however no Read or Write command can be issued, as the respective
ADD/CMD receivers may be disabled.
Table 15: Asynchronous ODT Timing Parameters for all Speed Bins
Symbol
Description
Min.
Max.
Unit
tAONPD
Asynchronous RTT turn-on delay (Power-Down with DLL frozen)
2
8.5
ns
tAOFPD
Asynchronous RTT turn-off delay (Power-Down with DLL frozen)
2
8.5
ns
Table 16: ODT timing parameters for Power Down (with DLL frozen) entry and exit transition period
Description
Min.
Max.
ODT to RTT
min{ ODTLon * tCK + tAONmin; tAONPDmin }
max{ ODTLon * tCK + tAONmax; tAONPDmax }
turn-on delay
min{ (WL - 2) * tCK + tAONmin; tAONPDmin }
max{ (WL - 2) * tCK + tAONmax; tAONPFmax }
ODT to RTT
min{ ODTLoff * tCK + tAOFmin; tAOFPDmin }
max{ ODTLoff * tCK + tAOFmax; tAOFPDmax }
turn-off delay
min{ (WL - 2) * tCK + tAOFmin; tAOFPDmin }
max{ (WL - 2) * tCK + tAOFmax; tAOFPDmax }
tANPD
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Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is a transition period
around power down entry, where the DDR3 SDRAM may show either synchronous or asynchronous ODT behavior.
The transition period is defined by the parameters tANPD and tCPDED(min). tANPD is equal to (WL-1) and is counted backwards in time from the clock cycle where CKE is first registered low. tCPDED(min) starts with the clock cycle where CKE is first
registered low. The transition period begins with the starting point of tANPD and terminates at the end point of tCPDED(min). If
there is a Refresh command in progress while CKE goes low, then the transition period ends at the later one of tRFC(min) after
the Refresh command and the end point of tCPDED(min). Please note that the actual starting point at tANPD is excluded from
the transition period, and the actual end point at tCPDED(min) and tRFC(min, respectively, are included in the transition period.
ODT assertion during the transition period may result in an RTT changes as early as the smaller of tAONPDmin and (ODTLon*tCK+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-assertion during the
transition period may result in an RTT change as early as the smaller of tAOFPDmin and (ODTLoff*tCK+tAOFmin) and as late as
the larger of tAOFPDmax and (ODTLoff*tCK+tAOFmax). Note that, if AL has a large value, the range where RTT is uncertain
becomes quite large. The following figure shows the three different cases: ODT_A, synchronous behavior before tANPD; ODT_B
has a state change during the transition period; ODT_C shows a state change after the transition period.
Fig. 54: Synchronous to asynchronous transition during Precharge Power Down (with DLL frozen) entry
(AL=0; CWL=5; tANPD=WL-1=4)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CK
CK
CM D
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CKE
tA N P D
tC P D E D m in
tC P D E D
P D e n try tra n s itio n p e rio d
L ast sync.
ODT
tA O F m in
RTT
RTT
O D T L o ff
tA O F m a x
Sync. O r
asy nc. O D T
RTT
RTT
tA O F P D m in
tA O F P D m a x
O D T L o ff+ tA O F P D m in
O D T L o ff+ tA O F P D m a x
F irs t a s y n c .
ODT
tA O F P D m a x
RTT
RTT
tA O F P D m in
T r a n s itio n in g
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Asynchronous to Synchronous ODT Mode transition during Power-Down Exit
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is also a transition
period around power down exit, where either synchronous or asynchronous response to a change in ODT must be expected from
the DDR3 SDRAM.
This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered high. tANPD
is equal to (WL -1) and is counted (backwards) from the clock cycle where CKE is first registered high.
ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPDmin and (ODTLon*tCK+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-assertion during the
transition period may result in an RTT change as early as the smaller of tAOFPDmin and (ODTLoff*tCK+tAOFmin) and as late as
the larger of tAOFPDmax and (ODToff*tCK+tAOFmax). Note that if AL has a large value, the range where RTT is uncertain
becomes quite large. The following figure shows the three different cases: ODT_C, asynchronous response before tANPD;
ODT_B has a state change of ODT during the transition period; ODT_A shows a state change of ODT after the transition period
with synchronous response.
Fig. 55: Asynchronous to synchronous transition during Precharge Power Down (with DLL frozen) exit
(CL=6; AL=CL-1; CWL=5; tANPD=WL-1=9)
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Td0
Td1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
CK
CKE
CMD
NOP
NOP
NOP
NOP
tANPD
tXPDLL
PD exit transition period
ODT_C
_sync
tAOFPDmin
DRAM
_RTT_
C_sync
RTT
tAOFPDmax
ODT_B
_tran
tAOFPDmin
DRAM
_RTT_
B_tran
RTT
tAOFPDmax
ODTLoff + tAOFmin
ODTLoff + tAOFmax
ODTLoff
ODT_A
_async
tAOFmax
tAOFmin
DRAM_
RTT_A_
async
RTT
Transitioning
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M15F1G1664A (2R)
Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low
periods
If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit may
overlap. In this case, the response of the DDR3 SDRAMs RTT to a change in ODT state at the input may be synchronous or
asynchronous from the state of the PD entry transition period to the end of the PD exit transition period (even if the entry ends
later than the exit period).
If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case, the response of
the DDR3 SDRAMs RTT to a change in ODT state at the input may be synchronous or asynchronous from the state of the PD
exit transition period to the end of the PD entry transition period. Note that in the following figure, it is assumed that there was no
Refresh command in progress when Idle state was entered.
Fig. 56: Transition period for short CKE cycles with entry and exit period overlapping (AL=0; WL=5;
tANPD=WL-1=4)
T0
T1
T2
T3
REF
NOP
NOP
NOP
T4
T5
T6
NOP
NOP
T7
T8
T9
T10
T11
T12
T13
T14
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
CK
CMD
NOP
NOP
CKE
tANPD
tANPD
PD exit transition period
PD entry transition period
tRFC(min)
tXPDLL
CKE
Short CKE high transition period
tXPDLL
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ZQ Calibration Commands
ZQ Calibration Description
ZQ Calibration command is used to calibrate DRAM Ron and ODT values. DDR3 SDRAM needs longer time to calibrate output
driver and on-die termination circuits at initialization and relatively smaller time to perform periodic calibrations.
ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command may be issued
at any time by the controller depending on the system environment. ZQCL command triggers the calibration engine inside the
DRAM and once calibration is achieved the calibrated values are transferred from calibration engine to DRAM IO which gets
reflected as updated output driver and on-die termination values.
The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the transfer of
values. All other ZQCL commands except the first ZQCL command issued after RESET is allowed a timing period of tZQoper.
ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS.
No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit, tZQoper, or tZQCS.
The quiet time on the DRAM channel allows calibration of output driver and on-die termination values. Once DRAM calibration is
achieved, the DRAM should disable ZQ current consumption path to reduce power.
All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller.
ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self refresh. Upon self-refresh exit,
DDR3 SDRAM will not perform an IO calibration without an explicit ZQ calibration command. The earliest possible time for ZQ
Calibration command (short or long) after self refresh exit is tXS.
In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper, tZQinit, or tZQCS
between ranks.
Fig. 57: ZQ Calibration Timing
T0
T1
Ta0
Ta1
ZQCL
NOP
NOP
NOP
Ta2
Ta3
Tb0
Tb1
Valid
Valid
ZQCS
Address
Valid
Valid
A10
Valid
Valid
Tc0
Tc1
Tc2
NOP
NOP
Valid
CK
CK
CMD
NOP
Valid
CKE
(1)
Valid
Valid
(1)
Valid
ODT
(2)
Valid
Valid
(2)
Valid
DQ Bus
(3)
Hi-Z
Activities
(3)
tZQCS
Hi-Z
Activities
tZQCS
Do not
care
Time
Break
Note:
1. CKE must be continuously registered high during the calibration procedure.
2. On-die termination must be disabled via the ODT signal or MRS during the calibration procedure.
3. All devices connected to the DQ bus should be high impedance during the calibration procedure.
ZQ External Resistor Value, Tolerance, and Capacitive loading
In order to use the ZQ calibration function, a 240 ohm +/- 1% tolerance external resistor connected between the ZQ pin and
ground. The single resistor can be used for each SDRAM or one resistor can be shared between two SDRAMs if the ZQ
calibration timings for each SDRAM do not overlap. The total capacitive loading on the ZQ pin must be limited.
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Absolute Maximum Ratings
Table 17: Absolute Maximum DC Ratings
Symbol
VDD
VDDQ
Vin, Vout
Tstg
Parameter
Rating
Units
Note
Voltage on VDD pin relative to Vss
-0.4 ~ 1.975
V
1,3
Voltage on VDDQ pin relative to Vss
-0.4 ~ 1.975
V
1,3
Voltage on any pin relative to Vss
-0.4 ~ 1.975
V
1
-55 ~ 100
°C
1,2
Storage Temperature
Note:
1.
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2.
Storage Temperature is the case surface temperature on the center/top side of the DRAM.
3.
VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6VDDQ,
when VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
Table 18: Refresh parameters
Parameter
REF command to ACT or REF
command time
Symbol
Value
Unit
tRFC
110
ns
Table 19: Temperature Range
Symbol
Condition
Toper
Commercial
Parameter
Value
Units
Notes
Normal Operating Temperature Range
0 to 85
°C
1,2
Extended Temperature Range
85 to 95
°C
1,3
Note:
1.
Operating Temperature Toper is the case surface temperature on the center/top side of the DRAM.
2.
The Normal Temperature Range specifies the temperatures where all DRAM specification will be supported. During
operation, the DRAM case temperature must be maintained between 0-85°C under all operating conditions.
Some applications require operation of the DRAM in the Extended Temperature Range between 85°C and 95°C
case temperature. Full specifications are guaranteed in this range, but the following additional apply.
a) Refresh commands must be doubled in frequency, therefore, reducing the Refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the
Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6=0 and MR2 A7=1) or enable
the optional Auto Self-Refresh mode (MR2 A6=1 and MR2 A7=0).
3.
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AC & DC Operating Conditions
Table 20: Recommended DC Operating Conditions
Symbol
Rating
Parameter
Min.
Typ.
Max.
Unit
Note
VDD
Supply Voltage
1.425
1.5
1.575
V
1,2
VDDQ
Supply Voltage for Output
1.425
1.5
1.575
V
1,2
Note:
1.
Under all conditions VDDQ must be less than or equal to VDD.
2.
VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
AC & DC Input Measurement Levels
Table 21: AC and DC Logic Input Levels for Single-Ended Signals & Command and Address
Symbol
DDR3-1600
Parameter
Unit Note
Min.
Max.
VIH.CA(DC100)
DC input logic high
VREF + 0.100
VDD
V
1,5
VIL.CA(DC100)
DC input logic low
VSS
VREF - 0.100
V
1,6
VIH.CA(AC175)
AC input logic high
VREF + 0.175
Note2
V
1,2,7
VIL.CA(AC175)
AC input logic low
Note2
VREF - 0.175
V
1,2,8
VIH.CA(AC150)
AC input logic high
VREF + 0.150
Note2
V
1,2,7
VIL.CA(AC150)
AC input logic low
Note2
VREF - 0.150
V
1,2,8
VREFCA(DC)
Reference Voltage for ADD, CMD inputs
0.49 * VDD
0.51 * VDD
V
3,4
Note:
1. For input only pins except RESET .VREF=VREFCA(DC)
2. See "Overshoot and Undershoot Specifications"
3. The ac peak noise on VREF may not allow Vref to deviate from VREF(DC) by more than +/- 0.1% VDD.
4. For reference: approx. VDD/2 +/- 15mV
5. VIH(DC) is used as a simplified symbol for VIH.CA(DC100)
6. VIL(DC) is used as a simplified symbol for VIL.CA(DC100)
7. VIH(AC) is used as a simplified symbol for VIH.CA(AC175) and VIH.CA(AC150); VIH.CA(AC175) value is used when
Vref + 0.175V is referenced, VIH.CA(AC150) value is used when Vref + 0.150V is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175) and VIL.CA(AC150); VIL.CA(AC175) value is used when
Vref - 0.175V is referenced, VIL.CA(AC150) value is used when Vref - 0.150V is referenced.
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Table 22: AC and DC Logic Input Levels for Single-Ended Signals & DQ and DM
Symbol
DDR3-1600
Parameter
Min.
Max.
Unit
Note
VIH.DQ(DC100)
DC input logic high
VREF + 0.100
VDD
V
1
VIL.DQ(DC100)
DC input logic low
VSS
VREF- 0.1
V
1
VIH.DQ(AC175)
AC input logic high
VREF + 0.150
Note2
V
1,2
VIL.DQ(AC175)
AC input logic low
Note2
VREF - 0.15
V
1,2
VIH.DQ(AC150)
AC input logic high
VREF + 0.150
Note2
V
1,2
VIL.DQ(AC150)
AC input logic low
Note2
VREF - 0.15
V
1,2
VREFDQ(DC)
Reference Voltage for DQ, DM inputs
0.49 * VDD
0.51 * VDD
V
3,4
Note:
1. For input only pins except RESET . VREF = VREFDQ(DC)
2. See "Overshoot and Undershoot Specifications"
3. The ac peak noise on VREF may not allow Vref to deviate from VREF (DC) by more than ± 0.1% VDD.
4. For reference: approx. VDD/2 ±15mV
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M15F1G1664A (2R)
VREF Tolerances
The dc-tolerance limits and ac-moist limits for the reference voltages VREFCA and VREFDQ are illustrated in the following figure.
It shows a valid reference voltage VREF (t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g.,1 sec). This average has to meet the min/max
requirement in previous page. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ±1% VDD.
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on VREF.
“VREF” shall be understood as VREF(DC).
The clarifies that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and
therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC)
deviations from the optimum position within the data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and de-rating values need to include time and voltage associated with
VREF ac-noise. Timing and voltage effects due to ac-noise on VREF up to the specified limit (±1% of VDD) are included in DRAM
timing and their associated de-ratings.
Fig. 58: Illustration of VREF(DC) tolerance and VREF ac-noise limits
V o lta g e
VDD
V re f a c - n o is e
V r e f ( D C )m a x
V re f (D C )
V D D /2
V r e f( D C ) m in
V SS
tim e
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Table 23: AC and DC Logic Input Levels for Differential Signals
Symbol
DDR3-1600
Parameter
VIHdiff
VILdiff
VIHdiff(ac)
VILdiff(ac)
Min.
Differential input logic high
Differential input logic low
Differential input high ac
Differential input low ac
+0.2
Note3
2 x ( VIH(ac) – VREF )
Note3
Unit
Max.
Note3
-0.2
Note3
2 x ( VREF- VIL(ac) )
V
V
V
V
Notes
1
1
2
2
Note:
1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS , DQSL, DQSL , DQSU, DQSU use VIH/VIL(ac) of
DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also there.
3. These values are not defined, however the single-ended signals CK, CK , DQS, DQS need to be within the respective limits
(VIH(dc)max, VIL(dc)min) for single-ended signals as well as limitations for overshoot and undershoot.
Differential Input Voltage(i.e. DQS –DQS, CK– CK)
Fig. 59: Definition of differential ac-swing and “time above ac-level”
tDVAC
VIH.Diff.AC.min
VIH.Diff. DC min
0
Half cycle
VIL. Diff. DC max
VIL.Diff.AC.max
tDVAC
Time
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Table 24: Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS -1.5V
Slew Rate [V/ns]
tDVAC [ps]
tDVAC [ps]
@ IVIH/Ldiff(ac)I = 350Mv
@ IVIH/Ldiff(ac)I = 300mV
Min.
Max.
Min.
Max.
> 4.0
75
-
175
-
4.0
57
-
170
-
3.0
50
-
167
-
2.0
38
-
163
-
1.8
34
-
162
-
1.6
29
-
161
-
1.4
22
-
159
-
1.2
13
-
155
-
1.0
0
-
150
-
< 1.0
0
-
150
-
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, CK , DQS ) has also to comply with certain requirements for
single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for
ADD/CMD signals) in every half-cycle. DQS, DQS have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac) /
VIL (ac)) for DQ signals) in every half-cycle proceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if VIH150 (ac)/VIL150(ac) is
used for ADD/CMD signals, then these ac-levels apply also for the singleended signals CK and CK Elite Semiconductor Memory Technology Inc
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Table 25: Single-ended levels for CK, DQS, CK , DQS Symbol
VSEH
VSEL
DDR3-1600
Parameter
Unit
Notes
note3
V
1, 2
(VDDQ/2) + 0.175
note3
V
1, 2
Single-ended low-level for strobes
note3
(VDDQ/2) - 0.175
V
1, 2
Single-ended Low-level for CK, CK
note3
(VDDQ/2) - 0.175
V
1, 2
Min.
Max.
Single-ended high-level for strobes
(VDDQ/2) + 0.175
Single-ended high-level for CK, CK
Note:
1. For CK, CK use VIH/VIL(ac) of ADD/CMD; for strobes (DQS, DQS ) use VIH/VIL(ac) of DQs.
2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/VIL(ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or
ac-low level is used for a signal group, then the reduced level applies also there.
3. These values are not defined, however the single-ended signals CK, CK , DQS, DQS need to be within the respective
limits (VIH(dc)max, VIL(dc)min) for single-ended signals as well as limitations for overshoot and undershoot.
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point
voltage of differential input signals (CK, CK and DQS, DQS ) must meet the requirements in the following table. The
differential input cross point voltage Vix is measured from the actual cross point of true and complete signal to the midlevel
between of VDD and VSS.
Fig. 60: Vix Definition
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Table 26: Cross point voltage for differential input signals (CK, DQS)
Symbol
Vix
DDR3-1600
Parameter
Unit
Min.
Max.
Differential Input Cross Point Voltage relative to VDD/2
-150
150
mV
for CK, CK
-175
175
mV
-150
150
mV
Differential Input Cross Point Voltage relative to VDD/2
Note
1
for DQS, DQS
Note 1: Extended range for Vix is only allowed for clock and if single-ended clock input signals CK and CK are monotonic
with a single-ended swing VSEL / VSEH of at least VDD/2 ± 250mV, and when the differential slew rate of CK
- CK is larger than 3V/ns.
2: The relation between Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2)+Vix (Min.)-VSEL≧25mV
VSEH – ((VDD/2) +Vix (Max.))≧25mV
Slew Rate Definition for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS ) are defined and measured as shown below.
Table 27: Differential Input Slew Rate Definition
Description
Differential input slew rate for rising edge (CK- CK &
Measured
Defined by
From
To
VILdiffmax
VIHdiffmin
[VIHdiffmin-VILdiffmax] / DeltaTRdiff
VIHdiffmin
VILdiffmax
[VIHdiffmin-VILdiffmax] / DeltaTFdiff
DQS- DQS )
Differential input slew rate for falling edge (CK- CK &
DQS- DQS )
The differential signal (i.e., CK- CK & DQS- DQS ) must be linear between these thresholds.
Fig. 61: Input Nominal Slew Rate Definition for single ended signals
Delta
TRdiff
VIHdiffMin
0
VILdiffMax
Delta
TFdiff
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AC and DC Output Measurement Levels
Table 28: Single Ended AC and DC Output Levels
Symbol
Parameter
Value
Unit
Notes
VOH(DC)
DC output high measurement level (for IV curve linearity)
0.8xVDDQ
V
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.5xVDDQ
V
VOL(DC)
DC output low measurement level (fro IV curve linearity)
0.2xVDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
VTT+0.1xVDDQ
V
1
VOL(AC)
AC output low measurement level (for output SR)
VTT-0.1xVDDQ
V
1
Note:
1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver
impedance of 40 Ω and an effective test load of 25 Ω to VTT = VDDQ/2.
Table 29: Differential AC and DC Output Levels
Symbol
Parameter
DDR3
Unit
Notes
VOHdiff(AC) AC differential output high measurement level (for output SR)
+0.2 x VDDQ
V
1
VOLdiff(AC) AC differential output low measurement level (for output SR)
-0.2 x VDDQ
V
1
Note:
1. The swing of ± 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver
impedance of 40 Ω and an effective test load of 25 Ω to VTT=VDDQ/2 at each of the differential outputs.
Table 30: Single Ended Output Slew Rate
Description
Measured
From
To
Defined by
Single ended output slew rate for rising edge
VOL(AC) VOH(AC)
[VOH(AC)-VOL(AC)] / DeltaTRse
Single ended output slew rate for falling edge
VOH(AC) VOL(AC)
[VOH(AC)-VOL(AC)] / DeltaTFse
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
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Fig. 62: Single Ended Output Slew Rate Definition
D elta T F se
Single Ended Output Voltage (i.e. DQ)
V O H (A C )
V TT
V O L (A C )
D elta T F se
Table 31: Output Slew Rate (single-ended)
Parameter
Single-ended Output Slew Rate
DDR3-1600
Symbol
SRQse
Unit Note
Min.
Max.
TBD
5
V/ns
Note:
SR: Slew Rate.
Q: Query Output (like in DQ, which stands for Data-in, Query -Output).
se: Single-ended signals.
For Ron = RZQ/7 setting.
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Table 32: Differential Output Slew Rate
Measured
From
To
Description
Defined by
Differential output slew rate for rising edge
VOLdiff(AC) VOHdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / DeltaTRdiff
Differential output slew rate for falling edge
VOHdiff(AC) VOLdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / DeltaTFdiff
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
Fig. 63: Differential Output Slew Rate Definition
D e lta T F s e
Differential Output Voltage (i.e. DQS-DQS)
V
O h d iff (A C )
0
V O L d iff (A C )
D e lta T F s e
Table 33: Differential Output Slew Rate
Parameter
Single-ended Output Slew Rate
DDR3-1600
Symbol
SRQse
Unit
Min.
Max.
TBD
10
V/ns
Note:
SR: Slew Rate.
Q: Query Output (like in DQ, which stands for Data-in, Query -Output).
diff: Differential signals.
For Ron = RZQ/7 setting.
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Reference Load for AC Timing and Output Slew Rate
The following figure represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the
device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by
a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system
environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines
terminated at the tester electronics.
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Overshoot and Undershoot Specifications
Table 34: AC Overshoot/Undershoot Specification for Address and Control Pins
Item
DDR3-1600
Units
Maximum peak amplitude allowed for overshoot area
0.4
V
Maximum peak amplitude allowed for undershoot area
0.4
V
Maximum overshoot area above VDD
0.33
V-ns
Maximum undershoot area below VSS
0.33
V-ns
(A0-A12, BA0-BA3, CS , RAS , CAS , WE , CKE, ODT)
Table 35: AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask Item
DDR3-1600
Units
Maximum peak amplitude allowed for overshoot area
0.4
V
Maximum peak amplitude allowed for undershoot area
0.4
V
Maximum overshoot area above VDD
0.13
V-ns
Maximum undershoot area below VSS
0.13
V-ns
Volts (V)
(CK, CK , DQ, DQS, DQS , DM)
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34 Ohm Output Driver DC Electrical Characteristics
A Functional representation of the output buffer is shown as below. Output driver impedance RON is defined by the value of the
external reference resistor RZQ as follows:
RON34 = RZQ / 7 (nominal 34.4ohms +/-10% with nominal RZQ=240ohms)
The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows:
RONPu = [VDDQ-Vout] / l Iout l ------------------- under the condition that RONPd is turned off (1)
RONPd = Vout / I Iout I -------------------------------under the condition that RONPu is turned off (2)
Fig. 64: Output Driver: Definition of Voltages and Currents
Chip in Drive Mode
Output Driver
VDDQ
I Pu
To
other
circuitry
like
RCV, ...
RONPu
DQ
I Pd
RONPd
I
Out
V Out
VSSQ
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Table 36: Output Driver DC Electrical Characteristics, assuming RZQ = 240ohms; entire operating
temperature range; after proper ZQ calibration
RONNom
Resistor
RON34Pd
34 ohms
RON34Pu
RON40pd
40 ohms
RON40pu
Mismatch between pull-up and pull-down, MMPuPd
Vout
Min.
Nom.
Max.
Unit
Notes
VOLdc = 0.2 x VDDQ
0.6
1.0
1.1
RZQ / 7
1,2,3
VOMdc = 0.5 x VDDQ
0.9
1.0
1.1
RZQ / 7
1,2,3
VOHdc = 0.8 x VDDQ
0.9
1.0
1.4
RZQ / 7
1,2,3
VOLdc = 0.2 x VDDQ
0.9
1.0
1.4
RZQ / 7
1,2,3
VOMdc = 0.5 x VDDQ
0.9
1.0
1.1
RZQ / 7
1,2,3
VOHdc = 0.8 x VDDQ
0.6
1.0
1.1
RZQ / 7
1,2,3
VOLdc = 0.2 × VDDQ
0.6
1.0
1.1
RZQ / 6
1,2,3
VOMdc = 0.5 × VDDQ
0.9
1.0
1.1
RZQ / 6
1,2,3
VOHdc = 0.8 × VDDQ
0.9
1.0
1.4
RZQ / 6
1,2,3
VOLdc = 0.2 × VDDQ
0.9
1.0
1.4
RZQ / 6
1,2,3
VOMdc = 0.5 × VDDQ
0.9
1.0
1.1
RZQ / 6
1,2,3
VOHdc = 0.8 × VDDQ
0.6
1.0
1.1
RZQ / 6
1,2,3
VOMdc = 0.5 x VDDQ
-10
+10
%
1,2,4
Note:
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance
limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ. Other calibration
schemes may be used to achieve the linearity spec shown above. e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ.
4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd:
Measure RONPu and RONPd, but at 0.5 x VDDQ:
MMPuPd = [RONPu - RONPd] / RONNom x 100
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Output Driver Temperature and Voltage sensitivity
If temperature and/or voltage after calibration, the tolerance limits widen according to the following table.
Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ
Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization.
Table 37: Output Driver Sensitivity Definition
Items
Min.
Max.
Unit
[email protected]
0.6 - dRONdTH*lDelta Tl - dRONdVH*lDelta Vl
1.1 + dRONdTH*lDelta Tl - dRONdVH*lDelta Vl
RZQ/7
[email protected]
0.9 - dRONdTM*lDelta Tl - dRONdVM*lDelta Vl
1.1 + dRONdTM*lDelta Tl - dRONdVM*lDelta Vl
RZQ/7
[email protected]
0.6 - dRONdTL*lDelta Tl - dRONdVL*lDelta Vl
1.1 + dRONdTL*lDelta Tl - dRONdVL*lDelta Vl
RZQ/7
Table 38: Output Driver Voltage and Temperature Sensitivity
Speed Bin
Items
DDR3-1600
Unit
Min.
Max.
dRONdTM
0
1.5
%/°C
dRONdVM
0
0.13
%/mV
dRONdTL
0
1.5
%/°C
dRONdVL
0
0.13
%/mV
dRONdTH
0
1.5
%/°C
dRONdVH
0
0.13
%/mV
Note: These parameters may not be subject to production test. They are verified by design and characterization.
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On-Die Termination (ODT) Levels and I-V Characteristics
On-Die Termination effective resistance RTT is defined by bits A9, A6, and A2 of the MR1 Register.
ODT is applied to the DQ, DM, DQS/ DQS .
A functional representation of the on-die termination is shown in the following figure. The individual pull-up and pull-down
resistors (RTTPu and RTTPd) are defined as follows:
RTTPu = [VDDQ - Vout] / I Iout I ------------------ under the condition that RTTPd is turned off (3)
RTTPd = Vout / I Iout I ------------------------------ under the condition that RTTPu is turned off (4)
Fig. 65: On-Die Termination: Definition of Voltages and Currents
Chip in Termination M ode
ODT
VDDQ
I Pu
I
To other
circuitry
like
RCV, ...
RTT
Out
=I
Pd
-I
Pu
Pu
DQ
I Pd
RTT
I
Out
V Out
Pd
VSSQ
ODT DC Electrical Characteristics
The following table provides an overview of the ODT DC electrical characteristics. The values for RTT60Pd120, RTT60Pu120,
RTT120Pd240, RTT120Pu240, RTT40Pd80, RTT40Pu80, RTT30Pd60, RTT30Pu60, RTT20Pd40, RTT20Pu40 are not specification requirements, but
can be used as design guide lines:
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Table 39: ODT DC Electrical Characteristics, assuming RZQ = 240ohms +/- 1% entire operating temperature
range; after proper ZQ calibration
MR1 A9,A6,A2
RTT
Resistor
Vout
VOLdc = 0.2 x VDDQ
RTT120Pd240
0,1,0
120Ω
RTT120Pu240
RTT120
RTT60Pd120
0, 0, 1
60Ω
RTT60Pu120
RTT60
RTT40Pd80
0, 1, 1
40Ω
RTT40Pu80
RTT40
RTT30Pd60
1, 0, 1
30Ω
RTT30Pu60
1, 0, 0
Min.
Nom.
Max.
Unit
Notes
0.6
1
1.1
RZQ
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.4
RZQ
1,2,3,4
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ
1,2,3,4
0.5 x VDDQ
0.9
1
1,1
RZQ
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ
1,2,3,4
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ /2
1,2,5
VOLdc = 0.2 x VDDQ
0.6
1
1.1
RZQ/2
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/2
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.4
RZQ/2
1,2,3,4
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ/2
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/2
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ/2
1,2,3,4
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ/4
1,2,5
VOLdc = 0.2 x VDDQ
0.6
1
1.1
RZQ/3
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/3
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.4
RZQ/3
1,2,3,4
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ/3
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/3
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ/3
1,2,3,4
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ/6
1,2,5
VOLdc = 0.2 x VDDQ
0.6
1
1.1
RZQ/4
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/4
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.4
RZQ/4
1,2,3,4
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ/4
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/4
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ/4
1,2,3,4
RTT30
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ/8
1,2,5
RTT20Pd40
VOLdc = 0.2 x VDDQ
0.5 x VDDQ
VOHdc = 0.8 x VDDQ
0.6
0.9
0.9
1
1
1
1.1
1.1
1.4
RZQ/6
RZQ/6
RZQ/6
1,2,3,4
1,2,3,4
1,2,3,4
20Ω
RTT20Pu40
RTT20
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ/6
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/6
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ/6
1,2,3,4
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ/12
1,2,5
Deviation of VM w.r.t. VDDQ/2, DVM
-5
+5
%
1,2,5,6
Note:
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits
if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 x VDDQ. Other calibration may be used to
achieve the linearity spec shown above.
4. Not a specification requirement, but a design guide line.
5. Measurement definition for RTT:
Apply VIH(ac) to pin under test and measure current / (VIH(ac)), then apply VIL(ac) to pin under test and measure current /
(VIL(ac)) respectively.
RTT = [VIH(ac) - VIL(ac)] / [I(VIH(ac)) - I(VIL(ac))]
6. Measurement definition for VM and DVM:
Measure voltage (VM) at test pin (midpoint) with no lead:
Delta VM = [2VM / VDDQ -1] x 100
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ODT Temperature and Voltage sensitivity
If temperature and/or voltage after calibration, the tolerance limits widen according to the following table.
Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ
Table 40: ODT Sensitivity Definition
Min.
Max.
RTT 0.9 - dRTTdT*lDelta Tl - dRTTdV*lDelta Vl
Unit
1.6 + dRTTdT*lDelta Tl + dRTTdV*lDelta Vl
RZQ/2,4,6,8,12
Table 41: ODT Voltage and Temperature Sensitivity
Min.
Max.
Unit
dRTTdT
0
1.5
%/°C
dRTTdV
0
0.15
%/mV
Note: These parameters may not be subject to production test. They are verified by design and characterization.
Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in the following figure.
Fig. 66: ODT Timing Reference Load
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Table 42: ODT Timing Definitions
Definitions for tAON, tAONPD, tAOF, tAOFPD, and tADC are provided in the following table and subsequent figures.
Symbol
Begin Point Definition
End Point Definition
tAON
Rising edge of CK - CK defined by the end point of ODTLon
Extrapolated point at VSSQ
tAONPD
Rising edge of CK - CK with ODT being first registered high
Extrapolated point at VSSQ
tAOF
Rising edge of CK - CK defined by the end point of ODTLoff
End point: Extrapolated point at VRTT_Nom
tAOFPD
Rising edge of CK - CK with ODT being first registered low
End point: Extrapolated point at VRTT_Nom
Rising edge of CK - CK defined by the end point of ODTLcnw,
End point: Extrapolated point at VRTT_Wr and
ODTLcwn4, or ODTLcwn8
VRTT_Nom respectively
tADC
Table 43: Reference Settings for ODT Timing Measurements
Measured Parameter tAON
tAONPD
tAOF
tAOFPD
tADC
RTT_Nom Setting
RTT_Wr Setting
VSW1[V]
VSW2[V]
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/12
RZQ/2
0.20
0.30
Note
Fig. 67: Definition of tAON B e g in p o in t: R is in g e d g e o f C K – C K #
D e fin e d b y th e e n d p o in t o f O D T L o n
C K
V T T
C K #
tA O N
T sw 2
T sw 1
D Q , D M
D Q S , D Q S #
T D Q S , T D Q S #
V sw 2
V sw 1
V S S Q
E n d p o in t: E x tr a p o la te d p o in t a t V S S Q
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Fig. 68: Definition of tAONPD
B e g in p o in t: R is in g e d g e o f C K – C K #
w ith O D T b e in g fir s t r e g is te r h ig h
C K
V TT
C K #
tA O N P D
Tsw 2
Tsw 1
D Q , D M
D Q S , D Q S #
TD Q S , TD Q S #
V sw 2
V sw 1
V S S Q
E n d p o in t: E x tr a p o la te d p o in t a t V S S Q
Fig. 69: Definition of tAOF
B e g in p o in t: R is in g e d g e o f C K – C K #
d e fin e d b y th e e n d p o in t o f O D T L o ff
C K
VTT
C K#
tA O F
VR TT_N om
E n d p o in t: E x tr a p o la te d p o in t a t V R T T _ N o m
Tsw 2
D Q , D M
D Q S, D Q S#
TD Q S, TD Q S#
Tsw 1
V sw 2
V sw 1
VSSQ
Fig. 70: Definition of tAOFPD
B e g in p o in t: R is in g e d g e o f C K – C K #
w ith O D T b e in g fir s t r e g is te r e d lo w
CK
VTT
CK#
tA O F P D
VRTT_Nom
E n d p o in t: E x tr a p o la te d p o in t a t V R T T _ N o m
Tsw 2
DQ, DM
DQS, DQS#
TDQS, TDQS#
Tsw 1
V sw 2
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V sw 1
VSSQ
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M15F1G1664A (2R)
Fig. 71: Definition of tADC
Begin point: Rising edge of CK – CK#
defined by the end of ODTLcnw
CK
Begin point: Rising edge of CK – CK# defined
by the end of ODTLcwn4 or ODTLcwn8
CK
VTT
CK#
CK#
tADC
VRTT_Nom
tADC
End point: Extrapolated point at VRTT_Nom
Tsw22
Tsw21
DQ, DM
DQS, DQS#
TDQS, TDQS#
VRTT_Nom
Tsw12
Tsw11
Vsw2
VRTT_Wr
End point: Extrapolated point at VRTT_Wr
Vsw1
VSSQ
Table 44: Input / Output Capacitance
Symbol
Parameter
DDR3-1600
Min.
Max.
Units
Notes
CIO
Input/output capacitance (DQ, DM, DQS, DQS )
1.50
2.30
pF
1,2,3
CCK
Input capacitance, CK and CK
0.80
1.40
pF
2,3
CDCK
Input capacitance delta, CK and CK
0.00
0.15
pF
2,3,4
CDDQS
Input/output capacitance delta, DQS and DQS
0.00
0.15
pF
2,3,5
CI
Input capacitance, CTRL, ADD, CMD input-only pins
0.75
1.30
pF
2,3,7,8
CDI_CTRL
Input capacitance delta, all CTRL input-only pins
-0.40
0.20
pF
2,3,7,8
CDI_ADD_CMD
Input capacitance delta, all ADD/CMD input-only pins
-0.40
0.40
pF
2,3,9,10
CDIO
Input/output capacitance delta, DQ, DM, DQS, DQS
-0.50
0.30
pF
2,3,11
CZQ
Input/output capacitance of ZQ pin
-
3.00
pF
2,3,12
Note:
1.
2.
3.
4.
5.
Although the DM pins have different functions, the loading matches DQ and DQS
This parameter is not subject to production test. It is verified by design and characterization. VDD=VDDQ=1.5V or 1.35V
VBIAS=VDD/2 and on-die termination off.
This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
Absolute value of CCK-CCK
Absolute value of CIO(DQS)-CIO(DQS)
6.
CI applies to ODT, CS , CKE, A0-A12, BA0-BA2, RAS , CAS , WE .
7.
8.
CDI_CTRL applies to ODT, CS and CKE
CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A12, BA0-BA2, RAS , CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CK)+CI(/CK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO( DQS ))
12. Maximum external load capacitance on ZQ pin: 5 pF.
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M15F1G1664A (2R)
IDD Specifications and Measurement Conditions
Table 45: IDD Specifications
Symbol
Parameter/Condition
DDR3-1600
Unit
49
mA
65
mA
11
mA
13
mA
Operating Current 0
IDD0
-> One Bank Activate
-> Precharge
Operating Current 1
IDD1
-> One Bank Activate
-> Read
-> Precharge
IDD2P0
IDD2P1
Precharge Power-Down Current
Slow Exit - MR0 bit A12 = 0
Precharge Power-Down Current
Fast Exit - MR0 bit A12 = 1
IDD2Q
Precharge Quiet Standby Current
19
mA
IDD2N
Precharge Standby Current
24
mA
IDD2Q2NT
Precharge Standby ODT IDDQ Current
35
mA
18
mA
IDD3P
Active Power-Down Current
Always Fast Exit
IDD3N
Active Standby Current
28
mA
IDD4R
Operating Current Burst Read
135
mA
IDD4W
Operating Current Burst Write
140
mA
IDD5B
Burst Refresh Current
95
mA
11
mA
12
mA
200
mA
11
mA
IDD6
IDD6ET
Self-Refresh Current: Normal Temperature Range
(Tcase: 0-85°C)
Self-Refresh Current: Extended Temperature Range
(Tcase: 0-95°C)
IDD7
All Bank Interleave Read Current
IDD8
Reset Low Current
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M15F1G1664A (2R)
Table 46: IDD Measurement Conditions Symbol
Parameter/Condition
Operating One Bank Active-Precharge Current
IDD0
CKE: High; External clock: On; BL: 8(1); AL: 0; CS : High between ACT and PRE; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0, 0, 1,1,2,2...
Output Buffer and RTT: Enabled in Mode Registers (2); ODT Signal: stable at 0.
Operating One Bank Active-Read-Precharge Current
IDD1
CKE: High; External clock: On; BL: 8(1, 7); AL: 0; CS : High between ACT, RD and PRE;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0, 0, 1,1,2,2...
Output Buffer and RTT: Enabled in Mode Registers (2); ODT Signal: stable at 0.
Precharge Standby Current
IDD2N
CKE: High; External clock: On; BL: 8(1); AL: 0; CS : stable at 1; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers (2); ODT Signal: stable at 0.
Precharge Power-Down Current Slow Exit
IDD2P(0)
CKE: Low; External clock: On; BL: 8(1); AL: 0; CS : stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers (2);
ODT Signal: stable at 0; Pecharge Power Down Mode: Slow Exit (3).
Precharge Power-Down Current Fast Exit
IDD2P(1)
CKE: Low; External clock: On; BL: 8(1); AL: 0; CS : stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers (2);
ODT Signal: stable at 0; Pecharge Power Down Mode: Fast Exit (3).
Precharge Quiet Standby Current
IDD2Q
CKE: High; External clock: On; BL: 8(1); AL: 0; CS : stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers (2); ODT Signal: stable at 0.
Active Standby Current
IDD3N
CKE: High; External clock: On; BL: 8(1); AL: 0; CS : stable at 1; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers (2); ODT Signal: stable at 0.
Active Power-Down Current
IDD3P
CKE: Low; External clock: On; BL: 8(1); AL: 0; CS : stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers (2); ODT Signal: stable at 0.
Operating Burst Read Current
IDD4R
CKE: High; External clock: On; BL: 8(1, 7); AL: 0; CS : High between RD; DM:stable at 0;
Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...;
Output Buffer and RTT: Enabled in Mode Registers (2); ODT Signal: stable at 0.
Operating Burst Write Current
IDD4W
CKE: High; External clock: On; BL: 8(1); AL: 0; CS : High between WR; DM: stable at 0;
Bank Activity: all banks open, WR commands cycling through banks: 0, 0, 1,1,2,2...;
Output Buffer and RTT: Enabled in Mode Registers (2); ODT Signal: stable at HIGH.
Burst Refresh Current
IDD5B
CKE: High; External clock: On; BL: 8(1); AL: 0; CS : High between REF; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: REF command every nRFC;
Output Buffer and RTT: Enabled in Mode Registers (2); ODT Signal: stable at 0.
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M15F1G1664A (2R)
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled(4); Self-Refresh Temperature Range (SRT): Normal(5);
IDD6
CKE: Low; External clock: Off; CK and CK : LOW; CL: see Table 47 or 48; BL: 8(1); AL: 0;
CS , Command, Address, Bank Address, Data IO: MID-LEVEL; DM:stable at 0;
Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers (2);
ODT Signal: MID-LEVEL
Self-Refresh Current: Extended Temperature Range (optional) (6)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled(4); Self-Refresh Temperature Range (SRT): Extended(5);
IDD6ET
CKE: Low; External clock: Off; CK and CK : LOW; CL: see Table 47 or 48; BL: 8(1); AL: 0;
CS , Command, Address, Bank Address, Data IO: MID-LEVEL;DM: stable at 0;
Bank Activity: Extended Temperature Self-Refresh operation;
Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: MID-LEVEL.
Operating Bank Interleave Read Current
IDD7
CKE: High; External clock: On; BL: 8(1, 7); AL: CL-1; CS : High between ACT and RDA; DM:stable at 0;
Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing;
Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at 0.
RESET Low Current
IDD8
RESET: LOW; External clock: Off; CK and CK : LOW; CKE: FLOATING; CS , Command, Address,
Bank Address, Data IO: FLOATING; ODT Signal: FLOATING RESET Low current reading is valid once power is
stable and RESET has been LOW for at least 1ms.
NOTE 1. Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
NOTE 2. Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
NOTE 3. Pecharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
NOTE 4. Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
NOTE 5. Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
NOTE 6. Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are
supported by DDR3 SDRAM device
NOTE 7. Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
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M15F1G1664A (2R)
Table 47: Definition of SWITCHING for Address and Command Input Signals
SWITCHING for Address (row, column) and Command Signals ( CS , RAS , CAS , WE ) is defined as:
If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks and change then to
Address
the opposite value
(row, column)
(e.g. Ax Ax Ax Ax / x /Ax /Ax /Ax Ax Ax Ax Ax…
Please see each IDDx definition for details
Bank Address
If not otherwise mentioned the bank addresses should be switched like the row/column address please see each IDDx for details
Define D = { CS , RAS , CAS , WE }:= {HIGH, LOW, LOW, LOW}
Define D = { CS , RAS , CAS , WE }:= {HIGH, HIGH, HIGH, HIGH}
Command
Define Command Background Pattern = D D /D /D D D /D /D D D /D /D....
( CS , RAS , CAS , WE )
If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R), the Background Pattern
Command is substituted by the respective CS , RAS , CAS , WE levels of the necessary
command. See each IDDx definition for details.
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M15F1G1664A (2R)
Standard Speed Bins
Table 48:DDR3-1600Mbps Speed Bin
DDR3-1600
CL-nRCD-nRP
10-10-10
Parameter
Symbol
Min.
Unit
Max.
Internal read command to first data
tAA
12.5
20
ns
ACT to internal read or write delay time
tRCD
12.5
-
ns
PRE command period
tRP
12.5
-
ns
ACT to ACT or REF command period
tRC
47.5
-
ns
ACT to PRE command period
CWL=5
CL=5
CWL=6,7,8
CWL =5
tRAS
tCK(AVG)
tCK(AVG)
tCK(AVG)
35
2.5
Reserved
2.5
9*tREFI
3.3
Reserved
3.3
ns
ns
ns
ns
CWL =6
tCK(AVG)
Reserved
Reserved
ns
CWL =7
tCK(AVG)
Reserved
Reserved
ns
CWL =8
tCK(AVG)
Reserved
Reserved
ns
CWL =5
tCK(AVG)
Reserved
Reserved
ns
CWL =6
tCK(AVG)
1.875
<2.5
ns
CWL =7
tCK(AVG)
Reserved
Reserved
ns
CWL =8
tCK(AVG)
Reserved
Reserved
ns
CWL =5
tCK(AVG)
Reserved
Reserved
ns
CWL =6
tCK(AVG)
1.875
<2.5
ns
CWL =7
tCK(AVG)
Reserved
Reserved
ns
CWL =8
tCK(AVG)
Reserved
Reserved
ns
CWL =5
tCK(AVG)
Reserved
Reserved
ns
CWL =6
tCK(AVG)
Reserved
Reserved
ns
CWL =7
tCK(AVG)
1.5
<1.875
ns
CWL =8
tCK(AVG)
Reserved
Reserved
ns
CWL =5
tCK(AVG)
Reserved
Reserved
ns
CWL =6
tCK(AVG)
Reserved
Reserved
ns
CWL =7
tCK(AVG)
1.5
<1.875
ns
CWL =8
tCK(AVG)
1.25
<1.5
ns
CWL =5
tCK(AVG)
Reserved
Reserved
ns
CWL =6
tCK(AVG)
Reserved
Reserved
ns
CWL =7
tCK(AVG)
Reserved
Reserved
ns
CWL =8
tCK(AVG)
1.25
<1.5
ns
CL=6
CL=7
CL=8
CL=9
CL=10
CL=11
Supported CL Settings
5,6,7,8,9,10,11
nCK
Supported CWL Settings
5,6,7,8
nCK
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M15F1G1664A (2R)
Electrical Characteristics & AC Timing
Table 49: Timing Parameter by Speed Bin (DDR3-1600Mbps)
Parameter
Symbol
DDR3-1600
Min.
Units
Max.
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
Average high pulse width
Average low pulse width
tCK (DLL_OFF)
tCK(avg)
tCH(avg)
tCL(avg)
Absolute Clock Period
tCK(abs)
Absolute clock HIGH pulse width
Absolute clock LOW pulse width
Clock Period Jitter
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter during DLL locking
period
Duty Cycle Jitter
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
tCH(abs)
tCL(abs)
JIT(per)
JIT(per, lck)
tJIT(cc)
8
Refer to "Standard Speed Bins”
0.47
0.53
0.47
0.53
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT(per)max
0.43
0.43
-70
70
-60
60
140
JIT(cc, lck)
120
ps
-103
103
-122
122
-136
136
-147
147
-155
155
-163
163
-169
169
-175
175
-180
180
-184
184
-188
188
tERR(nper)min = (1 + 0.68ln(n)) *
tJIT(per)min
tERR(nper)max = (1 + 0.68ln(n)) *
tJIT(per)max
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Cumulative error across n = 13, 14 . . . 49, 50
cycles
tJIT(duty)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
tERR(nper)
Note
ns
ps
tCK(avg)
tCK(avg)
ps
tCK(avg)
tCK(avg)
ps
ps
ps
ps
Data Timing
DQS, DQS to DQ skew, per group, per access
tDQSQ
-
100
DQ output hold time from DQS, DQS
ps
tQH
0.38
-
DQ low-impedance time from CK, CK
tLZ(DQ)
-450
225
ps
DQ high impedance time from CK, CK
tHZ(DQ)
-
225
ps
Data setup time to DQS, DQS referenced to
Vih(ac) / Vil(ac) levels
tDS(base)
AC175/160
Data setup time to DQS, DQS referenced to
Vih(ac) / Vil(ac) levels
tDS(base)
AC150/135
Data hold time from DQS, DQS referenced to
Vih(dc) / Vil(dc) levels
DQ and DM Input pulse width for each input
Data Strobe Timing
tDH(base)
DC100/90
tDIPW
DQS, DQS differential READ Preamble
tRPRE
0.9
Note 19 tCK(avg)
DQS, DQS differential READ Postamble
tRPST
0.3
Note 11 tCK(avg)
DQS, DQS differential output high time
tQSH
0.4
-
tCK(avg)
DQS, DQS differential output low time
tQSL
0.4
-
tCK(avg)
DQS, DQS differential WRITE Preamble
tWPRE
0.9
-
tCK(avg)
DQS, DQS differential WRITE Postamble
tWPST
0.3
-
tCK(avg)
tCK(avg)
ps
See the page 105~106
ps
ps
360
-
ps
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DQS, DQS rising edge output access time from
M15F1G1664A (2R)
tDQSCK
-225
225
tCK(avg)
DQS and DQS low-impedance time
(Referenced from RL - 1)
tLZ(DQS)
-450
225
tCK(avg)
DQS and DQS high-impedance time
(Referenced from RL + BL/2)
tHZ(DQS)
-
225
tCK(avg)
DQS, DQS differential input low pulse width
tDQSL
0.45
0.55
tCK(avg)
DQS, DQS differential input high pulse width
tDQSH
0.45
0.55
tCK(avg)
DQS, DQS rising edge to CK, CK rising edge tDQSS
-0.27
0.27
tCK(avg)
DQS, DQS falling edge setup time to CK, CK
rising edge
0.18
-
tCK(avg)
0.18
-
tCK(avg)
rising CK, CK
tDSS
DQS, DQS falling edge hold time from CK, CK tDSH
rising edge
Command and Address Timing
DLL locking time
tDLLK
Internal READ Command to PRECHARGE
tRTP
Command delay
Delay from start of internal write
tWTR
transaction to internal read command
WRITE recovery time
tWR
Mode Register Set command cycle time
tMRD
Mode Register Set command update delay
tMOD
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
tRCD
tRP
tRC
CAS to CAS command delay
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period for 2KB
page size
Four activate window for 2KB page size
tCCD
Command and Address setup time to CK, CK
referenced to Vih(ac) / Vil(ac) levels
Command and Address setup time to CK, CK
referenced to Vih(ac) / Vil(ac) levels
Command and Address hold time from CK,
CK referenced to Vih(dc) / Vil(dc) levels
Control and Address Input pulse width for each
input
Calibration Timing
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation Short calibration time
Reset Timing
tDAL(min)
tMPRR
tRAS
tRRD
tFAW
512
tRTPmin.: max(4nCK, 7.5ns)
tRTPmax. tWTRmin.: max(4nCK, 7.5ns)
tWTRmax.: 15
4
tMODmin.: max(12nCK, 15ns)
tMODmax.: 12.5
12.5
47.5
4
-
WR + roundup(tRP / tCK(avg))
1
Standard Speed Bins
tRRDmin.: max(4nCK, 7.5ns)
tRRDmax.: 40
0
tIS(base) AC175/160
tIS(base) AC150/135
nCK
ns
nCK
ns
ns ns nCK
nCK
nCK
ns
ps
See the page 103~104
ps
tIH(base) DC100/90
ps
tIPW
560
-
ps
tZQinit
tZQoper
tZQCS
512
256
64
-
nCK
nCK
nCK
Exit Reset from CKE HIGH to a valid command tXPR
tXPRmin.: max(5nCK, tRFC(min) +
10ns)
tXPRmax.: -
Self Refresh Timings
Exit Self Refresh to commands not requiring a
locked DLL
tXS
Exit Self Refresh to commands requiring a
locked DLL
tXSDLL
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tXSmin.: max(5nCK, tRFC(min) +
10ns)
tXSmax.: tXSDLLmin.: tDLLK(min)
tXSDLLmax.: -
nCK
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M15F1G1664A (2R)
Minimum CKE low width for Self Refresh entry
tCKESR
to exit timing
Valid Clock Requirement after Self Refresh
Entry (SRE)
tCKSRE
or Power-Down Entry (PDE)
Valid Clock Requirement before Self Refresh
Exit (SRX)
or Power-Down Exit (PDX) or Reset Exit
tCKSRX
Power Down Timings
Exit Power Down with DLL on to any valid
command;
Exit Precharge Power Down with DLL frozen to tXP
commands
not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to
tXPDLL
commands
requiring a locked DLL
CKE minimum pulse width
tCKE
Command pass disable delay
tCPDED
Power Down Entry to Exit Timing
tPD
Timing of ACT command to Power Down entry tACTPDEN
Timing of PRE or PREA command to Power
Down entry
Timing of RD/RDA command to Power Down
entry
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tPRPDEN
tRDPDEN
tWRPDEN
Timing of WRA command to Power Down entry
tWRAPDEN
(BL8OTF, BL8MRS, BC4OTF)
Timing of WR command to Power Down entry
(BC4MRS)
tWRPDEN
Timing of WRA command to Power Down entry
tWRAPDEN
(BC4MRS)
Timing of REF command to Power Down entry tREFPDEN
Timing of MRS command to Power Down entry tMRSPDEN
tCKESRmin.: tCKE(min) + 1 nCK
tCKESRmax.: tCKSREmin.: max(5 nCK, 10 ns)
tCKSREmax.: tCKSRXmin.: max(5 nCK, 10 ns)
tCKSRXmax.: -
tXPmin.: max(3nCK, 6ns)
tXPmax.: -
tXPDLLmin.: max(10nCK, 24ns)
tXPDLLmax.: tCKEmin.: max(3nCK ,5ns)
tCKEmax.: tCPDEDmin.: 2
tCPDEDmin.: tPDmin.: tCKE(min)
tPDmax.: 9*tREFI
tACTPDENmin.: 1
tACTPDENmax.: tPRPDENmin.: 1
tPRPDENmax.: tRDPDENmin.: RL+4+1
tRDPDENmax.: tWRPDENmin.: WL + 4 + (tWR /
tCK(avg))
tWRPDENmax.: tWRAPDENmin.: WL+4+WR+1
tWRAPDENmax.: tWRPDENmin.: WL + 2 + (tWR /
tCK(avg))
tWRPDENmax.: tWRAPDENmin.: WL + 2 +WR + 1
tWRAPDENmax.: tREFPDENmin.: 1
tREFPDENmax.: tMRSPDENmin.: tMOD(min)
tMRSPDENmax.: -
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
ODT Timings
ODT turn on Latency
ODTLon
WL-2=CWL+AL-2
nCK
ODT turn off Latency
ODTLoff
WL-2=CWL+AL-2
nCK
ODT high time without write command or
with write command and BC4
ODTH4
ODT high time with Write command and BL8
ODTH8
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
RTT turn-on
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
RTT dynamic change skew
Write Leveling Timings
First DQS/ DQS rising edge after
write leveling mode is programmed
ODTH4min.: 4
ODTH4max.: ODTH8min.: 6
ODTH8max.: -
nCK
nCK
tAONPD
2
8.5
ns
tAOFPD
2
8.5
ns
tAON
-225
225
ps
tAOF
0.3
0.7
tCK(avg)
tADC
0.3
0.7
tCK(avg)
tWLMRD
40
-
nCK
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DQS/ DQS delay after write leveling mode is
programmed
Write leveling setup time from rising CK, CK
crossing to rising DQS, DQS crossing
Write leveling hold time from rising DQS, DQS
crossing to rising CK, CK crossing
Write leveling output delay
Write leveling output error
M15F1G1664A (2R)
tWLDQSEN
25
-
nCK
tWLS
165
-
ps
tWLH
165
-
ps
0
0
7.5
2
ns
ns
tWLO
tWLOE
Jitter Notes
Specific Note a
Unit “tCK(avg)” represents the actual tCK(avg) of the input clock under operation. Unit “nCK” represents one clock cycle of the
input clock, counting the actual clock edges. ex) tMRD=4 [nCK] means; if one Mode Register Set command is registered at Tm,
anther Mode Register Set command may be registered at Tm+4, even if (Tm+4-Tm) is 4 x tCK(avg) + tERR(4per), min.
Specific Note b
These parameters are measured from a command/address signal (CKE, CS , RAS , CAS , WE , ODT, BA0, A0, A1, etc) transition edge to its respective clock signal (CK/ CK ) crossing. The spec values are not affected by the amount of clock jitter
applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not.
Specific Note c
These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U) ) crossing to its respective clock signal (CK,
CK ) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc), as these are
relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
Specific Note d
These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data
strobe signal (DQS(L/U), DQS(L/U) ) crossing.
Specific Note e
For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{tPARAM[ns] / tCK(avg)[ns]}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied.
Specific Note f
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper), act of the
input clock, where 2 <= m <=12. (Output derating is relative to the SDRAM input clock.)
Specific Note g
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input
clock. (Output deratings are relative to the SDRAM input clock.)
Timing Parameter Notes
1.
Actual value dependent upon measurement level definitions which are TBD.
2.
Commands requiring a locked DLL are: READ (and RAP) are synchronous ODT commands.
3.
The max values are system dependent.
4.
WR as programmed in mode register.
5.
Value must be rouned-up to next higher integer value.
6.
There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7.
For definition of RTT-on time tAON. See “Timing Parameters”.
8.
For definition of RTT-off time tAOF. See “Timing Parameters”.
9.
tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles are programmed in MR0.
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11. The maximum read postamble is bounded by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right
side.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this
parameter needs to be derated by TBD.
13. Value is only valid for RON34.
14. Single ended signal parameter.
15. tREFI depends on TOPER.
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate.
Note for DQ and DM signals, VREF(DC)=VREFDQ(DC). For input only pins except RESET , VREF(DC)=VREFCA(DC).
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note
for DQ and DM signals, VREF(DC)=VREFDQ(DC). For input only pins except RESET , VREF(DC)=VREFCA(DC).
18. Start of internal write transaction is defined as follows:
For BL8 (fixed by MRS and on-the-fly): Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL.
For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.
19. The maximum preamble is bound by tLZ (DQS) max on the left side and tDQSCK(max) on the right side.
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in
progress, but power-down IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN (min) is satisfied, there are
cases where additional time such as tXPDLL (min) is also required.
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error within
64 nCK for all speed bins assuming the maximum sensitivities specified in the “Output Driver Voltage and Temperature
Sensitivity” and “ODT Voltage and Temperature Sensitivity” tables. The appropriate interval between ZQCS commands can
be determined from these tables and other application-specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following
formula: ZQCorrection / [(TSens x Tdriftrate) + (VSens x Vdriftrate)] where TSens = max(dRTTdT, dRONdTM) and VSens =
max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5%/C, VSens = 0.15%/mV, Tdriftrate = 1 C/sec and Vdriftrate = 15mV/sec, then the interval
between ZQCS commands is calculated as 0.5 / [(1.5x1)+(0.15x15)] = 0.133 ~ 128ms
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling
edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising
edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of derating
to accommodate for the lower altemate threshold of 150mV and another 25ps to account for the earlier reference point
[(175mV - 150mV) / 1V/ns].
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Address / Command Setup, Hold, and Derating
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and
tIH(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively.
Example: tIS (total setup time) = tIS(base) + delta tIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first
crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between
shaded ‘VREF (dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate
line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of the tangent line to the actual signal from the ac level to
dc level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first
crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded
‘dc to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc)
level is used for derating value. For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the
time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
Table 50: ADD/CMD Setup and Hold Base-Values for 1V/ns
Symbol
Reference
DDR3-1600
Units
tIS(base) AC175
VIH/L(ac)
45
ps
tIS(base) AC150
VIH/L(ac)
170
ps
tIS(base) AC135
VIH/L(ac)
-
ftIH(base) DC100
VIH/L(dc)
120
ps
Note:
1. (ac/dc referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate.
2. The tIS(base) AC150 (AC135) specifications are adjusted from the tIS(base) specification by adding an additional 100ps of
derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference
point [(175mV- 150mV) / 1V/ns or [(160mV - 135mV) / 1V/ns].
CMD/ADD Slew rate (V/ns)
Table 51: Derating values DDR3-1600 tIS/tIH – (AC175)
2
1.5
1
0.9
0.8
0.7
0.6
0.5
0.4
4.0 V/ns
D tIS
D tIH
88
50
59
34
0
0
-2
-4
-6
-10
-11
-16
-17
-26
-35
-40
-62
-60
3.0 V/ns
D tIS
D tIH
88
50
59
34
0
0
-2
-4
-6
-10
-11
-16
-17
-26
-35
-40
-62
-60
Delta tIS, Delta tIH derating in AC/DC based
CK, /CK Differential Slew Rate
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
D tIS
D tIH D tIS
D tIH D tIS
D tIH D tIS
D tIH
88
50
96
58
104
66
112
74
59
34
67
42
75
50
83
58
0
0
8
8
16
16
24
24
-2
-4
6
4
14
12
22
20
-6
-10
2
-2
10
6
18
14
-11
-16
-3
-8
5
0
13
8
-17
-26
-9
-18
-1
-10
7
-2
-35
-40
-27
-32
-19
-24
-11
-16
-62
-60
-54
-52
-46
-44
-38
-36
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1.2 V/ns
D tIS
D tIH
120
84
91
68
32
34
30
30
26
24
21
18
15
8
-2
-6
-30
-26
1.0 V/ns
D tIS
D tIH
128
100
99
84
40
50
38
46
34
40
29
34
23
24
5
10
-22
-10
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M15F1G1664A (2R)
C M D /AD D Slew rate (V/ns )
Table 52: Derating values DDR3-1600 tIS/tIH – (AC150)
2
1.5
1
0.9
0.8
0.7
0.6
0.5
0.4
4.0 V/ns
D tIS D tIH
75
50
50
34
0
0
0
-4
0
-10
0
-16
-1
-26
-10
-40
-25
-60
3.0 V/ns
D tIS D tIH
75
50
50
34
0
0
0
-4
0
-10
0
-16
-1
-26
-10
-40
-25
-60
Delta tIS, Delta tIH derating in AC/DC based
CK,/CK Differential Slew Rate
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH
75
50
83
58
91
66
99
74
50
34
58
42
66
50
74
58
0
0
8
8
16
16
24
24
0
-4
8
4
16
12
24
20
0
-10
8
-2
16
6
24
14
0
-16
8
-8
16
0
24
8
-1
-26
7
-18
15
-10
23
-2
-10
-40
-2
-32
6
-24
14
-16
-25
-60
-17
-52
-9
-44
-1
-36
1.2 V/ns
D tIS D tIH
107
84
82
68
32
34
32
30
32
24
32
18
31
8
22
-6
7
-26
1.0 V/ns
D tIS D tIH
115
100
90
84
40
50
40
46
40
40
40
34
39
24
30
10
15
-10
Table 53: Required time tVAC above VIH(AC) {below VIL(AC)} for ADD/CMD transition Slew Rate [V/ns]
[email protected] [ps]
[email protected] [ps]
[email protected] [ps]
[email protected] [ps]
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
>2.0
75
-
TBD
-
175
-
TBD
-
2
57
-
TBD
-
170
-
TBD
-
1.5
50
-
TBD
-
167
-
TBD
-
1
38
-
TBD
-
163
-
TBD
-
0.9
34
-
TBD
-
162
-
TBD
-
0.8
29
-
TBD
-
161
-
TBD
-
0.7
22
-
TBD
-
159
-
TBD
-
0.6
13
-
TBD
-
155
-
TBD
-
0.5
0
-
TBD
-
150
-
TBD
-
<0.5
0
-
TBD
-
150
-
TBD
-
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Data Setup, Hold, and Slew Rate De-rating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDH(base) and
tDH(base) value to the delta tDS and delta tDH derating value respectively.
Example: tDS (total setup time) = tDS(base) + delta tDS
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first
crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between
shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate
line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of the tangent line to the actual signal from the ac level to
dc level is used for derating value.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first
crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded
‘dc level to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate
line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to
VREF(dc) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the
time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in the following tables, the derating values may be obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Table 54: Data Setup and Hold Base-Values
Symbol
Reference
DDR3-1600
Units
tDS(base) AC175
VIH/L(ac)
-
ps
tDS(base) AC 150
VIH/L(ac)
10
ps tDS(base) AC 135
VIH/L(ac)
-
ps
tDH(base) DC100
VIH/L(dc)
45
ps Note: ac/dc referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate
DQ Slew rate (V/ns)
Table 55: Derating values DDR3-1600 tDS/tDH – (AC175)
2
1.5
1
0.9
0.8
0.7
0.6
0.5
0.4
Delta tDS, Delta tDH derating in AC/DC based
DQS, /DQS Differential Slew Rate
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
4.0 V/ns
3.0 V/ns
D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH
88
50
88
50
88
50
59
34
59
34
59
34
67
42
0
0
0
0
0
0
8
8
16
16
-2
-4
-2
-4
6
4
14
12
22
20
-6
-10
2
-2
10
6
18
14
26
24
-3
-8
5
0
13
8
21
18
29
34
-1
-10
7
-2
15
8
23
24
-11
-16
-2
-6
5
10
-30
-26
-22
-10
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DQ Slew rate (V/ns)
Table 56: Derating values DDR3-1600 tDS/tDH – (AC150)
2
1.5
1
0.9
0.8
0.7
0.6
0.5
0.4
Delta tDS, Delta tDH derating in AC/DC based
DQS, /DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH
75
50
75
50
75
50
50
34
50
34
50
34
58
42
0
0
0
0
0
0
8
8
16
16
0
-4
0
-4
8
4
16
12
24
20
0
-10
8
-2
16
6
24
14
32
24
8
-8
16
0
24
8
32
18
40
34
15
-10
23
-2
31
8
39
24
14
-16
22
-6
30
10
7
-26
15
-10
Table 57: Required time tVAC above VIH(ac) {below VIL(ac)} for valid DQ transition
DDR3-1600 (AC150)
DDR3-1600 (AC135)
tVAC[ps]
tVAC[ps]
Slew Rate [V/ns]
Min.
Max.
Min.
Max.
>2.0
175
-
TBD
-
2
170
-
TBD
-
1.5
167
-
TBD
-
1
163
-
TBD
-
0.9
162
-
TBD
-
0.8
161
-
TBD
-
0.7
159
-
TBD
-
0.6
155
-
TBD
-
0.5
155
-
TBD
-
<0.5
150
-
TBD
-
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Package Dimensions (96 balls; 0.8mmx0.8mm Pitch; BGA)
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Revision History
Revision
Date
1.0
2013.06.26
Original
1.1
2013.09.05
Add the specification of tRFC
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Important Notice
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any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the
time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples
for the application of our products. No responsibility is assumed by ESMT for
any infringement of patents, copyrights, or other intellectual property rights of
third parties which may result from its use. No license, either express, implied
or otherwise, is granted under any patents, copyrights or other intellectual
property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure,
should be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.
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