HA12181FP AM Radio Noise Reduction System REJ03F0130-0200 (Previous: ADE-207-171A) Rev.2.00 Jun 15, 2005 Functions • • • • Buffer amp. for audio Linear approximate circuit for noise reduction IF Amp., detector, audio amp. and AGC circuit for noise detection Gate pulse generator Features • • • • • High noise cancelling capacity: 46 dB typ. Less gain loss: GV = –0.5 dB typ. Low total harmonic destortion and high signal-to noise ratio: THD = 0.06% typ., S/N = 75 dB typ. Operation supply voltage range: 7.0 V to 10 V (8.2 V typ.) Less external parts count Rev.2.00 Jun 15, 2005 page 1 of 19 Rev.2.00 Jun 15, 2005 page 2 of 19 ANT RF OSC MIX 1st IFT IF AM-IC Det. 2nd IFT 7 4 C513 1µ + 3 AF Input R506 12 k C501 1000 p 16 IF Input SW1 C500 0.033µ 2 C503 SW2 5 Pulse Det. Det. Capacitor for Pahse C512 0.068µ Level Diff. Det. Circuit Phase Circuit SW3 HPF1 LPF + C502 0.01µ 3.3µ Det. 1 14 IF AGC Stabilized Voltage Circuit Stabi. Volt. IF Amp. LPF R500 100 k IF AGC HPF AF AGC 6 Capacitor for Hold C511 0.033µ Stabilized Current Circuit (waveform compensation) 15 (2) (1) 10 Buffer Amp. 9 Gate pulse (2) Gate pulse (1) Pulse Det.(2) Gate pulse Gen. Unit 11 13 + VCC (8.2 V) Gate Time Constant C507 2200 p C506 100µ R:Ω C:F AF Output Capacitor C509 + for By-pass R503 0.033µ 180 k C508 C510 R504 1µ 0.033µ Capacitor 4.7 k for waveform compensation SW5 SW4 12 R502 22 k Pulse Det.(1) R505 47 k AF AGC Noise AGC OR 8 Hight-pass Amp. (waveform compensation) AF Amp. C504 0.22µ HA12181FP Block Diagram HA12181FP Table of Pin Description and External Parts External parts No. of pin 1 Name IF AGC Function Time constant for IF AGC. DC voltage (V) (No input) 2.7 1 R500 100k 2 3 Bias1 AF input No. Equivalent circuit Bypass for voltage Stabi. 3.2 Input of AF. 3.3 recommended value R500 C502 100 K 3.3 µ C500 Influence of External parts Larger than recommended value Smaller than recommended value Longer Longer time to stabilize AGC. distortion of recover. 0.033 µ — Increased noise. C513 1µ — — R506 12 K Cut off frequency of L·P·F and H·P·F shifted lower. Cut off frequency of L·P·F and H·P·F shifted higher. C512 0.068 µ Must be used on the recommended value. C502 3.3µ + 2 C500 0.033µ 20k 3 + C513 AF IN 4 5 Bias2 Phase Decide the current of filter network. 1.3 Phase circuit 3.3 4 5 C512 0.068µ Rev.2.00 Jun 15, 2005 page 3 of 19 HA12181FP Table of Pin Description and External Parts (cont.) External parts No. of pin 6 Name Function Hold Hold of level difference. DC voltage (V) (No input) No. Equivalent circuit 3.3 recommended value Influence of External parts Larger than recommended value Smaller than recommended value C511 0.033 µ Must be used on the recommended value. — — — C510 0.033 µ Must be used on the recommended value. 6 C511 0.033µ 7 GND GND 8 HighPass. HighPass AMP. (Waveform Compensation) 3.3 Output of AF 3.3 9 AF out — — 8 C510 0.033µ C508 1µ Output DC cut R504 4.7 K Output load C509 0.033 µ Must be used on the recommended value. + 9 C508 1µ 10 Wave form Waveform Compensation R504 4.7k 3.3 10 C509 0.033µ Rev.2.00 Jun 15, 2005 page 4 of 19 HA12181FP Table of Pin Description and External Parts (cont.) External parts No. of pin 11 Name Function Gate Gate pulse generation DC voltage (V) (No input) No. Equivalent circuit 4.5V recommended value R503 180 K C507 2200 P Vth Determination of noise detection sensitivity R502 Smaller than recommended value Gate pulse width become narrow. 22 K Higher noise detection sensitivity. Lower noise detection sensitivity. — — — — C503 0.01 µ — — R505 47 K C504 0.22 µ Longer time to stabilize AGC. Missoperation in noise detector. IF Input Coupling Instability 11 12 Larger than recommended value Gate pulse width become wider. 0 C507 2200p Influence of External parts R503 180k 1.1 12 R502 22k 13 VCC VCC 8.2 14 IF Det. IF AGC detector 3.3 — 14 13 C503 0.01µ 15 AF AGC Time constant for AF AGC 0 15 C504 0.22µ 16 IF in IF input R505 47k 1.3 — 30k 16 C501 1000p IF IN Rev.2.00 Jun 15, 2005 page 5 of 19 HA12181FP Absolute Maximum Ratings (Ta = 25°C) Item Symbol Supply voltage Power dissipation Operating temperature Storage temperature Note: 1. Value at Ta = 85°C VCC Pd Topr Tstg Ratings Unit 16 400*1 –40 to +85 –55 to +125 V mW °C °C Electrical Characteristics (Tentative) (VCC = 8.2 V, Ta = 25°C, Pin 3 input: Vin = 100 mVrms, f = 1 KHz, Pin 16 input: Vin = 74 dBµ, fc = 450 KHz, fm = 1 KHz, m = 30%) Item Supply current Output voltage Symbol ICC Vout — 70 Min Typ 11.0 95 Max — 120 Unit mA mVrms Total harmonic distortion Signal-to-noise ratio THD1 — 0.06 0.3 % S/N (1) 60 75 — dB Pin 3 input Vin = 100 mVrms (Reference), Rg = 10 KΩ Strong input total harmonic distortion THD2 — 1.0 2.5 % Recovered output voltage VO (AF) 50 78 120 mVrms Pin 3 input Vin = 500 mVrms Pin 16 input only Recovered output signal-to-noise-ratio S/N (2) 35 45 — dB Noise suppression ratio NSR 35 46 — dB 100mV Test Conditions No input signal, IC only Pin 3 input only Input the waveform below. Pin 3 input Vin = 100 mVrms (Reference) no input sine wave 10µs Pin 16 Input 2ms Figure 1 Input Waveform at Measurement of Noise Suppression Ratio Rev.2.00 Jun 15, 2005 page 6 of 19 HA12181FP Test Circuit VCC (8.2V) Det.Out + B A R505 C504 47k 0.22µ R502 R503 C507 C509 15k 180k 2200p 0.033µ + C503 0.01µ IF-IN PULSE-IN C501 1000p 50 R504 4.7k C OUT C506 100µ + C508 1µ 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 AM-SG AF-IN + C513 1µ 50 R500 100k + C502 3.3µ C500 0.033µ R506 12k C512 C511 0.068µ 0.033µ C510 0.033µ AF-SG Unit R:Ω C:F Note: 1. Resistors tolerance are within ±5%. 2. Capacitors tolerance (C509 to C512) are within ±5%, other capacitor are within ±10%. Operation Principle ANT. Noise Detector 16 IF 3 Processing Waveform Circuit B 1st IFT A RF CONV. IF DET 9 C AM-IC HA12181FP Figure 2 System Block Diagram of AM Radio Rev.2.00 Jun 15, 2005 page 7 of 19 D Out HA12181FP A system block diagram of AM Radio using the HA12181FP is shown in Figure 2 and waveforms at each point in the system are illustrated in Figure 3. For AM wave with impulse noise from ANT, the pulse spreads its width each time when the AM wave passes through a selection filter. The pulse width becomes the order of several hundred microseconds at detector output (Point C). A radio without a noise canceller produces large noise to the audience. This IC perfectly detects every noise by using the signals from 1st IFT (Point B) in front of the narrow band filter. The wave process circuit approximates the voltage linearly at the pulse to reduce the noise in the output. The principle for wave processing follows. Further investigation make it clear that the pulse width of impulse noise is constant (several handred microseconds) and independent of the waveform or waveheight. Therefore the former and later voltage (VA, VB) of the pulse can be found at the same time (T1) by means of the wave and the delayed one for this time, as shown in the right figure. Each Point in the Figure Waveform including Noise A Narrower Pulse Width and Higher Wave Height B Point D VB Point C C VA Wider Pulse Width and Lower Wave Height T1 T2 D Noiseless Figure 3 Waveforms at Each Point in the System In an actual circuit, the differential voltage between input and output of phase shift circuit is changed to the capacitor C511 at pin 6. At the time of T1, when the switch turns to the noise processing mode (the switch positions in Figure 4 are inverted), the voltage difference (VA – VB) is held in C511. C509 at pin 10 is changed by the differential voltage between the held voltage and the output voltage at pin 9 (VA): VA – (VA – VB) = VB. Rev.2.00 Jun 15, 2005 page 8 of 19 HA12181FP As the initial voltage of C509 is equal to the output voltage (VA) before the switch change, the voltage between terminals of C509 is changed from VA to VB. The waveform which change up to C509 becomes the output, because the voltage of C509 appears at pin 9 through the buffer. The changed up waveform of C509 is almost linearly approximated because of the constant current change by the feedback from the output at pin 9. At the time of T2 when the awitches change to the normal mode (the switch position in Figure 4), the output recovers smoothly as the voltage of C509 is VB. However the unmatch of the wave delay time due to the pulse width or the phase circuit and the offset of circuit make a slight step difference on the waverform at the moment of switch change. LPF, consisting of R1 and C509 make it smooth. The frequency characteristics, which is detriorated by LPF in the normalmode, is compensated so that it might become flat. C509 and C510 should have the same capacity, and the tolerance must be within ±5%. Phase Circuit 3 R1 HPFAmp. + Subtraction – Circuit + Constant Current – Circuit(Subtraction R2 Circuit) 5 6 C512 Buffer C511 8 10 C510 C509 Figure 4 Waveform Processing Circuit Rev.2.00 Jun 15, 2005 page 9 of 19 9 Out Rev.2.00 Jun 15, 2005 page 10 of 19 50 AM SG. Pulse SG. 50 Two signals dummy ANT. RF OSC MIX 1st IFT IF AM-IC Det. 2nd IFT 7 4 C513 1µ + 3 AF Input R506 12 k C501 1000 p 16 IF Input C500 0.033µ 2 C503 SW2 5 Pulse Det. Det. Capacitor for Pahse C512 0.068µ Level Diff. Det. Circuit Phase Circuit SW3 HPF1 LPF + C502 0.01µ 3.3µ Det. 1 14 IF AGC Stabilized Voltage Circuit SW1 Stabi. Volt. IF Amp. LPF R500 100 k IF AGC HPF AF AGC 6 Capacitor for Hold C511 0.033µ Stabilized Current Circuit (waveform compensation) 15 8 (2) (1) Buffer Amp. Gate pulse (2) Gate pulse (1) Pulse Det.(2) Gate pulse Gen. + VCC (8.2 V) C506 100µ Meter 13 Unit R:Ω C:F 10 9 11 Gate Time AF Output Capacitor C509 Constant + for By-pass R503 0.033µ C507 180 k C508 C510 2200 p 0.033µ Capacitor 1µ R504 for waveform 4.7 k Noise compensation SW5 SW4 12 R502 22 k Pulse Det.(1) R505 47 k AF AGC Noise AGC OR Hight-pass Amp. (waveform compensation) AF Amp. C504 0.22µ HA12181FP Evaluation Circuit for Noise Reduction Effect HA12181FP Example of Noise Reduction Effect 20 VCC=8.2V AM SG : fc=999kHz, m=30%, fm=1kHz Pulse : No input 10 Vout 0 Two Signals dummy ANT. Output (dB) –10 50Ω NRoff 16Ω 16Ω 15p To ANT Pulse SG. 50Ω 16Ω 30Ω 65p Pulse SG Output (EMF) AM SG. –20 10µs 100mVP-P 2µs –30 Figure.2 NRon AM SG : fc=999kHz, no mod. Pulse SG : Refer to Figure.2 Noise –40 Pulse : No input –50 –60 0 10 20 30 40 50 60 70 80 AM SG Output (EMF) (dBµ) 90 100 110 120 20 VCC=8.2V AM SG : fc=999kHz, m=30%, fm=1kHz Pulse : No input 10 Vout 0 Two Signals dummy ANT. Output (dB) –10 50Ω 16Ω 16Ω 15p Pulse SG. NRoff –20 50Ω 16Ω 30Ω 65p To ANT Pulse SG Output (EMF) AM SG. 10µs NRon 100mVP-P 10µs –30 Figure.3 –40 Noise AM SG : fc=999kHz, no mod. Pulse SG : Refer to Figure.2 –50 –60 0 10 20 Rev.2.00 Jun 15, 2005 page 11 of 19 30 40 50 60 70 80 AM SG Output (EMF) (dBµ) 90 100 110 120 HA12181FP PC Board Layout Pattern C507 VCC C506 + R503 C504 R502 R501 R504 C503 C508 C501 C509 + IF in C513 16 R506 C511 C502 R500 C512 + Vout C510 C505 AF in + HA12181FP (Top view) FN-8648 HA12181FP (Bottom view) Rev.2.00 Jun 15, 2005 page 12 of 19 HA12181FP 10 0 -2 -4 Vin max (Vrms) Vout (dB) Main Characteristics Vout : Vin = 100 mVrms const Vout (0 dB = 96 mVrms) 2.0 1.5 -6 1.0 Vin Max (THD ≥ 1.0%) -8 -10 -12 0.5 0 40 100 200 400 1k 2k 4k 10 k 20 k f (Hz) 0.5 Vin = 100 mVrms THD (%) 0.4 0.3 0.2 0.1 0 40 100 200 400 f (Hz) Rev.2.00 Jun 15, 2005 page 13 of 19 1k 2k 4k 10 k 50 k HA12181FP 10 Vo (AF) : 0 dB = 76 mVrms 0 -10 Vout (dB) -20 fc = 450 kHz, m = 30%, fm = 1kHz -30 -40 Noise (no modulation) -50 -60 -70 10 20 30 40 50 60 70 80 90 100 110 Vin (EMF) (dBm) 50 20 V pulse (mVp-p) 10 Pulse input at Gate ON 10µs V pulse 2ms 5 2 1 0.5 0.2 1k 5k 10 k R502 (Ω) Rev.2.00 Jun 15, 2005 page 14 of 19 50 k 100 k 120 Vout (mVrms) THD1 (%) HA12181FP 120 Vout 0.5 100 0.4 80 0.3 60 0.2 40 0.1 20 0 0 THD1 6 7 8 9 10 11 12 13 14 15 16 S/N1 (dB) THD2 (%) VCC (V) 120 1.0 100 S : 100 mVrms = 0 dB 0.8 80 0.6 60 0.4 40 0.2 20 0 0 S/N1 N : no-input THD2 (Vin = 500 mVrms, f = 1 kHz) 6 7 8 9 10 11 VCC (V) Rev.2.00 Jun 15, 2005 page 15 of 19 12 13 14 15 16 Vo (AF) (mVrms) S/N2 (dB) HA12181FP 60 120 S/N2 50 100 40 80 30 60 20 40 10 20 0 0 Vo (AF) Vin = 74 dBµ fc = 450 kHz fm = 1 kHZ m = 30% 6 7 8 9 10 11 12 13 14 15 16 14 15 16 NSR (dB) ICC (mA) VCC (V) 60 60 50 50 40 40 30 30 20 20 NSR (pulse input) ICC (no-input) 10 10 0 0 6 7 8 9 10 11 VCC (V) Rev.2.00 Jun 15, 2005 page 16 of 19 12 13 V pulse (mVp-p) HA12181FP 1.0 0.8 V pulse (Pulse input level at Gate on) 0.6 0.4 0.2 0 6 7 8 9 10 11 12 13 14 15 Vout (AF) (mVrms) THD1 (%) VCC (V) 0.5 100 Vout 0.4 80 0.3 60 0.2 40 0.1 20 VCC = 8.2 V Vin = 100 mVrms, f = 1 kHz THD1 0 0 -40 -20 0 20 40 Ta (°C) Rev.2.00 Jun 15, 2005 page 17 of 19 60 80 100 16 NSR (dB) ICC (mA) HA12181FP 60 60 VCC = 8.2 V 50 50 40 40 30 30 20 20 NSR (pulse input) ICC (no-input) 10 0 10 0 -40 -20 0 20 40 Ta (°C) Rev.2.00 Jun 15, 2005 page 18 of 19 60 80 100 HA12181FP Package Dimensions JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-A *1 Previous Code FP-16DA MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 9 bp c1 c HE *2 E b1 Index mark Reference Symbol Terminal cross section 1 Z *3 bp Nom Max D 10.06 10.5 E 5.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.20 0.34 0.42 0.50 2.20 A L1 b p b 1 A c A1 θ y L Detail F 0.22 0.27 0.20 1 θ 0° HE 7.50 8° 7.80 8.00 1.27 e x 0.12 y 0.15 0.80 Z 0.50 L L Rev.2.00 Jun 15, 2005 page 19 of 19 0.40 0.17 c 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 2.0