IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B

IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
512K x36 and 1024K x18 18Mb,
SYNCHRONOUS FLOW-THROUGH SRAM
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Burst sequence control using MODE input
Three chip enable option for simple depth
expansion and address pipelining
Common data inputs and data outputs
Auto Power-down during deselect
Single cycle deselect
Snooze MODE for reduced-power standby
JEDEC 100-pin QFP, 165-ball BGA and 119-ball
BGA packages
Power supply:
LF: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
VF: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)
VVF: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%)
JTAG Boundary Scan for BGA packages
Commercial, Industrial and Automotive
temperature support
Lead-free available
For leaded options, please contact ISSI
FAST ACCESS TIME
Symbol
Parameter
-6.5
-7.5
Units
tKQ
Clock Access
Time
6.5
7.5
ns
tKC
Cycle time
7.5
8.5
ns
Frequency
133
117
MHz
MAY 2015
DESCRIPTION
The 18Mb product family features high-speed, lowpower synchronous static RAMs designed to provide
burstable, high-performance memory for
communication and networking applications. The
IS61(64)LF/VF/VVF51236(32)B organized as 524,288
words by 36(32)bits. The IS61(64)LF/VF/VVF102418B
are organized as 1,048,576 words by 18 bits.
Fabricated with ISSI's advanced CMOS technology,
the device integrates a 2-bit burst counter, high-speed
SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass
through registers controlled by a positive-edgetriggered single clock input.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock input. Write cycles can
be one to four bytes wide as controlled by the write
control inputs.
Separate byte enables allow individual bytes to be
written. The byte write operation is performed by using
the byte write enable (/BWE) input combined with one
or more individual byte write signals (/BWx). In
addition, Global Write (/GW) is available for writing all
bytes at one time, regardless of the byte write controls.
Bursts can be initiated with either /ADSP (Address
Status Processor) or /ADSC (Address Status Cache
Controller) input pins. Subsequent burst addresses can
be generated internally and controlled by the /ADV
(burst address advance) input pin.
The mode pin is used to select the burst sequence
order. Linear burst is achieved when this pin is tied
LOW. Interleave burst is achieved when this pin is tied
HIGH or left floating
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
1
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
BLOCK DIAGRAM
E
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
2
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
PIN CONFIGURATION
512K x 36, 165-Ball BGA (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
7
8
9
10
11
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
A
A
NC
DQc
DQc
DQc
DQc
VSS
DQd
DQd
DQd
DQd
NC
NC
NC
/CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
/BWc
/BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
/BWb
/BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
/CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
A1*
A0*
/BWE
/GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
/ADSC
/OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
/ADV
/ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Bottom View
165-Ball, 13 mm x 15mm BGA
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
Symbol
CLK
A0,A1
A
/ADV
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
/BWx (x=a-d)
/GW
/OE
DQx
DQPx
TCK,TDI,
TDO,TMS
ZZ
NC
VDD
VDDQ
VSS
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Global Write Enable
Output Enable
Data Inputs/Outputs
Parity Data I/O
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
3
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
512K x 32, 165-Ball BGA (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
MODE
A
A
NC
DQc
DQc
DQc
DQc
VSS
DQd
DQd
DQd
DQd
NC
NC
NC
/CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
/BWc
/BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
/BWb
/BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
/CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
A1*
A0*
/BWE
/GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
/ADSC
/OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
/ADV
/ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
NC
NC
NC
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
NC
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Bottom View
165-Ball, 13 mm x 15mm BGA
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
Symbol
CLK
A0,A1
A
/ADV
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
/BWx (x=a-d)
/GW
/OE
DQx
DQPx
TCK,TDI,
TDO,TMS
ZZ
NC
VDD
VDDQ
VSS
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Global Write Enable
Output Enable
Data Inputs/Outputs
Parity Data I/O
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
4
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
1024K x 18, 165-Ball BGA (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
MODE
A
A
NC
DQb
DQb
DQb
DQb
VSS
NC
NC
NC
NC
NC
NC
NC
/CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
/BWb
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
NC
/BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
/CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
A1*
A0*
/BWE
/GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
/ADSC
/OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
/ADV
/ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
A0,A1
A
/ADV
Bottom View
165-Ball, 13 mm x 15mm BGA
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
/BWx (x=a-b)
/GW
/OE
DQx
DQPx
TCK,TDI,
TDO,TMS
ZZ
NC
VDD
VDDQ
VSS
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Global Write Enable
Output Enable
Data Inputs/Outputs
Parity Data I/O
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
5
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
512K x 36, 119-Ball BGA (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
2
3
VDDQ
NC
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
NC
VDDQ
A
A
A
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
NC
TMS
A
A
A
VSS
VSS
VSS
/BWc
VSS
NC
VSS
/BWd
VSS
VSS
VSS
MODE
A
TDI
4
/ADSP
/ADSC
VDD
NC
/CE
/OE
/ADV
/GW
VDD
CLK
NC
/BWE
A1*
A0*
VDD
A
TCK
5
6
7
A
A
A
VSS
VSS
VSS
/BWb
VSS
NC
VSS
/BWa
VSS
VSS
VSS
NC
A
TDO
A
A
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
VDDQ
NC
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
ZZ
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
A0,A1
A
/ADV
Bottom View
119-Ball, 14 mm x 22 mm BGA
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
/ADSP
/ADSC
MODE
/CE
/BWE
/BWx (x=a-d)
/GW
/OE
DQx
DQPx
TCK,TDI,
TDO,TMS
ZZ
NC
VDD
VDDQ
VSS
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Global Write Enable
Output Enable
Data Inputs/Outputs
Parity Data I/O
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
6
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
512K x 32, 119-Ball BGA (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
2
3
VDDQ
NC
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
NC
VDDQ
A
A
A
NC
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
NC
A
NC
TMS
A
A
A
VSS
VSS
VSS
/BWc
VSS
NC
VSS
/BWd
VSS
VSS
VSS
MODE
A
TDI
4
/ADSP
/ADSC
VDD
NC
/CE
/OE
/ADV
/GW
VDD
CLK
NC
/BWE
A1*
A0*
VDD
A
TCK
5
6
7
A
A
A
VSS
VSS
VSS
/BWb
VSS
NC
VSS
/BWa
VSS
VSS
VSS
NC
A
TDO
A
A
A
NC
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
NC
A
NC
NC
VDDQ
NC
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
ZZ
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
A0,A1
A
/ADV
Bottom View
119-Ball, 14 mm x 22 mm BGA
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
/ADSP
/ADSC
MODE
/CE
/BWE
/BWx (x=a-d)
/GW
/OE
DQx
TCK,TDI,
TDO,TMS
ZZ
NC
VDD
VDDQ
VSS
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Global Write Enable
Output Enable
Data Inputs/Outputs
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
7
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
1024K x 18, 119-Ball BGA (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
2
3
VDDQ
NC
NC
DQb
NC
VDDQ
NC
DQb
VDDQ
NC
DQb
VDDQ
DQb
NC
NC
NC
VDDQ
A
A
A
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
A
TMS
A
A
A
VSS
VSS
VSS
/BWb
VSS
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
TDI
4
/ADSP
/ADSC
VDD
NC
/CE
/OE
/ADV
/GW
VDD
CLK
NC
/BWE
A1*
A0*
VDD
NC
TCK
5
6
7
A
A
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
/BWa
VSS
VSS
VSS
NC
A
TDO
A
A
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
A
NC
VDDQ
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
DQa
NC
ZZ
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
A0,A1
A
/ADV
Bottom View
119-Ball, 14 mm x 22 mm BGA
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
/ADSP
/ADSC
MODE
/CE
/BWE
/BWx (x=a-b)
/GW
/OE
DQx
DQPx
TCK,TDI,
TDO,TMS
ZZ
NC
VDD
VDDQ
VSS
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Global Write Enable
Output Enable
Data Inputs/Outputs
Parity Data I/O
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
8
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
/CE
CE2
/BWd
/BWc
/BWb
/BWa
/CE2
VDD
VSS
CLK
/GW
/BWE
/OE
/ADSC
/ADSP
/ADV
A
A
512K x 36, 100PIN QFP (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
512K x 36
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
A0,A1
A
/ADV
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
/BWx (x=a-d)
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
Symbol
/GW
/OE
DQx
DQPx
ZZ
NC
VDD
VDDQ
VSS
Pin Name
Global Write Enable
Output Enable
Data Inputs/Outputs
Parity Data I/O
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
9
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
/CE
CE2
/BWd
/BWc
/BWb
/BWa
/CE2
VDD
VSS
CLK
/GW
/BWE
/OE
/ADSC
/ADSP
/ADV
A
A
512K x 32, 100PIN QFP (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
512K x 32
NC
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
NC
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
NC
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
A0,A1
A
/ADV
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
/BWx (x=a-d)
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
Symbol
/GW
/OE
DQx
ZZ
NC
VDD
VDDQ
VSS
Pin Name
Global Write Enable
Output Enable
Data Inputs/Outputs
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
10
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
/CE
CE2
NC
NC
/BWb
/BWa
/CE2
VDD
VSS
CLK
/GW
/BWE
/OE
/ADSC
/ADSP
/ADV
A
A
1024K x 18, 100PIN
QFP (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1024K x 18
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
A0,A1
A
/ADV
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
/BWx (x=a-b)
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
Symbol
/GW
/OE
DQx
DQPx
ZZ
NC
VDD
VDDQ
VSS
Pin Name
Global Write Enable
Output Enable
Data Inputs/Outputs
Parity Data I/O
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
11
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
TRUTH TABLE
SYNCHRONOUS TRUTH TABLE
OPERATION
ADDRESS
/CE
/CE2
CE2
ZZ
/ADSP
/ADSC
/ADV
/WRITE
/OE
CLK
DQ
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Snooze Mode, Power-Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
H
X
X
L
X
L
X
X
X
L-H
High-Z
None
L
X
L
L
L
X
X
X
X
L-H
High-Z
None
L
H
X
L
L
X
X
X
X
L-H
High-Z
None
L
X
L
L
H
L
X
X
X
L-H
High-Z
None
L
H
X
L
H
L
X
X
X
L-H
High-Z
None
X
X
X
H
X
X
X
X
X
X
High-Z
External
L
L
H
L
L
X
X
X
L
L-H
Q
External
L
L
H
L
L
X
X
X
H
L-H
High-Z
External
L
L
H
L
H
L
X
L
X
L-H
D
External
L
L
H
L
H
L
X
H
L
L-H
Q
External
L
L
H
L
H
L
X
H
H
L-H
High-Z
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Next
X
X
X
L
H
H
L
H
H
L-H
High-Z
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Next
H
X
X
L
X
H
L
H
H
L-H
High-Z
Next
X
X
X
L
H
H
L
L
X
L-H
D
Next
H
X
X
L
X
H
L
L
X
L-H
D
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Current
X
X
X
L
H
H
H
H
H
L-H
High-Z
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Current
H
X
X
L
X
H
H
H
H
L-H
High-Z
Current
X
X
X
L
H
H
H
L
X
L-H
D
Current
H
X
X
L
X
H
H
L
X
L-H
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (/BWa-d) and /BWE are LOW or /GW is LOW. /WRITE = H for all /BWx, /BWE, /GW HIGH.
3. /BWa enables WRITEs to DQa’s and DQPa. /BWb enables WRITEs to DQb’s and DQPb. /BWc enables WRITEs to DQc’s and DQPc. /BWd enables
WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except /OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, /OE must be HIGH before the input data setup time and held HIGH during the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. /ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and
/BWE LOW or /GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
12
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
PARTIAL TRUTH TABLE
Operation
READ
READ
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ALL BYTEs
/GW
/BWE
/BWa
/BWb
/BWc
/BWd
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
X
X
H
L
H
H
H
L
X
X
H
H
L
H
H
L
X
X
H
H
H
L
H
L
X
X
H
H
H
H
L
L
X
Notes:
1.
X means "Don't Care".
2.
All inputs in this table must beet setup and hold time around the rising edge of CLK.
ADDRESS SEQUENCE IN BURST MODE
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC)
External Address
1st Burst Address
2nd Burst Address
A1 A0
A1 A0
A1 A0
00
01
10
01
00
11
10
11
00
11
10
01
3rd Burst Address
A1 A0
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = Vss )
0,0
A1', A0' = 1,1
0,1
1,0
Power Up Sequence
VDDQ → VDD1 → I/O Pins2
Notes:
1. VDD can be applied at the same time as VDDQ
2. Applying I/O inputs is recommended after VDDQ is stable. The inputs of the I/O pins can be applied at the same time as VDDQ as long as Vih (level of I/O
pins) is lower than VDDQ.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
13
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Tstg
Storage Temperature
Pd
Power Dissipation
Iout
Output Current (per I/O)
Vin, Vout Voltage Relative to Vss for I/O Pins
Vin
Voltage Relative to Vss for Address and
Control Inputs
LF Value
–65 to +150
1.6
20
–0.5 to VDDQ+0.3
–0.3 to VDD+0.5
VF/VVF Value
–65 to +150
1.6
20
–0.5 to VDDQ + 0.3
–0.3 to VDD + 0.3
Unit
°C
W
mA
V
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to
avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE (IS61LFx)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
-40°C to +85°C
Automotive
-40°C to +125°C
VDD
3.3V ± 5%
3.3V ± 5%
3.3V ± 5%
VDDQ
3.3V / 2.5V ± 5%
3.3V / 2.5V ± 5%
3.3V / 2.5V ± 5%
VDD
VDDQ
VDD
1.8V ± 5%
1.8V ± 5%
VDDQ
1.8V ± 5%
1.8V ± 5%
OPERATING RANGE (IS61VFx)
Range
Commercial
Industrial
Automotive
Ambient Temperature
0°C to +70°C
-40°C to +85°C
OPERATING RANGE (IS61VVFx)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
-40°C to +85°C
Automotive
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
*Please contact ISSI
*Please contact ISSI
14
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS (Over operating temperature range)
Symbol
Parameter
Voh
Output HIGH
Voltage
Vol
Vih
Vil
Ili
Ilo
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Leakage
Current
Output Leakage
Current
Test Conditions
3.3V
Min.
Max.
Min
.
2.4
—
—
2.5V
1.8V
Unit
Max.
Min.
Max.
2.0
—
VDDQ
-0.4
—
V
0.4
—
0.4
—
0.4
V
2.0
VDD
+0.3
1.7
0.7* VDD
–0.3
0.8
–
0.3
VDD
+0.3
0.7
–0.3
Vss≤Vin≤ VDD
–1
1
–1
1
–1
1
μA
Vss≤Vout≤ VDD,/OE=Vih
–1
1
–1
1
–1
1
μA
Ioh=-4.0 mA(3.3V)
Ioh=–1.0 mA(2.5V,1.8V)
Iol=8.0 mA(3.3V)
Iol=1.0 mA(2.5V,1.8V)
VDD
+0.3
0.3*
VDD
V
V
Notes:
1. All voltages referenced to ground.
2. Overshoot:
3.3V and 2.5V: Vih (AC) ≤ VDD + 1.5V (Pulse width less than tkc /2)
1.8V: Vih (AC) ≤ VDD + 0.5V (Pulse width less than tkc /2)
3. Undershoot:
3.3V and 2.5V: Vil (AC) ≥ -1.5V (Pulse width less than tkc /2)
1.8V: Vil (AC) ≥ -0.5V (Pulse width less than tkc /2)
4. MODE pin has an internal pull-up and should be tied to VDD or Vss . It exhibits ±100μA maximum leakage current when tied to ≤Vss+0.2V or ≥ VDDQ–
0.2V.
5. ZZ pin has an internal pull-down and should be tied to VDD or Vss . It exhibits ±100μA maximum leakage current when tied to ≤Vss+0.2V or ≥ VDD–0.2V.
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol
Icc
Isb
Isb1
Com.
Ind.
-6.5
Max
x18
x36
240
240
260
260
-7.5
Max
x18
x36
190
190
210
210
Device Deselected, VDD = Max.,All Inputs ≤ Vil
or ≥ Vih,ZZ ≤ Vil, f = Max.
Com.
80
80
70
70
Ind.
90
90
80
80
Device Deselected, VDD = Max.,Vin ≤ Vss +
0.2V or ≥ VDD – 0.2V,f = 0
Com.
60
60
60
60
Ind.
70
70
70
70
Parameter
Test Conditions
Temp.
range
AC Operating,
Supply Current
Standby
Current TTL
Input
Standby
Current CMOS
Input
Device Selected, OE = Vih, ZZ ≤ Vil,All Inputs
≤ 0.2V or ≥ VDD – 0.2V,Cycle Time ≥ tkc min.
Unit
mA
mA
mA
Note:
1.
Power-up assumes a linear ramp from 0V to VDD (min) within 200ms. During this time Vih < VDD and VDDQ < VDD
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
15
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
CAPACITANCE
Symbol
Cin
Cout
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, VDD = 3.3V.
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-6.5
-7.5
Symbol
Parameter
Min.
Max.
Min.
fmax
Clock Frequency
—
133
—
tkc
Cycle Time
7.5
—
8.5
tkh
Clock High Time
2.2
—
2.5
tkl
Clock Low Time
2.2
—
2.5
tkq
Clock Access Time
—
6.5
—
(2)
tkqx
Clock High to Output Invalid
2.5
—
2.5
tkqlz(2,3)
Clock High to Output Low-Z
2.5
—
2.5
tkqhz(2,3)
Clock High to Output High-Z
—
3.8
—
toeq
Output Enable to Output Valid
—
3.2
—
toelz(2,3)
Output Enable to Output Low-Z
0
—
0
toehz(2,3)
Output Disable to Output High-Z
—
3.5
—
tas
Address Setup Time
1.5
—
1.5
tws
Read/Write Setup Time
1.5
—
1.5
tces
Chip Enable Setup Time
1.5
—
1.5
tse
Clock Enable Setup Time
1.5
—
1.5
tadvs
Address Advance Setup Time
1.5
—
1.5
tds
Data Setup Time
1.5
—
1.5
tah
Address Hold Time
0.5
—
0.5
the
Clock Enable Hold Time
0.5
—
0.5
twh
Write Hold Time
0.5
—
0.5
tceh
Chip Enable Hold Time
0.5
—
0.5
tadvh
Address Advance Hold Time
0.5
—
0.5
tdh
Data Hold Time
0.5
—
0.5
Max.
6
8
Max.
117
—
—
—
7.5
—
—
4.0
3.4
—
3.5
—
—
—
—
—
—
—
—
—
—
—
—
Unit
pF
pF
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
16
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
3.3V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing and Reference Level
VTT
VLOAD
R1, R2
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
1.5V
3.3V
317Ω, 351Ω
See Figures 1 and 2
2.5V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing and Reference Level
VTT
VLOAD
R1, R2
Output Load
Unit
0V to 2.5V
1.5 ns
1.25V
1.25V
2.5V
1667Ω, 1538Ω
See Figures 1 and 2
1.8V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing and Reference Level
VTT
VLOAD
R1, R2
Output Load
Unit
0V to 1.8V
1.5 ns
0.9V
0.9V
1.8V
1KΩ, 1KΩ
See Figures 1 and 2
I/O OUTPUT LOAD EQUIVALENT
R1
VLOAD
OUTPUT
ZO =50Ω
OUTPUT
50Ω
R2
5 pF
Including
jig and
scope
VTT
Figure1
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
Figure2
17
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
READ/WRITE CYCLE TIMING
tKC
CLK
tKH
tSS
tSH
/ADSP is blocked by /CE inactive
tKL
/ADSP
tSS
tSH
/ADSC
/ADV
tAS
tAH
Address
RD1
WR1
tWS
tWH
tWS
tWH
RD2
RD3
/GW
/BWE
tWH
tWS
WR1
/BWd-/BWa
tCES
tCEH
tCES
tCEH
tCES
tCEH
/CE Masks /ADSP
/CE
CE2 and /CE2 only sampled with /ADSP or /ADSC
CE2
Unselected with /CE2
/CE2
tOELZ
tOEQ
/OE
tOEHZ
tKQX
DATAOUT
High-Z
tKQLZ
High-Z
tKQLZ
tKQ
1a
tKQ
DATAIN
2a
2b
tKQX
2c
2d
tKQHZ
1a
High-Z
Single Read
Flow-through
tDH
tDS
Single Write
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Burst Read
Unselected
18
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
WRITE CYCLE TIMING
tKC
CLK
tSS
tKH
tSH
/ADSP is blocked by /CE inactive
tKL
/ADSP
/ADSC initiates Write
/ADSC
/ADV must be inactive for /ADSP Write
tAVS
tAVH
/ADV
tAS
Address
tAH
WR1
WR2
tWS
tWH
tWS
tWH
tWS
tWH
WR3
/GW
/BWE
/BWx
tWS
WR1
tCES
tCEH
tCES
tCEH
tCES
tCEH
tWH
WR2
WR3
/CE Masks /ADSP
/CE
Unselected with CE2
CE2 and /CE2 only sampled with /ADSP or/ ADSC
CE2
/CE2
/OE
DATAOUT
High-Z
tDS
DATAIN
High-Z
tDH
1a
Single Write
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Rev. B
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/BW1-/BW4 only are applied to first cycle of WR2
2a
2b
Burst Write
2c
2d
3a
Write
Unselected
19
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
ISB2
Current during SNOOZE MODE
tPDS
tPUS
tZZI
tRZZI
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
ZZ ≥ Vih
Temperature Range
Com.
Ind.
Auto.
—
—
—
—
Min.
—
—
—
—
2
—
0
Max.
40
50
TBD
2
—
2
—
Unit
mA
cycle
cycle
cycle
ns
SLEEP MODE TIMING
CLK
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All Inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs (Q)
High-Z
Don't Care
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IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and printed
circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core.
In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register, boundary
scan register, bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST signal
is not required
Disabling the JTAG feature
The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be left disconnected. They
may alternately be connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up, the
device will come up in a reset state, which will not interfere with device operation.
Test Access Port Signal List:
1. Test Clock (TCK)
This signal uses VDD as a power supply. The test clock is used only with the TAP controller. All inputs are captured
on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
2. Test Mode Select (TMS)
This signal uses VDD as a power supply. The TMS input is used to send commands to the TAP controller and is
sampled on the rising edge of TCK.
3. Test Data-In (TDI)
This signal uses VDD as a power supply. The TDI input is used to serially input test instructions and information into
the registers and can be connected to the input of any of the registers. The register between TDI and TDO is
chosen by the instruction that is loaded into the TAP instruction register. TDI is connected to the most significant
bit (MSB) of any register. For more information regarding instruction register loading, please see the TAP
Controller State Diagram.
4. Test Data-Out (TDO)
This signal uses VDDQ as a power supply. The TDO output ball is used to serially clock test instructions and data
out from the registers. The TDO output driver is only active during the Shift-IR and Shift-DR TAP controller states.
In all other states, the TDO pin is in a High-Z state. The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register. For more information, please see the TAP Controller
State Diagram.
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IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
TAP Controller State and Block Diagram
...
Boundary Scan Register (75
90 bits)
Bypass Register (1 bit)
TDI
Identification Register (32 bits)
TDO
Instruction Register (3 bits)
Control Signals
TMS
TAP Controller
TCK
TAP Controller State Machine
1
Test Logic
Reset
0
Run Test
Idle
1
0
Select DR
1
Select IR
0
1
0
1
Capture
DR
0
Capture
IR
0
0
Shift DR
1
1
Exit1 DR
Exit1 IR
0
0
0
Pause DR
1
Exit2 DR
0
Exit2 IR
1
1
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0
Pause IR
1
Update
DR
0
Shift IR
1
1
1
0
1
Update IR
0
1
0
22
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM
test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.
1. Instruction Register
This register is loaded during the update-IR state of the TAP controller. At power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a
reset state as described in the previous section. When the TAP controller is in the capture-IR state, the two LSBs
are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path.
2. Bypass Register
The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to
be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS
instruction is executed.
3. Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the SRAM. Several balls are
also included in the scan register to reserved balls. The boundary scan register is loaded with the contents of the
SRAM Input and Output ring when the TAP controller is in the capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the shift-DR state. Each bit corresponds to one of the balls on
the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
4. Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE
command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out
when the TAP controller is in the shift-DR state.
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan
Bit Size
3
1
32
90
TAP Instruction Set
Many instructions are possible with an eight-bit instruction register and all valid combinations are listed in the TAP
Instruction Code Table. All other instruction codes that are not listed on this table are reserved and should not be
used. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the
TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the
Update-IR state.
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IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
1. EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-scan register
cells at output balls are used to apply a test vector, while those at input balls capture test results. Typically, the first
test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the
PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output driver is turned on, and the
PRELOAD data is driven onto the output balls.
2. IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the
device when the TAP controller enters the shift-DR state. The IDCODE instruction is loaded into the instruction
register upon power-up or whenever the TAP controller is given a test logic reset state.
3. SAMPLE Z
If the SAMPLE-Z instruction is loaded in the instruction register, all SRAM outputs are forced to an inactive drive
state (high-Z), moving the TAP controller into the capture-DR state loads the data in the SRAMs input into the
boundary scan register, and the boundary scan register is connected between TDI and TDO when the TAP
controller is moved to the shift-DR state.
4. SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the
capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the
SRAM clock operates significantly faster. Because there is a large difference between the clock frequencies, it is
possible that during the capture-DR state, an input or output will undergo a transition. The TAP may then try to
capture a signal while in transition. This will not harm the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible. To ensure that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture
setup plus hold time. The SRAM clock input might not be captured correctly if there is no way in a design to stop
(or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is an issue, it is still possible to capture all other
signals and simply ignore the value of the CLK captured in the boundary scan register. Once the data is captured,
it is possible to shift out the data by putting the TAP into the shift-DR state. This places the boundary scan register
between the TDI and TDO balls.
6. BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a shift-DR state, the
bypass register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected together on a board.
7. PRIVATE
Do not use these instructions. They are reserved for future use and engineering mode.
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IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
JTAG DC Operating Characteristics
(Over the Operating Temperature Range, 2.5V and 3.3V Option)
Parameter
Symbol
Min
JTAG Input High Voltage
VIH1
2.0
JTAG Input Low Voltage
VIL1
–0.3
JTAG Output High Voltage
VOH1
1.7
JTAG Output Low Voltage
VOL1
JTAG Output High Voltage
VOH2
2.1
JTAG Output Low Voltage
VOL2
JTAG Input Leakage Current
ILIJTAG
-10
JTAG Output Leakage Current
ILOJTAG
-10
Max
VDD+0.3
0.7
0.7
0.2
+10
+10
Units
V
V
V
V
V
V
µA
µA
Max
TBD
TBD
TBD
TBD
TBD
TBD
Units
V
V
V
V
µA
µA
Notes:
1.
All voltages referenced to VSS (GND); All JTAG inputs and outputs are LVTTL-compatible.
JTAG DC Operating Characteristics
(Over the Operating Temperature Range, 1.8V Option)
Parameter
Symbol
Min
JTAG Input High Voltage
VIH1
TBD
JTAG Input Low Voltage
VIL1
TBD
JTAG Output High Voltage
VOH1
TBD
JTAG Output Low Voltage
VOL1
TBD
JTAG Input Leakage Current
ILIJTAG
TBD
JTAG Output Leakage Current
ILOJTAG
TBD
Notes:
1.
All voltages referenced to VSS (GND); All JTAG inputs and outputs are LVTTL-compatible.
JTAG AC Test Conditions
(Over the Operating Temperature Range)
Parameter
Input Pulse High Level
Input Pulse Low Level
Input rise and fall time
Test load termination supply voltage
Input and Output Timing Reference
Level
Symbol
VIH1
VIL1
TR1
VREF
VREF
Notes
|IOH1|=2mA
IOL1=2mA
|IOH2|=100µA
IOL2=100µA
0 ≤ Vin ≤ VDD
0 ≤ Vout ≤ VDD
Notes
1.8V Option 2.5V Option 3.3V Option
TBD
2.5
3.0
TBD
0
0
TBD
1.5
1.5
TBD
1.25
1.5
TBD
1.25
1.5
Units
V
V
ns
V
V
TAP Output Load Equivalent
VREF
50Ω
Output
50Ω
20pF
Test Comparator
VREF
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IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
JTAG AC Characteristics
(Over the Operating Temperature Range)
Parameter
Symbol
TCK cycle time
tTHTH
TCK high pulse width
tTHTL
TCK low pulse width
tTLTH
TMS Setup
tMVTH
TMS Hold
tTHMX
TDI Setup
tDVTH
TDI Hold
tTHDX
TCK Low to Valid Data
tTLOV
Min
100
40
40
10
10
10
10
–
Max
–
–
–
–
–
–
–
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
JTAG Timing Diagram
tTHTL
tTHTH
tTLTH
TCK
tMVTH
tTHMX
tDVTH
tTHDX
TMS
TDI
tTLOV
TDO
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IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Instruction Set
Code
Instruction
TDO Output
Notes
000
001
010
EXTEST
IDCODE
SAMPLE-Z
Boundary Scan Register
32-bit Identification Register
Boundary Scan Register
2, 6
011
PRIVATE
Do Not Use
5
100
SAMPLE(/PRELOAD)
Boundary Scan Register
4
101
PRIVATE
Do Not Use
5
110
PRIVATE
Do Not Use
5
111
BYPASS
Bypass Register
3
1, 2
Notes:
1. Places DQs in high-Z in order to sample all input data, regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the
shift-DR state.
4. SAMPLE instruction does not place DQs in high-Z.
5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality.
6. This EXTEST is not IEEE 1149.1-compliant. By default, it places DQ in high-Z. If the internal register on the scan chain is set high, DQ will be updated
with information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR state after EXTEST is loaded. The value of
the internal register can be changed during SAMPLE and EXTEST only.
ID Register Definition
Instruction Field
Revision Number (31:28)
Device Depth (27:23)
Device Width (22:18)
ISSI Device ID (17:12)
ISSI JEDEC ID (11:1)
ID Register Presence (0)
Description
Reserved for version number.
512K x 36
xxxx
1024K x 18
xxxx
Defines depth of SRAM. 512K or
1024K
Defines Width of the SRAM. x36 or
x18
Reserved for future use.
00111
01000
00100
00011
xxxxxx
xxxxxx
Allows unique identification of
SRAM vendor.
Indicate the presence of an ID
register.
00001010101
00001010101
1
1
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IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Boundary Scan Order
(TBA – 119 BGA)
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
X36
Bump ID
N6
N7
N10
P11
P8
R8
R9
P9
P10
R10
R11
H11
N11
M11
L11
M10
L10
K11
J11
K10
J10
H9
H10
G11
F11
G10
E11
D11
F10
E10
D10
C11
A11
B11
A10
B10
A9
B9
C10
A8
165 BGA
Signal
A9
NC
NC
A8
A18
A17
A16
A15
A14
A13
A12
ZZ
DQa0
DQa1
DQa2
DQa3
DQa4
DQa5
DQa6
DQa7
DQa8
NC
NC
DQb8
DQb7
DQb6
DQb5
DQb4
DQb3
DQb2
DQb1
DQb0
NC
NC
A11
A10
/ADV
/ADSP
NC
/ADSC
Continued on next page
X18
Bump ID
N6
N7
N10
P11
P8
R8
R9
P9
P10
R10
R11
H11
N11
M11
L11
M10
L10
K11
J11
K10
J10
H9
H10
G11
F11
G10
E11
D11
C11
E10
D10
F10
A11
B11
A10
B10
A9
B9
C10
A8
Signal
A9
NC
NC
A8
A18
A17
A16
A15
A14
A13
A12
ZZ
NC
NC
NC
DQa8
DQa7
NC
NC
DQa6
DQa5
NC
NC
DQa4
DQa3
NC
DQa2
DQa1
DQa0
NC
NC
NC
A19
NC
A11
A10
/ADV
/ADSP
NC
/ADSC
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IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
165 BGA
X36
X18
Bump ID
Signal
Bump ID
B8
/OE
B8
A7
/BWE
A7
B7
/GW
B7
B6
CLK
B6
A6
/CE2
A6
B5
/Bwa
B5
A5
/Bwb
A5
A4
/Bwc
A4
B4
/Bwd
B4
B3
CE2
B3
A3
/CE1
A3
A2
A7
A2
B2
A6
B2
C2
NC
C2
B1
NC
B1
A1
NC
A1
C1
DQc0
C1
D1
DQc1
D1
E1
DQc2
E1
D2
DQc3
D2
E2
DQc4
E2
F1
DQc5
F1
G1
DQc6
G1
F2
DQc7
F2
G2
DQc8
G2
H1
NC
H1
H2
NC
H2
H3
NC
H3
J1
DQd8
J1
K1
DQd7
K1
J2
DQd6
J2
L1
DQd5
L1
M1
DQd4
M1
K2
DQd3
N1
L2
DQd2
L2
M2
DQd1
M2
N1
DQd0
K2
N2
NC
N2
P1
NC
P1
R1
MODE
R1
Signal
/OE
/BWE
/GW
CLK
/CE2
/Bwa
NC
/Bwb
NC
CE2
/CE1
A7
A6
NC
NC
NC
NC
NC
NC
DQb8
DQb7
NC
NC
DQb6
DQb5
NC
NC
NC
DQb4
DQb3
NC
DQb2
DQb1
DQb0
NC
NC
NC
NC
NC
MODE
Continue on next page
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IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Bit #
81
82
83
84
85
86
87
88
89
90
165 BGA
X36
X18
Bump ID
Signal
Bump ID
Signal
R2
NC
R2
NC
P3
A5
P3
A5
R3
A4
R3
A4
P2
NC
P2
NC
P4
A2
P4
A2
R4
A3
R4
A3
N5
NC
N5
NC
P6
A1
P6
A1
R6
A0
R6
A0
*
Int
*
Int
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IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
VDD
Speed
6.5ns
VDD=3.3V, VDDQ=2.5V/3.3V
7.5ns
VDD =2.5V, VDDQ=2.5V
VDD=1.8V, VDDQ=1.8V
X36
IS61LF51236B-6.5TQ
IS61LF51236B-6.5B3
IS61LF51236B-6.5B2
IS61LF51236B-6.5TQL
IS61LF51236B-6.5B3L
IS61LF51236B-6.5B2L
IS61LF51236B-7.5TQ
IS61LF51236B-7.5B3
IS61LF51236B-7.5B2
IS61LF51236B-7.5TQL
IS61LF51236B-7.5B3L
IS61LF51236B-7.5B2L
X18
IS61LF102418B-6.5TQ
IS61LF102418B-6.5B3
IS61LF102418B-6.5B2
IS61LF102418B-6.5TQL
IS61LF102418B-6.5B3L
IS61LF102418B-6.5B2L
IS61LF102418B-7.5TQ
IS61LF102418B-7.5B3
IS61LF102418B-7.5B2
IS61LF102418B-7.5TQL
IS61LF102418B-7.5B3L
IS61LF102418B-7.5B2L
6.5ns
*Please contact ISSI Marketing
7.5ns
*Please contact ISSI Marketing
6.5ns
*Please contact ISSI Marketing
7.5ns
*Please contact ISSI Marketing
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
Package
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
31
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
VDD
Speed
6.5ns
VDDQ=3.3V, VDDQ=2.5V/3.3V
7.5ns
VDD=2.5V, VDDQ=2.5V
VDD=1.8V, VDDQ=1.8V
6.5ns
7.5ns
6.5ns
7.5ns
X36
X18
IS61LF51236B-6.5TQI
IS61LF102418B-6.5TQI
IS61LF51236B-6.5B3I
IS61LF102418B-6.5B3I
IS61LF51236B-6.5B2I
IS61LF102418B-6.5B2I
IS61LF51236B-6.5TQLI IS61LF102418B-6.5TQLI
IS61LF51236B-6.5B3LI IS61LF102418B-6.5B3LI
IS61LF51236B-6.5B2LI IS61LF102418B-6.5B2LI
IS61LF51236B-7.5TQI
IS61LF102418B-7.5TQI
IS61LF51236B-7.5B3I
IS61LF102418B-7.5B3I
IS61LF51236B-7.5B2I
IS61LF102418B-7.5B2I
IS61LF51236B-7.5TQLI IS61LF102418B-7.5TQLI
IS61LF51236B-7.5B3LI IS61LF102418B-7.5B3LI
IS61LF51236B-7.5B2LI IS61LF102418B-7.5B2LI
*Please contact ISSI Marketing
*Please contact ISSI Marketing
*Please contact ISSI Marketing
*Please contact ISSI Marketing
Package
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
Automotive Range: -40°C to +125°C
VDD
Speed
6.5ns
VDD=3.3V, VDDQ=2.5V/3.3V
7.5ns
X36
IS64LF51236B-6.5TQLA3
IS64LF51236B-6.5B3LA3
IS64LF51236B-6.5B2LA3
IS64LF51236B-7.5TQLA3
IS64LF51236B-7.5B3LA3
IS64LF51236B-7.5B2LA3
Package
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
*For all other voltages and options in automotive grade, please contact ISSI.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
32
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
33
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
34
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/07/2015
35