IS61lPD51236a

IS61VPD51236a IS61VPD102418a
IS61lPD51236a IS61LPD102418a
512K x 36, 1024K x 18
18Mb SYNCHRONOUS PIPELINED,
DOUBLE CYCLE DESELECT STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Double cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
LPD: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5%
VPD: Vdd 2.5V + 5%, Vddq 2.5V + 5%
• JEDEC 100-Pin TQFP and 165-pin PBGA package
• Lead-free available
JULY 2008
DESCRIPTION
The ISSI IS61LPD/VPD51236A and IS61LPD/VPD102418A are high-speed, low-power synchronous
static RAMs designed to provide burstable, high-performance
memory for communication and networking applications.
The IS61LPD/VPD51236A is organized as 524,288 words
by 36 bits, and the IS61LPD/VPD102418A is organized
as 1,048,576 words by 18 bits. Fabricated with ISSI's
advanced CMOS technology, the device integrates a
2-bit burst counter, high-speed SRAM core, and highdrive capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte write
enable (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left
floating.
FAST ACCESS TIME
Symbol
tkq
tkc
Parameter
Clock Access Time
Cycle Time
Frequency
250
2.6
4
250
200
3.1
5
200
Units
ns
ns
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
1
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
BLOCK DIAGRAM
MODE
Q0
CLK
CLK
A0
BINARY
COUNTER
ADSC
ADSP
A
Q1
CE
ADV
A1
A0'
A1'
512Kx36;
1024Kx18
MEMORY ARRAY
CLR
19/20
D
Q
17/18
19/20
ADDRESS
REGISTER
CE
CLK
36,
or 18
GW
BWE
BWd
(x36)
D
36,
or 18
Q
DQd
BYTE WRITE
REGISTERS
CLK
BWc
(x36)
D
DQc Q
BYTE WRITE
REGISTERS
CLK
D
BWb
(x36/x18)
Q
DQb
BYTE WRITE
REGISTERS
CLK
BWa
(x36/x18)
D
DQa Q
BYTE WRITE
REGISTERS
CLK
CE
CE2
CE2
4
D
Q
ENABLE
REGISTER
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
36,
or 18
DQa - DQd
OE
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
165-pin BGA
165-Ball, 13x15 mm BGA
1mm Ball Pitch, 11x15 Ball Array
Bottom view
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
3
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
165 PBGA PACKAGE PIN CONFIGURATION
512K x 36 (TOP VIEW)
A
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE
BWc
BWb
CE2
BWE
ADSC
ADV
A
NC
NC
DQPb
B
NC
A
CE2
BWd
BWa
CLK
GW
OE
ADSP
A
C
DQPc
NC
Vddq
Vss
Vss
Vss
Vss
Vss
Vddq
D
DQc
DQc
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
NC
DQb
E
DQc
DQc
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQb
DQb
F
DQc
DQc
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQb
DQb
G
DQc
DQc
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQb
DQb
H
NC
Vss
NC
Vdd
Vss
Vss
Vss
Vdd
NC
NC
ZZ
J
DQd
DQd
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
DQa
K
DQd
DQd
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
DQa
L
DQd
DQd
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
DQa
M
DQd
DQd
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
DQa
N
DQPd
NC
Vddq
Vss
NC
A
Vss
Vss
Vddq
NC
DQPa
DQb
P
NC
NC
A
A
TDI
A1*
TDO
A
A
A
A
R
MODE
NC
A
A
TMS
A0*
TCK
A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
Symbol
Pin Name
A
Address Inputs
BWE
Byte Write Enable
A0, A1
Synchronous Burst Address Inputs
OE
Output Enable
ADV
ADSP
Synchronous Burst Address
Advance
Address Status Processor
ZZ
Power Sleep Mode
MODE
Burst Sequence Selection
Address Status Controller
GW
Global Write Enable
CLK
Synchronous Clock
CE
Synchronous Chip Select
CE2
Synchronous Chip Select
CE2
Synchronous Chip Select
TCK, TDO
TMS, TDI
NC
DQa-DQb
DQPa-Pb
Vdd
Vddq
JTAG Pins
ADSC
BWx (x=a,b,c,d) Synchronous Byte Write Controls
4
Vss
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Power Supply
Output Power Supply Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
165 PBGA PACKAGE PIN CONFIGURATION
1M x 18 (TOP VIEW)
A
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE
BWb
NC
CE2
BWE
ADSC
ADV
A
A
NC
DQPa
B
NC
A
CE2
NC
BWa
CLK
GW
OE
ADSP
A
C
NC
NC
Vddq
Vss
Vss
Vss
Vss
Vss
Vddq
D
NC
DQb
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
NC
NC
E
NC
DQb
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
NC
DQa
F
NC
DQb
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
NC
DQa
G
NC
DQb
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
NC
DQa
H
NC
Vss
NC
Vdd
Vss
Vss
Vss
Vdd
NC
NC
ZZ
J
DQb
NC
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
NC
K
DQb
NC
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
NC
L
DQb
NC
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
NC
M
DQb
NC
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
NC
N
DQPb
NC
Vddq
Vss
NC
A
Vss
Vss
Vddq
NC
NC
P
NC
NC
A
A
TDI
A1*
TDO
A
A
A
A
R
MODE
NC
A
A
TMS
A0*
TCK
A
A
A
A
DQa
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
Symbol Pin Name
BWE
Byte Write Enable
A0, A1
ADV
ADSP
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
OE
Output Enable
ZZ
Power Sleep Mode
MODE
Burst Sequence Selection
ADSC
GW
Address Status Controller
Global Write Enable
JTAG Pins
CLK
CE
CE2
CE2
Synchronous Clock
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
TCK, TDO
TMS, TDI
NC
DQa-DQb
DQPa-Pb
Vdd
Vddq
BWx (x=a,b)
Synchronous Byte Write Controls
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
Vss
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Power Supply
Output Power Supply Ground
5
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
PIN CONFIGURATION
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin TQFP
DQPc
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
512K x 36
PIN DESCRIPTIONS
A0, A1
A
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
ADSC Synchronous Controller Address Status
ADSP Synchronous Processor Address Status
ADV Synchronous Burst Address Advance
BWa-BWd
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
CE, CE2 Synchronous Chip Enable
CE2
CLK Synchronous Chip Enable
Synchronous Clock
6
DQa-DQd
Synchronous Data Input/Output
DQPa-DQPd
Parity Data Input/Output
GW
MODE Synchronous Global Write Enable
Burst Sequence Mode Selection
OE
Output Enable
Vdd
3.3V/2.5V Power Supply
Vddq
Isolated Output Buffer Supply:
3.3V/2.5V
Ground
Snooze Enable
Vss
ZZ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
PIN CONFIGURATION
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
1024K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
Synchronous Controller Address Status
ADSC ADSP Synchronous Processor Address Status
ADV Synchronous Burst Address Advance
BWa-BWb
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
CE, CE2, CE2 Synchronous Chip Enable
CLK Synchronous Clock
DQa-DQb
Synchronous Data Input/Output
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
DQPa-DQPb
Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8
GW
MODE Synchronous Global Write Enable
Burst Sequence Mode Selection
OE
Vdd
Vddq
Vss
ZZ
Output Enable
3.3V/2.5V Power Supply
Isolated Output Buffer Supply:
3.3V/2.5V
Ground
Snooze Enable
7
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
TRUTH TABLE(1-8) (3CE option)
OPERATIONADDRESS CE
Deselect Cycle, Power-Down
None
H
Deselect Cycle, Power-Down
None
L
Deselect Cycle, Power-Down
None
L
Deselect Cycle, Power-Down
None
L
Deselect Cycle, Power-Down
None
L
Snooze Mode, Power-Down
None
X
Read Cycle, Begin Burst
External
L
Read Cycle, Begin Burst
External
L
Write Cycle, Begin Burst
External
L
Read Cycle, Begin Burst
External
L
Read Cycle, Begin Burst
External
L
Read Cycle, Continue Burst
Next
X
Read Cycle, Continue Burst
Next
X
Read Cycle, Continue Burst
Next
H
Read Cycle, Continue Burst
Next
H
Write Cycle, Continue Burst
Next
X
Write Cycle, Continue Burst
Next
H
Read Cycle, Suspend Burst
Current
X
Read Cycle, Suspend Burst
Current
X
Read Cycle, Suspend Burst
Current
H
Read Cycle, Suspend Burst
Current
H
Write Cycle, Suspend Burst
Current
X
Write Cycle, Suspend Burst
Current
H
CE2
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP ADSC ADV WRITE OE
X
L
X
X
X
L
X
X
X
X
L
X
X
X
X
H
L
X
X
X
H
L
X
X
X
X
X
X
X
X
L
X
X
X
L
L
X
X
X
H
H
L
X
L
X
H
L
X
H
L
H
L
X
H
H
H
H
L
H
L
H
H
L
H
H
X
H
L
H
L
X
H
L
H
H
H
H
L
L
X
X
H
L
L
X
H
H
H
H
L
H
H
H
H
H
X
H
H
H
L
X
H
H
H
H
H
H
H
L
X
X
H
H
L
X
CLK
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW.
WRITE = H for all BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and
DQPd are only available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
TRUTH TABLE(1-8) (1CE option)
NEXT CYCLEADDRESS
Deselected
None
Read, Begin Burst
External
Read, Begin Burst
External
Write, Begin Burst
External
Read, Begin Burst
External
Read, Begin Burst
External
Read, Continue Burst
Next
Read, Continue Burst
Next
Read, Continue Burst
Next
Read, Continue Burst
Next
Write, Continue Burst
Next
Write, Continue Burst
Next
Read, Suspend Burst
Current
Read, Suspend Burst
Current
Read, Suspend Burst
Current
Read, Suspend Burst
Current
Write, Suspend Burst
Current
Write, Suspend Burst
Current
CE
H
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
ADSP
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSC
L
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WRITE
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
DQ
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW.
WRITE = H for all BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and
DQPd are only available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
GW
H
H
H
H
L
BWE
H
L
L
L
X
BWa
X
H
L
L
X
BWb
X
H
H
L
X
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
BWc
X
H
H
L
X
BWd
X
H
H
L
X
9
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or No Connect)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0A1 A0A1 A0A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = Vss)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Tstg
Pd
Iout
Vin, Vout
Vin
Vdd
Parameter
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to Vss for I/O Pins
Voltage Relative to Vss for for Address and Control Inputs
Voltage on Vdd Supply Relative to Vss
Value
Unit
–55 to +150
°C
1.6
W
100
mA
–0.5 to Vddq + 0.5 V
–0.5 to Vdd + 0.5
V
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
OPERATING RANGE (IS61LPDXXXXX)
RangeAmbient Temperature
Commercial
0°C to +70°C
Vdd
3.3V + 5%
Vddq
3.3 / 2.5V + 5%
Industrial
3.3V + 5%
3.3 / 2.5V + 5%
RangeAmbient Temperature
Commercial
0°C to +70°C
Vdd
2.5V + 5%
Vddq
2.5V + 5%
Industrial
2.5V + 5%
2.5V + 5%
–40°C to +85°C
OPERATING RANGE (IS61VPDXXXXX)
–40°C to +85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V
Symbol Parameter
Test Conditions
Min.
Max.
Voh
Output HIGH Voltage
Ioh = –4.0 mA (3.3V)
2.4
—
Ioh = –1.0 mA (2.5V)
Vol
Output LOW Voltage
Iol = 8.0 mA (3.3V)
—
0.4
Iol = 1.0 mA (2.5V)
Vih
Input HIGH Voltage 2.0 Vdd + 0.3
Vil
Input LOW Voltage
-0.3
0.8
Ili
Input Leakage Current Vss ≤ Vin ≤ Vdd(1)
-5
5
Ilo
Output Leakage Current Vss ≤ Vout ≤ Vddq, -5
5
OE = Vih
2.5V
Min.
Max.
2.0
—
—
Unit
V 0.4
V 1.7 Vdd + 0.3
-0.3
0.7
-5
5
-5
5
V
V
µA
µA
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Icc
AC Operating
Supply Current
Isb
Standby Current
TTL Input
Isbi
Standby Current
CMOS Input
Isb2
Sleep Mode
-250
MAX
Test Conditions
Temp. range x18
x36
Device Selected, Com.
450
450
OE = Vih, ZZ ≤ Vil, Ind.
500
500
All Inputs ≤ 0.2V or ≥ Vdd – 0.2V,
Cycle Time ≥ tkc min.
Device Deselected, Com.
150
150
Vdd = Max.,
Ind.
150
150
All Inputs ≤ Vil or ≥ Vih,
ZZ ≤ Vil, f = Max.
Device Deselected,
Com.
110
110
Vdd = Max.,
Ind.
125
125
Vin ≤ Vss + 0.2V or ≥Vdd – 0.2V
f=0
ZZ>Vih Com.
60
60
Ind.
75
75
-200
MAX
x18
x36
425
425
475
475
Unit
mA
150
150
150
150
mA
110
125
110
125
mA
60
75
60
75
mA
Note:
1. MODE pin has an internal pullup and should be tied to Vdd or Vss. It exhibits ±100µA maximum leakage current when tied to ≤
Vss + 0.2V or ≥ Vdd – 0.2V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
11
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
CAPACITANCE(1,2)
Symbol
Cin
Cout
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
317 Ω
3.3V
ZO = 50Ω
Output
Buffer
50Ω
1.5V
Figure 1
12
OUTPUT
5 pF
Including
jig and
scope
351 Ω
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
2.5V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 2.5V
1.5 ns
1.25V
See Figures 3 and 4
2.5 I/O OUTPUT LOAD EQUIVALENT
317 Ω
2.5V
ZO = 50Ω
Output
Buffer
50Ω
1.25V
Figure 3
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
OUTPUT
5 pF
Including
jig and
scope
351 Ω
Figure 4
13
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
fmax
Clock Frequency
tkc
Cycle Time
tkh
Clock High Time
tkl
Clock Low Time
tkq
Clock Access Time (2)
tkqx Clock High to Output Invalid
tkqlz(2,3) Clock High to Output Low-Z
tkqhz(2,3) Clock High to Output High-Z
toeq
Output Enable to Output Valid
(2,3)
toelz Output Enable to Output Low-Z
toehz(2,3) Output Disable to Output High-Z
tas
tws
tces
tavs
tds
tah
twh
tceh
tavh
tdh
tpds
tpus
Address Setup Time
Read/Write Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Data Setup Time
Address Hold Time
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
Data Hold Time
ZZ High to Power Down
ZZ Low to Power Down
-250
Min.
Max.
—
250
4.0
—
1.7
—
1.7
—
—
2.6
0.8
—
0.8
—
—
2.6
—
2.6
0
—
—
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
—
—
2.6
—
—
—
—
—
—
—
—
—
—
2
2
-200
Min.
—
5
2
2
—
1.5
1
—
—
0
Max.
200
—
—
—
3.1
—
—
3.0
3.1
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
—
—
3.0
—
—
—
—
—
—
—
—
—
—
2
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
Note:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
READ/WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
tSS
tSH
ADSC initiate read
ADSC
tAVH
tAVS
Suspend Burst
ADV
tAS
Address
tAH
RD1
RD3
RD2
tWS
tWH
tWS
tWH
GW
BWE
BWx
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE Masks ADSP
CE
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
CE2
CE2
tOEHZ
tOEQ
OE
DATAOUT
tKQX
tOEQX
tOELZ
High-Z
1a
2a
2b
2c
2d
tKQLZ
3a
tKQHZ
tKQ
DATAIN
High-Z
Pipelined Read
Single Read
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
Burst Read
Unselected
15
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
ADSC initiate Write
ADSC
ADV must be inactive for ADSP Write tAVS
tAVH
ADV
tAS
Address
tAH
WR1
WR3
WR2
tWS
tWH
tWS
tWH
tWS
tWH
GW
BWE
WR1
BWx
tCES
tCEH
tCES
tCEH
tCES
tCEH
tWS
tWH
WR2
WR3
CE Masks ADSP
CE
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
CE2
CE2
OE
DATAOUT
High-Z
tDS
DATAIN
High-Z
Single Write
16
tDH
1a
BW4-BW1 only are applied to first cycle of WR2
2a
2b
2c
2d
Burst Write
3a
Write
Unselected
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
Isb2
tpds
tpus
tzzi
trzzi
Parameter
Current during SNOOZE MODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
Conditions
ZZ ≥ Vih
Min.
—
—
2
—
0
Max.
60
2
—
2
—
Unit
mA
cycle
cycle
cycle
ns
SNOOZE MODE TIMING
CLK
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All Inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
17
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Access Port (TAP) - Test Clock
The IS61LPD/VPD51236A and IS61LPD/VPD102418A
have a serial boundary scan Test Access Port (TAP) in the
PBGA package only. (The TQFP package not available.)
This port operates in accordance with IEEE Standard
1149.1-1900, but does not include all functions required
for full 1149.1 compliance. These functions from the IEEE
specification are excluded because they place added delay
in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the
performance of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC standard 2.5V I/O
logic levels.
The test clock is only used with the TAP controller. All inputs
are captured on the rising edge of TCK and outputs are
driven from the falling edge of TCK.
Disabling the JTAG Feature
The SRAM can operate without using the JTAG feature.
To disable the TAP controller, TCK must be tied LOW
(Vss) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be disconnected. They may
alternately be connected to Vdd through a pull-up resistor.
TDO should be left disconnected. On power-up, the device
will start in a reset state which will not interfere with the
device operation.
Test Mode Select (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The pin
is internally pulled up, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information to the
registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the
instruction loaded into the TAP instruction register. For
information on instruction register loading, see the TAP
Controller State Diagram. TDI is internally pulled up and
can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB)
on any register.
tap controller block diagram
0
Bypass Register
2
1
0
Instruction Register
TDI
Selection Circuitry
31 30 29
Selection Circuitry
. . .
2
1
0
2
1
0
TDO
Identification Register
x
. . . . .
Boundary Scan Register*
TCK
TMS
18
TAP CONTROLLER
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK
and TDO is connected to the Least Significant Bit (LSB)
of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (Vdd) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins
and allow data to be scanned into and out of the SRAM
test circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on
the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed
between the TDI and TDO pins. (See TAP Controller Block
Diagram) At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset
state as previously described.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass reg-
ister is set LOW (Vss) when the BYPASS instruction is
executed.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 75-bit-long
register and the x18 configuration also has a 75-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved
to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE-Z instructions can be used to capture the
contents of the Input and Output ring.
The Boundary Scan Order tables show the order in which
the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan
Bit Size (x18)
3
1
32
75
Bit Size (x36)
3
1
32
75
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE
is hardwired into the SRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has vendor code and other information described in the
Identification Register Definitions table.
Identification Register Definitions
Instruction Field
Revision Number (31:28) Device Depth (27:23)
Device Width (22:18)
ISSI Device ID (17:12)
ISSI JEDEC ID (11:1)
ID Register Presence (0)
Description
Reserved for version number.
Defines depth of SRAM. 512K or 1M
Defines with of the SRAM. x36 or x18
Reserved for future use.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
512K x 36
xxxx
00111
00100
xxxxx
00011010101
1
1M x 18
xxxx
01000
00011
xxxxx
00011010101
1
19
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
TAP Instruction Set
SAMPLE/PRELOAD
Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as RESERVED
and should not be used and the other five instructions are
described below. The TAP controller used in this SRAM
is not fully compliant with the 1149.1 convention because
some mandatory instructions are not fully implemented.
The TAP controller cannot be used to load address, data or
control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD; instead it performs a capture of the Inputs and
Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI
and TDO. During this state, instructions are shifted from
the instruction register through the TDI and TDO pins. To
execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction.The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant. When the
SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock
runs more than an order of magnitude faster. Because of
the clock frequency differences, it is possible that during
the Capture-DR state, an input or output will under-go a
transition. The TAP may attempt a signal capture while in
transition (metastable state).The device will not be harmed,
but there is no guarantee of the value that will be captured
or repeatable results.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up
plus hold times (tcs and tch). To insure that the SRAM clock
input is captured correctly, designs need a way to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction.
If this is not an issue, it is possible to capture all other
signals and simply ignore the value of the CLK and CLK
captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the UpdateDR state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with
all 0s. Because EXTEST is not implemented in the TAP
controller, this device is not 1149.1 standard compliant.
The TAP controller recognizes an all-0 instruction. When an
EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is a difference between the instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST
places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit
code to be loaded into the instruction register. It also places
the instruction register between the TDI and TDO pins
and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a
test logic reset state.
Bypass
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state,
the bypass register is placed between the TDI and TDO
pins. The advantage of the BYPASS instruction is that it
shortens the boundary scan path when multiple devices
are connected together on a board.
SAMPLE-Z
Reserved
The SAMPLE-Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also places
all SRAM outputs into a High-Z state.
These instructions are not implemented but are reserved
for future use. Do not use these instructions.
20
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
Instruction Codes
Code
000
Instruction
EXTEST
001
IDCODE
010
SAMPLE-Z
011
100
RESERVED
SAMPLE/PRELOAD
101
110 111
RESERVED
RESERVED
BYPASS
Description
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
Run Test/Idle
1
Select DR
0
0
1
1
1
Capture DR
0
Shift DR
1
Exit1 DR
0
Select IR
0
1
Exit1 IR
0
Pause DR
0
1
0
1
Exit2 DR
1
Update DR
0
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
Capture IR
0
Shift IR
1
0
Pause IR
1
0
1
1
0
1
0
Exit2 IR
1
Update IR
0
21
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
TAP Electrical Characteristics Over the Operating Range(1,2)
Symbol
Voh1
Voh2
Vol1
Vol2
Vih
Vil
Ix
Parameter
Test Conditions
Output HIGH Voltage
Ioh = –2.0 mA
Output HIGH Voltage
Ioh = –100 µA
Output LOW Voltage
Iol = 2.0 mA
Output LOW Voltage
Iol = 100 µA
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Vss ≤ V I ≤ Vddq
Min.
1.7
2.1
—
—
1.7
–0.3
–5
Max.
—
—
0.7
0.2
Vdd +0.3
0.7
5
Units
V
V
V
V
V
V
mA
Max.
—
10
—
—
—
—
—
—
—
—
20
—
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: Vih (AC) ≤ Vdd +1.5V for t ≤ ttcyc/2,
Undershoot:Vil (AC) ≤ 0.5V for t ≤ ttcyc/2,
Power-up: Vih < 2.6V and Vdd < 2.4V and Vddq < 1.4V for t < 200 ms.
TAP AC ELECTRICAL CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
ttcyc
ftf
tth
ttl
ttmss
ttdis
tcs
ttmsh
ttdih
tch
ttdov
ttdox
Parameter
TCK Clock cycle time
TCK Clock frequency
TCK Clock HIGH
TCK Clock LOW
TMS setup to TCK Clock Rise
TDI setup to TCK Clock Rise
Capture setup to TCK Rise
TMS hold after TCK Clock Rise TDI Hold after Clock Rise
Capture hold after Clock Rise
TCK LOW to TDO valid
TCK LOW to TDO invalid
Min.
100
—
40
40
10
10
10
10
10
10
—
0
Notes:
1. Both tcs and tch refer to the set-up and hold time latching data requirements from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tr/tf = 1 ns.
22
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
TAP Output Load Equivalent
TAP AC TEST CONDITIONS (2.5/3.3V)
Input pulse levels
0 to 2.5V/0 to 3.0V
Input rise and fall times
1ns
Input timing reference levels
1.25V/1.5V
Output reference levels
1.25V/1.5V
Test load termination supply voltage
1.25V/1.5V
50Ω
1.25V
TDO
20 pF
Z0 = 50Ω
GND
Tap timing
1
2
tTHTH
3
4
5
6
tTLTH
TCK
tTHTL
tMVTH tTHMX
TMS
tDVTH tTHDX
TDI
tTLOV
TDO
tTLOX
DON'T CARE
UNDEFINED
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
23
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
165 PBGA Boundary Scan Order (x 36)
Signal Bump
Bit # Name ID
1
MODE 1R
2
A
6N
3
A
11P
4
A
8P
5
A
8R
6
A
9R
7
A
9P
8
A
10P
9
A
10R
10
A
11R
11
ZZ
11H
12
DQa 11N
13
DQa 11M
14
DQa 11L
15
DQa 11K
16
DQa 11J
17
DQa 10M
18
DQa 10L
19
DQa 10K
20
DQa 10J
24
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Signal Bump
Name
ID
Bit #
DQb
11G
41
DQb
11F
42
DQb
11E
43
DQb
11D
44
DQb
10G
45
DQb
10F
46
DQb
10E
47
DQb
10D
48
DQb
11C
49
NC
11A
50
A
10A
51
A
10B
52
ADV
9A
53
ADSP
9B
54
ADSC
8A
55
OE
8B
56
BWE
7A
57
GW
7B
58
CLK
6B
59
NC
11B
60
Signal
Name
NC
CE2
BWa
BWb
BWc
BWd
CE2
CE
A
A
NC
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
Bump
ID
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Signal
Name
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
A
A
A
A
A1
A0
Bump
ID
1J
1K
1L
1M
2J
2K
2L
2M
1N
3P
3R
4R
4P
6P
6R
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
165 PBGA Boundary Scan Order (x 18)
Signal Bump
Bit # Name ID
1
MODE 1R
2
A
6N
3
A
11P
4
A
8P
5
A
8R
6
A
9R
7
A
9P
8
A
10P
9
A
10R
10
A
11R
11
ZZ
11H
12
NC
11N
13
NC
11M
14
NC
11L
15
NC
11K
16
NC
11J
17
DQa 10M
18
DQa 10L
19
DQa 10K
20
DQa 10J
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Signal Bump
Name
ID
Bit #
DQa
11G
41
DQa
11F
42
DQa
11E
43
DQa
11D
44
DQa
11C
45
NC
10F
46
NC
10E
47
NC
10D
48
NC
10G
49
A
11A
50
A
10A
51
A
10B
52
ADV
9A
53
ADSP
9B
54
ADSC
8A
55
OE
8B
56
BWE
7A
57
GW
7B
58
CLK
6B
59
NC
11B
60
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
Signal
Name
NC
CE2
BWa
NC
BWb
NC
CE2
CE
A
A
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
Bump
ID
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Signal
Name
DQb
DQb
DQb
DQb
DQb
NC
NC
NC
NC
A
A
A
A
A1
A0
Bump
ID
1J
1K
1L
1M
1N
2K
2L
2M
2J
3P
3R
4R
4P
6P
6R
25
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O)
Commercial Range: 0°C to +70°C
Configuration
512Kx36
Frequency
Order Part Number
Package
250
200
IS61LPD51236A-250TQ
IS61LPD51236A-250B3
IS61LPD51236A-200TQ
IS61LPD51236A-200B3
100 TQFP
165 PBGA
100 TQFP
165 PBGA
250
200
IS61LPD102418A-250TQ
IS61LPD102418A-250B3
IS61LPD102418A-200TQ
IS61LPD102418A-200B3
100 TQFP
165 PBGA
100 TQFP
165 PBGA
1Mx18
Industrial Range: -40°C to +85°C
Configuration
512Kx36
Frequency
Order Part Number
Package
250
200
IS61LPD51236A-250TQI
IS61LPD51236A-250B3I
IS61LPD51236A-250B3LI
IS61LPD51236A-200TQI
IS61LPD51236A-200TQLI
IS61LPD51236A-200B3I
100 TQFP
165 PBGA
165 PBGA, Lead-free
100 TQFP
100 TQFP, Lead-free
165 PBGA
250
200
IS61LPD102418A-250TQI
IS61LPD102418A-250B3I
IS61LPD102418A-200TQI
IS61LPD102418A-200B3I
100 TQFP
165 PBGA
100 TQFP
165 PBGA
1Mx18
26
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
ORDERING INFORMATION (2.5V core/2.5V I/O)
Commercial Range: 0°C to +70°C
Configuration
512Kx36
Frequency
Order Part Number
Package
250
200
IS61VPD51236A-250TQ
IS61VPD51236A-250B3
IS61VPD51236A-200TQ
IS61VPD51236A-200B3
100 TQFP
165 PBGA
100 TQFP
165 PBGA
250
200
IS61VPD102418A-250TQ
IS61VPD102418A-250B3
IS61VPD102418A-200TQ
IS61VPD102418A-200B3
100 TQFP
165 PBGA
100 TQFP
165 PBGA
Frequency
Order Part Number
Package
250
200
IS61VPD51236A-250TQI
IS61VPD51236A-250B3I
IS61VPD51236A-200TQI
IS61VPD51236A-200B3I
100 TQFP
165 PBGA
100 TQFP
165 PBGA
250
200
IS61VPD102418A-250TQI
IS61VPD102418A-250B3I
IS61VPD102418A-200TQI
IS61VPD102418A-200B3I
100 TQFP
165 PBGA
100 TQFP
165 PBGA
1Mx18
Industrial Range: -40°C to +85°C
Configuration
512Kx36
1Mx18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
27
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
D
D1
E
E1
N
L1
L
C
1
e
SEATING
PLANE
A2
A
b
A1
Millimeters
Min
Max
Thin Quad Flat Pack (TQ)
Inches
Millimeters
Min
Max
Min
Max
Symbol
Ref. Std.
No. Leads (N)
100
A
—
1.60
—
0.063
A1
0.05 0.15
0.002 0.006
A2
1.35 1.45
0.053 0.057
b
0.22 0.38
0.009 0.015
D
21.90 22.10
0.862 0.870
D1
19.90 20.10
0.783 0.791
E
15.90 16.10
0.626 0.634
E1
13.90 14.10
0.547 0.555
e
0.65 BSC
0.026 BSC
L
0.45 0.75
0.018 0.030
L1
1.00 REF.
0.039 REF.
o
o
C
0
7
0o
7o
128
—
1.60
0.05 0.15
1.35 1.45
0.17 0.27
21.80 22.20
19.90 20.10
15.80 16.20
13.90 14.10
0.50 BSC
0.45 0.75
1.00 REF.
0o
7o
Integrated Silicon Solution, Inc. — 1-800-379-4774
PK13197LQ Rev. D 05/08/03
Inches
Min
Max
—
0.063
0.002 0.006
0.053 0.057
0.007 0.011
0.858 0.874
0.783 0.791
0.622 0.638
0.547 0.555
0.020 BSC
0.018 0.030
0.039 REF.
0o
7o
Notes:
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
3. Controlling dimension:
millimeters.
PACKAGING INFORMATION
Ball Grid Array
Package Code: B (165-pin)
BOTTOM VIEW
TOP VIEW
A1 CORNER
1
2
3
4
A1 CORNER
φ b (165X)
5
6
7
8
9
10
11 10
11
9
8
7
6
5
4
3
2
1
A
A
B
B
C
C
D
D
E
E
e
F
F
G
G
D D1
H
H
J
J
K
K
L
L
M
M
N
N
P
P
R
R
E1
E
A2
e
A
A1
BGA - 13mm x 15mm
MILLIMETERS
Sym.
Min.
N0.
Leads
Nom. Max.
Notes:
1. Controlling dimensions are in millimeters.
INCHES
Min.
165
Nom. Max.
165
A
—
—
1.20
—
A1
0.25
0.33
0.40
0.010
—
0.047
0.013 0.016
A2
—
0.79
—
—
0.031
—
D
14.90
15.00
15.10
0.587
0.591
0.594
D1
13.90
14.00
14.10
0.547
0.551
0.555
E
12.90
13.00
13.10
0.508
0.512
0.516
E1
9.90
10.00
10.10
0.390
0.394
0.398
e
—
1.00
—
—
0.039
—
b
0.40
0.45
0.50
0.016
0.018
0.020
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
06/11/03