IS31FL3191 1-CHANNEL FUN LED DRIVER July 2015 GENERAL DESCRIPTION IS31FL3191 is a 1-channel fun LED driver which has One Shot Programming mode and PWM Control mode for LED lighting effects. The maximum output current can be adjusted in 5 levels (5mA~42mA). In PWM Control mode, the PWM duty cycle of each output can be independently programmed and controlled in 256 steps to simplify color mixing. In One Shot Programming mode, the timing characteristics for output current - current rising, holding, falling and off time, can be adjusted individually. IS31FL3191 is available in UTQFN-9 (1.5mm × 1.5mm). It operates from 2.7V to 5.5V over the temperature range of -40°C to +85°C. FEATURES Independently controlled automatic and semiautomatic breathing system-free pre-established pattern I2C interface, automatic address increment function Independently controlled output of 256 PWM steps 2.7V to 5.5V supply voltage 5 levels programmable output current Over-temperature protection Operating temperature TA = −40°C ~ +85°C UTQFN-9 (1.5mm × 1.5mm) package APPLICATIONS Mobile phones and other hand-held devices for LED display LED in home appliances TYPICAL APPLICATION CIRCUIT Figure 1 Typical Application Circuit Note: The IC should be placed far away from the mobile antenna in order to prevent the EMI. Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 1 IS31FL3191 PIN CONFIGURATION Package Pin Configuration (Top View) UTQFN-9 PIN DESCRIPTION No. Pin Description A1 SDB Shutdown the chip when pulled to low. A2, A3 NC No connection. B1, B2 GND Ground. B3 SDA I2C serial data. C1 OUT Current source output. C2 VCC Power supply. C3 SCL I2C serial clock. Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 2 IS31FL3191 ORDERING INFORMATION Industrial Range: -40°C to +85°C Order Part No. Package QTY/Reel IS31FL3191-UTLS2-TR UTQFN-9, Lead-free 3000 Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 3 IS31FL3191 ABSOLUTE MAXIMUM RATINGS Supply voltage, VCC Voltage at any input pin Maximum junction temperature, TJMAX Operating temperature range, TA Storage temperature range, TSTG ESD (HBM) ESD (CDM) -0.3V ~ +6.0V -0.3V ~ VCC+0.3V 150°C -40°C ~ +85°C -65°C ~ +150°C 8kV 1kV Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS TA = -40°C ~ +85°C, VCC = 5V, unless otherwise noted. Typical value are TA = 25°C. Symbol Parameter Condition VCC Supply voltage ICC Quiescent power supply current VSDB = VCC ISD Shutdown current VSDB = 0V or software shutdown IOUT Output current PWM Control mode, VDS = 0.5V PWM Register(04h) = 0xFF Current Register(03h) = 0x00 VHR Current sink headroom voltage IOUT = 42mA Min. Typ. 2.7 Max. Unit 5.5 V 0.36 mA 2.5 μA 42 (Note 1) mA 500 mV Logic Electrical Characteristics (SDA, SCL, SDB, AD) VIL Logic “0” input voltage VCC = 2.7V VIH Logic “1” input voltage VCC = 5.5V IIL Logic “0” input current 5 (Note 2) nA IIH Logic “1” input current 5 (Note 2) nA Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 0.4 1.4 V V 4 IS31FL3191 DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 3) Symbol Parameter Condition Min. Typ. Max. Unit 400 kHz fSCL Serial-Clock frequency tBUF Bus free time between a STOP and a START condition 1.3 μs tHD, STA Hold time (repeated) START condition 0.6 μs tSU, STA Repeated START condition setup time 0.6 μs tSU, STO STOP condition setup time 0.6 μs tHD, DAT Data hold time tSU, DAT Data setup time 100 ns tLOW SCL clock low period 1.3 μs tHIGH SCL clock high period 0.7 μs 0.9 μs tR Rise time of both SDA and SCL signals, receiving (Note 4) 20+0.1Cb 300 ns tF Fall time of both SDA and SCL signals, receiving (Note 4) 20+0.1Cb 300 ns Note 1: IOUT represents the average output current. See PWM Register, Table 7. Note 2: The LED is on. Note 3: Guaranteed by design. Note 4: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 × VCC and 0.7 × VCC. Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 5 IS31FL3191 DETAILED DESCRIPTION The 8-bit chip address is sent next, most significant bit first. Each address bit must be stable while the SCL level is high. I2C INTERFACE The IS31FL3191 uses a serial bus, which conforms to the I2C protocol, to control the chip’s functions with two wires: SCL and SDA. The IS31FL3191 has a 7-bit slave address (A7:A1), followed by the R/W bit, A0. Since IS31FL3191 only supports write operations, A0 must always be “0”. After the last bit of the chip address is sent, the master checks for the IS31FL3191’s acknowledge. The master releases the SDA line high (through a pull-up resistor). Then the master sends an SCL pulse. If the IS31FL3191 has received the address correctly, then it holds the SDA line low during the SCL pulse. If the SDA line is not low, then the master should send a “STOP” signal (discussed later) and abort the transfer. The complete slave address is: Table 1 Slave Address (Write only): Bit A7:A1 A0 Value 1101 000 0 Following acknowledge of IS31FL3191, the register address byte is sent, most significant bit first. IS31FL3191 must generate another acknowledge indicating that the register address has been received. The SCL line is uni-directional. The SDA line is bi-directional (open-collector) with a pull-up resistor (typically 4.7kΩ). The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the microcontroller and the slave is the IS31FL3191. Then 8-bit of data byte are sent next, most significant bit first. Each data bit should be valid while the SCL level is stable high. After the data byte is sent, the IS31FL3191 must generate another acknowledge to indicate that the data was received. The timing diagram for the I2C is shown in Figure 2. The SDA is latched in on the stable high level of the SCL. When there is no interface activity, the SDA line should be held high. The “STOP” signal ends the transfer. To signal “STOP”, the SDA signal goes high while the SCL signal is high. The “START” signal is generated by lowering the SDA signal while the SCL signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own chip address. To write multiple bytes of data into IS31FL3191, load the address of the data register that the first data byte is intended for. During the IS31FL3191 acknowledge of receiving the data byte, the internal address pointer will increment by one. The next data byte sent to IS31FL3191 will be placed in the new address, and so on (Figure 5). Figure 2 ADDRESS AUTO INCREMENT Interface Timing Figure 3 Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 Bit Transfer 6 IS31FL3191 Writing to IS31FL3191 (Typical) Figure 4 Writing to IS31FL3191 (Automatic Address Increment) Figure 5 REGISTERS DEFINITIONS Table 2 Register Function Address Name Function Table Default 0000 0001 00h Shutdown Register Set software shutdown mode 3 01h Breathing Control Register Set the breathing function 4 02h LED Mode Register Set operation mode 5 03h Current Setting Register Set output current 6 04h PWM Register Channel PWM duty cycle data registers 7 07h PWM Update Register Load PWM Registers data - 0Ah T0 Register Set the T0 time 8 10h T1&T2 Register Set the T1&T2 time 9 16h T3&T4 Register Set the T3&T4 time 10 1Ch Time Update Register Load time registers’ data 1Dh LED Control Register OUT enable bit 2Fh Reset Register Reset all registers to default value Table 3 00h Shutdown Register Bit D7:D6 D5 D4:D1 D0 Name - EN - SSD Default 00 0 0000 1 The Shutdown Register sets software shutdown mode of IS31FL3191. Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 0000 0000 xxxx xxxx 0000 0000 - xxxx xxxx 11 0000 0001 - xxxx xxxx EN 0 1 Channel Control Channel disable Channel enable SSD 0 1 Software Shutdown Enable Normal operation Software shutdown mode 7 IS31FL3191 Table 7 04h PWM Register Table 4 01h Breathing Control Register Bit D7:D6 D5 D4 D3:D0 Bit D7:D0 Name - RM HT - Name PWM Default 00 0 0 0000 Default 0000 0000 The Breathing Control Register sets the breathing function. Ramping Mode Enable Disable Enable RM 0 1 I OUT Hold Time Selection Hold on T2 Hold on T4 HT 0 1 Table 5 02h LED Mode Register Bit D7:D6 D5 D4:D0 Name - LED - Default 00 0 00000 The LED Mode Register sets operation mode of IS31FL3191. LED 0 1 LED Mode Selection PWM Control Mode One Shot Programming Mode I MAX 7 D[n] * 2 n 256 n0 (1) Where D[n] stands for the individual bit value, 1 or 0, in location n. For example: if D7:D0 = 10110101, IOUT = IMAX (20+22+24+25+27)/256 IMAX is set by Current Setting Register. 07h PWM Update Register The data sent to the PWM Registers will be stored in temporary registers. A write operation of “0000 0000” value to the PWM Update Register is required to update the registers (04h). Table 8 0Ah T0 Register Table 6 03h Current Setting Register Bit D7:D5 D4:D2 D1:D0 Name - CS - Default 000 000 00 The Current Setting Register stores the maximum current setting, IMAX, for all of the LED output channels. CS 000 001 010 011 1xx The value in the PWM Registers modulate the LEDs in 256 steps. The value of the PWM Register decides the average output current. The average output current may be computed using the Formula (1): Current Setting 42mA 10mA 5mA 30mA 17.5mA Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 Bit D7:D4 D3:D0 Name T0 - Default 0000 0000 The T0 Registers set the T0 time in One Shot Programming mode. T0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Others T0 Setting 0s 0.13s 0.26s 0.52s 1.04s 2.08s 4.16s 8.32s 16.64s 33.28s 66.56s Unavailable 8 IS31FL3191 Table 9 10h T1&T2 Register Bit D7:D5 D4:D1 D0 Name T1 T2 - Default 000 0000 0 The T1&T2 Registers set the T1&T2 time in One Shot Programming mode. T1 000 001 010 011 100 101 110 111 T1 Setting 0.13s 0.26s 0.52s 1.04s 2.08s 4.16s 8.32s 16.64s T2 0000 0001 0010 0011 0100 0101 0110 0111 1000 Others T2 Setting 0s 0.13s 0.26s 0.52s 1.04s 2.08s 4.16s 8.32s 16.64s Unavailable T4 Setting 0s 0.13s 0.26s 0.52s 1.04s 2.08s 4.16s 8.32s 16.64s 33.28s 66.56s Unavailable 1Ch Time Update Register The data sent to the time registers will be stored in temporary registers. A write operation of “0000 0000” value to the Time Update Register is required to update the registers (0Ah, 10h, 16h). Table 11 1Dh LED Control Register Bit D7:D1 D0 Name - OUT Default 0000 000 1 The LED Control Registers store the on or off state of each channel LED. OUT 0 1 Table 10 16h T3&T4 Register Bit D7:D5 D4:D1 D0 Name T3 T4 - Default 000 0000 0 The T3&T4 Registers set the T3&T4 time in One Shot Programming mode. T3 000 001 010 011 100 101 110 111 T4 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Others LED State LED off LED on 2Fh Reset Register Once user writes “0000 0000” to the Reset Register, IS31FL3191 will reset all registers to their default value. On initial power-up, the IS31FL3191 registers are reset to their default values for a blank display. T3 Setting 0.13s 0.26s 0.52s 1.04s 2.08s 4.16s 8.32s 16.64s Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 9 IS31FL3191 FUNCTIONAL BLOCK DIAGRAM OSC Bandgap Reference Voltage VCC SDA SCL I2C Interface Digital Control Bias OUT PWM& Breath Control GND SDB Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 10 IS31FL3191 APPLICATION INFORMATION GENERAL DESCRIPTION SEMIAUTOMATIC BREATHING IS31FL3191 is a 1-channel LED driver with two-dimensional auto breathing and PWM Control mode. It can drive two individual LEDs. By setting the LED bits of the LED Mode Register (02h) to “1” and the RM bit of the Breathing Control Register (01h) to “1”, the ramping function is enabled. HT is the time select bit. When HT bit is set to “0”, T2 will be held forever, and the LED will remain at the programmed maximum intensity. When HT bit is set to “1”, T3 will continue and T4 will be held, causing the LED to complete one breathing cycle and then remain off. PWM CONTROL By setting the LED bits of the LED Mode Register (03h) to “0”, the IS31FL3191 will operate in PWM Control mode. The PWM Registers (04h) can modulate LED brightness of one channel with 256 steps. For example, if the data in PWM Register is “0000 0100”, then the PWM is the fourth step, with a duty cycle of 4/256. In PWM control mode, a new value must be written to the PWM registers to change the output PWM duty cycle. Writing new data continuously to the registers can modulate the brightness of the LEDs to achieve a breathing effect, blinking, or any other effects that the user defines. LED BREATHING CONTROL By setting the LED bits of the LED Mode Register (03h) to “1”, the IS31FL3191 will operate in One Shot Programming mode. In this mode, PWM Registers (04h) are unavailable and the LED intensity is automatically modulated in a breathing cycle, independently controlled by T0~T4. T0 is an offset time period which runs only once at the start of the cycle. The full cycle is T1 to T4 (Figure 6). Figure 6 SHUTDOWN MODE Shutdown mode can either be used as a means of reducing power consumption or generating a flashing display (repeatedly entering and leaving shutdown mode). During shutdown mode all registers retain their data. SOFTWARE SHUTDOWN By setting SSD bit of the Shutdown Register (00h) to “1”, the IS31FL3191 will operate in software shutdown mode, wherein they consume only 3.5μA (typ.) current. When the IS31FL3191 is in software shutdown mode, all current sources are switched off. HARDWARE SHUTDOWN The chip enters hardware shutdown mode when the SDB pin is pulled low, wherein they consume only 2.5μA (typ.) current. Breathing Timing Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 11 IS31FL3191 CLASSIFICATION REFLOW PROFILES Profile Feature Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 217°C 60-150 seconds Peak package body temperature (Tp)* Max 260°C Time (tp)** within 5°C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Figure 7 Classification Profile Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 12 IS31FL3191 PACKAGE INFORMATION UTQFN-9 Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 13 IS31FL3191 RECOMMENDED LAND PATTERN Note: 1. Land pattern complies to IPC-7351. 2. All dimensions in MM. 3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since land pattern design depends on many factors unknown (eg. user’s board manufacturing specs), user must determine suitability for use. Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 14 IS31FL3191 REVISION HISTORY Revision A B Detail Information Initial release 1. Update I2C writing figure 2. Add land pattern 3. Add ESD value 4. Add functional block Integrated Silicon Solution, Inc. – www.issi.com Rev. B, 07/10/2015 Date 2012.07.05 2015.07.10 15