IS42RM/SM32160C

IS42SM32160C
IS42RM32160C
16Mx32
512Mb Mobile Synchronous DRAM
FEATURES:
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access and precharge
• Programmable CAS latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8, and Full
Page
• Programmable Burst Sequence:
• Sequential and Interleave
• Auto Refresh (CBR)
• TCSR (Temperature Compensated Self Refresh)
• PASR (Partial Arrays Self Refresh): 1/16, 1/8,
1/4, 1/2, and Full
• Deep Power Down Mode (DPD)
• Driver Strength Control (DS): 1/4, 1/2, and Full
NOVEMBER 2010
DESCRIPTION:
ISSI's IS42SM/RM32160C is a 512Mb Mobile Synchronous DRAM configured as a quad 4M x32 DRAM.
It achieves high-speed data transfer using a pipeline
architecture with a synchronous interface. All inputs and
outputs signals are registered on the rising edge of the
clock input, CLK. The 512Mb SDRAM is internally configured by stacking two 256Mb, 16Mx16 devices. Each
of the 4M x32 banks is organized as 8192 rows by 512
columns by 32 bits.
KEY TIMING PARAMETERS
Parameter
-7
-75
Unit
CAS Latency = 3
7
7.5
ns
CAS Latency = 2
9.6
9.6
ns
CAS Latency = 3
143
133
Mhz
CAS Latency = 2
104
104
Mhz
CAS Latency = 3
5.4
5.4
ns
CAS Latency = 2
7
7
ns
CLK Cycle Time
CLK Frequency
OPTIONS:
• Configuration: 16Mx32
• Power Supply:
IS42SMxxx - Vdd/Vddq = 3.3V
IS42RMxxx - Vdd/Vddq = 2.5V
• Package: 90 Ball BGA (8x13mm)
• Temperature Range: Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
• Die revision: C
Access Time from CLK
ADDRESS TABLE
Parameter
16Mx32
Configuration
4M x 32 x 4 banks
Bank Address Pins
BA0, BA1
Autoprecharge Pins
A10/AP
Row Addresses
A0 – A12
Column Addresses
A0 – A8
Refresh Count
8K / 64ms
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. Rev. A
11/09/2010
1
IS42SM32160C
IS42RM32160C
FUNCTIONAL BLOCK DIAGRAM (16Mx16)
16
16
REFRESH
CONTROLLER
MODE
REGISTER
13
2
SELF
REFRESH
A10
A12
CONTROLLER
16
DQ 0-15
VDD/VDDQ
DATA OUT
BUFFER
Vss/VssQ
16
REFRESH
COUNTER
13
MULTIPLEXER
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
DQML
DQMH
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
ROW
ADDRESS
LATCH
13
13
ROW
ADDRESS
BUFFER
ROW DECODER
CLK
CKE
CS
RAS
CAS
WE
8192
8192
8192
8192
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
512
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
FUNCTIONAL BLOCK DIAGRAM (16Mx32)
CS
CLK
CKE
Die 01
Die 02
Command
Addresses
DQ0 –DQ31
2
Integrated Silicon Solution, Inc.
Rev. A
11/09/2010
IS42SM32160C
IS42RM32160C
PIN DESCRIPTIONS
Symbol
Type
Description
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of
CLK. CLK also increments the internal burst counter and controls the output registers.
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE goes low synchronously
with clock (set-up and hold time same as other inputs), the internal clock is suspended from the next clock
cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks
are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes.
CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE
becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during
Power Down and Self Refresh modes, providing low standby power.
BA0, BA1
Input
Bank Select: BA0 and BA1 defines to which bank the BankActivate, Read, Write, or BankPrecharge
command is being applied.
A0-A12
Input
Address Inputs:A0-A12 are sampled during the BankActivate command (row address A0-A12) and Read/
Write command (column address A0-A8 with A10 defining Auto Precharge) to select one location in the
respective bank. During a Precharge command,A10 is sampled to determine if all banks are to be precharged
(A10 =HIGH).
CS
Input
Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the command decoder.All commands
are masked when CS is sampled HIGH. CS provides for external bank selection on systems with multiple
banks. It is considered part of the command code.
RAS
Input
Row Address Strobe: The RAS signal defines the operation commands in conjunction with the CAS and
WE signals and is latched at the positive edges of CLK. When RAS and CS are asserted “LOW” and CAS
is asserted “HIGH,” either the BankActivate command or the Precharge command is selected by the WE
signal. When the WE is asserted “HIGH,” the BankActivate command is selected and the bank designated
by BA is turned on to the active state. When the WE is asserted “LOW,” the Precharge command is selected
and the bank designated by BA is switched to the idle state after the precharge operation.
CAS
Input
Column Address Strobe: The CAS signal defines the operation commands in conjunction with the RAS
and WE signals and is latched at the positive edges of CLK. When RAS is held “HIGH” and CS is asserted
“LOW,” the column access is started by asserting CAS ”LOW.” Then, the Read or Write command is selected
by asserting WE “LOW” or “HIGH.”
WE
Input
Write Enable: The WE signal defines the operation commands in conjunction with the RAS and CAS signals
and is latched at the positive edges of CLK. The WE input is used to select the BankActivate or Precharge
command and Read or Write command.
DQM0-3
Input
Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer controls. The I/O buffers
are placed in a high-z state when DQM is sampled HIGH. Input data is masked when DQM is sampled
HIGH during a write cycle. Output data is masked (two-clock latency) when DQM is sampled HIGH during
a read cycle. DQM3 masks DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0
masks DQ7-DQ0
DQ0-31
Input/
Output
Data I/O: The DQ0-31 input and output data are synchronized with the positive edge of CLK. The I/Os are
byte-maskable during Reads and Writes.
The address inputs also provide the op-code during a Mode Register Set .
Integrated Silicon Solution, Inc. Rev. A
11/09/2010
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IS42SM32160C
IS42RM32160C
PIN CONFIGURATION
PACKAGE CODE: B 90 BALL FBGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 m Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ26 DQ24 VSS
VDD DQ23 DQ21
DQ28 VDDQ VSSQ
VDDQ VSSQ DQ19
VSSQ DQ27 DQ25
DQ22 DQ20 VDDQ
VSSQ DQ29 DQ30
DQ17 DQ18 VDDQ
VDDQ DQ31 NC
NC
DQ16 VSSQ
VSS DQM3 A3
A2
DQM2 VDD
A4
A5
A6
A10
A0
A1
A7
A8
A12
NC
BA1
A11
CLK
CKE
A9
BA0
CS
RAS
DQM1 NC
NC
CAS
WE DQM0
VDDQ DQ8
VSS
VDD
DQ7 VSSQ
VSSQ DQ10 DQ9
DQ6
DQ5 VDDQ
VSSQ DQ12 DQ14
DQ1
DQ3 VDDQ
DQ11 VDDQ VSSQ
VDDQ VSSQ DQ4
DQ13 DQ15 VSS
VDD
DQ0 DQ2
PIN DESCRIPTIONS
A0-A12
Row Address Input
WE
Write Enable
A0-A8
Column Address Input
DQM0-DQM3
x32 Input/Output Mask
BA0, BA1
Bank Select Address
Vdd
Power
DQ0 to DQ31
Data I/O
Vss
Ground
CLK
System Clock Input
Vddq
Power Supply for I/O Pin
CKE
Clock Enable
Vssq
Ground for I/O Pin
CS
Chip Select
NC
No Connect
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
4
Integrated Silicon Solution, Inc.
Rev. A
11/09/2010
IS42SM32160C
IS42RM32160C
Mobile SDRAM Functionality
ISSI’s 512Mb Mobile SDRAMs are pin compatible and have similar functionality with ISSI’s standard SDRAMs, but
offer lower operating voltages and power saving features. For detailed descriptions of pin functions, command truth
tables, functional truth tables, device operation as well as timing diagrams please refer to ISSI document “Mobile
Synchronous DRAM Device Operations & Timing Diagrams” listed at www.issi.com
REGISTER DEFINITION
Mode Register (MR) & Extended Mode Register (EMR)
There are two mode registers in the Mobile SDRAM; Mode Register (MR) and Extended Mode Register (EMR). The
Mode Register is discussed below, followed by the Extended Mode Register. The Mode Register is used to define
the specific mode of operation of the SDRAM. This definition includes the selection of burst length, a burst type, CAS
Latency, operating mode, and a write burst mode. The mode register is programmed via the LOAD MODE REGISTER
command and will retain the stored information until it is programmed again or the device loses power.
The EMR controls the functions beyond those controlled by the MR. These additional functions are special features
of the Mobile SDRAM. They include temperature-compensated self refresh (TCSR) control, partial-array self refresh
(PASR), and output drive strength. The EMR is programmed via the MODE REGISTER SET command with BA1
= 1 and BA0 = 0 and retains the stored information until it is programmed again or the device loses power. Not
programming the extended mode register upon initialization will result in default settings for the low-power features.
The extended mode will default with the temperature sensor enabled, full drive strength, and full array (all 4 banks)
refresh.
Mode Register Definition
The MR is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a
burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure MODE
REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed again or the device loses power.
Mode register bits M0 - M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4 M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10,
M11, and M12 are reserved for future use.
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.
Integrated Silicon Solution, Inc. Rev. A
11/09/2010
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IS42SM32160C
IS42RM32160C
MODE REGISTER DEFINITION
BA1 BA0 A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
Mode Register (Mx)
Burst Length
(1)
Reserved
M2
M1
M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
Reserved
Reserved
Reserved
Full Page
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7
M6-M0
Mode
0 0
— —
Defined
—
Standard Operation
All Other States Reserved
Write Burst Mode
BA1
BA0
0
0
Mode Register Definition
Program Mode Register
0
1
Reserved
1
1
0
1
Program Extended Mode Register
Reserved
M9
0
1
Mode
Programmed Burst Length
Single Location Access
To ensure compatibility with future devices,
should program A12, A11, A10 = "0"
Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in
MODE REGISTER DEFINITION. The burst length determines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst
is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states
should not be used, as unknown operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-A8 (x32) when the burst length is set to two; by A2-A8 (x32) when the
burst length is set to four; and by A3-A8 (x32) when the burst length is set to eight. The remaining (least significant)
address bit(s) are used to select the starting location within the block. Full-page bursts wrap within the page if the
boundary is reached.
6
Integrated Silicon Solution, Inc.
Rev. A
11/09/2010
IS42SM32160C
IS42RM32160C
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in BURST DEFINITION table.
Burst Definition
BurstStarting Column
Order of Accesses Within a Burst
Length
Address
Type = Sequential
Type = Interleaved
A0
2
0
0-1
0-1
1
1-0
1-0
A1
A0
0
0
0-1-2-3
0-1-2-3
4
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
A2
A1
A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
8
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full n = A0-A9 (x8)
Cn, Cn + 1, Cn + 2
Not Supported
Page (location 0-y) Cn + 3, Cn + 4...
(y)
…Cn - 1,
Cn…
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency
is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS
Latency diagrams.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8
are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.
Integrated Silicon Solution, Inc. Rev. A
11/09/2010
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IS42SM32160C
IS42RM32160C
Test modes and reserved states should not be used because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
CAS Latency
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tAC
DOUT
DQ
tOH
tLZ
CAS Latency - 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tAC
DOUT
DQ
tLZ
tOH
CAS Latency - 3
DON'T CARE
UNDEFINED
8
Integrated Silicon Solution, Inc.
Rev. A
11/09/2010
IS42SM32160C
IS42RM32160C
Extended Mode Register Definition
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
Ext. Mode Reg. (Ex)
PASR
E2 E1 E0 Partial Array Self Refresh Coverage
0 0 0 Fully array (4 banks) - (Default)
0 0 1 Half array (banks 0, 1)
0 1 0 Quarter array (bank 0)
0 1 1 Reserved
1 0 0 Reserved
1 0 1 One-eighth array (1/2 bank 0)
1 1 0 One-sixteenth array (1/4 bank 0)
1 1 1 Reserved
TCSR
E4
0
0
1
1
DS
E6
0
0
1
1
set to "0"
E12 E11 E10 E9
0
0
0
0
–
–
–
–
E8
0
–
E7
0
–
E5
0
1
0
1
E3
0
1
0
1
Max. Case Temp.
70oC
45oC
15oC
85oC (Default)
Driver Strength
Full strength driver (Default)
Half strength driver
Quarter strength driver
Reserved
E6-E0
Valid Normal operation
–
All other states reserved
BA1 BA0 Mode Register Definition
0
0 Program Mode Register
0
1 Reserved
1
0 Program Extended mode Register
1
1 Reserved
The extended mode register is programmed via the MODE REGISTER SET command (BA1 = 1, BA0 = 0) and
retains the stored information until it is programmed again or the device loses power. The extended mode register
must be programmed with E7 through E12 set to “0.” The extended mode register must be loaded when all banks are
idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent
operation. Violating either of these requirements results in unspecified operation. The extended mode register must be
programmed to ensure proper operation.
Temperature-Compensated Self Refresh (TCSR)
TCSR allows the controller to program the refresh interval during self refresh mode, according to the case temperature
of the mobile device. This allows great power savings during self refresh during most operating temperature ranges.
Only during extreme temperatures would the controller have to select a higher TCSR level that will guarantee data
during self refresh.
Integrated Silicon Solution, Inc. Rev. A
11/09/2010
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IS42SM32160C
IS42RM32160C
Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is
dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures,
requiring the cells to be refreshed more often. Historically, during self refresh, the refresh rate has been set to
accommodate the worst case, or highest temperature range, expected. Thus, during ambient temperatures, the
power consumed during refresh was unnecessarily high because the refresh rate was set to accommodate the higher
temperatures. Setting E4 and E3 allows the DRAM to accommodate more specific temperature regions during self
refresh. The default for ISSI 512Mb Mobile SDRAM is TCSR = 85°C to guarantee refresh operation. This mode of
operation has a higher current consumption because the self refresh oscillator is set to refresh the SDRAM cells
more often than needed. By using an external temperature sensor to determine the operating temperature the Mobile
SDRAM can be programmed for lower temperature and refresh rates, effectively reducing current consumption by
a significant amount. There are four temperature settings, which will vary the self refresh current according to the
selected temperature. This selectable refresh rate will save power when the Mobile DRAM is operating at normal
temperatures.
Partial-Array Self Refresh (PASR)
For further power savings during self refresh, the PASR feature allows the controller to select the amount of memory
that will be refreshed during self refresh. The refresh options are all banks (banks 0, 1, 2, and 3); two banks (banks
0 and 1); and one bank (bank 0). In addition partial amounts of bank 0 (half or quarter of the bank) may be selected. WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks in
PASR will be refreshed during self refresh. It’s important to note that data in banks 2 and 3 will be lost when the twobank option is used. Data will be lost in banks 1, 2, and 3 when the one-bank option is used.
Driver Strength (DS)
Bits E5 and E6 of the EMR can be used to select the driver strength of the DQ outputs. This value should be set
according to the application’s requirements. The default is Full Driver Strength.
Deep Power Down (DPD)
Deep power down mode is for maximum power savings and is achieved by shutting down power to the entire memory
array of the mobile device. Data will be lost once deep power down mode is executed.
DPD mode is entered by having all banks idle, CS and WE held low, with RAS and CAS HIGH at the rising edge of
the clock, while CKE is LOW. CKE must be held LOW during DPD mode. To exit DPD mode, CKE must be asserted
HIGH. Upon exit from DPD mode, at least 200ms of valid clocks with either NOP or COMMAND INHIBIT commands
are applied to the command bus, followed by a full Mobile SDRAM initialization sequence, is required.
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Integrated Silicon Solution, Inc.
Rev. A
11/09/2010
IS42SM32160C
IS42RM32160C
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vdd
Vddq
Vin
Vout
Ics
Pd
Topt
Tstg
Parameters
Supply Voltage (with respect to Vss)
Supply Voltage for Output (with respect to Vssq)
Input Voltage (with respect to Vss)
Output Voltage (with respect to Vssq)
Short circuit output current
Power Dissipation (Ta = 25oC)
Operating Temperature
Com.
Ind.
Storage Temperature
Rating
-0.5 to +4.6
-0.5 to +4.6
-0.5 to Vdd+0.5
-1.0 to Vdd+0.5
50
1
0 to +70
-40 to +85
–65 to +150
Unit
V
V
V
V
mA
W
°C
°C
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All voltages are reference to Vss.
CAPACITANCE
Symbol
Cin
Cclk
Cio
Parameter
Input Capacitance, address and control pin
Input Capacitance, CLK pin Data Input/Output Capacitance
Integrated Silicon Solution, Inc. Rev. A
11/09/2010
Min.
5.0
5.0
4
Max.
7.0
7.6
6.5
Unit
pF
pF
pF
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IS42SM32160C
IS42RM32160C
DC RECOMMENDED OPERATING CONDITIONS
IS42SMxxx - 3.3V Operation
Symbol
Vdd
Vddq
Vih(1)
Vil(2)
Iil
Iol
Voh
Vol
Parameters
Supply Voltage
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current (0V ≤ Vin ≤ Vdd)
Output Leakage Current (Output disabled, 0V ≤ Vout ≤ Vdd)
Output High Voltage Current (Ioh = -2mA)
Output Low Voltage Current (Iol = 2mA)
Min.
3.0
3.0
2.0
-0.3
-5
-5
2.4
–
Typ.
3.3
3.3
–
–
–
–
–
–
Max.
3.6
3.6
Vddq+0.3
0.8
+5
+5
–
0.4
Unit
V
V
V
V
µA
µA
V
V
Max.
2.7
2.7
Vdd+0.3
0.55
+5
+5
0.2
Unit
V
V
V
V
µA
µA
V
V
IS42RMxxx - 2.5V Operation
Symbol
Vdd
Vddq
Vih(1)
Vil(2)
Iil
Iol
Voh
Vol
Parameters
Supply Voltage
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current (0V ≤ Vin ≤ Vdd)
Output Leakage Current (Output disabled, 0V ≤ Vout ≤ Vdd)
Output High Voltage Current (Ioh = -2mA)
Output Low Voltage Current (Iol = 2mA)
Min.
2.3
2.3
2.0
-0.3
-5
-5
Vdd-0.2
-
Typ.
2.5
2.5
–
–
–
–
Notes:
1. Vih (overshoot): Vih (max) = Vddq +1.2V (pulse width < 3ns).
2. Vil (undershoot): Vih (min) = -1.2V (pulse width < 3ns).
3. All voltages are referenced to Vss.
Contact Product Marketing for 3.0V + 10% support.
12
Integrated Silicon Solution, Inc.
Rev. A
11/09/2010
IS42SM32160C
IS42RM32160C
DC ELECTRICAL CHARACTERISTICS VDD = 3.3V / 2.5V x32
Symbol
Parameter
Test Condition
Idd1
Operating Current
One Bank Active, CL = 3, BL = 1,
(1)
-7
–75
Unit
140
130
mA
2
2
mA
2
2
mA
50
50
mA
30
30
mA
5
5
mA
5
5
mA
65
65
mA
35
35
mA
180
170
mA
tCLK = tCLK(min), tRC = tRC(min)
Idd2p
(4)
Idd2ps
(4)
Precharge Standby Current
CKE ≤ Vil (max), tCK = 15ns
(In Power-Down Mode)
CS ≥ Vdd - 0.2V
Precharge Standby Current CKE ≤ Vil (max), CLK ≤ Vil (max)
With Clock Stop
CS ≥ Vdd - 0.2V
(In Power-Down Mode)
Idd2n
(2)
Idd2ns
Precharge Standby Current
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
(In Non Power-Down Mode)
tCK = 15 ns
Precharge Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
With Clock Stop
All Inputs Stable
(In Non-Power Down Mode)
Idd3p
(2)
Idd3ps
Active Standby Current
CKE ≤ Vil (max), CS ≥ Vdd - 0.2V
(In Power-Down Mode)
tCK = 15 ns
Active Standby Current
CKE ≤ Vil (max), CLK ≤ Vil (max)
With Clock Stop
CS ≥ Vdd - 0.2V
(In Power-Down Mode)
Idd3n(2)
Idd3ns
Active Standby Current
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
(In Non Power-Down Mode)
tCK = 15 ns
Active Standby Current
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
With Clock Stop
All Inputs Stable
(In Non Power-Down Mode)
Idd4
Operating Current
All Banks Active, BL =Full, CL = 3
tCK = tCK(min)
Idd5
Auto-Refresh Current
tRC = tRC(min), tCLK = tCLK(min)
260
250
mA
Idd6
Self-Refresh Current
CKE ≤ 0.2V
2.4
2.4
mA
Idd7
Self-Refresh: CKE = LOW; tck = tck (MIN);
Address, Control, and Data bus inputs are
stable
Full Array, 85oC
Full Array, 45oC
Half Array, 85oC
Half Array, 45oC
1/4th Array, 85oC
1/4th Array, 45oC
1/8th Array, 85oC
1/8th Array, 45oC
1/16th Array, 85oC
1/16th Array, 45oC
Izz(3,4)
Deep Power Down Current
CKE ≤ 0.2V
mA
2.4
1.6
2.0
1.3
1.6
1.1
1.4
0.9
1.2
0.8
40
40
mA
Notes:
1. Idd (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3. Izz values shown are nominal at 25oC. Izz is not testsed.
4. Tested after 500ms delay.
Integrated Silicon Solution, Inc. Rev. A
11/09/2010
13
IS42SM32160C
IS42RM32160C
AC ELECTRICAL CHARACTERISTICS (1, 2, 3)
-7
-75
Min. Max.
7.5
–
Symbol Parameter
tCK3
Clock Cycle Time
CAS Latency = 3
Min.
7
Max.
–
tCK2
tAC3
Access Time From CLK
CAS Latency = 2
CAS Latency = 3
9.6
–
–
5.4
9.6
–
–
5.4
ns
ns
tAC2
tCHI
tCL
tOH3
CAS Latency = 2
CLK HIGH Level Width
CLK LOW Level Width
Output Data Hold Time
–
2.5
2.5
2.7
7.0
–
–
–
–
2.5
2.5
2.7
7.0
–
–
–
ns
ns
ns
ns
tOH2
tLZ
tHZ
Output LOW Impedance Time
Output HIGH Impedance Time
2.7
0
2.7
–
–
5.4
2.7
0
2.7
–
–
5.4
ns
ns
ns
2.7
1.5
1.0
1.5
1.0
1.5
1.0
1.5
7.0
–
–
–
–
–
–
–
2.7
1.5
1.0
1.5
1.0
1.5
1.0
1.5
7.0
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
1.0
–
1.0
–
ns
67.5
–
67.5
–
ns
45
19
19
100K
–
–
45
19
19
100K
–
–
ns
ns
ns
14
–
15
–
ns
14
–
15
–
ns
35
–
37.5
–
ns
14
7
80
0.3
–
–
–
–
1.2
64
15
7.5
80
0.3
–
–
–
–
1.2
64
ns
ns
ns
ns
ms
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tRC
tRAS
tRP
tRCD
tRRD
tDPL
tDAL
tMRD
tDDE
tSRX
tT
tREF
Input Data Setup Time
Input Data Hold Time (2)
Address Setup Time (2)
Address Hold Time (2)
CKE Setup Time (2)
CKE Hold Time (2)
Command Setup Time (CS, RAS,
CAS, WE, DQM)(2)
Command Hold Time (CS, RAS,
CAS, WE, DQM)(2)
Command Period (REF to REF /
ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Active Command to Read/Write
Command Delay Time
Command Period (ACT [0] to
ACT [1])
Input Data to Precharge
Command Delay Time
Input Data to Active/Refresh
Command Delay Time (During
Auto-Precharge)
Mode Register Program Time
Power Down Exit Setup Time
Exit Self-Refresh to Active Time
Transition Time
8K times
Refresh Cycle Time
(2)
Unit
ns
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns. If clock rising time is longer than 1ns, (tR /2 - 0.5) ns should be added to the parameter.
3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between
Vih(min.) and Vil (max).
14
Integrated Silicon Solution, Inc.
Rev. A
11/09/2010
IS42SM32160C
IS42RM32160C
OPERATING
FREQUENCY / LATENCY RELATIONSHIPS
Symbol
Parameter
-7
-75
Units
—
Clock Cycle Time
7
7.5
ns
—
Operating Frequency
143
133
MHz
tcac
CAS Latency
3
3
cycle
trcd
Active Command To Read/Write Command Delay Time
3
3
cycle
trac
RAS Latency (trcd + tcac)
6
6
cycle
trc
Command Period (REF to REF / ACT to
ACT)
10
9
cycle
tras
Command Period (ACT to PRE)
7
6
cycle
trp
Command Period (PRE to ACT)
3
3
cycle
trrd
Command Period (ACT[0] to ACT [1])
2
2
cycle
tccd
Column Command Delay Time
(READ, READA, WRIT, WRITA)
1
1
cycle
tdpl
Input Data To Precharge Command Delay
Time
2
2
cycle
tdal
Input Data To Active/Refresh Command
Delay Time
(During Auto-Precharge)
5
5
cycle
trbd
Burst Stop Command To Output in HIGH-Z
Delay Time
(Write)
3
3
cycle
twbd
Burst Stop Command To Input in Invalid
Delay Time
(Write)
0
0
cycle
trql
Precharge Command To Output in HIGH-Z
Delay Time
(Read)
3
3
cycle
twdl
Precharge Command To Input in Invalid
Delay Time
(Write)
0
0
cycle
tpql
Last Output To Auto-Precharge Start
Time (Read)
-2
-2
cycle
tqmd
DQM To Output Delay Time (Read)
2
2
cycle
tdmd
DQM To Input Delay Time (Write)
0
0
cycle
tmrd
Mode Register Set To Command Delay
Time
2
2
cycle
Integrated Silicon Solution, Inc. Rev. A
11/09/2010
CAS Latency = 3
CAS Latency = 3
CAS Latency = 3
CAS Latency = 3
15
IS42SM32160C
IS42RM32160C
Ordering Information – Vdd = 3.3V
Commercial Range: (0°C to +70°C)
Frequency
143 MHz
133 MHz
Speed (ns)
7.0
7.5
Order Part No.
IS42SM32160C-7BL
IS42SM32160C-75BL
Package
8x13mm BGA, Lead-free
8x13mm BGA, Lead-free
Industrial Range: (-40°C to +85°C)
Frequency
143 MHz
133 MHz
Speed (ns)
7.0
7.5
Order Part No.
IS42SM32160C-7BLI
IS42SM32160C-75BLI
Package
8x13mm BGA, Lead-free
8x13mm BGA, Lead-free
Ordering Information – Vdd = 2.5V
Commercial Range: (0°C to +70°C)
Frequency
133 MHz
Speed (ns)
7.5
Order Part No.
IS42RM32160C-75BL
Package
8x13mm BGA, Lead-free
Industrial Range: (-40°C to +85°C)
Frequency
133 MHz
Speed (ns)
7.5
Order Part No.
IS42RM32160C-75BLI
Package
8x13mm BGA, Lead-free
*Contact ISSI for leaded parts support.
16
Integrated Silicon Solution, Inc.
Rev. A
11/09/2010
Integrated Silicon Solution, Inc. Rev. A
11/09/2010
Package Outline
08/28/2008
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MS-207
NOTE :
IS42SM32160C
IS42RM32160C
17