Error Correction Code (ECC) Based New High Speed Low Power 4Mb Asynchronous SRAM ISSI’s latest Error Correction based 4Mb High Speed Low Power Asynchronous SRAM is currently sampling. This innovative design reinforces ISSI’s long-term commitment to SRAMs with the highest quality and performance. This industry’s first Error Correction Code (ECC) based Asynchronous SRAM meets high quality requirements in automotive, industrial, military-aerospace, and other applications. Error Detection and Error Correction • Independent ECC with hamming code for each byte • Detect and correct one bit error per each byte • Better reliability than parity code schemes which can only detect an error but not correct an error • Backward Compatible: Drop in replacement to current in industry standard devices (without ECC) A0-A17 IO0-7 IO8-15 Memory Lower IO Array 256Kx8 Decoder 8 8 /CE /OE /WE /UB /LB 12 8 I/O Data Circuit 8 ECC Array 256K x4 4 ECC 8 ECC Memory Upper IO Array 256Kx8 8 ► Applications • Automotive • Military-Aerospace/Medical • Industrial • Telecom/Networking ECC Array 256K x4 4 ► Click here for datasheet Column I/O 12 ► Additional ECC Async SRAMs Control Circuit • 2Mb, 8Mb Key Features IS64WV25616EDBLL (A1) IS64WV25616EDBLL (A3) Comments Temperature Support Industrial (-40oC to +85oC) Automotive (-40oC to +125oC) Contact ISSI for military temperature Technology 65nm 65nm Standby Current 9mA 20mA Typical value 2mA Operating Current 45mA 65mA Typical value 25 mA Data Retention Current 9mA 15mA Typical value 2mA TSOP-II (44 pins) BGA (48 pins) TSOP-II (44 pins) BGA (48 pins) Pin compatible with industry standard 4Mb Async. SRAM Speed 10ns 10ns Copper Leadframe Yes Yes Improved thermal performance Lead-free and Leaded Yes Yes RoHS Compliant Sampling Sampling Packaging Availability June 2012 1940 Zanker Rd., San Jose, CA. 95112 • Tel: 408.969.6600 • Support: [email protected] • www.issi.com