XMC1100 Data Sheet

XMC1100
Microcontroller Series
for Industrial Applications
XMC1000 Family
ARM® Cortex™-M0
32-bit processor core
Data Sheet
V1.4 2014-05
Microcontrollers
Edition 2014-05
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
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and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
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be endangered.
XMC1100
Microcontroller Series
for Industrial Applications
XMC1000 Family
ARM® Cortex™-M0
32-bit processor core
Data Sheet
V1.4 2014-05
Microcontrollers
XMC1100
XMC1000 Family
XMC1100 Data Sheet
Revision History: V1.4 2014-05
Previous Version: V1.3
Page
Subjects
Page 10
ADC channels of Table 2 is updated. Table 3 is added.
Page 10
Description for Chip Identification Number of Section 1.4 is updated.
Page 17
The pad type is corrected for P1.6 in Table 6.
Page 29
The tC12 , fC12, tC10, fC10, tC8 and fC8 parameters are updated in Table 12.
Page 32
Figure 8 is added.
Page 33
The tSR and tTSAL parameters are updated in Table 13.
Page 36
Parameter name for tPSER is updated. The NWSFLASH parameter and test
condition for tRET are added to Table 16.
Page 39
The min value for VDDPBO parameter is added to Table 18. Footnote 1 is
updated.
Page 41
The ΔfLTT parameter is added to Table 19.
Page 47
Figure 13 is added.
Trademarks
C166™, TriCore™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered® and AMBA® are registered trademarks of ARM, Limited.
Cortex™, CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace
Buffer™ are trademarks of ARM, Limited.
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
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Please send your proposal (including a reference to this document) to:
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Data Sheet
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Table of Contents
Table of Contents
1
1.1
1.2
1.3
1.4
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
2.1
2.2
2.2.1
2.2.2
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
14
17
20
3
3.1
3.1.1
3.1.2
3.1.3
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.7.1
3.3.7.2
3.3.7.3
Electrical Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog to Digital Converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Sensor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up and Supply Threshold Charcteristics . . . . . . . . . . . . . . . . . .
On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . .
SPD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . .
Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . .
23
23
23
24
25
26
26
29
33
34
36
37
37
38
39
41
43
44
45
45
48
50
4
4.1
4.1.1
4.2
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
52
52
54
5
Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Data Sheet
5
V1.4, 2014-05
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XMC1100
XMC1000 Family
About this Document
About this Document
This Data Sheet is addressed to embedded hardware and software developers. It
provides the reader with detailed descriptions about the ordering designations, available
features, electrical and physical characteristics of the XMC1100 series devices.
The document describes the characteristics of a superset of the XMC1100 series
devices. For simplicity, the various device types are referred to by the collective term
XMC1100 throughout this document.
XMC1000 Family User Documentation
The set of user documentation includes:
•
•
•
Reference Manual
– decribes the functionality of the superset of devices.
Data Sheets
– list the complete ordering designations, available features and electrical
characteristics of derivative devices.
Errata Sheets
– list deviations from the specifications given in the related Reference Manual or
Data Sheets. Errata Sheets are provided for the superset of devices.
Attention: Please consult all parts of the documentation set to attain consolidated
knowledge about your device.
Application related guidance is provided by Users Guides and Application Notes.
Please refer to http://www.infineon.com/xmc1000 to get access to the latest versions
of those documents.
Data Sheet
6
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XMC1100
XMC1000 Family
Summary of Features
1
Summary of Features
The XMC1100 devices are members of the XMC1000 family of microcontrollers based
on the ARM Cortex-M0 processor core. The XMC1100 series devices are designed for
general purpose applications.
Cortex-M0
CPU
Analog system
EVR
2 x DCO
Debug
system
NVIC
SWD
SPD
ANACTRL SFRs
PRNG
16-bit APB Bus
Temperature sensor
AHB to APB
Bridge
PAU
AHB-Lite Bus
Flash SFRs
64k + 0.5k1)
Flash
PORTS
CCU40
16k
SRAM
WDT
USIC0
8k ROM
SCU
VADC
RTC
Memories
ERU0
1) 0.5kbytes of sector 0 (readable only).
Figure 1
System Block Diagram
CPU Subsystem
•
CPU Core
– High Performance 32-bit ARM Cortex-M0 CPU
– Most of 16-bit Thumb instruction set
– Subset of 32-bit Thumb2 instruction set
Data Sheet
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XMC1100
XMC1000 Family
Summary of Features
•
•
– High code density with 32-bit performance
– Single cycle 32-bit hardware multiplier
– System timer (SysTick) for Operating System support
– Ultra low power consumption
Nested Vectored Interrupt Controller (NVIC)
Event Request Unit (ERU) for programmable processing of external and internal
service requests
On-Chip Memories
•
•
•
8 kbytes on-chip ROM
16 kbytes on-chip high-speed SRAM
up to 64 kbytes on-chip Flash program and data memory
On-Chip Peripherals
•
•
•
•
•
•
•
•
Two Universal Serial Interface Channels (USIC), usable as UART, double-SPI,
quad-SPI, IIC, IIS and LIN interfaces
A/D Converters, up to 12 channels, includes a 12-bit analog to digital converter
Capture/Compare Units 4 (CCU4) for use as general purpose timers
Window Watchdog Timer (WDT) for safety sensitive applications
Real Time Clock module with alarm support (RTC)
System Control Unit (SCU) for system configuration and control
Pseudo random number generator (PRNG), provides random data with fast
generation times
Temperature Sensor (TSE)
Input/Output Lines
•
•
•
•
•
Programmable port driver control module (PORTS)
Individual bit addressability
Tri-stated in input mode
Push/pull or open drain output mode
Configurable pad hysteresis
On-Chip Debug Support
•
•
Support for debug features: 4 breakpoints, 2 watchpoints
Various interfaces: ARM serial wire debug (SWD), single pin debug (SPD)
1.1
Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. The code “XMC1<DDD>-<Z><PPP><T><FFFF>” identifies:
•
<DDD> the derivatives function set
Data Sheet
8
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Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Summary of Features
•
•
•
•
<Z> the package variant
– T: TSSOP
– Q: VQFN
<PPP> package pin count
<T> the temperature range:
– F: -40°C to 85°C
– X: -40°C to 105°C
<FFFF> the Flash memory size.
For ordering codes for the XMC1100 please contact your sales representative or local
distributor.
This document describes several derivatives of the XMC1100 series, some descriptions
may not apply to a specific product. Please see Table 1.
For simplicity the term XMC1100 is used for all derivatives throughout this document.
1.2
Device Types
These device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
Table 1
Synopsis of XMC1100 Device Types
Derivative
Package
Flash
Kbytes
SRAM
Kbytes
XMC1100-T016F0008
PG-TSSOP-16-8
8
16
XMC1100-T016F0016
PG-TSSOP-16-8
16
16
XMC1100-T016F0032
PG-TSSOP-16-8
32
16
XMC1100-T016F0064
PG-TSSOP-16-8
64
16
XMC1100-T016X0064
PG-TSSOP-16-8
64
16
XMC1100-T038F0016
PG-TSSOP-38-9
16
16
XMC1100-T038F0032
PG-TSSOP-38-9
32
16
XMC1100-T038F0064
PG-TSSOP-38-9
64
16
XMC1100-T038X0064
PG-TSSOP-38-9
64
16
XMC1100-Q024F0008
PG-VQFN-24-19
8
16
XMC1100-Q024F0016
PG-VQFN-24-19
16
16
XMC1100-Q024F0032
PG-VQFN-24-19
32
16
XMC1100-Q024F0064
PG-VQFN-24-19
64
16
XMC1100-Q040F0016
PG-VQFN-40-13
16
16
Data Sheet
9
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XMC1100
XMC1000 Family
Summary of Features
Table 1
Synopsis of XMC1100 Device Types (cont’d)
Derivative
Package
Flash
Kbytes
SRAM
Kbytes
XMC1100-Q040F0032
PG-VQFN-40-13
32
16
XMC1100-Q040F0064
PG-VQFN-40-13
64
16
1.3
Device Type Features
The following table lists the available features per device type.
Features of XMC1100 Device Types1)
Table 2
Derivative
ADC channel
XMC1100-T016
6
XMC1100-T038
12
XMC1100-Q024
8
XMC1100-Q040
12
1) Features that are not included in this table are available in all the derivatives
Table 3
ADC Channels
Package
VADC0 G0
VADC0 G1
PG-TSSOP-16
CH0..CH5
−
PG-TSSOP-38
CH0..CH7
CH1, CH5 .. CH7
PG-VQFN-24
CH0..CH7
−
PG-VQFN-40
CH0..CH7
CH1, CH5 .. CH7
1.4
Chip Identification Number
The Chip Identification Number allows software to identify the marking. It is a 8 words
value with the most significant 7 words stored in Flash configuration sector 0 (CS0) at
address location : 1000 0F00H (MSB) - 1000 0F1BH (LSB). The least significant word and
most significant word of the Chip Identification Number are the value of registers
DBGROMID and IDCHIP, respectively.
Data Sheet
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Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Summary of Features
Table 4
XMC1100 Chip Identification Number
Derivative
Value
Marking
XMC1100-T016F0008
00011032 01CF00FF 00001F37 00000000
00000B00 00001000 00003000 101ED083H
AA
XMC1100-T016F0016
00011032 01CF00FF 00001F37 00000000
00000B00 00001000 00005000 101ED083H
AA
XMC1100-T016F0032
00011032 01CF00FF 00001F37 00000000
00000B00 00001000 00009000 101ED083H
AA
XMC1100-T016F0064
00011032 01CF00FF 00001F37 00000000
00000B00 00001000 00011000 101ED083H
AA
XMC1100-T016X0064
00011033 01CF00FF 00001F37 00000000
00000B00 00001000 00011000 101ED083H
AA
XMC1100-T038F0016
00011012 01CF00FF 00001F37 00000000
00000B00 00001000 00005000 101ED083H
AA
XMC1100-T038F0032
00011012 01CF00FF 00001F37 00000000
00000B00 00001000 00009000 101ED083H
AA
XMC1100-T038F0064
00011012 01CF00FF 00001F37 00000000
00000B00 00001000 00011000 101ED083H
AA
XMC1100-T038X0064
00011013 01CF00FF 00001F37 00000000
00000B00 00001000 00011000 101ED083H
AA
XMC1100-Q024F0008
00011062 01CF00FF 00001F37 00000000
00000B00 00001000 00003000 101ED083H
AA
XMC1100-Q024F0016
00011062 01CF00FF 00001F37 00000000
00000B00 00001000 00005000 101ED083H
AA
XMC1100-Q024F0032
00011062 01CF00FF 00001F37 00000000
00000B00 00001000 00009000 101ED083H
AA
XMC1100-Q024F0064
00011062 01CF00FF 00001F37 00000000
00000B00 00001000 00011000 101ED083H
AA
XMC1100-Q040F0016
00011042 01CF00FF 00001F37 00000000
00000B00 00001000 00005000 101ED083H
AA
XMC1100-Q040F0032
00011042 01CF00FF 00001F37 00000000
00000B00 00001000 00009000 101ED083H
AA
XMC1100-Q040F0064
00011042 01CF00FF 00001F37 00000000
00000B00 00001000 00011000 101ED083H
AA
Data Sheet
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XMC1100
XMC1000 Family
General Device Information
2
General Device Information
This section summarizes the logic symbols and package pin configurations with a
detailed list of the functional I/O mapping.
2.1
Logic Symbols
VDDP
VSSP
(2)
(2)
VDDP
VSSP
(1)
(1)
Port 0
16 bit
XMC1100
TSSOP -38
Port 0
8 bit
Port 1
6 bit
XMC1100
TSSOP-16
Port 2
4 bit
Port 2
3 bit
Port 2
8 bit
Figure 2
Data Sheet
Port 2
3 bit
XMC1100 Logic Symbol for TSSOP-38 and TSSOP-16
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XMC1100
XMC1000 Family
General Device Information
V DD VSS VDDP VSSP
(1)
(1)
(2)
(1)
V DDP
VSSP
(1)
(1)
Port 0
10 bit
Port 0
16 bit
XMC1100
VQFN-40
Port 1
7 bit
XMC1100
VQFN-24
Port 2
4 bit
Data Sheet
Port 2
4 bit
Port 2
4 bit
Port 2
8 bit
Figure 3
Port 1
4 bit
XMC1100 Logic Symbol for VQFN-24 and VQFN-40
13
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XMC1100
XMC1000 Family
General Device Information
2.2
Pin Configuration and Definition
The following figures summarize all pins, showing their locations on the different
packages.
P2.4
1
38
P2.3
Top View
Figure 4
Data Sheet
P2.5
2
37
P2.2
P2.6
3
36
P2.1
P2.7
4
35
P2.0
P2.8
5
34
P0.15
P2.9
6
33
P0.14
P2.10
7
32
P0.13
P2.11
8
31
P0.12
VSSP /VSS
9
30
P0.11
VDDP/VDD
10
29
P0.10
P1.5
11
28
P0.9
P1.4
12
27
P0.8
P1.3
13
26
VDDP
P1.2
14
25
VSSP
P1.1
15
24
P0.7
P1.0
16
23
P0.6
P0.0
17
22
P0.5
P0.1
18
21
P0.4
P0.2
19
20
P0.3
XMC1100 PG-TSSOP-38 Pin Configuration (top view)
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XMC1100
XMC1000 Family
General Device Information
P2.7/P2.8
1
16
P2.6
Top View
2
15
P2.0
P2.10
3
14
P0.15
P2.11
4
13
P0.14
VSSP/VSS
5
12
P0.9
VDDP/VDD
6
11
P0.8
P0.0
7
10
P0.7
P0.5
8
9
P0.6
P1.1
P1.0
P0.0
P0.5
P0.6
XMC1100 PG-TSSOP-16 Pin Configuration (top view)
P0.7
Figure 5
P2.9
18 17 16 15 14 13
12
P1.2
P0.9
20
11
P1.3
P0.12
21
10
VDDP /V DD
P0.13
22
9
VSSP /V SS
P0.14
23
8
P2.11
P0.15
24
7
P2.10
P2.2
4 5
6
P2.9
3
P2.7/P2.8
2
P2.6
1
P2.1
Data Sheet
19
P2.0
Figure 6
P0.8
XMC1100 PG-VQFN-24 Pin Configuration (top view)
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XMC1100
XMC1000 Family
P1.1
P1.0
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
General Device Information
30 29 28 27 26 25 24 23 22 21
V SSP
31
20
P1.2
VDDP
32
19
P1.3
P0.8
33
18
P1.4
P0.9
34
17
P1.5
P0.10
35
16
P1.6
P0.11
36
15
VDDP
P0.12
37
14
V DD
P0.13
38
13
V SS
P0.14
39
12
P2.11
P0.15
40
11
P2.10
7
8
9
10
P2.6
P2.7
P2.8
P2.9
6
P2.5
P2.4
P2.2
4 5
P2.3
3
P2.1
Data Sheet
2
P2.0
Figure 7
1
XMC1100 PG-VQFN-40 Pin Configuration (top view)
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XMC1100
XMC1000 Family
General Device Information
2.2.1
Package Pin Summary
The following general building block is used to describe each pin:
Table 5
Package Pin Mapping Description
Function
Package A
Package B
Px.y
N
N
...
Pad Type
Pad Class
The table is sorted by the “Function” column, starting with the regular Port pins (Px.y),
followed by the supply pins.
The following columns, titled with the supported package variants, lists the package pin
number to which the respective function is mapped in that package.
The “Pad Type” indicates the employed pad type:
•
•
•
•
•
STD_INOUT (standard bi-directional pads)
STD_INOUT/AN (standard bi-directional pads with analog input)
High Current (high current bi-directional pads)
STD_IN/AN (standard input pads with analog input)
Power (power supply)
Details about the pad properties are defined in the Electrical Parameters.
Table 6
Package Pin Mapping
Function VQFN
40
TSSOP VQFN
38
24
TSSOP Pad Type
16
P0.0
23
17
15
7
STD_INOUT
P0.1
24
18
-
-
STD_INOUT
P0.2
25
19
-
-
STD_INOUT
P0.3
26
20
-
-
STD_INOUT
P0.4
27
21
-
-
STD_INOUT
P0.5
28
22
16
8
STD_INOUT
P0.6
29
23
17
9
STD_INOUT
P0.7
30
24
18
10
STD_INOUT
P0.8
33
27
19
11
STD_INOUT
P0.9
34
28
20
12
STD_INOUT
P0.10
35
29
-
-
STD_INOUT
P0.11
36
30
-
-
STD_INOUT
P0.12
37
31
21
-
STD_INOUT
Data Sheet
17
Notes
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
General Device Information
Table 6
Package Pin Mapping
Function VQFN
40
TSSOP VQFN
38
24
TSSOP Pad Type
16
P0.13
38
32
22
-
STD_INOUT
P0.14
39
33
23
13
STD_INOUT
P0.15
40
34
24
14
STD_INOUT
P1.0
22
16
14
-
High Current
P1.1
21
15
13
-
High Current
P1.2
20
14
12
-
High Current
P1.3
19
13
11
-
High Current
P1.4
18
12
-
-
High Current
P1.5
17
11
-
-
High Current
P1.6
16
-
-
-
STD_INOUT
P2.0
1
35
1
15
STD_INOUT/AN
P2.1
2
36
2
-
STD_INOUT/AN
P2.2
3
37
3
-
STD_IN/AN
P2.3
4
38
-
-
STD_IN/AN
P2.4
5
1
-
-
STD_IN/AN
P2.5
6
2
-
-
STD_IN/AN
P2.6
7
3
4
16
STD_IN/AN
P2.7
8
4
5
1
STD_IN/AN
P2.8
9
5
5
1
STD_IN/AN
Notes
P2.9
10
6
6
2
STD_IN/AN
P2.10
11
7
7
3
STD_INOUT/AN
P2.11
12
8
8
4
STD_INOUT/AN
VSS
13
9
9
5
Power
Supply GND, ADC
reference GND
VDD
14
10
10
6
Power
Supply VDD, ADC
reference voltage/
ORC reference
voltage. VDD has to
be supplied with the
same voltage as
VDDP
Data Sheet
18
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
General Device Information
Table 6
Package Pin Mapping
Function VQFN
40
TSSOP VQFN
38
24
TSSOP Pad Type
16
Notes
15
10
10
6
Power
I/O port supply
VSSP
31
25
-
-
Power
I/O port ground
VDDP
32
26
-
-
Power
I/O port supply
VSSP
Exp.
Pad
-
Exp.
Pad
-
Power
Exposed Die Pad
The exposed die
pad is connected
internally to VSSP.
For proper
operation, it is
mandatory to
connect the
exposed pad to the
board ground.
For thermal
aspects, please
refer to the
Package and
Reliability chapter.
VDDP
Data Sheet
19
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
General Device Information
2.2.2
Port I/O Functions
The following general building block is used to describe each PORT pin:
Table 7
Port I/O Function Description
Function
Outputs
ALT1
P0.0
Pn.y
ALTn
Inputs
HWO0
HWI0
MODA.OUT MODB.OUT MODB.INA
MODA.OUT
Input
Input
MODC.INA
MODA.INA
MODC.INB
Pn.y is the port pin name, defining the control and data bits/registers associated with it.
As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT
defines the output value.
Up to seven alternate output functions (ALT1/2/3/4/5/6/7) can be mapped to a single port
pin, selected by Pn_IOCR.PC. The output value is directly driven by the respective
module, with the pin characteristics controlled by the port registers (within the limits of
the connected pad).
The port pin input can be connected to multiple peripherals. Most peripherals have an
input multiplexer to select between different possible input sources.
The input path is also active while the pin is configured as output. This allows to feedback
an output to on-chip resources without wasting an additional external pin.
By Pn_HWSEL, it is possible to select between different hardware “masters”
(HWO0/HWI0, HWO1/HWI1). The selected peripheral can take control of the pin(s).
Hardware control overrules settings in the respective port pin registers.
Data Sheet
20
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
Data Sheet
Table 8
Port I/O Functions
Function
Outputs
ALT1
ALT2
ALT3
ALT4
ALT5
Inputs
ALT6
ALT7
HWO0
HWO1
HWI0
HWI1
Input
USIC0_CH0.
SELO0
USIC0_CH1.
SELO0
CCU40.IN0C
SCU. VDROP
CCU40.IN1C
P0.0
ERU0.
PDOUT0
ERU0.
GOUT0
CCU40.OUT0
P0.1
ERU0.
PDOUT1
ERU0.
GOUT1
CCU40.OUT1
P0.2
ERU0.
PDOUT2
ERU0.
GOUT2
CCU40.OUT2
VADC0.
EMUX02
CCU40.IN2C
P0.3
ERU0.
PDOUT3
ERU0.
GOUT3
CCU40.OUT3
VADC0.
EMUX01
CCU40.IN3C
P0.4
CCU40.OUT1
VADC0.
EMUX00
WWDT.
SERVICE_OU
T
P0.5
CCU40.OUT0
P0.6
CCU40.OUT0
USIC0_CH1.
MCLKOUT
USIC0_CH1.
DOUT0
Input
Input
Input
CCU40.IN0B
Input
Input
USIC0_CH0.
DX2A
USIC0_CH1.
DX2A
USIC0_CH1.
DX0C
CCU40.OUT1
USIC0_CH0.
SCLKOUT
USIC0_CH1.
DOUT0
CCU40.IN1B
USIC0_CH0.
DX1C
USIC0_CH1.
DX0D
CCU40.OUT2
USIC0_CH0.
SCLKOUT
USIC0_CH1.
SCLKOUT
CCU40.IN2B
USIC0_CH0.
DX1B
USIC0_CH1.
DX1B
P0.9
CCU40.OUT3
USIC0_CH0.
SELO0
USIC0_CH1.
SELO0
CCU40.IN3B
USIC0_CH0.
DX2B
USIC0_CH1.
DX2B
USIC0_CH0.
SELO1
USIC0_CH1.
SELO1
USIC0_CH0.
DX2C
USIC0_CH1.
DX2C
USIC0_CH0.
SELO2
USIC0_CH1.
SELO2
USIC0_CH0.
DX2D
USIC0_CH1.
DX2D
21
P0.7
P0.8
P0.10
USIC0_CH0.
MCLKOUT
P0.12
P0.13
USIC0_CH0.
SELO3
WWDT.
SERVICE_OU
T
USIC0_CH0.
DOUT0
P0.15
USIC0_CH0.
DOUT0
P1.0
CCU40.IN0A
USIC0_CH0.
SELO4
P0.14
CCU40.OUT0
P1.1
VADC0.
EMUX00
CCU40.OUT1
VADC0.
EMUX01
CCU40.OUT2
USIC0_CH0.
DOUT0
P1.3
VADC0.
EMUX02
CCU40.OUT3
P1.4
VADC0.
EMUX10
USIC0_CH1.
SCLKOUT
USIC0_CH0.
SELO0
P1.5
VADC0.
EMUX11
USIC0_CH0.
DOUT0
USIC0_CH0.
SELO1
USIC0_CH1.
SCLKOUT
CCU40.IN2A
CCU40.IN3A
USIC0_CH0.
DX2E
USIC0_CH0.
DX2F
USIC0_CH0.
SCLKOUT
USIC0_CH0.
DX0A
USIC0_CH1.
MCLKOUT
USIC0_CH0.
DOUT0
P1.2
CCU40.IN1A
USIC0_CH1.
DX1C
USIC0_CH0.
DX1A
USIC0_CH0.
DX0B
USIC0_CH0.
DOUT0
USIC0_CH0.
HWIN0
USIC0_CH0.
DX0C
USIC0_CH1.
SELO0
USIC0_CH0.
DOUT1
USIC0_CH0.
HWIN1
USIC0_CH0.
DX0D
USIC0_CH1.
DOUT0
USIC0_CH0.
DOUT2
USIC0_CH0.
HWIN2
USIC0_CH1.
DX0B
USIC0_CH0.
DX1D
USIC0_CH1.
DOUT0
USIC0_CH0.
DOUT3
USIC0_CH0.
HWIN3
USIC0_CH1.
DX0A
USIC0_CH1.
DX1A
USIC0_CH1.
SELO1
USIC0_CH0.
DX5E
USIC0_CH1.
DX5E
USIC0_CH1.
SELO2
USIC0_CH1.
DX5F
USIC0_CH1.
DX2E
XMC1100
XMC1000 Family
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
P0.11
Input
Data Sheet
Table 8
Port I/O Functions (cont’d)
Function
Outputs
ALT3
ALT4
ALT2
P1.6
VADC0.
EMUX12
USIC0_CH1.D
OUT0
P2.0
ERU0.
PDOUT3
CCU40.OUT0 ERU0.
GOUT3
USIC0_CH0.
DOUT0
USIC0_CH0.
SCLKOUT
P2.1
ERU0.
PDOUT2
CCU40.OUT1 ERU0.
GOUT2
USIC0_CH0.
DOUT0
USIC0_CH1.
SCLKOUT
USIC0_CH0.S
CLKOUT
ALT5
Inputs
ALT1
ALT6
ALT7
HWO0
HWO1
HWI0
HWI1
Input
Input
USIC0_CH0.S USIC0_CH1.S
ELO2
ELO3
P2.2
Input
Input
Input
Input
Input
ERU0.0B0
USIC0_CH0.
DX0E
USIC0_CH0.
DX1E
USIC0_CH1.
DX2F
USIC0_CH0.D
X5F
VADC0.
G0CH5
VADC0.
G0CH6
ERU0.1B0
USIC0_CH0.
DX0F
USIC0_CH1.
DX3A
USIC0_CH1.
DX4A
VADC0.
G0CH7
ERU0.0B1
USIC0_CH0.
DX3A
USIC0_CH0.
DX4A
USIC0_CH1.
DX5A
P2.3
VADC0.
G1CH5
ERU0.1B1
USIC0_CH0.
DX5B
USIC0_CH1.
DX3C
USIC0_CH1.
DX4C
P2.4
VADC0.
G1CH6
ERU0.0A1
USIC0_CH0.
DX3B
USIC0_CH0.
DX4B
USIC0_CH1.
DX5B
P2.5
VADC0.
G1CH7
ERU0.1A1
USIC0_CH0.
DX5D
USIC0_CH1.
DX3E
USIC0_CH1.
DX4E
P2.6
VADC0.
G0CH0
ERU0.2A1
USIC0_CH0.
DX3E
USIC0_CH0.
DX4E
USIC0_CH1.
DX5D
P2.7
VADC0.
G1CH1
ERU0.3A1
USIC0_CH0.
DX5C
USIC0_CH1.
DX3D
USIC0_CH1.
DX4D
P2.8
VADC0.
G0CH1
ERU0.3B1
USIC0_CH0.
DX3D
USIC0_CH0.
DX4D
USIC0_CH1.
DX5C
22
P2.9
ERU0.
PDOUT1
CCU40.OUT2 ERU0.
GOUT1
P2.11
ERU0.
PDOUT0
CCU40.OUT3 ERU0.
GOUT0
USIC0_CH1.
SCLKOUT
VADC0.
G0CH2
VADC0.
G1CH4
ERU0.3B0
USIC0_CH0.
DX5A
USIC0_CH1.
DX3B
USIC0_CH1.
DX4B
USIC0_CH1.
DOUT0
VADC0.
G0CH3
VADC0.
G1CH2
ERU0.2B0
USIC0_CH0.
DX3C
USIC0_CH0.
DX4C
USIC0_CH1.
DX0F
USIC0_CH1.
DOUT0
VADC0.
G0CH4
VADC0.
G1CH3
ERU0.2B1
USIC0_CH1.
DX0E
USIC0_CH1.
DX1E
XMC1100
XMC1000 Family
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
P2.10
VADC0.
G1CH0
XMC1100
XMC1000 Family
Electrical Parameter
3
Electrical Parameter
This section provides the electrical parameter which are implementation-specific for the
XMC1100.
3.1
General Parameters
3.1.1
Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the XMC1100
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are indicated by the abbreviations in the
“Symbol” column:
•
•
CC
Such parameters indicate Controller Characteristics, which are distinctive feature of
the XMC1100 and must be regarded for a system design.
SR
Such parameters indicate System Requirements, which must be provided by the
application system in which the XMC1100 is designed in.
Data Sheet
23
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
3.1.2
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 9
Absolute Maximum Rating Parameters
Parameter
Symbol
Values
Min. Typ. Max.
Unit Note /
Test Cond
ition
115
°C
–
125
°C
–
6
V
–
TJ
SR -40 –
TS
SR -40 –
VDDP SR -0.3 –
Voltage on any pin with
respect to VSSP
VIN
VDDP + 0.5 V
Voltage on any analog input
pin with respect to VSSP
VAIN
-0.5 –
VAREF SR
IIN
SR -10 –
10
mA
–
Absolute sum of all input
currents during overload
condition
Σ|IIN| SR −
50
mA
–
Analog comparator input
voltage
VCM
Junction temperature
Storage temperature
Voltage on power supply pin
with respect to VSSP
Input current on any pin
during overload condition
Data Sheet
SR -0.5 –
SR
–
-0.3 –
24
or max. 6
whichever
is lower
VDDP + 0.5 V
–
or max. 6
VDDP + 0.3 V
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
3.1.3
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the XMC1100. All parameters specified in the following tables
refer to these operating conditions, unless noted otherwise.
Table 10
Operating Conditions Parameters
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
°C
Temp. Range F
Temp. Range X
Ambient Temperature
TA SR
-40
−
85
-40
−
105
°C
Digital supply voltage1)
VDDP SR
fMCLK CC
fPCLK CC
1.8
−
5.5
V
−
−
33.2
MHz CPU clock
−
−
66.4
MHz Peripherals
clock
MCLK Frequency
PCLK Frequency
1) See also the Supply Monitoring thresholds, Chapter 3.3.3.
Data Sheet
25
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
3.2
DC Parameters
3.2.1
Input/Output Characteristics
Table 11 provides the characteristics of the input/output pins of the XMC1100.
Table 11
Input/Output Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Min.
Output low voltage on
port pins
(with standard pads)
VOLP
Output low voltage on
high current pads
VOLP1
Output high voltage on
port pins
(with standard pads)
VOHP
Unit
Test Conditions
V
IOL = 11 mA (5 V)
IOL = 7 mA (3.3 V)
IOL = 5 mA (5 V)
IOL = 3.5 mA (3.3 V)
IOL = 50 mA (5 V)
IOL = 25 mA (3.3 V)
IOL = 10 mA (5 V)
IOL = 5 mA (3.3 V)
IOH = -10 mA (5 V)
IOH = -7 mA (3.3 V)
IOH = -4.5 mA (5 V)
IOH = -2.5 mA (3.3 V)
IOH = -6 mA (5 V)
V
IOH = -8 mA (3.3 V)
V
IOH = -4 mA (3.3 V)
0.19 × V
CMOS Mode
(5 V, 3.3 V & 2.2 V)
Max.
CC –
1.0
V
–
0.4
V
CC –
1.0
V
–
0.32
V
–
0.4
V
–
V
VDDP - –
V
CC VDDP 1.0
0.4
Output high voltage on
high current pads
VOHP1 CC VDDP - –
0.32
VDDP - –
1.0
VDDP - –
0.4
Input low voltage on port VILPS
pins
(Standard Hysteresis)
SR
VIHPS
SR
Input high voltage on
port pins
(Standard Hysteresis)
Input low voltage on port VILPL
pins
(Large Hysteresis)
Data Sheet
–
VDDP
0.7 ×
–
V
VDDP
SR
0.08 × V
–
VDDP
26
CMOS Mode
(5 V, 3.3 V & 2.2 V)
CMOS Mode
(5 V, 3.3 V & 2.2 V)3)
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
Table 11
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values
Min.
Input high voltage on
port pins
(Large Hysteresis)
VIHPL
Input Hysteresis1)
HYS
SR
Unit
Test Conditions
V
CMOS Mode
(5 V, 3.3 V & 2.2 V)3)
V
CMOS Mode (5 V),
Standard Hysteresis
V
CMOS Mode (3.3 V),
Standard Hysteresis
V
CMOS Mode (2.2 V),
Standard Hysteresis
Max.
0.85 × –
VDDP
CC 0.08 × –
VDDP
0.03 × –
VDDP
0.02 × –
VDDP
0.5 ×
0.75 × V
VDDP
VDDP
0.4 ×
0.75 × V
VDDP
VDDP
0.2 ×
0.65 × V
VDDP
VDDP
CMOS Mode(5 V),
Large Hysteresis
CMOS Mode(3.3 V),
Large Hysteresis
CMOS Mode(2.2 V),
Large Hysteresis
Pull-up resistor on port
pins
RPUP
CC 20
50
kohm VIN = VSSP
Pull-down resistor on
port pins
RPDP
CC 20
50
kohm VIN = VDDP
Input leakage current2)
IOZP
CC -1
1
μA
SR
-5
5
mA
Overload current on any IOVP
pin
0 < VIN < VDDP,
TA ≤ 105 °C
Absolute sum of
overload currents
Σ|IOV|
SR
–
25
mA
3)
Voltage on any pin
during VDDP power off
VPO
SR
–
0.3
V
4)
Maximum current per
pin (excluding P1, VDDP
and VSS)
IMP
SR
-10
11
mA
–
Maximum current per
high currrent pins
IMP1A
SR
-10
50
mA
–
Data Sheet
27
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
Table 11
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values
Min.
Unit
Test Conditions
Max.
Maximum current into
VDDP (TSSOP28/16,
VQFN24)
IMVDD1 SR –
130
mA
3)
Maximum current into
VDDP (TSSOP38,
VQFN40)
IMVDD2 SR –
260
mA
3)
Maximum current out of IMVSS1 SR
VSS (TSSOP28/16,
VQFN24)
–
130
mA
3)
Maximum current out of IMVSS2 SR
VSS (TSSOP38,
VQFN40)
–
260
mA
3)
1) Not subject to production test, verified by design/characterization. Hysteresis is implemented to avoid meta
stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses
switching due to external system noise.
2) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.
3) Not subject to production test, verified by design/characterization.
4) Not subject to production test, verified by design/characterization. However, for applications with strict low
power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin
when VDDP is powered off.
Data Sheet
28
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
3.2.2
Analog to Digital Converters (ADC)
Table 12 shows the Analog to Digital Converter (ADC) characteristics.
Table 12
ADC Characteristics (Operating Conditions apply)
Parameter
Supply voltage range
(internal reference)
Symbol
VDD_int SR
Values
Typ.
Max.
1.8
–
3.0
V
SHSCFG.AREF =
11B
3.0
–
5.5
V
SHSCFG.AREF =
10B
3.0
–
5.5
V
SHSCFG.AREF =
00B
VSSP
–
VDDP
V
VDD_ext SR
Analog input voltage
range
VAIN SR
Auxiliary analog
reference ground
(SH0-CH0, SH1-CH0)
VREFGND SR VSSP
Internal reference
voltage (full scale
value)
VREFINT CC 4.82
Switched capacitance
of an analog input1)
CAINS CC
Total capacitance of
the reference input
- 0.05
Data Sheet
+ 0.05
–
- 0.05
CAREFT CC
Note /
Test Condition
Min.
Supply voltage range
(external reference)
Total capacitance of an CAINT CC
analog input
Unit
VDDP
V
+ 0.05
5
5.18
V
-40°C - 105°C
4.9
5
5.1
V
0°C - 85°C 1)
–
1.2
2
pF
GNCTRxz.GAINy
= 00B (unity gain)
–
1.2
2
pF
GNCTRxz.GAINy
= 01B (gain g1)
–
4.5
6
pF
GNCTRxz.GAINy
= 10B (gain g2)
–
4.5
6
pF
GNCTRxz.GAINy
= 11B (gain g3)
–
–
10
pF
1)
–
–
10
pF
1)
29
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
Table 12
ADC Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Values
Min.
Gain settings
Sample Time
GIN CC
tsample CC
3
Unit
Note /
Test Condition
1
–
GNCTRxz.GAINy
= 00B (unity gain)
3
–
GNCTRxz.GAINy
= 01B (gain g1)
6
–
GNCTRxz.GAINy
= 10B (gain g2)
12
–
GNCTRxz.GAINy
= 11B (gain g3)
1/
VDDP = 5.0 V
Typ.
–
Max.
–
fADC
3
–
–
1/
VDDP = 3.3 V
fADC
30
–
–
1/
VDDP = 1.8 V
fADC
Sigma delta loop hold
time
tSD_hold CC
Conversion time
in fast compare mode
tCF CC
Conversion time
in 12-bit mode
tC12 CC
Maximum sample rate
in 12-bit mode 3)
fC12 CC
20
–
–
9
μs
Residual charge
stored in an active
sigma delta loop
remains available
1/
2)
fADC
20
1/
–
fADC /
–
–
1 sample
pending
–
2 samples
pending
1/
2)
42.5
–
fADC /
–
62.5
Conversion time
in 10-bit mode
tC10 CC
Maximum sample rate
in 10-bit mode 3)
fC10 CC
18
fADC
–
fADC /
–
–
1 sample
pending
–
2 samples
pending
1/
2)
40.5
–
fADC /
–
58.5
Conversion time
in 8-bit mode
Data Sheet
2)
fADC
tC8 CC
16
fADC
30
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XMC1100
XMC1000 Family
Electrical Parameter
Table 12
ADC Characteristics (Operating Conditions apply) (cont’d)
Parameter
Maximum sample rate
in 8-bit mode 3)
Symbol
fC8 CC
Values
Min.
Typ.
Max.
–
–
fADC /
Unit
Note /
Test Condition
–
1 sample
pending
–
2 samples
pending
38.5
–
–
fADC /
54.5
DNL error
EADNL CC
–
±2.0
–
LSB
12
INL error
EAINL CC
–
±4.0
–
LSB
12
Gain error with external EAGAIN CC
reference
–
±0.5
–
%
SHSCFG.AREF =
00B (calibrated)
Gain error with internal EAGAIN CC
reference
–
±3.6
–
%
SHSCFG.AREF =
1XB (calibrated),
-40°C - 105°C
–
±2.0
–
%
SHSCFG.AREF =
1XB (calibrated),
0°C - 85°C
–
±6.0
–
LSB
12
Calibrated
Offset error
EAOFF CC
1) Not subject to production test, verified by design/characterization.
2) No pending samples assumed, excluding sampling time and calibration.
3) Includes synchronization and calibration (average of gain and offset calibration).
Data Sheet
31
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
VAIN
0
VSS
1X
VAREF
VREFINT
00
1
VREFGND
VDD
SAR
Converter
:
VAGND
CH7
.
.
CH0
Internal
Reference
VDDint/
VDD
VDDext
CHNR
REFSEL
AREF
MC_VADC_AREFPATHS
Figure 8
Data Sheet
ADC Voltage Supply
32
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XMC1100
XMC1000 Family
Electrical Parameter
3.2.3
Table 13
Temperature Sensor Characteristics
Temperature Sensor Characteristics1)
Parameter
Symbol
Values
Min.
Measurement time
Temperature sensor range
Sensor Accuracy
2)
tM CC
−
TSR SR
-40
TTSAL CC −
Typ.
Max.
Unit Note /
Test Condition
−
10
ms
−
115
°C
+/-20
−
°C
TJ = -40 °C
(calibrated)
−
+/-12
−
°C
TJ = -25 °C
(calibrated)
-5
−
5
°C
-2
−
2
°C
TJ = 0 °C
TJ = 25 °C
(calibrated)
-4
−
4
°C
-2
−
2
°C
TJ = 70 °C
TJ = 115 °C
(calibrated)
1) Not subject to production test, verified by design/characterization.
2) The temperature sensor accuracy is independent of the supply voltage.
Data Sheet
33
V1.4, 2014-05
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XMC1100
XMC1000 Family
Electrical Parameter
3.2.4
Power Supply Current
The total power supply current defined below consists of a leakage and a switching
component.
Application relevant values are typically lower than those given in the following tables,
and depend on the customer's system operating conditions (e.g. thermal connection or
used application configurations).
Table 14
Power Supply Parameters1)
Parameter
Symbol
Values
Min. Typ.
2)
Unit
Note /
Test Condition
fMCLK = 32 MHz
fPCLK = 64 MHz
fMCLK = 1 MHz
fPCLK = 1 MHz
fMCLK = 32 MHz
fPCLK = 64 MHz
fMCLK = 1 MHz
fPCLK = 1 MHz
Max.
IDDPA CC −
8.4
11.0
mA
−
3.7
−
mA
IDDPSE CC −
Sleep mode current
Peripherals clock enabled4)
5.9
−
mA
IDDPSD CC −
Sleep mode current
Peripherals clock disabled5)
1.2
−
mA
Deep Sleep mode current6) IDDPDS CC −
Active mode current3)
0.24
−
mA
Wake-up time from Sleep to tSSA CC
Active mode7)
−
6
−
cycles
tDSA CC
−
280
−
μsec
Wake-up time from Deep
Sleep to Active mode8)
1) Not all parameters are 100% tested, but are verified by design/characterisation and test correlation.
2) The typical values are measured at TA = + 25 °C and VDDP = 5 V.
3) CPU and all peripherals clock enabled, Flash is in active mode.
4) CPU is sleep, all peripherals clock enabled and Flash is in active mode.
5) CPU is sleep, Flash is powered down and code executed from RAM after wake-up.
6) CPU is sleep, peripherals clock disabled, Flash is powered down and code executed from RAM after wake-up.
7) CPU is sleep, Flash is in active mode during sleep mode.
8) CPU is sleep, Flash is in power down mode during deep sleep mode.
Data Sheet
34
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
Table 15 provides the active current consumption of some modules operating at 5 V
power supply at 25° C. The typical values shown are used as a reference guide on the
current consumption when these modules are enabled.
Table 15
Typical Active Current Consumption1)
Active Current
Consumption
Symbol
Limit
Values
Unit
Test Condition
Typ.
Baseload current
ICPUDDC
5.04
mA
Modules including Core, SCU,
PORT, memories, ANATOP2)
VADC and SHS
IADCDDC
IUSIC0DDC
ICCU40DDC
IWDTDDC
IRTCDDC
3.4
mA
Set CGATCLR0.VADC to 13)
0.87
mA
Set CGATCLR0.USIC0 to 14)
0.94
mA
Set CGATCLR0.CCU40 to 15)
0.03
mA
Set CGATCLR0.WDT to 16)
0.01
mA
Set CGATCLR0.RTC to 17)
USIC0
CCU40
WDT
RTC
1) Not subject to production test, verified by design/characterisation.
2) Baseload current is measured with device running in user mode, MCLK=PCLK=32 MHz, with an endless loop
in the flash memory. The clock to the modules stated in CGATSTAT0 are gated.
3) Active current is measured with: module enabled, MCLK=32 MHz, running in auto-scan conversion mode
4) Active current is measured with: module enabled, alternating messages sent to PC at 57.6kbaud every 200ms
5) Active current is measured with: module enabled, MCLK=PCLK=32 MHz, 1 CCU4 slice for PWM switching
from 1500Hz and 1000Hz at regular intervals, 1 CCU4 slice in capture mode for reading period and duty cycle
6) Active current is measured with: module enabled, MCLK=32 MHz, time-out mode; WLB = 0, WUB =
0x00008000; WDT serviced every 1s
7) Active current is measured with: module enabled, MCLK=32 MHz, Periodic interrupt enabled
Data Sheet
35
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
3.2.5
Flash Memory Parameters
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 16
Flash Memory Parameters
Parameter
Symbol
6.8
7.1
7.6
ms
102
152
204
μs
−
32.2 −
μs
−
50
−
ns
10
−
−
years
NWSFLASH CC 0
0.5
−
0
1.4
−
1
1.9
−
−
−
5*104 cycles
−
−
2*106 cycles
tERASE CC
Program time per block tPSER CC
Wake-Up time
tWU CC
ta CC
Read time per word
Data Retention Time
tRET CC
Erase Cycles per page NECYC CC
Total Erase Cycles
Unit
Typ. Max.
Erase Time per page
Flash Wait States 1)
Values
Min.
NTECYC CC
Note /
Test Condition
Max. 100 erase /
program cycles
fMCLK = 8 MHz
fMCLK = 16 MHz
fMCLK = 32 MHz
1) Flash wait states are automatically inserted by the Flash module during memory read when needed. Typical
values are calculated from the execution of the Dhrystone benchmark program.
Data Sheet
36
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
3.3
AC Parameters
3.3.1
Testing Waveforms
VD D P
VSS
90%
90%
10%
10%
tR
Figure 9
tF
Rise/Fall Time Parameters
VD D P
VD D P / 2
Test Points
VD D P / 2
VSS
Figure 10
Testing Waveform, Output Delay
VL OAD + 0.1V
VL OAD - 0.1V
Figure 11
Data Sheet
Timing
Reference
Points
VOH - 0.1V
VOL + 0.1V
Testing Waveform, Output High Impedance
37
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XMC1100
XMC1000 Family
Electrical Parameter
3.3.2
Output Rise/Fall Times
Table 17 provides the characteristics of the output rise/fall times in the XMC1100.
Figure 9 describes the rise time and fall time parameters.
Table 17
Output Rise/Fall Times Parameters (Operating Conditions apply)
Parameter
Rise/fall times on High
Current Pad1)2)
Rise/fall times on
Standard Pad1)2)
Symbol
tHCPR,
tHCPF
tR, tF
Limit Values
Unit Test Conditions
Min.
Max.
–
9
ns
50 pF @ 5 V3)
–
12
ns
50 pF @ 3.3 V4)
–
25
ns
50 pF @ 1.8 V5)
–
12
ns
50 pF @ 5 V6)
–
15
ns
50 pF @ 3.3 V7).
–
31
ns
50 pF @ 1.8 V8).
1) Rise/Fall time parameters are taken with 10% - 90% of supply.
2) Not all parameters are 100% tested, but are verified by design/characterisation and test correlation.
3) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.150 ns/pF at 5 V supply voltage.
4) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.205 ns/pF at 3.3 V supply voltage.
5) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.445 ns/pF at 1.8 V supply voltage.
6) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.225 ns/pF at 5 V supply voltage.
7) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.288 ns/pF at 3.3 V supply voltage.
8) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.588 ns/pF at 1.8 V supply voltage.
Data Sheet
38
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
3.3.3
Power-Up and Supply Threshold Charcteristics
Table 18 provides the characteristics of the supply threshold in XMC1100.
Table 18
Power-Up and Supply Threshold Parameters (Operating Conditions
apply) 1)
Parameter
Symbol
Values
VDDP ramp-up time
tRAMPUP SR
VDDP/
−
SVDDPrise
107
μs
VDDP slew rate
SVDDPOP SR
0
−
0.1
V/μs Slope during
normal operation
SVDDP10 SR
0
−
10
V/μs Slope during fast
transient within +/10% of VDDP
SVDDPrise SR 0
−
10
V/μs Slope during
power-on or
restart after
brownout event
SVDDPfall2) SR 0
−
0.25
V/μs Slope during
supply falling out
of the +/-10%
limits3)
VDDPPW CC
2.1
2.25
2.4
V
ANAVDEL.VDEL_
SELECT = 00B
2.85
3
3.15
V
ANAVDEL.VDEL_
SELECT = 01B
4.2
4.4
4.6
V
ANAVDEL.VDEL_
SELECT = 10B
Min.
VDDP prewarning
voltage
Unit
Typ. Max.
Note /
Test Condition
VDDP brownout reset
voltage
VDDPBO CC
1.55
1.62
1.75
V
calibrated, before
user code starts
running
Start-up time from
power-on reset
tSSW SR
−
320
–
μs
Time to the first
user code
instruction4)
1) Not all parameters are 100% tested, but are verified by design/characterisation.
2) A capacitor of at least 100 nF has to be added between VDDP and VSSP to fulfill the requirement as stated for
this parameter.
Data Sheet
39
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
3) Valid for a 100 nF buffer capacitor connected to supply pin where current from capacitor is forwarded only to
the chip. A larger capacitor value has to be chosen if the power source sink a current.
4) This values does not include the ramp-up time. During startup firmware execution, MCLK is running at 32 MHz
and the clocks to peripheral as specified in register CGATSTAT0 are gated.
5.0V
}
VDDP
VDDPPW
V DDPBO
Figure 12
Data Sheet
Supply Threshold Parameters
40
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XMC1100
XMC1000 Family
Electrical Parameter
3.3.4
On-Chip Oscillator Characteristics
Table 19 provides the characteristics of the 64 MHz clock output from the digital
controlled oscillator, DCO1 in XMC1100.
Table 19
64 MHz DCO1 Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Nominal frequency
fNOM CC 63.5
64
64.5
MHz under nominal
conditions1) after
trimming
Accuracy
ΔfLT
-1.7
–
3.4
%
with respect to fNOM(typ),
over temperature
(0 °C to 85 °C)2)
-3.9
–
4.0
%
with respect to fNOM(typ),
over temperature
(-40 °C to 105 °C)2)
-1.3
–
1.25
%
with respect to fNOM(typ),
over temperature
(TA = 0 °C to 105 °C)2)
-2.6
–
1.25
%
with respect to fNOM(typ),
over temperature
(TA = -40 °C to 105 °C)2)
Min.
CC
Accuracy with
ΔfLTT CC
calibration based on
temperature sensor
Unit Test Conditions
Typ. Max.
1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA = + 25 °C.
2) Not subject to production test, verified by design/characterisation.
Data Sheet
41
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
Figure 13 shows the typical curves for the accuracy of DCO1, with and without
calibration based on temperature sensor, respectively.
4.00
3.00
Accuracy [%]
2.00
Without calibration based
on temperature sensor
1.00
With calibration based on
temperature sensor
0.00
- 1.00
- 2.00
- 3.00
- 4.00
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100 110 120
Temperature [ °C]
Figure 13
Typical DCO1 accuracy over temperature
Table 20 provides the characteristics of the 32 kHz clock output from digital controlled
oscillators, DCO2 in XMC1100.
Table 20
32 kHz DCO2 Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Nominal frequency
fNOM CC 32.5
32.75 33
kHz under nominal
conditions1) after trimming
Accuracy
ΔfLT CC -1.7
–
3.4
%
with respect to fNOM(typ),
over temperature
(0 °C to 85 °C)2)
-3.9
–
4.0
%
with respect to fNOM(typ),
over temperature
(-40 °C to 105 °C)2)
Min.
Typ.
Unit Test Conditions
Max.
1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA = + 25 °C.
2) Not subject to production test, verified by design/characterisation.
Data Sheet
42
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
3.3.5
Serial Wire Debug Port (SW-DP) Timing
The following parameters are applicable for communication through the SW-DP
interface.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 21
SWD Interface Timing Parameters(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
t1 SR
t2 SR
t3 SR
50
–
500000 ns
–
50
–
500000 ns
–
10
–
–
ns
–
SWDIO input hold
t4 SR
after SWDCLK rising edge
10
–
–
ns
–
SWDCLK high time
SWDCLK low time
SWDIO input setup
to SWDCLK rising edge
SWDIO output valid time t5
after SWDCLK rising edge
CC –
–
68
ns
CL = 50 pF
–
–
62
ns
CL = 30 pF
t6
SWDIO output hold time
from SWDCLK rising edge
CC 4
–
–
ns
t1
t2
SWDCLK
t6
SWDIO
(Output )
t5
t3
t4
SWDIO
(Input )
Figure 14
Data Sheet
SWD Timing
43
V1.4, 2014-05
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XMC1100
XMC1000 Family
Electrical Parameter
3.3.6
SPD Timing Requirements
The optimum SPD decision time between 0B and 1B is 0.75 µs. With this value the
system has maximum robustness against frequency deviations of the sampling clock on
tool and on device side. However it is not always possible to exactly match this value
with the given constraints for the sample clock. For instance for a oversampling rate of
4, the sample clock will be 8 MHz and in this case the closest possible effective decision
time is 5.5 clock cycles (0.69 µs).
Table 22
Optimum Number of Sample Clocks for SPD
Sample
Effective Remark
Sample Sampling Sample
Freq.
Factor
Clocks 0B Clocks 1B Decision
Time1)
8 MHz
4
1 to 5
6 to 12
0.69 µs
The other closest option
(0.81 µs) for the effective
decision time is less robust.
1) Nominal sample frequency period multiplied with 0.5 + (max. number of 0B sample clocks)
For a balanced distribution of the timing robustness of SPD between tool and device, the
timing requirements for the tool are:
•
•
Frequency deviation of the sample clock is +/- 5%
Effective decision time is between 0.69 µs and 0.75 µs (calculated with nominal
sample frequency)
Data Sheet
44
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
3.3.7
Peripheral Timings
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
3.3.7.1
Synchronous Serial Interface (USIC SSC) Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: Operating Conditions apply.
Table 23
USIC SSC Master Mode Timing
Parameter
Symbol
Values
Min.
Unit
Typ. Max.
Slave select output SELO t1
active to first SCLKOUT
transmit edge
CC 80
−
−
ns
Slave select output SELO t2
inactive after last
SCLKOUT receive edge
CC 0
−
−
ns
CC -10
−
10
ns
Receive data input
t4
DX0/DX[5:3] setup time to
SCLKOUT receive edge
SR 80
−
−
ns
Data input DX0/DX[5:3]
t5
hold time from SCLKOUT
receive edge
SR 0
−
−
ns
Data output DOUT[3:0]
valid time
Table 24
t3
USIC SSC Slave Mode Timing
Parameter
Symbol
Values
Min.
Unit
Typ. Max.
t10
Select input DX2 setup to
first clock input DX1 transmit
edge1)
SR 10
−
−
ns
t11
SR 10
−
−
ns
Select input DX2 hold after
last clock input DX1 receive
edge1)
Data Sheet
Note /
Test Condition
45
Note /
Test Condition
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Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
Table 24
USIC SSC Slave Mode Timing (cont’d)
Parameter
Symbol
Values
Min.
Unit
Typ. Max.
t12
SR 10
−
−
ns
Data input DX0/DX[5:3] hold t13
time from clock input DX1
receive edge1)
SR 10
−
−
ns
Data output DOUT[3:0] valid t14
time
CC -
−
80
ns
Receive data input
DX0/DX[5:3] setup time to
shift clock receive edge1)
Note /
Test Condition
1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Data Sheet
46
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
Master Mode Timing
t1
Select Output
SELOx
t2
Inactive
Inactive
Active
Clock Output
SCLKOUT
Receive
Edge
First Transmit
Edge
t3
Last Receive
Edge
Transmit
Edge
t3
Data Output
DOUT[3:0]
t4
Data Input
DX0/DX[5:3]
t4
t5
Data
valid
t5
Data
valid
Slave Mode Timing
t1 0
Select Input
DX2
Clock Input
DX1
t1 1
Active
Inactive
Receive
Edge
First Transmit
Edge
t1 2
Data Input
DX0/DX[5:3]
Inactive
Last Receive
Edge
Transmit
Edge
t1 2
t1 3
Data
valid
t13
Data
valid
t14
t1 4
Data Output
DOUT[3:0]
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched
.
Drawn for BRGH .SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal.
USIC_SSC_TMGX.VSD
Figure 15
USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration, for which the slave select
signal is low-active, and the serial clock signal is not shifted and not inverted.
Data Sheet
47
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
3.3.7.2
Inter-IC (IIC) Interface Timing
The following parameters are applicable for a USIC channel operated in IIC mode.
Note: Operating Conditions apply.
Table 25
USIC IIC Standard Mode Timing1)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Fall time of both SDA and t1
SCL
CC/SR
-
-
300
ns
Rise time of both SDA and t2
SCL
CC/SR
-
-
1000
ns
0
-
-
µs
250
-
-
ns
4.7
-
-
µs
4.0
-
-
µs
4.0
-
-
µs
4.7
-
-
µs
4.0
-
-
µs
4.7
-
-
µs
-
-
400
pF
Data hold time
t3
Note /
Test Condition
CC/SR
Data set-up time
t4
CC/SR
LOW period of SCL clock
t5
CC/SR
HIGH period of SCL clock t6
CC/SR
t7
Hold time for (repeated)
START condition
CC/SR
Set-up time for repeated
START condition
CC/SR
Set-up time for STOP
condition
CC/SR
t8
t9
Bus free time between a
STOP and START
condition
t10
Capacitive load for each
bus line
Cb SR
CC/SR
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Data Sheet
48
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
Table 26
USIC IIC Fast Mode Timing 1)
Parameter
Symbol
Values
Min.
Fall time of both SDA and t1
SCL
CC/SR
Typ.
Unit
Max.
20 +
0.1*Cb
300
ns
20 +
0.1*Cb
300
ns
0
-
-
µs
100
-
-
ns
1.3
-
-
µs
0.6
-
-
µs
0.6
-
-
µs
0.6
-
-
µs
0.6
-
-
µs
1.3
-
-
µs
-
-
400
pF
Note /
Test Condition
2)
Rise time of both SDA and t2
SCL
CC/SR
Data hold time
t3
CC/SR
Data set-up time
t4
CC/SR
LOW period of SCL clock
t5
CC/SR
HIGH period of SCL clock t6
CC/SR
t7
Hold time for (repeated)
START condition
CC/SR
Set-up time for repeated
START condition
CC/SR
Set-up time for STOP
condition
CC/SR
t8
t9
Bus free time between a
STOP and START
condition
t10
Capacitive load for each
bus line
Cb SR
CC/SR
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
2) Cb refers to the total capacitance of one bus line in pF.
Data Sheet
49
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
t1
SDA
t2
t4
70%
30%
t1
t3
t2
t6
SCL
th
t7
9
clock
t5
t10
S
SDA
t8
t7
t9
SCL
th
9
clock
Sr
Figure 16
3.3.7.3
P
S
USIC IIC Stand and Fast Mode Timing
Inter-IC Sound (IIS) Interface Timing
The following parameters are applicable for a USIC channel operated in IIS mode.
Note: Operating Conditions apply.
Table 27
USIC IIS Master Transmitter Timing
Parameter
Clock period
Clock HIGH
Symbol
t1 CC
t2 CC
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
VDDP ≥ 3 V
VDDP < 3 V
2/fMCLK
-
-
ns
4/fMCLK
-
-
ns
0.35 x
-
-
ns
-
-
ns
0
-
-
ns
-
-
0.15 x
ns
t1min
Clock Low
t3 CC
0.35 x
t1min
Hold time
Clock rise time
t4 CC
t5 CC
t1min
Data Sheet
50
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Electrical Parameter
t1
t2
t5
t3
SCK
t4
WA/
DOUT
Figure 17
USIC IIS Master Transmitter Timing
Table 28
USIC IIS Slave Receiver Timing
Parameter
Symbol
t6 SR
t7 SR
Clock period
Clock HIGH
Values
Unit
Min.
Typ.
Max.
4/fMCLK
-
-
ns
0.35 x
-
-
ns
-
-
ns
-
-
ns
-
-
ns
Note /
Test Condition
t6min
t8 SR
Clock Low
0.35 x
t6min
t9 SR
Set-up time
0.2 x
t6min
t10 SR
Hold time
10
t6
t7
t8
SCK
t9
t10
WA/
DIN
Figure 18
Data Sheet
USIC IIS Slave Receiver Timing
51
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XMC1100
XMC1000 Family
Package and Reliability
4
Package and Reliability
The XMC1100 is a member of the XMC1000 Derivatives of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the exposed die pad may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
4.1
Package Parameters
Table 29 provides the thermal characteristics of the packages used in XMC1100.
Table 29
Thermal Characteristics of the Packages
Parameter
Symbol
Limit Values
Exposed Die Pad
Dimensions
Ex × Ey
CC
Thermal resistance
Junction-Ambient
RΘJA CC -
Unit
Package Types
Min.
Max.
-
2.7 × 2.7
mm
PG-VQFN-24-19
-
3.7 × 3.7
mm
PG-VQFN-40-13
104.6
K/W
PG-TSSOP-16-81)
-
70.3
K/W
PG-TSSOP-38-91)
-
46.0
K/W
PG-VQFN-24-191)
-
38.4
K/W
PG-VQFN-40-131)
1) Device mounted on a 4-layer JEDEC board (JESD 51-5); exposed pad soldered.
Note: For electrical reasons, it is required to connect the exposed pad to the board
ground VSSP, independent of EMC and thermal requirements.
4.1.1
Thermal Considerations
When operating the XMC1100 in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting thermal
damage.
The maximum heat that can be dissipated depends on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 115 °C.
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
Data Sheet
52
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Package and Reliability
The internal power consumption is defined as
PINT = VDDP × IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
•
•
•
•
Reduce VDDP, if possible in the system
Reduce the system frequency
Reduce the number of output pins
Reduce the load on active output drivers
Data Sheet
53
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Package and Reliability
4.2
Figure 19
Data Sheet
Package Outlines
PG-TSSOP-38-9
54
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Package and Reliability
Figure 20
Data Sheet
PG-TSSOP-16-8
55
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Package and Reliability
Figure 21
Data Sheet
PG-VQFN-24-19
56
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Package and Reliability
Figure 22
PG-VQFN-40-13
All dimensions in mm.
Data Sheet
57
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Quality Declaration
5
Quality Declaration
Table 30 shows the characteristics of the quality parameters in the XMC1100.
Table 30
Quality Parameters
Parameter
Symbol Limit Values
Unit
Notes
Min.
Max.
VHBM
ESD susceptibility
according to Human Body SR
Model (HBM)
-
2000
V
Conforming to
EIA/JESD22A114-B
ESD susceptibility
according to Charged
Device Model (CDM) pins
VCDM
-
500
V
Conforming to
JESD22-C101-C
Moisture sensitivity level
MSL
-
3
-
JEDEC
J-STD-020C
SR
CC
Data Sheet
58
V1.4, 2014-05
Subject to Agreement on the Use of Product Information
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Published by Infineon Technologies AG