M62393P/FP 8-bit 8ch I2C BUS D/A Converter with Buffer Amplifiers REJ03D0884-0300 Rev.3.00 Mar 25, 2008 Description The M62393P/FP is an integrated circuit semiconductor of CMOS structure with 8 channels of built-in D/A converters with output buffer operational amplifiers. The input is 2-wires serial method is used for the transfer format of digital data to allow connection with a microcomputer with minimum wiring. The output buffer operational amplifier employs AB class output circuit with sink and source drive capacity of 1.0 mA or more, and it operates in the whole voltage range from VrefU to ground. And because of connects maximum 8 pieces to 64 channels control. Features • Digital data transfer format: I2C BUS serial data method • Output buffer operational amplifier It operates in the whole voltage range from VrefU (0 to 5 V) to ground. • High output current drive capacity: ±1.0 mA over • Preparation two high level reference voltage terminal because there are two high level reference voltage terminal, it can set up two kinds differ voltage range. Application Conversion from digital control data to analog control data for home-use and industrial equipment. Signal gain control or automatic adjustment of display-monitor or CTV. Block Diagram CS0 CS1 CS2 20 19 18 VDD AO4 AO3 AO2 AO1 VCC VrefU 2 17 15 14 13 12 16 11 Chip select Address decoder I2C BUS transceiver 1 R + − + − + − + − 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R + + + + 8 2 SCL 3 SDA − − − − 8 4 5 6 7 10 9 VrefL AO5 AO6 AO7 AO8 GND VrefU1 REJ03D0884-0300 Rev.3.00 Mar 25, 2008 Page 1 of 6 M62393P/FP Pin Arrangement M62393P/FP R 1 20 CS0 SCL 2 19 CS1 SDA 3 18 CS2 AO5 4 17 VDD AO6 5 16 VCC AO7 6 15 AO4 AO8 7 14 AO3 VrefL 8 13 AO2 VrefU1 9 12 AO1 GND 10 11 VrefU2 (Top view) Outline: 20P4 PRSP0020DA-A (20P2N-A) Pin Description Pin No. 3 1 2 12 13 14 15 4 5 6 7 16 17 10 8 9 11 18 19 20 Pin Name SDA R SCL Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 Ao7 Ao8 VCC VDD GND VrefL Function Analog power supply terminal Digital power supply terminal Analog and digital common GND D/A converter low level reference voltage input terminal VrefU1 VrefU2 CS2 CS1 CS0 D/A converter high level reference voltage input terminal 1 D/A converter high level reference voltage input terminal 2 Chip select data input terminal 2 Chip select data input terminal 1 Chip select data input terminal 0 Serial data input terminal Reset signal input terminal Serial clock input terminal 8-bit D/A converter output terminal REJ03D0884-0300 Rev.3.00 Mar 25, 2008 Page 2 of 6 M62393P/FP Absolute Maximum Ratings Item Supply voltage Supply voltage D/A converter high level reference voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Symbol VCC VDD VrefU1, 2 VIN VO Pd Topr Tstg Ratings –0.3 to +7.0 –0.3 to +7.0 –0.3 to +7.0 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 990 (P) / 590 (FP) –20 to +85 –40 to +125 Unit V V V V V mW °C °C Electrical Characteristics <Digital Part> (VCC, VDD, VrefU1, 2 = +5 V ± 10%, VCC ≥ VrefU1, 2, GND = VrefL = 0 V, Ta = –20 to +85°C, unless otherwise noted.) Item Symbol Min Limits Typ Max Unit Supply voltage Supply current VDD IDD 4.5 — 5.0 — 5.5 1.0 V mA Output low voltage (SDA) VOL — — 0.4 V Input leak current Input low voltage Input high voltage IILK VIL VIH –10 — 0.8 VCC — — — 10 0.2 VCC — µA V V Conditions CLK = 1 MHz operation, IAO = 0 µA Isink = 3 mA VIN = 0 to VCC <Analog Part> (VCC, VDD, VrefU1, 2 = +5 V ± 10%, VCC ≥ VrefU1, 2, GND = VrefL = 0 V, Ta = –20 to +85°C, unless otherwise noted.) Symbol Min Limits Typ Max Unit VCC ICC IrefU 4.5 — — 5.0 1.6 1.0 5.5 3.2 2.0 V mA mA D/A converter high level reference voltage range VrefU 3.5 — VCC V D/A converter low level reference voltage range VrefL GND — VCC – 3.5 V Buffer amplifier output voltage range VAO Buffer amplifier output current range IAO 0.1 0.2 –1.0 — — — VCC – 0.1 VCC – 0.2 1.0 V V mA Differential nonlinearity Nonlinearity Zero code error Full scale error Output capacitive load SDL SL SZERO SFULL CO Buffer amplifier output impedance RO –1.0 –1.5 –2.0 –2.0 — — — — — — — 5.0 1.0 1.5 2.0 2.0 0.1 — LSB LSB LSB LSB µF Ω Item Supply voltage Supply current D/A converter high level reference voltage input current REJ03D0884-0300 Rev.3.00 Mar 25, 2008 Page 3 of 6 Conditions CLK = 1 MHz operation, IAO = 0 µA VrefU = 5 V, VrefL = 0 V Data condition: at maximum current The output dose not necessarily be the values within the reference voltage setting range. IAO = ±100 µA IAO = ±500 µA Upper side saturation voltage = 0.3 V Lower side saturation voltage = 0.2 V VrefU = 4.79 V VrefL = 0.95 V VCC = 5.5 V (15 mV/LSB) Without load (IAO = 0) M62393P/FP I2C BUS Line Characteristics Item Symbol Normal Mode Min Max High Speed Mode Min Max Unit SCL clock frequency fSCL Time the bus must be free before a new transmission can start tBUF 0 4.7 100 — 0 1.3 400 — kHz µs Hold time start condition. After this period. The first clock pulse is generated. Low period of the clock High period of the clock tHD : STA 4.0 — 0.6 — µs tLOW tHIGH Setup time for start condition (only relevant for a repeated start condition) Hold time data Setup time data Rise time of both SDA and SCL lines Fall time of both SDA and SCL lines Setup time for stop condition tSU : STA 4.7 4.0 4.7 — — — 1.3 0.6 4.7 — — — µs µs µs tHD : DAT tSU : DAT tR tF tSU : STO 0 250 — — 4.0 — — 1000 300 — 0 100 20 20 0.6 0.9 — 300 300 — µs ns ns ns µs Note: Transmitter must internally at reset a hold time to bridge the undefined region (300 ns Max) of the falling edge of SCL. Timing Chart tr, tf tBUF VIH SDA VIL tHD:STA tSU:DAT tHD:DAT tSU:STA tSU:STO VIH SCL VIL tLOW tHIGH Start REJ03D0884-0300 Rev.3.00 Mar 25, 2008 Page 4 of 6 Start Stop Start M62393P/FP I2C BUS Format STA Slave address W A Sub address A DAC data A STP Digital Data Format • Slave Address • Sub Address First 1 Last 0 0 1 A2 (Slave address) A1 First A0 Last X X Chip select data X X S3 S2 S1 S0 Channel select data Don't care • DAC Data First MSB D7 Last LSB D6 D5 D4 D3 D1 D2 (1) Chip Select Data MSB A2 0 A1 0 0 0 : 1 0 1 : 1 LSB A0 0 D0 (2) Channel Select Data CS2 0 CS1 0 CS0 0 0 0 : 1 0 1 : 1 1 0 : 1 1 0 : 1 MSB S3 0 S2 0 S1 0 LSB S0 0 0 0 : 0 1 1 : 1 0 0 : 1 0 0 : 1 0 1 : 1 0 0 : 1 1 0 : 1 0 1 : 1 Channel Selection Don’t care ch1 selection ch2 selection : ch7 selection ch8 selection Don’t care : Don’t care (3) DAC Data First MSB Last LSB D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 : 1 1 0 0 0 0 : 1 1 0 0 0 0 : 1 1 0 0 0 0 : 1 1 0 0 0 0 : 1 1 0 0 0 0 : 1 1 0 0 1 1 : 1 1 0 1 0 1 : 0 1 REJ03D0884-0300 Rev.3.00 Mar 25, 2008 Page 5 of 6 DAC Output (VrefU − VrefL ) / 256 × 1 + VrefL (VrefU − VrefL ) / 256 × 2 + VrefL (VrefU − VrefL ) / 256 × 3 + VrefL (VrefU − VrefL ) / 256 × 4 + VrefL : (VrefU − VrefL ) / 256 × 255 + VrefL VrefU M62393P/FP Package Dimensions 20P4 Plastic 20pin 300mil DIP EIAJ Package Code DIP20-P-300-2.54 Weight(g) 1.3 Lead Material Alloy 42/Cu Alloy 11 1 10 E 20 e1 c JEDEC Code — Symbol D A2 A A1 A2 b b1 b2 c D E e e1 L LA A1 SEATING PLANE e JEITA Package Code P-SOP20-5.3x12.6-1.27 RENESAS Code PRSP0020DA-A b1 b Previous Code 20P2N-A b2 Dimension in Millimeters Min Nom Max 4.5 — — 0.51 — — 3.3 — — 0.4 0.5 0.6 1.4 1.5 1.8 0.9 1.0 1.3 0.22 0.27 0.34 23.8 24.0 24.2 6.15 6.3 6.45 2.54 — — 7.62 — — 3.0 — — 0° 15° — MASS[Typ.] 0.3g 20 E *1 HE 11 F 1 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 10 c Index mark *2 A2 D A1 L A Reference Symbol *3 e bp y Detail F D E A2 A1 A bp c HE e y L REJ03D0884-0300 Rev.3.00 Mar 25, 2008 Page 6 of 6 Dimension in Millimeters Min Nom Max 12.5 12.6 12.7 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0° 8° 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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