IRFHM8342TRPBF Product Datasheet

IRFHM8342TRPbF
HEXFET® Power MOSFET
VDSS
30
RDS(on) max
(@ VGS = 10V)
(@ VGS = 4.5V)
V
16
m
25
Qg (typical)
5.0
nC
ID
(@TC (Bottom) = 25°C)
20
A
PQFN 3.3 x 3.3 mm
Applications

Control MOSFET for synchronous buck converter

Load Switch
Features
Low Charge (typical 5.2 nC)
Low Thermal Resistance to PCB (<6.2°C/W)
Low Profile (<0.9 mm)
Industry-Standard Pinout
Compatible with Existing Surface Mount Techniques
RoHS Compliant, Halogen-Free
MSL1, Consumer Qualification
Base part number
Standard Pack
Form
Quantity
Tape and Reel
4000
Package Type
IRFHM8342PbF
Benefits
Low Switching Losses
Enable better Thermal Dissipation
results in Increased Power Density
 Multi-Vendor Compatibility
Easier Manufacturing
Environmentally Friendlier
Increased Reliability
PQFN 3.3mm x 3.3mm
Orderable Part Number
IRFHM8342TRPbF
Absolute Maximum Ratings
Parameter
Max.
Units
V
VGS
Gate-to-Source Voltage
± 20
ID @ TA = 25°C
Continuous Drain Current, VGS @ 10V
10
ID @ TC(Bottom) = 25°C
Continuous Drain Current, VGS @ 10V
28
ID @ TC(Bottom) = 100°C
Continuous Drain Current, VGS @ 10V
18
IDM
Continuous Drain Current, VGS @ 10V
(Source Bonding Technology Limited)
Pulsed Drain Current 
PD @TA = 25°C
Power Dissipation 
ID @ TC = 25°C
PD @TC(Bottom) = 25°C
A
20
112
2.6
Power Dissipation
W
20
Linear Derating Factor
0.020
W/°C
TJ
Operating Junction and
-55 to + 150
°C
TSTG
Storage Temperature Range
Notes  through  are on page 10
1
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IRFHM8342TRPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
BVDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
BVDSS/TJ
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
VGS(th)
IDSS
IGSS
Gate Threshold Voltage
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
Total Gate Charge
Pre-Vth Gate-to-Source Charge
Gate-to-Drain Charge
Gate Charge Overdrive
Output Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
gfs
Qg
Qg
Qgs
Qgd
Qgodr
Qoss
RG
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Min.
30
–––
–––
–––
1.35
–––
–––
–––
–––
19
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
20
13
20
1.8
-5.2
–––
–––
–––
–––
10
5.0
1.8
1.7
1.5
3.3
2.6
8.1
30
7.6
5.6
560
102
48
Max.
–––
–––
16
25
2.35
–––
1.0
100
-100
–––
–––
7.5
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Units
Conditions
V
VGS = 0V, ID = 250µA
mV/°C Reference to 25°C, ID = 1mA
m VGS = 10V, ID = 17A 
VGS = 4.5V, ID = 14A 
V
VDS = VGS, ID = 25µA
mV/°C
µA VDS = 24V, VGS = 0V
nA VGS = 20V
VGS = -20V
S
VDS = 10V, ID = 17A
nC VGS = 10V, VDS = 15V, ID = 17A
VDS = 15V
nC VGS = 4.5V
ID = 17A
nC
 VDS = 16V, VGS = 0V
ns
VDD = 15V, VGS = 4.5V
ID = 17A
RG=1.8
pF
VGS = 0V
VDS = 25V
ƒ = 1.0MHz
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy 
EAS
Diode Characteristics
Parameter
IS
Continuous Source Current
(Body Diode)
ISM
Pulsed Source Current
(Body Diode) 
VSD
Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
Thermal Resistance
Typ.
–––
Min.
–––
Typ.
–––
Max.
21
Max.
20
Units
Conditions
A
MOSFET symbol
showing the
integral reverse
p-n junction diode.
V
TJ = 25°C, IS = 17A, VGS = 0V 
ns TJ = 25°C, IF = 17A, VDD = 15V
nC di/dt = 330A/µs 
D
–––
–––
112
G
–––
–––
–––
–––
9.4
5.8
1.0
14
8.7
S
Parameter
RJC (Bottom) Junction-to-Case 
Junction-to-Case 
RJC (Top)
Units
mJ
Typ.
–––
Max.
6.2
Units
–––
50
°C/W
RJA
Junction-to-Ambient 
–––
49
RJA (<10s)
Junction-to-Ambient 
–––
34
2
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IRFHM8342TRPbF
1000
1000
100
BOTTOM
100
10
2.75V
BOTTOM
10
2.75V
60µs PULSE WIDTH
60µs PULSE WIDTH
Tj = 150°C
Tj = 25°C
1
1
0.1
1
10
0.1
100
100
1.8
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000
100
TJ = 150°C
10
TJ = 25°C
V DS = 10V
60µs PULSE WIDTH
1.0
ID = 17A
V GS = 10V
1.6
1.4
1.2
1.0
0.8
0.6
1.0
2.0
3.0
4.0
5.0
6.0
7.0
-60 -40 -20 0
V GS, Gate-to-Source Voltage (V)
10000
Fig 4. Normalized On-Resistance vs. Temperature
14.0
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = C gd
V GS, Gate-to-Source Voltage (V)
ID= 17A
Coss = Cds + Cgd
1000
Ciss
Coss
100
20 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
C, Capacitance (pF)
10
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
ID, Drain-to-Source Current (A)
1
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Crss
10
12.0
V DS= 24V
10.0
V DS= 15V
V DS= 6.0V
8.0
6.0
4.0
2.0
0.0
1
10
100
0
V DS, Drain-to-Source Voltage (V)
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2
4
6
8
10
12
14
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
3
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.25V
3.0V
2.75V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.25V
3.0V
2.75V
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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IRFHM8342TRPbF
1000
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
TJ = 150°C
10
TJ = 25°C
1
100
100µsec
1msec
10
1
10msec
0.1
V GS = 0V
0.01
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.1
1.6
1
10
100
VDS, Drain-to-Source Voltage (V)
V SD, Source-to-Drain Voltage (V)
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode Forward Voltage
30
3.0
V GS(th) , Gate threshold Voltage (V)
Limited by package
25
ID, Drain Current (A)
DC
Tc = 25°C
Tj = 150°C
Single Pulse
20
15
10
5
0
2.5
2.0
1.5
1.0
ID = 25µA
ID = 250µA
ID = 1.0mA
ID = 1.0A
0.5
25
50
75
100
125
150
-75 -50 -25
TC , Case Temperature (°C)
0
25
50
75 100 125 150
TJ , Temperature ( °C )
Fig 10. Drain-to-Source Breakdown Voltage
Fig 9. Maximum Drain Current vs. Case Temperature
Thermal Response ( Z thJC ) °C/W
10
D = 0.50
0.20
1
0.10
0.05
0.02
0.01
0.1
SINGLE PULSE
( THERMAL RESPONSE )
0.01
0.001
1E-006
1E-005
0.0001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
4
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IRFHM8342TRPbF
100
50
ID = 17A
EAS , Single Pulse Avalanche Energy (mJ)
RDS(on), Drain-to -Source On Resistance (m )
40
30
TJ = 125°C
20
TJ = 25°C
ID
TOP
2.8A
5.9A
BOTTOM 17A
80
60
40
20
0
10
2
4
6
8
10
12
14
16
18
25
20
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
V GS, Gate -to -Source Voltage (V)
Fig 13. Maximum Avalanche Energy vs. Drain Current
Fig 12. On–Resistance vs. Gate Voltage
100
Avalanche Current (A)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 125°C and
Tstart =25°C (Single Pulse)
10
1
0.1
1.0E-06
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming  j = 25°C and
Tstart = 125°C.
1.0E-05
1.0E-04
1.0E-03
1.0E-02
tav (sec)
Fig 14. Single Avalanche Event: Pulse Current vs. Pulse Width
5
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IRFHM8342TRPbF
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
tp
15V
L
VDS
D.U.T
RG
IAS
20V
tp
DRIVER
+
V
- DD
A
I AS
0.01
Fig 16a. Unclamped Inductive Test Circuit
Fig 16b. Unclamped Inductive Waveforms
Fig 17b. Switching Time Waveforms
Fig 17a. Switching Time Test Circuit
Id
Vds
Vgs
VDD Vgs(th)
Qgs1 Qgs2
Fig 18. Gate Charge Test Circuit
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Qgd
Qgodr
Fig 19. Gate Charge Waveform
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IRFHM8342TRPbF
Placement and Layout Guidelines
The typical application topology for this product is the synchronous buck converter. These converters operate at high
frequencies (typically around 400 kHz). During turn-on and turn-off switching cycles, the high di/dt currents circulating in
the parasitic elements of the circuit induce high voltage ringing which may exceed the device rating and lead to
undesirable effects. One of the major contributors to the increase in parasitics is the PCB power circuit inductance.
This section introduces a simple guideline that mitigates the effect of these parasitics on the performance of the circuit
and provides reliable operation of the devices.
To reduce high frequency switching noise and the effects of Electromagnetic Interference (EMI) when the control
MOSFET (Q1) is turned on, the layout shown in Figure 20 is recommended. The input bypass capacitors, control
MOSFET and output capacitors are placed in a tight loop to minimize parasitic inductance which in turn lowers the
amplitude of the switch node ringing, and minimizes exposure of the MOSFETs to repetitive avalanche conditions.
Fig 20. Placement and Layout Guidelines
7
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IRFHM8342TRPbF
PQFN 3.3 x 3.3 Package Details
For more information on board mounting, including footprint and stencil recommendation, please refer to application note
AN-1136: http://www.irf.com/technical-info/appnotes/an-1136.pdf
For more information on package inspection techniques, please refer to application note AN-1154:
http://www.irf.com/technical-info/appnotes/an-1154.pdf
PQFN 3.3 x 3.3 Part Marking
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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IRFHM8342TRPbF
PQFN 3.3 x 3.3 Tape and Reel
REEL DIMENSIONS
TAPE DIMENSIONS
CODE
Ao
Bo
Ko
DIMENSION (MM)
MIN
MAX
3.50
3.70
3.50
3.70
1.10
1.30
7.90
P1
11.80
W
12.30
W1
Qty
Reel Diameter
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
DIMENSION (INCH)
MIN
MAX
.138
.146
.138
.146
.043
.051
8.10
12.20
12.50
.311
.465
.484
.319
.480
.492
4000
13 Inches
CODE
Ao
Bo
Ko
W
P1
DESCRIPTION
Dimension design to accommodate the component width
Dimension design to accommodate the component lenght
Dimension design to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
9
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IRFHM8342TRPbF
Qualification Information† Consumer
Qualification Level (per JEDEC JESD47F†† guidelines)
MSL1
(per JEDEC J-STD-020D††)
PQFN 3.3mm x 3.3mm
Moisture Sensitivity Level
Yes
RoHS Compliant
† Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability
†† Applicable version of JEDEC standard at the time of product release.
Notes:
 Repetitive rating; pulse width limited by max. junction temperature.
 Starting TJ = 25°C, L = 0.15mH, RG = 50, IAS = 17A.
 Pulse width  400µs; duty cycle  2%.
 R is measured at TJ of approximately 90°C.
 When mounted on 1 inch square PCB (FR-4). Please refer to AN-994 for more details:
http://www.irf.com/technical-info/appnotes/an-994.pdf
 Calculated continuous current based on maximum allowable junction temperature.
 Current is limited to 20A by source bonding technology.
Revision History
Date
Comments
6/6/14


Updated schematic on page 1
Updated tape and reel on page 9
7/1/14

Remove “SAWN” package outline on page 8.
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
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