HT48RA0-6

Remote Type 8-bit MCU
HT48RA0-6
Revision: V1.10
Date: ��
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Table of Contents
Features............................................................................................................. 4
General Description ......................................................................................... 4
Block Diagram................................................................................................... 5
Pin Assignment................................................................................................. 5
Pin Description................................................................................................. 6
Absolute Maximum Ratings............................................................................. 6
D.C. Characteristics.......................................................................................... 7
A.C. Characteristics.......................................................................................... 7
Power-on Reset Characteristics...................................................................... 8
Characteristics Curves..................................................................................... 8
HIRC Oscillator Voltage/Temperature vs. Frequency............................................................... 8
IR Sink Current vs. VDD.......................................................................................................... 9
Functional Description................................................................................... 10
Execution Flow....................................................................................................................... 10
Program Counter – PC........................................................................................................... 10
Program Memory - ROM.........................................................................................................11
Stack...................................................................................................................................... 12
Data Memory – RAM.............................................................................................................. 12
Indirect Addressing Register.................................................................................................. 13
Accumulator........................................................................................................................... 13
Arithmetic and Logic Unit – ALU............................................................................................ 14
Status Register – STATUS..................................................................................................... 14
Oscillator Configuration.......................................................................................................... 14
External Crystal/Ceramic Oscillator – HXT............................................................................ 15
Internal RC Oscillator – HIRC................................................................................................ 15
Watchdog Timer – WDT......................................................................................................... 15
Power Down Operation – HALT............................................................................................. 16
Reset...................................................................................................................................... 17
Input/Output Ports.................................................................................................................. 19
Timer...................................................................................................................................... 20
Timer Operation..................................................................................................................... 20
Carrier Output........................................................................................................................ 22
Low Voltage Reset – LVR...................................................................................................... 25
Configuration Options.................................................................................... 26
Application Circuits........................................................................................ 27
Instruction Set................................................................................................. 29
Introduction............................................................................................................................ 29
Instruction Timing................................................................................................................... 29
Moving and Transferring Data................................................................................................ 29
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HT48RA0-6
Remote Type 8-bit MCU
Arithmetic Operations............................................................................................................. 29
Logical and Rotate Operation................................................................................................ 30
Branches and Control Transfer.............................................................................................. 30
Bit Operations........................................................................................................................ 30
Table Read Operations.......................................................................................................... 30
Other Operations.................................................................................................................... 30
Instruction Set Summary............................................................................... 31
Table Conventions.................................................................................................................. 31
Instruction Definition...................................................................................... 33
Package Information...................................................................................... 42
16-pin NSOP (150mil) Outline Dimensions............................................................................ 42
20-pin SSOP (150mil) Outline Dimensions............................................................................ 43
Product Tape and Reel Specifications.......................................................... 44
Reel Dimensions.................................................................................................................... 44
Carrier Tape Dimensions........................................................................................................ 45
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HT48RA0-6
Remote Type 8-bit MCU
Features
• Operating voltage:
– fSYS=4MHz at VDD=2.0V~3.6V (LVR enabled)
– fSYS=4MHz at VDD=1.8V~3.6V (LVR disabled)
• Oscillator types:
– External high frequency Crystal – HXT
– Internal high frequency RC – HIRC
• 1K×14 program memory
• 32×8 data memory
• One-level subroutine nesting
• 16 bidirectional I/O lines
• Fully integrated internal 4095kHz oscillator requires no external components
• One programmable carrier output - using 9-bit timer
• Carrier output pin (REM/REMDRV)
• Build-in IR Driver ([email protected])
• Watchdog Timer
• Low voltage reset function
• Power-down and wake-up features reduce power consumption
• 14-bit table read instructions
• Up to 1μs instruction cycle with 4MHz system clock
• 63 powerful instructions
• All instructions executed in 1 or 2 machine cycles
• Bit manipulation instructions
• 16-pin NSOP and 20-pin SSOP packages
• HT48RA0-6B use in internal IR driver
General Description
The HT48RA0-6 is 8-bit high performance, RISC architecture microcontroller device specifically
designed for multiple I/O control product applications.
The advantages of low power consumption, I/O flexibility, timer functions, watchdog timer, HALT
and wake-up functions, as well as low cost, enhance the versatility of this device to suit a wide range
of application possibilities such as industrial control, consumer products, and particularly suitable
for use in products such as infrared remote controllers and various subsystem controllers.
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HT48RA0-6
Remote Type 8-bit MCU
Block Diagram

Pin Assignment
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HT48RA0-6
Remote Type 8-bit MCU
Pin Description
Pin Name
PA0~PA7
PB0~PB3
PB5/OSC2
PB6/OSC1
PB7
I/O
Configuration
Option
Description
I/O
—
Bidirectional 8-bit input/output port with pull-high resistors. Software
instructions determine if the pin is an NMOS output or Schmitt Trigger
input. Each pin can have a wake-up function if configured as an input pin.
OSC
Bidirectional 7-bit input/output port with pull-high resistors. Software
instructions determine if the pin is an NMOS output or Schmitt Trigger
input. Each pin can have a wake-up function if configured as an input
pin. PB5 and PB6 are pin-shared with the external crystal pins named
OSC2 and OSC1 respectively determined by a configuration option.
RES
Bidirectional 1-bit input/output port without a pull-high resistor. Software
instructions determine if the pin is an NMOS output or Schmitt Trigger
input. This pin has the capability of wake-up when it is configured as
an input pin. PC0 is pin-shared with the external reset pin named RES
determined by a configuration option.
I/O
PC0/RES
ST
Carrier output dual function pin. REM is a CMOS carrier output pin
with an initial low level after a reset. REMDRV pin is a high sink current
REM/REMDRV NMOS open drain carrier output pin which will be in a floating condition
after a reset. The selection of REM or REMDRV is determined by a
configuration option.
REM/REMDRV
O
VDD
—
—
Positive power supply
VSS
—
—
Negative power supply, ground
VSS1
—
—
Negative power supply, ground of REM/REMDRV pin.
Absolute Maximum Ratings
Supply Voltage.................................................................................................VSS−0.3V to VSS+4.0V
Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V
Storage Temperature.....................................................................................................-50˚C to 125˚C
Operating Temperature...................................................................................................-20˚C to 70˚C
IOH Total...................................................................................................................................-100mA
IOL Total.................................................................................................................................... 150mA
Total Power Dissipation ......................................................................................................... 500mW
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum
Ratings" may cause substantial damage to these devices. Functional operation of these devices at
other conditions beyond those listed in the specification is not implied and prolonged exposure to
extreme conditions may affect devices reliability.
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HT48RA0-6
Remote Type 8-bit MCU
D.C. Characteristics
Ta= 25˚C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
LVR disable
1.8
─
3.6
V
LVR enable
2.0
─
3.6
V
VDD
Conditions
VDD
Operating Voltage
—
IDD
Operating Current
3V
No load, fSYS=4MHz
─
0.7
1.5
mA
─
0.1
1.0
μA
─
─
5.0
μA
ISTB1
Standby Current
3V
No load, system HALT,
WDT disable
ISTB2
Standby Current
3V
No load, system HALT,
WDT enable
VIL1
Input Low Voltage for I/O Ports
—
—
0
─
0.2VDD
V
VIH1
Input Low Voltage for I/O Ports
—
—
0.8VDD
─
VDD
V
VIL2
Input Low Voltage(RES)
—
—
0
─
0.4VDD
V
VIH2
Input Low Voltage(RES)
—
—
0.9VDD
─
VDD
V
IOH
REM Output Source Current
3V
VOH=0.9VDD
-5
-7
─
mA
IOL1
PA, PB, REM Output Sink Current
3V
VOL=0.1VDD
6
12
─
mA
IOL2
PC0 Sink Current
3V
VOL=0.1VDD
0.8
1.2
─
mA
IOL3
REMDRV Output Sink Current
3V
VOL=0.6VDD
300
330
─
mA
RPH
Pull-high Resistance of Port A,Port B
3V
—
100
150
200
kΩ
VLVR
Low Voltage Reset Voltage
—
—
1.8
1.9
2.0
V
A.C. Characteristics
Ta= 25˚C
Symbol
Parameter
Test Conditions
VDD
Condition
Min.
Typ.
Max.
Unit
fSYS
System Clock
1.8V~3.6V Ta= -20°C~70°C
400
─
4000
kHz
fHIRC
System Clock (HIRC)
2.2V~3.6V Ta= -10°C~50°C
-1%
4095
+1%
kHz
─
1024
─
tSYS
Power-up or wake-up
from HALT
tSST
System Start-up Timer Period
─
tWDTOSC
Watchdog Oscillator
3V
─
45
90
180
μs
tLVR
Low Voltage Width to Reset
─
─
0.25
1.00
2.00
ms
Note: 1. tSYS= 1/fSYS
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HT48RA0-6
Remote Type 8-bit MCU
Power-on Reset Characteristics
Ta= 25˚C
Symbol
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to EnsurePower-on Reset
—
—
—
—
100
mV
RRVDD
VDD Raising Rate to Ensure Power-on Reset
—
—
0.035
—
—
V/ms
tPOR
Minimum Time for VDD Stays at VPOR to ensure
Power-on Reset
—
—
1
─
─
ms
Characteristics Curves
HIRC Oscillator Voltage/Temperature vs. Frequency
HIRC Curve
4200
Frequency (kHz)
4150
4095kHz +1%
4100
-25°C
25°C
75°C
4050
4095kHz -1%
4000
2.0
2.5
3.0
3.6
VDD (V)
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Remote Type 8-bit MCU
IR Sink Current vs. VDD
IR Driver Curve Ta=25℃
800
REM Sink Current (mA)
700
600
500
400
300
200
100
0
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
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Remote Type 8-bit MCU
Functional Description
Execution Flow
The main system clock is derived from either an external crystal oscillator which requires the
connection of the external crystal or resonator or an internal RC oscillator which requires no
external component for its operation. It is internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction
cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme
causes each instruction to effectively execute within one cycle. If an instruction changes the program
counter, two cycles are required to complete the instruction.
Program Counter – PC
The 10-bit program counter (PC) controls the sequence in which the instructions stored in program
memory are executed and its contents specify a maximum of 1024 addresses.
After accessing a program memory word to fetch an instruction code, the contents of the program
counter are incremented by one. The program counter then points to the memory word containing
the next instruction code.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine
call, initial reset or return from subroutine, the PC manipulates the program transfer by loading the
address corresponding to each instruction.
The conditional skip is activated by instruction. Once the condition is met, the next instruction,
fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get
the proper instruction. Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving
data into the PCL performs a short jump. The destination will be within 256 locations.
When a control transfer takes place, an additional dummy cycle is required.
Execution Flow
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HT48RA0-6
Remote Type 8-bit MCU
Mode
Initial reset
Program Counter
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
0
0
0
0
0
0
0
0
0
0
@0
Skip
Program Counter + 2
Loading PCL
*9
*8
@7
@6
@5
@4
@3
@2
@1
Jump, call branch
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *9~*0: Program counter bits
S9~S0: Stack register bits
#9~#0: Instruction code bits
@7~@0: PCL bits
Program Memory - ROM
The program memory is used to store the program instructions which are to be executed. It also
contains data and table and is organized into 1024×14 bits, addressed by the program counter and
table pointer.
Certain locations in the program memory are reserved for special usage:
• Location 000H
This area is reserved for the initialization program. After a device reset, the program always
begins execution at location 000H.
• Table location
Any location in the Program Memory space can be used as a look-up table. The instructions
TABRDC [m] (the current page, one page=256 words) and TABRDL [m] (the last page) transfer
the contents of the lower-order byte to the specified data memory register, and the higher-order
byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower portion of TBLH, the remaining 2 bits are
read as “0”. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP)
is a read/write register (07H), where P indicates the table location. Before accessing the table,
the location must be placed in TBLP. The TBLH is read only and cannot be restored. All table
related instructions need 2 cycles to complete the operation. These areas may function as normal
program memory depending upon the requirements.

Program Memory
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HT48RA0-6
Remote Type 8-bit MCU
Instruction
Table location
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *9~*0: Table location bits
PC9~PC8: Current Program Counter bits
@7~@0: Table Pointer bits
Stack
This is a special part of the memory which is used to save the contents of the Program Counter only.
The stack is organized into one level and neither part of the data nor part of the program space,
and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is
neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of
the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value
from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
If the stack is full and a "CALL" is subsequently executed, stack overflow occurs and the first entry
will be lost and only the most recent return address is stored.
Data Memory – RAM
The data memory is divided into two functional groups: special function registers and general
purpose data memory (32×8). Most are read/write, but some are read only.
The remaining space before the 20H is reserved for future expanded usage and reading these
locations will return the result 00H. The general purpose data memory, addressed from 20H to
3FH, is used for data and control information under instruction command. All data memory areas
can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some
dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].
i instructions, respectively. They are also indirectly accessible through memory pointer register
(MP;01H).
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Remote Type 8-bit MCU

RAM Mapping
Indirect Addressing Register
Location 00H is an indirect addressing register that is not physically implemented. Any read/write
operation to [00H] accesses the data memory pointed to by MP (01H). Reading location 00H itself
indirectly will return the result 00H. Writing indirectly results in no operation.
The memory pointer register MP (01H) is a 7-bit register. Bit 7 of MP is undefined and reading will
return the result “1” .Any writing operation to MP will only transfer the lower 7-bits of data to MP.
Accumulator
The accumulator closely relates to ALU operations. It is also mapped to location 05H of the data
memory and is capable of carrying out immediate data operations. Data movement between two data
memory locations has to pass through the accumulator.
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HT48RA0-6
Remote Type 8-bit MCU
Arithmetic and Logic Unit – ALU
This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following
functions.
• Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
• Logic operations (AND, OR, XOR, CPL)
• Rotation (RL, RR, RLC, RRC)
• Increment and Decrement (INC, DEC)
• Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but also changes the contents of the status
register.
Status Register – STATUS
This 8-bit status register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC),
overflow flag (OV), power down flag (PDF) and watchdog time-out flag (TO). It also records the
status information and controls the operation sequence.
With the exception of the TO and PDF flags, the other status register bits can be altered by
instructions like most other register. Any data written into the status register will not change the TO
or PDF flags. In addition it should be noted that operations related to the status register may give
different results from those intended. The TO and PDF flags can only be changed by the Watchdog
Timer overflow, device power-up, clearing the Watchdog Timer and executing the HALT instruction.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
In addition, on executing a subroutine call, the status register will not be automatically pushed onto
the stack. If the contents of the status are important and if the subroutine can corrupt the status
register, precautions must be taken to save it properly.
Bit No.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if
a borrow does not take place during a subtraction operation; otherwise C is
cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or
no borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared when either a system power-up or executing the CLR WDT
instruction. PDF is set by executing the HALT instruction.
5
TO
TO is cleared by a system power-up or executing the CLR WDT or HALT
instruction. TO is set by a WDT time-out.
6~7
—
Unused bit, read as “0”
Status (0AH) Register
Oscillator Configuration
In this device there are two methods of generating the system clock, one external crystal oscillator
and one internal RC oscillator.
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HT48RA0-6
Remote Type 8-bit MCU
External Crystal/Ceramic Oscillator – HXT
The External Crystal/Ceramic System Oscillator is one of the system oscillator choices, which
is selected via a configuration option. For the crystal oscillator configuration, the connection of a
crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation.
Two external capacitors may be required to be connected as shown. However, the feedback resistor
named Rf shown in the following diagram for the crystal oscillator to oscillate properly can be
selected as either an internally or externally connected type via a configuration option. When
the external connection type of the feedback resistor is selected, the recommended value of the
external connected feedback resistor ranges from 300kΩ to 500kΩ. Using a ceramic resonator will
usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation
to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator
manufacturer’s specification.
Crystal/Resonator Oscillator – HXT
Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
4MHz
8pF
10pF
Note: C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
Internal RC Oscillator – HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has a fixed frequency of 4095kHz. Device trimming during the
manufacturing process and the inclusion of internal frequency compensation circuits are used to
ensure that the influence of the power supply voltage, temperature and process variations on the
oscillation frequency are minimised. As a result, at a power supply ranging from 2.2V to 3.6V and
in a temperature range from -10°C to 50°C degrees, the fixed oscillation frequency of 4095kHz will
have a tolerance within 1%. Note that if this internal system clock option is selected, as it requires
no external pins for its operation, I/O pins PB5 and PB6 are free for use as normal I/O pins.
Watchdog Timer – WDT
The WDT clock source is implemented by the instruction clock which is the system clock divided
by 4 or the internal RC oscillator with the frequency of 12kHz. The clock source is processed by a
frequency divider and a prescaler to provide various time out periods.
WDT time out period =
ClockSource
2n
Where n= 8~11 selected by a configuration option.
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Remote Type 8-bit MCU
The WDT timer is designed to prevent a software malfunction or sequence jumping to an unknown
location with unpredictable results. The Watchdog Timer can be disabled by configuration option. If
the Watchdog Timer is disabled, all the executions related to the WDT result in no operation and the
WDT will lose its protection purpose. In this situation the logic can only be restarted by external logic.
A WDT overflow under normal operation will initialise a “chip reset” and set the status bit “TO”.
To clear the contents of the WDT prescaler, two methods are adopted, software instructions or a
HALT instruction. There are two types of software instructions. One type is the single instruction
“CLR WDT”, the other type comprises two instructions, “CLR WDT1” and “CLR WDT2”. Of
these two types of instructions, only one can be active depending on the configuration option “CLR
WDT times selection option”. If the “CLR WDT” is selected (i.e.. CLR WDT times equal one),
any execution of the CLR WDT instruction will clear the WDT. In case “CLR WDT1” and “CLR
WDT2” are chosen (i.e. CLR WDT times equal two), these two instructions must be executed to
clear the WDT; otherwise, the WDT may reset the chip due to a time-out.

Power Down Operation – HALT
The Power-down mode is initialised by the HALT instruction and results in the following:
• The system oscillator turns off and the WDT stops.
• The contents of the on-chip Data Memory and registers remain unchanged.
• WDT prescaler is cleared.
• All I/O ports maintain their original status.
• The PDF flag is set and the TO flag is cleared.
The system can quit the HALT mode by means of an external falling edge signal on all I/O ports.
By examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is
cleared when the system powers up or when a CLR WDT instruction is executed and is set when
the HALT instruction is executed. The TO flag is set if the WDT time-out occurs during normal
operation.
The I/O ports wake-up can be considered as a continuation of normal execution. Each bit in I/O port
can be independently selected to wake up the device by the code option. Awakening from an I/O
port stimulus, the program will resume execution of the next instruction.
Once a wake-up event(s) occurs, it takes 1024 tSYS (system clock periods) to resume normal
operation. In other words, a dummy cycle period will be inserted after the wake-up.
To minimize power consumption, all I/O pins should be carefully managed before entering the
HALT status.
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Remote Type 8-bit MCU
Reset
There are several ways in which a reset can occur:
• Power On reset
• RES pin reset
• Low Voltage reset
• WDT time-out reset during normal operation
Some registers remain unchanged during reset conditions. Most registers are reset to the “initial
condition” when the reset conditions are met. By examining the PDF and TO flags, the program can
distinguish between different chip resets.
TO
PDF
0
0
Power-on reset
RESET Conditions
u
u
RES or LVR reset during NORMAL operation
1
u
WDT time-out reset during NORMAL operation
1
1
WDT time-out reset during power-down operation
Note: “u” stands for unchanged
To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer)
provides an extra-delay of 1024 system clock pulses when the system powers up or when the system
awakes from a HALT state.
When a system power up occurs, an SST delay is added during the reset period. Any wake-up from
HALT will enable the SST delay.
The functional unit chip reset status is shown below.
Program Counter
000H
WDT Prescaler
Clear
Timer/Event Counter
Timer Counter will be turned off
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
Carrier output
Low level state or floating
state*
“*” Determined by configuration option
Reset Timing Chart
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HT48RA0-6
Remote Type 8-bit MCU
H A L T
W D T
C o ld R e s e t
L V R
S S T
1 0 -s ta g e
R ip p le C o u n te r
O S C 1
P o w e r - o n D e te c tio n
Reset Configuration
Note: “*” It is recommended that this component is added for added ESD protection
“**” It is recommended that this component is added in environments where power line noise
is significant.
External RES Circuit
The chip reset status of the registers is summarised in the following table:
Register
Power-on Reset
0
0
H
RES or LVR Reset
0
0
H
0
MP
-xxx
xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
ACC
xxxx
xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx
xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx
xxxx
--uu
uuuu
--uu
uuuu
--uu
uuuu
STATUS
--00
xxxx
--uu
uuuu
--1u
uuuu
- - 11
uuuu
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
111 x 1111
111 x 1111
111 x 1111
uuuu uuuu
PC
----
----
----
----
TSR0
0000 0000
0000 0000
0000 0000
uuuu uuuu
TSR1
1000 0000
1000 0000
1000 0000
uuuu uuuu
CARL0
0000 0000
0000 0000
0000 0000
uuuu uuuu
CARL1
0000 0000
0000 0000
0000 0000
uuuu uuuu
CARH0
0000 0000
0000 0000
0000 0000
uuuu uuuu
CARH1
0000 0010
0000 0010
0000 0010
uuuu uuuu
---1
0
0
0
H
WDT Time-out
(HALT)*
PC
---1
0
WDT Time-out
(Operation)
---1
0
0
0
H
---u
Note: “-” stands for unimplemented “u” means unchanged “x” means unknown
Rev. 1.10
18
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Input/Output Ports
There are up to 17 bidirectional input/output lines in the device, labeled PA, PB and PC which are
mapped to [12H], [14H] and [16H] of the Data Memory, respectively. Each line of PA and PB can be
selected as NMOS output or Schmitt trigger input with pull-high resistor by a software instruction.
PC0 can be used as an input line with Schmitt trigger but without pull-high resistor or as the external
RES pin determined by the configuration option.
When the I/O ports are used for input operation, these ports are non-latched, that is, the inputs should
be ready at the T2 rising edge of the instruction “MOV A, [m]” (m=12H, 14H or 16H). For I/O ports
output operations, all data is latched and remains unchanged until the output latch is rewritten.
When the I/O Ports are used for input operations, it should be noted that before reading data
from the pads, a “1” should be written to the related bits to disable the NMOS device. That is, the
instruction “SET [m].i” (i=0~7 for PA, i=0~3, 5~7 for PB, i=0 for PC) is executed first to disable
related NMOS device, and then “MOV A, [m]” to get stable data.
After chip reset, the I/O Ports remain at a high level input line. Each bit of the I/O ports output latches can
be set or cleared by the “SET [m].i” and “CLR [m].i” (m=12H, 14H or 16H) instructions respectively.
Some instructions first input data and then follow the output operations. For example, “SET [m].i”,
“CLR [m]”, “CPL [m]” and “CPLA [m]” read the entire port states into the CPU, execute the defined
operations (bit-operation), and then write the results back to the latches or to the accumulator.
Each line of the I/O ports has a wake-up capability when the relevant pin is configured as an input line.

PA and PB Input/Output Ports
D a ta b u s
D
W r ite
Q
C K
C h ip R e s e t
P C 0 /R E S
Q
S
R e a d D a ta R e g is te r
S y s te m
W a k e -u p (P C 0 )
PC0 Input/Output Port
REM/REMDRV Output Pin Structure
Rev. 1.10
19
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Timer
The timer is an internal unit for creating a remote control transmission pattern. As shown, it consists
of a 9-bit down counter (t8 to t0), a flag (t9) permitting the 1-bit timer output, and a zero detector.
No.
Label
Function
0~7
t0~t7
Down counter
TSR0 (18H) Register
No.
Label
0
t8
Down counter
Function
1
t9
Timer enable, initial value is “0”.
2~6
—
Unused bit, read as “0”.
7
TOEF
Timer operation end flag, initial value is “1”.
TSR1 (19H) Register
Timer Operation
The timer starts counting down when a value other than “0” is set for the down counter with a timer
manipulation instruction. The timer manipulation instructions for making the timer start operation
are shown below:
MOV A,XXH ; XX = 00H ~ FFH
MOV TSR0,A
MOV A,XXH ; XX 01H, t8
MOV TSR1,A
SET TSR1.1 ; The timer is started by set t9=1
Addition notes for the 9-bit timer:
• Writing to TSR0 will only put the written data to the TSR0 register (t7~t0) and writing to TSR1 (t8)
will transfer the specified data and contents of TSR0 to the Down Counter. TOEF will be cleared
after the data transferred from TSR1 and TSR0 to the Down Counter is completed and then wait
until TSR1.1 is set by user.
• Setting TSR1.1=1, the timer will start counting. The timer will stop when its count is equal to “0”
and then TOEF is set equal to “1”.
• If the TSR1.1 is cleared during the timer counting, the timer will be stopped. Once the TSR1.1 is
set (1→0→1), the down counter will reload data from t8~t0, and then the down counter begins
counting down with the new load data.
• If TSR1.1 and TOEF are equal to 1 both, the timer can re-start, after new data is written to TSR0,
TSR1 (t0~t8) in sequence.
Note: If the contents of the Down counter is 000H, set the t9 to start the timer counting, the timer
will only count 1 step. The timer output time=64/fSYS. →[ (0+1) ×64/fSYS=64/fSYS]
Rev. 1.10
20
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
The down counter is decremented (-1) in the cycle of 64/fSYS. If the value of the down counter
becomes “0”, the zero detector generates the timer operation end signal to stop the timer operation.
At this time, TOEF will be set to “1”. The output of the timer operation end signal is continued
while the down counter is “0” and the timer is stopped. The following relational expression applies
between the timer’s output time and the down counter’s set value.
Timer output time = (Set value+1) ×64/fSYS
An example is shown below for fSYS = 4MHz
MOV A,0FFH
MOV TSR0,A
MOV A,01H
MOV TSR1,A
SET TSR1.1
In the case above, the timer output time is as follows.
(Set value+1) × 64/fSYS= (511+1) ×16μs= 8.192ms
Setting the t9 bit channels the timer to the REM pin. The REM pin will be a combination of the
timer and carrier signals.
Note:The carrier output results if bit 9 of the high-level period setting modulo register (CARH) is
cleared (“0”).
Timer Output when Carrier is not Output

Timer Configuration
Rev. 1.10
21
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Carrier Output
Carrier output generator
The carrier generator consists of a 9-bit counter and two modulo registers for setting the high-level
and low-level periods - CARH and CARL respectively.
Register
7
6
5
4
3
2
1
0
CARL0
CL.7
CL.6
CL.5
CL.4
CL.3
CL.2
CL.1
CL.0
CARL1
—
—
—
—
—
—
Fix“0”
CL.8
CARH0
CH.7
CH.6
CH.5
CH.4
CH.3
CH.2
CH.1
CH.0
—
CH.9
(CARY)
CH.8
CARH1
—
—
—
—
—
CARL0 (1AH) Register, CARL1 (1BH), CARH0 (1CH) Register, CARH1 (1DH), Register
Note: 1. CARH1.1 (CARY) initial value is “1”.
2. CARL1.2 (CARH1.2) ~ CARL1.7 (CARH1.7) are unused bits, read as “0”.
The carrier duty ratio and carrier frequency can be determined by setting the high-level and lowlevel widths using the respective modulo registers. Each of these widths can be set in a range of
500ns to 64μs at fSYS = 4MHz.
CARH (CARH1.0, CARH0.7~CARH0.0) and CARL (CARL1.0, CARL0.7~CARL0.0) are read and
written using instructions.
• Example:
MOV A,XXH MOV CARL0,A
MOV A,XXH MOV CARL1,A
MOV A,XXH MOV CARH0,A
MOV A,XXH MOV CARH1,A
CLR CARH1.1
; XXH = 00H~FFH
; XXH 01H, CL.8 (CARL1.0)
; XXH = 00H~FFH
; XXH 02H, CH.8 (CARH1.0)
; The carrier is started by clearing CARY(CARH1.1)= “0”

Configuration of Remote Controller Carrier Generator
Note: 1. Bit 9 of the modulo register for setting the low-level period (CARL) is fixed to “0”.
2. t9: Flag that enables timer output (timer block, see Timer Configuration)
Rev. 1.10
22
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
The values of CARH and CARL can be calculated from the following expressions.
CARL (CARL1.0, CARL0.7~CARL0.0) = ( fSYS × (1 D) × T) – 1 …… (1)
CARH (CARH1.0, CARH0.7~CARH0.0) = ( fSYS × D × T) – 1 ………. (2)
(1) + (2) => CARL + CARH = ( fSYS × T) – 2 => Actual Carrier Frequency = fSYS/(CARL + CARH +2)
D: Carrier duty ratio (0 < D < 1)
fSYS: Input clock (MHz)
T: Carrier cycle (μs)
Ensure to input values in the range of 001H to 1FFH to CARL and CARH.
• Example:
If fSYS= 4095kHz, Target fc= 38kHz, T= 1/fc= 26.3157μs= tL+tH, duty= 1/3
CARL= (4.095M×(1–1/3)×26.3157μs) – 1= 70.842
select 71= 47H , actual tL= (71+1)/4.095M= 17.58μs
CARH= (4.095M×1/3×26.3157μs) – 1= 34.921
select 35= 23H , actual tH= (35+1)/4.095M= 8.79μs
For actual Carrier Frequency= fSYS/(CARL+CARH+2)
So, actual fc= fSYS/(CARL+CARH+2)= 4095kHz/(71+35+2)= 37.917kHz
MOV A,045H
MOV CARL0,A
MOV A,022H
MOV CARH0,A
CLR CARH1.1
; The carrier is started by clearing CARY(CARH1.1)= “0”
Carrier output control
The remote controller carrier can be output from the REM pin by clearing to zero bit 9 (CARY) of
the modulo register for setting the high-level period (CARH).
When performing a carrier output, be sure to set the timer operation after setting the CARH
(CARH1.0, CARH0.7~CARH0.0) and CARL (CARL1.0, CARL0.7~CARL0.0) values.
Note that a malfunction may occur if the values of CARH (CARH1.0, CARH0.7~CARH0.0) and
CARL (CARL1.0, CARL0.7~CARL0.0) are changed while the carrier is being output on the REM
pin.
Executing the timer manipulation instruction starts the carrier output from the low level.
There is a dual function remote controller carrier output pin named REM. The selection of REM or
REMDRV is determined by a configuration option. After a reset, the REM carrier output pin will
have a low level while the REMDRV carrier output pin will be in a floating condition. The generic
structures of the REM or REMDRV function are illustrated in the accompanying diagram. As the
exact construction of the carrier output pin will differ from these drawings, they are supplied as a
guide only to assist with the functional understanding of the remote carrier output pins.
The output from the REM pin is in accordance with the value of bit 9 (CARY) of CARH and the
timer output enable flag (t9), and the value of the timer 9-bit down counter (t0 to t8).
Rev. 1.10
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November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
T im e r O u tp u t T im e :
( S e t v a lu e + 1 ) x 6 4 /fS Y
S
T im e r O u tp u t
C a r r ie r
tL
S e e N o te
tH
Timer Output when Carrier is Output
Note: When the carrier signal is active and during the time when the signal is high, if the timer
output should go low, the carrier signal will first complete its high level period before going
low.
CARH1.1
Timer Output
Enable Flag
(t9: TSR1.1)
0
0
0
0
0
Other than 0
0
1
0
9-bit
Down Counter
REM Function
(CMOS Output)
REMDRV Function
(NMOS Output)
Low-level output
Floating output
0
64/fSYS
(with carrier output)
64/fSYS
(with carrier output)
1
Other than 0
Carrier output (Note)
Carrier output
1
0
―
Low-level output
Floating output
1
1
―
High-level output
Low-level output
REM Pin Output Control
Note: Input values in the range of 001H to 1FFH to CARH (CARH1.0, CARH0.7~CARH0.0) and CARL
(CARL1.0, CARL0.7~CARL0.0).
Caution: CARH (CARH1.0, CARH0.7~CARH0.0) and CARL (CARL1.0, CARL0.7~CARL0.0) must be
set while the REM pin is at a low level (t9 = 0 or t0 to t8 = 0).
Target
Setting
Actual
fC(kHz)
Duty
CARH(CARH1.0,
CARH0.7~CARH0.0)
CARL(CARL1.0,
CARL0.7~CARL0.0)
tH(μs)
tL(μs)
T(μs)
fC(kHz)
36
1/3
25H
4BH
9.28
18.56
27.84
35.92
38
1/3
23H
47H
8.79
17.58
26.37
37.92
56
1/3
18H
2FH
6.11
11.72
17.83
56.10
56
1/2
23H
24H
8.79
9.04
17.83
56.10
Carrier Frequency Setting (fSYS= 4095kHz)
Target
Setting
Actual
fC(kHz)
Duty
CARH(CARH1.0,
CARH0.7~CARH0.0)
CARL(CARL1.0,
CARL0.7~CARL0.0)
tH(μs)
tL(μs)
T(μs)
fC(kHz)
36
1/3
24H
49H
9.25
18.50
27.75
36.04
38
1/3
22H
45H
8.75
17.50
26.25
38.10
56
1/3
17H
2EH
6.00
11.75
17.75
56.34
56
1/2
23H
22H
9.00
8.75
17.75
56.34
Carrier Frequency Setting (fSYS= 4MHz)
Rev. 1.10
24
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Low Voltage Reset – LVR
The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the
device. If the supply voltage of the device is within the range 0.9V~VLVR, such as when changing a
battery, the LVR will automatically reset the device internally.
The LVR includes the following specifications:
• The low voltage (0.9V~VLVR) has to remain in this state for a time in excess of 1ms. If the low
voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
The relationship between VDD and VLVR is shown below.
V
D D
3 .6 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
R e s e t
N o r m a l O p e r a tio n
*1
R e s e t
*2
Low Voltage Reset
Note: “*1” To make sure that the system oscillator has stabilised, the SST provides an extra delay of 1024
system clock pulses before entering normal operation.
“*2” Since low voltage has to be maintained in its original state and exceed 1ms, a 1ms delay enters
the reset mode.
Rev. 1.10
25
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Configuration Options
The following table shows the range of configuration options for the device. All the configuration
options must be defined to ensure proper system functioning.
No.
Code Options
Oscillator Options
1
System oscillator selection - fSYS:
XTAL oscillator without internal feedback resistor
XTAL oscillator with internal feedback resistor
Internal 4095kHz RC oscillator
REM/REMDRV Pin Options
2
REM or REMDRV output function selection
Watchdog Options
3
WDT clock selection - fS:
Internal RC oscillator or fSYS/4
4
WDT function: enable or disable
5
CLRWDT instruction selections: 1 or 2 instructions
6
WDT time-out period selections: 28/fS, 29/fS, 210/fS, 211/fS
LVR Options
7
LVR function: enable or disable
Reset Pin Options
8
Rev. 1.10
I/O or RES pin selection
26
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Application Circuits
• The following application circuit shows the situation when a transistor is added to IR driver
circuit. Here the MCU REM function must be enabled.
VBAT
Battery
R1
10 Ω
VDD
VDD1
C2
R3
2Ω
IR
LED
VDD
C1
0 .1 μF
R2
Q1
250Ω
8050
VSS
REM
VSS1
HT48RA0-6
Note: 1. The values of R1 and C2 should be selected in consultation with the actual application, R1=10Ω,
C1=0.1μF, C2=200~330μF are recommended values.
2. To obtain a better frequency stability and longer transmission distances, C2=330μF is a
recommended value. The frequency stability may be different and the transmission distance may
be shorter if a value other than 330μF is used.
3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor
should be connected between VDD and VSS on the PCB.
4. The C1 (0.1μF) decoupling capacitor should be located as close to the VDD and VSS pins as
possible.
5. R1 and C1 should be located as close to the VDD pin as possible.
6. VSS, VSS1, C2 and Q1 must be connected to the power GND terminal.
7. VDD and VDD1 must be connected to the power VBAT terminal.
8. The values of R1 and C2 should be selected in consultation with the actual application.
9. It should to be noted that when programming the device, the HT48RA0-6 writer type is the
e-Writer PRO, which when used together with the e-Socket, can ensure that the HIRC oscillator
frequency will have a tolerance within 1% in the actual application circuit.
Rev. 1.10
27
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
• The following application circuit shows the situation when the internal IR driver circuit is used.
Here the MCU REMDRV function must be enabled.
VDD
VBAT
Battery
R1
10 Ω
VDD1
C2
IR
LED
R3
2Ω
C1
0 .1 μF
VDD
VSS
REMDRV
VSS1
HT48RA0-6
Note: 1. The values of R1 and C2 should be selected in consultation with the actual application, R1=10Ω,
C1=0.1μF, C2=47~100μF are recommended values.
2. To obtain a better frequency stability and longer transmission distances, C2=100μF is a
recommended value. The frequency stability may be different and the transmission distance may
be shorter if a value other than 100μF is used.
3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor
should be connected between VDD and VSS on the PCB.
4. The C1 (0.1μF) decoupling capacitor should be located as close to the VDD and VSS pins as
possible.
5. R1 and C1 should be located as close to the VDD pin as possible.
6. VSS, VSS1, C2 and Q1 must be connected to the power GND terminal.
7. VDD and VDD1 must be connected to the power VBAT terminal.
8. The values of R1 and C2 should be selected in consultation with the actual application.
9. It should to be noted that when programming the device, the HT48RA0-6 writer type is the
e-Writer PRO, which when used together with the e-Socket, can ensure that the HIRC oscillator
frequency will have a tolerance within 1% in the actual application circuit.
Rev. 1.10
28
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5μs and branch or call instructions would be implemented within
1μs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.
Rev. 1.10
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November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Logical and Rotate Operation
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
which rotate data operations are used is to implement multiplication and division calculations.
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction
or to a subroutine using the CALL instruction. They differ in the sense that in the case of a
subroutine call, the program must return to the instruction immediately when the subroutine has
been carried out. This is done by placing a return instruction “RET” in the subroutine which will
cause the program to jump back to the address right after the CALL instruction. In the case of a JMP
instruction, the program simply jumps to the desired location. There is no requirement to jump back
to the original jumping off point as in the case of the CALL instruction. One special and extremely
useful set of branch instructions are the conditional branches. Here a decision is first made regarding
the condition of a certain data memory or individual bits. Depending upon the conditions, the
program will continue with the next instruction or skip over it and jump to the following instruction.
These instructions are the key to decision making and branching within the program perhaps
determined by the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i”
instructions respectively. The feature removes the need for programmers to first read the 8-bit output
port, manipulate the input data to ensure that other bits are not changed and then output the port with
the correct new data. This read-modify-write process is taken care of automatically when these bit
operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be setup as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the “HALT” instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
Rev. 1.10
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HT48RA0-6
Remote Type 8-bit MCU
Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function and
can be consulted as a basic instruction reference using the following listed conventions.
Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Rev. 1.10
31
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Mnemonic
Description
Cycles
Flag Affected
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no
skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the “CLR WDT1” and “CLR WDT2” instructions the TO and PDF flags may be affected by the
execution status. The TO and PDF flags are cleared after both “CLR WDT1” and “CLR WDT2”
instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.10
32
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Instruction Definition
ADC A,[m]
Description
Operation
Affected flag(s)
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C
ADCM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C
Add Data Memory to ACC
ADD A,[m]
Description
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C
ADD A,x
Description
Operation
Affected flag(s)
Add immediate data to ACC
The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator.
ACC ← ACC + x
OV, Z, AC, C
ADDM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C
AND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
AND A,x
Description
Operation
Affected flag(s)
Logical AND immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ x
Z
ANDM A,[m]
Description
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
Rev. 1.10
33
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
CALL addr
Description
Operation
Affected flag(s)
Subroutine call
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Stack ← Program Counter + 1
Program Counter ← addr
None
CLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
CLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
CLR WDT
Description
Operation
Affected flag(s)
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT1
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in
conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have
effect. Repetitively executing this instruction without alternately executing CLR WDT2 will
have no effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT2
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction
with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect.
Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CPL [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
Rev. 1.10
34
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
CPLA [m]
Description
which Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits
DAA [m]
Description
Operation
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or [m] ← ACC + 60H or
[m] ← ACC + 66H
C
DEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
DECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
HALT
Description
Operation
Affected flag(s)
Enter power down mode
This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
TO ← 0
PDF ← 1
TO, PDF
INC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
INCA [m]
Description
Accumulator. Operation
Affected flag(s)
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the
Rev. 1.10
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
35
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
JMP addr
Description
Operation
Affected flag(s)
Jump unconditionally
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Program Counter ← addr
None
MOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
MOV A,x
Description
Operation
Affected flag(s)
Move immediate data to ACC
The immediate data specified is loaded into the Accumulator.
ACC ← x
None
MOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
NOP
Description
Operation
Affected flag(s)
No operation
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Description
Operation
Affected flag(s)
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
OR A,x
Description
Operation
Affected flag(s)
Logical OR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ x
Z
ORM A,[m]
Description
Operation
Affected flag(s)
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
RET
Description
Operation
Affected flag(s)
Return from subroutine
The Program Counter is restored from the stack. Program execution continues at the restored
address.
Program Counter ← Stack
None
Rev. 1.10
36
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
RET A,x
Description
Operation
Affected flag(s)
Return from subroutine and load immediate data to ACC
The Program Counter is restored from the stack and the Accumulator loaded with the specified
immediate data. Program execution continues at the restored address.
Program Counter ← Stack
ACC ← x
None
RETI
Description
Operation
Affected flag(s)
Return from interrupt
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Program Counter ← Stack
EMI ← 1
None
RL [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
RLA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
RLC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
RLCA [m]
Description
the Operation
Affected flag(s)
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
RR [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
Rev. 1.10
37
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
RRA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
RRC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
RRCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
SBC A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C
SBCM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C
SDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
Rev. 1.10
38
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
SDZA [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
SET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
SET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
SIZ [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
SIZA [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
SNZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is not 0
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
SUB A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C
Rev. 1.10
39
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
SUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C
SUB A,x
Description
Operation
Affected flag(s)
Subtract immediate data from ACC
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − x
OV, Z, AC, C
SWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
SWAPA [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
SZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
SZA [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
SZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
Rev. 1.10
40
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
TABRDC [m]
Description
Operation
Affected flag(s)
Read table (current page) to TBLH and Data Memory
The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDL [m]
Description
Operation
Affected flag(s)
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
XOR A,[m]
Description
Operation
Affected flag(s)
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
XORM A,[m]
Description
Operation
Affected flag(s)
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
XOR A,x
Description
Operation
Affected flag(s)
Logical XOR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ x
Z
Rev. 1.10
41
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website
(http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package
information.
16-pin NSOP (150mil) Outline Dimensions
MS-012
Symbol
Min.
Nom.
Max.
A
0.228
―
0.244
B
0.150
―
0.157
C
C‫׳‬
0.012
―
0.020
0.386
―
0.402
D
―
―
0.069
E
―
0.050
―
F
0.004
―
0.010
G
0.016
―
0.050
H
0.007
―
0.010
α
0˚
―
8˚
Symbol
Rev. 1.10
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
5.79
―
6.20
B
3.81
―
3.99
C
C‫׳‬
0.30
―
0.51
9.80
―
10.21
D
―
―
1.75
E
―
1.27
―
F
0.10
―
0.25
G
0.41
―
1.27
H
0.18
―
0.25
α
0˚
―
8˚
42
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
20-pin SSOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.228
—
0.244
B
0.150
—
0.158
C
C‫׳‬
0.008
—
0.012
0.335
—
0.347
D
0.049
—
0.065
E
—
0.025
—
F
0.004
—
0.010
G
0.015
—
0.050
H
0.007
—
0.010
α
0°
—
8°
Symbol
Rev. 1.10
Dimensions in mm
Min.
Nom.
Max.
A
5.79
—
6.20
B
3.81
—
4.01
C
C‫׳‬
0.20
8.51
—
8.81
D
1.24
—
1.65
E
—
0.64
—
F
0.10
—
0.25
G
0.38
—
1.27
H
0.18
—
0.25
α
0°
—
8°
0.30
43
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Product Tape and Reel Specifications
Reel Dimensions
16-pin NSOP (150mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
13.0+0.5/-0.2
D
Key Slit Width
T1
Space Between Flang
16.8+0.3/-0.2
2.0±0.5
T2
Reel Thickness
22.2±0.2
20-pin SSOP (150mil)
Symbol
Rev. 1.10
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
13.0+0.5/-0.2
D
Key Slit Width
T1
Space Between Flang
16.8+0.3/-0.2
2.0±0.5
T2
Reel Thickness
22.2±0.2
44
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Carrier Tape Dimensions
16-pin NSOP (150mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
P
Cavity Pitch
16.0±0.3
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation(Width Direction)
7.5±0.1
D
Perforation Diameter
1.55+0.10/-0.00
D1
Cavity Hole Diameter
1.50+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation(Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
10.3±0.1
K0
Cavity Depth
2.1±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
20-pin SSOP (150mil)
Symbol
Rev. 1.10
Description
W
Carrier Tape Width
Dimensions in mm
16.0+0.3/-0.1
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation(Width Direction)
7.5±0.1
D
Perforation Diameter
1.5+0.1/-0.0
D1
Cavity Hole Diameter
1.50+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation(Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
9.0±0.1
K0
Cavity Depth
2.3±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
45
November 02, 2012
HT48RA0-6
Remote Type 8-bit MCU
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc.
Building No.10, Xinzhu Court, (No.1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright© 2012 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication.
However, Holtek assumes no responsibility arising from the use of the specifications described.
The applications mentioned herein are used solely for the purpose of illustration and Holtek makes
no warranty or representation that such applications will be suitable without further modification,
nor recommends the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical components in life
support devices or systems. Holtek reserves the right to alter its products without prior notification. For
the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
46
November 02, 2012

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