HT1623 - RAM Mapping 48x8 LCD Controller for I/O MCU

HT1623
RAM Mapping 48´8 LCD Controller for I/O MCU
PATENTED
PAT No. : TW 099352
Technical Document
· Application Note
Features
· Operating voltage: 2.7V~5.2V
· Built-in LCD display RAM
· Built-in RC oscillator
· R/W address auto increment
· External 32.768kHz crystal or 32kHz frequency
· Two selection buzzer frequencies (2kHz or 4kHz)
source input
· Power down command reduces power consumption
· 1/4 bias, 1/8 duty, frame frequency is 64Hz
· Software configuration feature
· Max. 48´8 patterns, 8 commons, 48 segments
· Data mode and Command mode instructions
· Built-in internal resistor type bias generator
· Three data accessing modes
· 3-wire serial interface
· VLCD pin to adjust LCD operating voltage
· 8 kinds of time base or WDT selection
· 100-pin LQFP package
· Time base or WDT overflow output
General Description
HT1623 make it suitable for multiple LCD applications
including LCD modules and display subsystems. Only
three lines are required for the interface between the
host controller and the HT1623. The HT162X series
have many kinds of products that match various applications.
HT1623 is a peripheral device specially designed for I/O
type MCU used to expand the display capability. The
max. display segment of the device are 384 patterns
(48´8). It also supports serial interface, buzzer sound,
watchdog timer or time base timer functions. The
HT1623 is a memory mapping and multi-function LCD
controller. The software configuration feature of the
Selection Table
HT162X
HT1620
HT1621
HT1622
HT16220
HT1623
HT1625
HT1626
COM
4
4
8
8
8
8
16
SEG
32
32
32
32
48
64
48
Built-in Osc.
¾
Ö
Ö
¾
Ö
Ö
Ö
Crystal Osc.
Ö
Ö
¾
Ö
Ö
Ö
Ö
Rev. 1.90
1
July 22, 2011
PATENTED
HT1623
Block Diagram
O S C O
D is p la y R A M
O S C I
C S
C o n tro l
a n d
T im in g
C ir c u it
R D
W R
C O M 0
C O M 7
L C D D r iv e r /
B ia s C ir c u it
D A T A
S E G 0
S E G 4 7
V D D
V S S
V L C D
B Z
W a tc h d o g T im e r
a n d
T im e B a s e G e n e r a to r
T o n e F re q u e n c y
G e n e ra to r
B Z
IR Q
Pin Assignment
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
N C
N C
N C
N C
N C
N C
N C
N C
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
N C
C S
R D
W R
D A T A
V S S
O S C I
O S C O
V D D
V L C D
IR Q
B Z
B Z
T 1
T 2
T 3
C O M 0
C O M 1
N C
N C
N C
N C
N C
N C
N C
N C
1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6
1
2
7 5
7 4
7 3
3
7 2
4
5
6
7
8
9
1 0
1 1
1 2
H T 1 6 2 3
1 0 0 L Q F P -A
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
N C
N C
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
N C
G 3 1
G 3 0
G 2 9
G 2 8
G 2 7
G 2 6
G 2 5
G 2 4
G 2 3
G 2 2
G 2 1
G 2 0
G 1 9
G 1 8
G 1 7
G 1 6
G 1 5
G 1 4
G 1 3
N C
N C
N C
N C
N C
N C
N C
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
C O M
C O M
C O M
C O M
C O M
C O M
N C
N C
1 2
1 1
1 0
9
8
7
7
2
6
5
4
3
2
1
0
6
5
4
3
2
Rev. 1.90
July 22, 2011
PATENTED
HT1623
Pad Assignment
6 0
5 9 5 8
S E G 3 2
6 1
S E G 3 3
S E G 3 4
6 3 6 2
S E G 3 5
6 4
S E G 3 6
6 6 6 5
S E G 3 7
S E G 4 2
6 7
S E G 3 8
S E G 4 3
6 8
S E G 3 9
S E G 4 4
6 9
S E G 4 0
S E G 4 5
S E G 4 1
S E G 4 6
7 0
5 7
5 6
3
D A T A
O S C I
7 1
2
R D
W R
V S S
S E G 4 7
1
C S
4
5
6
O S C O
7
V D D
8
V L C D
9
IR Q
1 0
B Z
1 1
B Z
1 2
T 1
1 3
S E G 2 5
4 8
S E G 2 4
4 7
S E G 2 3
4 6
S E G 2 2
4 5
S E G 2 1
4 4
S E G 2 0
4 3
S E G 1 9
4 2
S E G 1 8
4 1
S E G 1 7
4 0
S E G 1 6
3 9
3 8
S E G 1 5
3 7
S E G 1 3
S E G 5
S E G 4
S E G 3
3 0
3 1
3 2
3 3
3 4
3 5
3 6
S E G 1 2
2 9
S E G 2 6
S E G 2 7
4 9
S E G 1 1
2 8
2 6 2 7
5 0
S E G 1 0
2 4 2 5
S E G 2
2 3
S E G 0
2 1 2 2
S E G 1
2 0
C O M 6
1 9
S E G 2 8
S E G 9
1 8
S E G 2 9
5 2
5 1
S E G 8
C O M 2
S E G 3 0
5 3
S E G 7
1 7
S E G 3 1
5 4
S E G 6
1 6
C O M 1
C O M 7
C O M 0
C O M 5
1 5
C O M 4
1 4
T 3
C O M 3
T 2
(0 ,0 )
5 5
S E G 1 4
Chip size: 113 ´ 106 (mil)2
* The IC substrate should be connected to VDD in the PCB layout artwork.
Rev. 1.90
3
July 22, 2011
PATENTED
HT1623
Pad Coordinates
Unit: mm
Pad No.
X
Y
Pad No.
X
Y
1
-1328.790
1200.109
37
1322.060
-779.760
2
-1328.790
1008.378
38
1322.060
-522.546
3
-1328.785
909.341
39
1322.060
-423.524
4
-1337.200
696.447
40
1322.060
-324.425
5
-1337.162
475.635
41
1322.060
-225.404
6
-1337.925
376.661
42
1322.060
-126.305
7
-1337.925
277.639
43
1322.060
8
-1337.887
178.570
44
1322.060
-27.285
71.814
9
-1337.925
79.595
45
1322.060
170.835
10
-1343.075
-79.689
46
1322.060
269.935
11
-1337.925
-260.141
47
1322.060
368.956
12
-1337.925
-444.992
48
1322.060
468.055
13
-1337.925
-625.740
49
1322.060
567.076
14
-1337.925
-724.760
50
1322.060
666.174
15
-1337.925
-823.859
51
1322.060
765.195
16
-1337.925
-922.880
52
1322.060
864.294
17
-1337.925
-1021.979
53
1322.060
963.315
18
-1337.887
-1228.075
54
1322.060
1062.415
19
-1076.690
-1228.075
55
1322.060
1161.436
20
-977.669
-1228.075
56
451.081
1226.600
21
-878.570
-1228.075
57
352.060
1226.600
22
-779.549
-1228.075
58
252.960
1226.600
23
-680.449
-1228.075
59
153.939
1226.600
24
-488.720
-1228.075
60
54.840
1226.600
25
-389.620
-1228.075
61
-44.181
1226.600
26
-197.889
-1228.075
62
-143.279
1226.600
27
-1228.075
63
-242.301
1226.600
28
-98.790
92.941
-1228.075
64
-341.399
1226.600
29
192.040
-1228.075
65
-440.420
1226.600
30
383.771
-1228.075
66
-539.520
1226.600
31
482.871
-1228.075
67
-638.541
1226.600
32
674.600
-1228.075
68
-737.640
1226.600
33
773.701
-1228.075
69
-836.661
1226.600
34
965.431
-1228.075
70
-935.760
1226.600
35
1064.531
-1228.075
71
-1034.781
1226.600
36
1256.260
-1228.075
Rev. 1.90
4
July 22, 2011
PATENTED
HT1623
Pad Description
Pad No.
Pad Name
I/O
Description
1
CS
I
Chip selection input with pull-high resistor. When the CS is logic high, the
data and command read from or written to the HT1623 are disabled. The serial interface circuit is also reset But if the CS is at logic low level and is input
to the CS pad, the data and command transmission between the host controller and the HT1623 are all enabled.
2
RD
I
READ clock input with pull-high resistor. Data in the RAM of the HT1623 are
clocked out on the falling edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next rising edge to latch
the clocked out data.
3
WR
I
WRITE clock input with pull-high resistor. Data on the DATA line are latched
into the HT1623 on the rising edge of the WR signal.
4
DATA
I/O
Serial data input or output with pull-high resistor
5
VSS
¾
Negative power supply, ground
6
OSCI
I
7
OSCO
O
8
VDD
¾
9
VLCD
I
LCD operating voltage input pad.
10
IRQ
O
Time base or watchdog timer overflow flag, NMOS open drain output
11, 12
BZ, BZ
O
2kHz or 4kHz tone frequency output pair
13~15
T1~T3
I
Not connected
16~23
COM0~COM7
O
LCD common outputs
24~71
SEG0~SEG47
O
LCD segment outputs
The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to
generate a system clock. If the system clock comes from an external clock
source, the external clock source should be connected to the OSCI pad. But
if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads can
be left open.
Positive power supply
Absolute Maximum Ratings
Supply Voltage .........................................-0.3V to 5.5V
Storage Temperature ............................-50°C to 125°C
Input Voltage.............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-25°C to 75°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.90
5
July 22, 2011
PATENTED
HT1623
D.C. Characteristics
Symbol
Parameter
VDD
Operating Voltage
IDD1
Operating Current
Ta=25°C
Test Conditions
VDD
Conditions
¾
¾
3V
5V
IDD2
3V
Operating Current
5V
IDD11
3V
Operating Current
5V
IDD22
3V
Operating Current
5V
ISTB
No load or LCD ON
On-chip RC oscillator
No load or LCD ON
Crystal oscillator
No load or LCD OFF
On-chip RC oscillator
No load or LCD OFF
Crystal oscillator
3V
Standby Current
No load, Power down mode
5V
VIL
3V
Input Low Voltage
3V
Input High Voltage
IOH1
IOL2
IOH2
IOL3
IOH3
IOL4
IOH4
RPH
Unit
2.7
¾
5.2
V
¾
155
310
mA
¾
260
420
mA
¾
150
310
mA
¾
250
420
mA
¾
8
30
mA
¾
20
60
mA
¾
¾
20
mA
¾
¾
35
mA
¾
1
10
mA
¾
2
20
mA
0
¾
0.6
V
0
¾
1.0
V
2.4
¾
3
V
4.0
¾
5
V
3V
VOL=0.3V
0.9
1.8
¾
mA
5V
VOL=0.5V
1.7
3
¾
mA
3V
VOH=2.7V
-0.9
-1.8
¾
mA
5V
VOH=4.5V
-1.7
-3
¾
mA
3V
VOL=0.3V
0.9
1.8
¾
mA
5V
VOL=0.5V
1.7
3
¾
mA
3V
VOH=2.7V
-0.9
-1.8
¾
mA
5V
VOH=4.5V
-1.7
-3
¾
mA
3V
VOL=0.3V
80
160
¾
mA
5V
VOL=0.5V
180
360
¾
mA
3V
VOH=2.7V
-40
-80
¾
mA
5V
VOH=4.5V
-90
-180
¾
mA
3V
VOL=0.3V
50
100
¾
mA
5V
VOL=0.5V
120
240
¾
mA
3V
VOH=2.7V
-30
-60
¾
mA
5V
VOH=4.5V
-70
-140
¾
mA
100
200
300
kW
50
100
150
kW
BZ, BZ, IRQ
BZ, BZ
DATA
DATA
LCD Common Sink Current
LCD Common Source Current
LCD Segment Sink Current
LCD Segment Source Current
3V
Pull-high Resistor
DATA, WR, CS, RD
5V
Rev. 1.90
Max.
DATA, WR, CS, RD
5V
IOL1
Typ.
DATA, WR, CS, RD
5V
VIH
Min.
6
July 22, 2011
PATENTED
HT1623
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
fSYS1
System Clock
5V
On-chip RC oscillator
24
32
40
kHz
fSYS2
System Clock
¾
External clock source
¾
32
¾
kHz
fLCD1
LCD Frame Frequency
5V
On-chip RC oscillator
48
64
80
Hz
fLCD2
External clock source
¾
64
¾
Hz
n: Number of COM
¾
n/fLCD
¾
sec
4
¾
150
kHz
4
¾
300
kHz
¾
¾
75
kHz
¾
¾
150
kHz
CS
700
800
¾
ns
Write mode
3.34
¾
125
Read mode
6.67
¾
¾
Write mode
1.67
¾
125
Read mode
3.34
¾
¾
LCD Frame Frequency
¾
tCOM
LCD Common Period
¾
fCLK1
Serial Data Clock (WR Pin)
3V
Duty cycle 50%
5V
3V
fCLK2
Serial Data Clock (RD Pin)
tCS
Serial Interface Reset Pulse Width
(Figure 3)
Duty cycle 50%
5V
¾
3V
tCLK
WR, RD Input Pulse Width (Figure 1)
5V
ms
ms
tr , tf
Rise/Fall Time Serial Data Clock Width
(Figure 1)
¾
¾
¾
120
160
ns
tsu
Setup Time DATA to WR, RD Clock
Width (Figure 2)
¾
¾
60
120
¾
ns
th
Hold Time DATA to WR, RD Clock Width
(Figure 2)
¾
¾
1000
1200
¾
ns
tsu1
Setup Time for CS to WR, RD Clock
Width (Figure 3)
¾
¾
500
600
¾
ns
th1
Hold Time for CS to WR, RD Clock Width
(Figure 3)
¾
¾
1000
1200
¾
ns
1.5
2.0
2.5
kHz
5V
On-chip RC oscillator
3.0
4.0
5.0
kHz
Tone Frequency (2kHz)
fTONE
Tone Frequency (4kHz)
tOFF
VDD OFF Times (Figure 4)
¾
VDD drop down to 0V
20
¾
¾
ms
tSR
VDD Rising Slew Rate (Figure 4)
¾
¾
0.05
¾
¾
V/ms
tRSTD
Delay Time after Reset (Figure 4)
¾
¾
1
¾
¾
ms
Note:
1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal
Power-on Reset (POR) circuit will not operate normally.
2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions
of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for
20ms (min.) before rising to the normal operating voltage.
Rev. 1.90
7
July 22, 2011
PATENTED
HT1623
V A L ID D A T A
tf
W R , R D
C lo c k
9 0 %
5 0 %
1 0 %
tr
tC
- V
tC
L K
D B
D D
ts
G N D
L K
V
5 0 %
V D D
S
V
W R , R D
C lo c k
th
G N D
0 V
1
V
5 0 %
tO
0 .9 V
R
F F
D D
tR
D D
S T D
G N D
L a s t C lo c k
F ir s t C lo c k
tS
D D
5 0 %
u 1
D D
- G N D
Figure 2
tC
ts
D D
G N D
th
u
W R , R D
C lo c k
Figure 1
C S
V
5 0 %
C S
Figure 3
Figure 4. Power-on Reset Timing
Functional Description
Display Memory - RAM Structure
If an external clock is selected as the source of system
frequency, the SYS DIS command turns out invalid and
the power down mode fails to be carried out until the external clock source is removed.
The static display RAM is organized into 96´4 bits and
stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in
the RAM can be accessed by theREAD, WRITE and
READ-MODIFY-WRITE commands. The following is a
mapping from the RAM to the LCD patterns.
Buzzer Tone Output
A simple tone generator is implemented in the HT1623.
The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate
a single tone.
Time Base and Watchdog Timer - WDT
The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/CLR, WDT
DIS/EN/CLR and IRQ EN/DIS are independent from each
other. Once the WDT time-out occurs, the IRQ pin will
remain at logic low level until the CLR WDT or the IRQ
DIS command is issued.
C O M 7
C O M 6
C O M 5
Command Format
The HT1623 can be configured by the software setting.
There are two mode commands to configure the
HT1623 resource and to transfer the LCD display data.
C O M 3
C O M 4
C O M 2
C O M 1
C O M 0
S E G 0
1
0
S E G 1
3
2
S E G 2
5
4
S E G 3
7
6
S E G 4 7
9 5
9 4
D 3
D 2
D 1
D 0
A d d r
D 3
D a ta
D 2
D 1
D 0
A d d r e s s 7 B its
(A 6 , A 5 , ...., A 0 )
A d d r
D a ta
D a ta 4 B its
(D 3 , D 2 , D 1 , D 0 )
RAM Mapping
Rev. 1.90
8
July 22, 2011
PATENTED
HT1623
T im e B a s e
C lo c k S o u r c e
T IM E R
/2 5 6
V
C L R
T im e r
W D T E N /D IS
D D
Q
D
W D T
/4
IR Q
C K
C L R
IR Q
E N /D IS
E N /D IS
R
W D T
Timer and WDT Configurations
The following are the data mode ID and the command
mode ID:
Mode
ID
READ
Operation
Data
110
WRITE
Data
101
READ-MODIFY-WRITE
COMMAND
Name
Data
101
Command
100
If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the
non-successive address data mode, the CS pin should
be set to ²1² and the previous operation mode will be reset also. The CS pin returns to ²0², a new operation
mode ID should be issued first.
Command Code
Function
TONE OFF
0000-1000-X
Turn-off tone output
TONE 4K
010X-XXXX-X
Turn-on tone output, tone frequency is 4kHz
TONE 2K
0110-XXXX-X
Turn-on tone output, tone frequency is 2kHz
Rev. 1.90
9
July 22, 2011
PATENTED
HT1623
Timing Diagrams
READ Mode (Command Code : 1 1 0)
C S
W R
R D
D A T A
1
A 6
0
1
A 5
A 4
A 3
A 2
A 1
A 0
D 0
D 2
D 1
D 3
1
A 6
0
1
D a ta (M A 1 )
M e m o ry A d d re s s 1 (M A 1 )
A 5
A 3
A 4
A 2
A 1
A 0
D 0
M e m o ry A d d re s s 2 (M A 2 )
D 2
D 1
D 3
D a ta (M A 2 )
READ Mode (Successive Address Reading)
C S
W R
R D
1
D A T A
0
1
A 6
A 5
A 3
A 4
A 2
A 1
A 0
D 0
M e m o ry A d d re s s (M A )
D 2
D 1
D 3
D 0
D 2
D 1
D 3
D 0
D a ta (M A + 1 )
D a ta (M A )
D 2
D 1
D 3
D 0
D a ta (M A + 2 )
D 2
D 1
D 3
D 0
D 2
D 3
D a ta (M A + 3 )
WRITE Mode (Command Code : 1 0 1)
C S
W R
D A T A
1
A 6
1
0
A 5
A 4
A 3
A 2
A 1
A 0
M e m o ry A d d re s s 1 (M A 1 )
D 0
D 1
D 2
D 3
1
A 6
1
0
D a ta (M A 1 )
A 5
A 3
A 4
A 2
A 1
A 0
D 0
M e m o ry A d d re s s 2 (M A 2 )
D 1
D a ta (M A 2 )
WRITE Mode (Successive Address Writing)
C S
W R
D A T A
Rev. 1.90
1
0
1
A 6
A 5
A 4
A 3
A 2
A 1
M e m o ry A d d re s s (M A )
A 0
D 0
D 1
D 2
D a ta (M A )
10
D 3
D 0
D 1
D 2
D a ta (M A + 1 )
D 3
D 0
D 1
D 2
D a ta (M A + 2 )
D 3
D 0
D 1
D 2
D 3
D 0
D a ta (M A + 3 )
July 22, 2011
PATENTED
HT1623
READ-MODIFY-WRITE Mode (Command Code : 1 0 1)
C S
W R
R D
D A T A
1
A 6
1
0
A 5
A 4
A 3
A 2
A 1
A 0
D 0
D 2
D 1
M e m o ry A d d re s s 1 (M A 1 )
D 3
D 0
D 2
D 1
D 3
1
A 6
1
0
D a ta (M A 1 )
D a ta (M A 1 )
A 5
A 4
A 3
A 2
A 1
A 0
M e m o ry A d d re s s 2 (M A 2 )
D 0
D 1
D 2
D 3
D a ta (M A 2 )
READ-MODIFY-WRITE Mode (Successive Address Accessing)
C S
W R
R D
1
D A T A
A 6
1
0
A 5
A 4
A 3
A 2
A 1
A 0
D 0
M e m o ry A d d re s s (M A )
D 1
D 2
D 3
D 0
D 2
D 1
D 3
D 0
D a ta (M A )
D a ta (M A )
D 1
D 2
D 3
D 0
D a ta (M A + 1 )
D 1
D 2
D a ta (M A + 1 )
D 3
D 0
D 1
D 2
D 3
D 0
D a ta (M A + 2 )
Command Mode (Command Code : 1 0 0)
C S
W R
D A T A
1
0
0
C 8
C 7
C 6
C 5
C 4
C 3
C o m m a n d 1
C 2
C 1
C 8
C 0
C o m m a n d ...
C 7
C 6
C 5
C 4
C 3
C 2
C 1
C 0
C o m m a n d i
C o m m a n d
o r
D a ta M o d e
Mode (Data and Command Mode)
C S
W R
D A T A
C o m m a n d
o r
D a ta M o d e
A d d re s s a n d D a ta
C o m m a n d
o r
D a ta M o d e
A d d re s s a n d D a ta
C o m m a n d
o r
D a ta M o d e
A d d re s s a n d D a ta
R D
Rev. 1.90
11
July 22, 2011
PATENTED
HT1623
Application Circuits
V D D
C S
*
*V R
R D
V L C D
W R
D A T A
M C U
H T 1 6 2 3
*R
B Z
P ie z o
IR Q
B Z
O S C I
C lo c k O u t
C O M 0 ~ C O M 7
O S C O
E x te r n a l C lo c k 1 ( 3 2 k H z )
E x te r n a l C lo c k 2 ( 3 2 k H z )
S E G 0 ~ S E G 4 7
1 /4 B ia s , 1 /8 D u ty
O n - c h ip O S C
L C D
P a n e l
C ry s ta l
3 2 7 6 8 H z
Note:
The connection of IRQ and RD pin can be selected depending on the requirement of the MCU.
The voltage applied to VLCD pin must be equal to or lower than VDD.
Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW±20%.
Adjust R (external pull-high resistance) to fit user¢s time base clock.
Command Summary
Name
ID
Command Code
D/C
Function
Def.
READ
1 1 0 A6A5A4A3A2A1A0D0D1D2D3
D
Read data from the RAM
WRITE
1 0 1 A6A5A4A3A2A1A0D0D1D2D3
D
Write data to the RAM
READ-MODIFY1 0 1 A6A5A4A3A2A1A0D0D1D2D3
WRITE
D
Read and Write data to the RAM
SYS DIS
1 0 0 0000-0000-X
C
Turn off both system oscillator and LCD bias
Yes
generator
SYS EN
1 0 0 0000-0001-X
C
Turn on system oscillator
LCD OFF
1 0 0 0000-0010-X
C
Turn off LCD display
LCD ON
1 0 0 0000-0011-X
C
Turn on LCD display
TIMER DIS
1 0 0 0000-0100-X
C
Disable time base output
Yes
WDT DIS
1 0 0 0000-0101-X
C
Disable WDT time-out flag output
Yes
TIMER EN
1 0 0 0000-0110-X
C
Enable time base output
Yes
WDT EN
1 0 0 0000-0111-X
C
Enable WDT time-out flag output
TONE OFF
1 0 0 0000-1000-X
C
Turn off tone outputs
CLR TIMER
1 0 0 0000-1101-X
C
Clear the contents of the time base generator
CLR WDT
1 0 0 0000-1111-X
C
Clear the contents of the WDT stage
RC 32K
1 0 0 0001-10XX-X
C
System clock source, on-chip RC oscillator
EXT (XTAL) 32K 1 0 0 0001-11XX-X
C
System clock source, external 32kHz clock
source or crystal oscillator 32.768kHz
TONE 4K
C
Tone frequency output: 4kHz
Rev. 1.90
1 0 0 010X-XXXX-X
12
Yes
Yes
July 22, 2011
PATENTED
Name
ID
Command Code
D/C
HT1623
Function
TONE 2K
1 0 0 0110-XXXX-X
C
Tone frequency output: 2kHz
IRQ DIS
1 0 0 100X-0XXX-X
C
Disable IRQ output
IRQ EN
1 0 0 100X-1XXX-X
C
Enable IRQ output
F1
1 0 0 101X-0000-X
C
Time base clock output: 1Hz
The WDT time-out flag after: 4s
F2
1 0 0 101X-0001-X
C
Time base clock output: 2Hz
The WDT time-out flag after: 2s
F4
1 0 0 101X-0010-X
C
Time base clock output: 4Hz
The WDT time-out flag after: 1s
F8
1 0 0 101X-0011-X
C
Time base clock output: 8Hz
The WDT time-out flag after: 1/2s
F16
1 0 0 101X-0100-X
C
Time base clock output: 16Hz
The WDT time-out flag after: 1/4s
F32
1 0 0 101X-0101-X
C
Time base clock output: 32Hz
The WDT time-out flag after: 1/8s
F64
1 0 0 101X-0110-X
C
Time base clock output: 64Hz
The WDT time-out flag after: 1/16s
F128
1 0 0 101X-0111-X
C
Time base clock output: 128Hz
The WDT time-out flag after: 1/32s
TEST
1 0 0 1110-0000-X
C
Test mode, user don¢t use.
NORMAL
1 0 0 1110-0011-X
C
Normal mode
Note:
Def.
Yes
Yes
Yes
X : Don¢t care
A6~A0 : RAM address
D3~D0 : RAM data
D/C : Data/Command mode
Def. : Power on reset default
All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command
mode ID. If successive commands have been issued, the command mode ID except for the first command will
be omitted. The source of the tone frequency and of the time base or WDT clock frequency can be derived from
an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the
frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1623 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1623.
Rev. 1.90
13
July 22, 2011
PATENTED
HT1623
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for
the latest version of the package information.
100-pin LQFP (14mm´14mm) Outline Dimensions
C
D
7 5
G
5 1
H
I
5 0
7 6
F
A
B
E
1 0 0
2 6
a
K
J
2 5
1
Symbol
Rev. 1.90
Dimensions in inch
Min.
Nom.
Max.
A
0.626
¾
0.634
B
0.547
¾
0.555
C
0.626
¾
0.634
D
0.547
¾
0.555
E
¾
0.020
¾
F
¾
0.008
¾
G
0.053
¾
0.057
H
¾
¾
0.063
I
¾
0.004
¾
J
0.018
¾
0.030
K
0.004
¾
0.008
a
0°
¾
7°
14
July 22, 2011
PATENTED
HT1623
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.90
15
July 22, 2011