Data Sheet

Enhanced I/O 8-Bit OTP MCU
HT48R068B/HT48R069B
Revision: V1.30
Date: �����������������
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Table of Contents
Features............................................................................................................. 6
CPU Features.......................................................................................................................... 6
Peripheral Features.................................................................................................................. 6
General Description.......................................................................................... 7
Selection Table.................................................................................................. 7
Block Diagram................................................................................................... 7
Pin Assignment................................................................................................. 8
Pin Description............................................................................................... 10
Absolute Maximum Ratings............................................................................11
D.C. Characteristics........................................................................................ 12
A.C. Characteristics........................................................................................ 13
DAC Electrical Characteristics...................................................................... 14
Power-on Reset Characteristics.................................................................... 14
System Architecture....................................................................................... 15
Clocking and Pipelining.......................................................................................................... 15
Program Counter.................................................................................................................... 16
Stack...................................................................................................................................... 17
Arithmetic and Logic Unit – ALU............................................................................................ 17
Program Memory............................................................................................ 18
Structure................................................................................................................................. 18
Special Vectors...................................................................................................................... 19
Look-up Table......................................................................................................................... 19
Table Program Example......................................................................................................... 20
Table Read Program Example............................................................................................... 21
Data Memory................................................................................................... 22
Structure................................................................................................................................. 22
Special Purpose Data Memory.............................................................................................. 23
Special Function Registers............................................................................ 24
Indirect Addressing Registers – IAR0, IAR1.......................................................................... 24
Memory Pointers – MP0, MP1............................................................................................... 24
Accumulator – ACC................................................................................................................ 27
Program Counter Low Register – PCL................................................................................... 27
Bank Pointer – BP.................................................................................................................. 27
Status Register – STATUS..................................................................................................... 28
Input/Output Ports and Control Registers.............................................................................. 29
System Control Registers – CTRL0, CTRL1, CTRL2............................................................ 30
Wake-up Function Register – PAWK..................................................................................... 32
Pull-high Registers – PAPU~PHPU....................................................................................... 32
Software COM Register – SCOMC........................................................................................ 32
Rev. 1.30
2
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Oscillator......................................................................................................... 32
System Oscillator Overview................................................................................................... 32
External Crystal/Resonator Oscillator – HXT......................................................................... 32
External RC Oscillator – ERC................................................................................................ 33
Internal RC Oscillator – HIRC................................................................................................ 34
External 32768Hz Crystal Oscillator – LXT............................................................................ 34
LXT Oscillator Low Power Function....................................................................................... 35
Internal Low Speed Oscillator – LIRC.................................................................................... 35
Operating Modes............................................................................................ 36
Mode Types and Selection..................................................................................................... 36
Mode Switching...................................................................................................................... 37
Standby Current Considerations............................................................................................ 37
Wake-up................................................................................................................................. 38
Watchdog Timer Operation.................................................................................................... 39
Reset and Initialisation................................................................................... 40
Reset Functions..................................................................................................................... 41
Reset Initial Conditions.......................................................................................................... 43
Input/Output Ports.......................................................................................... 45
Pull-high Resistors................................................................................................................. 45
Port A Wake-up...................................................................................................................... 45
I/O Port Control Registers...................................................................................................... 47
Pin-shared Functions............................................................................................................. 48
Pin Remapping Configuration................................................................................................ 49
I/O Pin Structures................................................................................................................... 49
Programming Considerations................................................................................................. 51
Timer/Event Counters.................................................................................... 51
Configuring the Timer/Event Counter Input Clock Source..................................................... 51
Timer Registers – TMR0, TMR1, TMR2L, TMR2H................................................................ 52
Timer Control Registers – TMR0C, TMR1C, TMR2C............................................................ 52
Timer Mode............................................................................................................................ 56
Event Counter Mode.............................................................................................................. 56
Pulse Width Capture Mode.................................................................................................... 57
Prescaler................................................................................................................................ 58
PFD Function......................................................................................................................... 58
I/O Interfacing......................................................................................................................... 59
Programming Considerations................................................................................................. 59
Timer Program Example........................................................................................................ 60
Time Base.............................................................................................................................. 60
Pulse Width Modulator................................................................................... 61
PWM Operation...................................................................................................................... 62
6+2 PWM Mode..................................................................................................................... 62
7+1 PWM Mode..................................................................................................................... 63
PWM Output Control.............................................................................................................. 64
Rev. 1.30
3
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Interrupts......................................................................................................... 65
Interrupt Register................................................................................................................... 65
Interrupt Operation................................................................................................................. 67
Interrupt Priority...................................................................................................................... 68
External Interrupt.................................................................................................................... 69
Timer/Event Counter Interrupt................................................................................................ 69
Multi-function Interrupt........................................................................................................... 69
Programming Considerations................................................................................................. 70
LCD SCOM Function...................................................................................... 71
LCD Operation ...................................................................................................................... 71
LCD Bias Control................................................................................................................... 72
Serial Interface Module – SIM........................................................................ 73
SPI Interface.......................................................................................................................... 73
SPI Registers......................................................................................................................... 75
SPI Communication.............................................................................................................. 78
I2C Interface........................................................................................................................... 80
I2C Registers.......................................................................................................................... 81
I2C Bus Communication......................................................................................................... 85
I2C Bus Start Signal................................................................................................................ 86
Slave Address........................................................................................................................ 86
I2C Bus Read/Write Signal..................................................................................................... 87
I2C Bus Slave Address Acknowledge Signal.......................................................................... 87
I2C Bus Data and Acknowledge Signal.................................................................................. 87
Peripheral Clock Output................................................................................. 89
Peripheral Clock Operation.................................................................................................... 89
SPIA Serial Interface – SPIA.......................................................................... 90
SPIA Interface Communication.............................................................................................. 90
SPIA Registers....................................................................................................................... 90
SPIA Bus Enable/Disable....................................................................................................... 90
SPIA Operation...................................................................................................................... 92
SPIA Configuration Options................................................................................................... 93
Error Detection....................................................................................................................... 94
Programming Considerations................................................................................................. 94
Digital to Analog Converter – DAC ............................................................... 94
Operation............................................................................................................................... 94
Low Voltage Detector – LVD.......................................................................... 96
LVD Register.......................................................................................................................... 96
LVD Operation........................................................................................................................ 96
Configuration Options.................................................................................... 97
Application Circuit.......................................................................................... 98
Rev. 1.30
4
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Instruction Set................................................................................................. 99
Introduction............................................................................................................................ 99
Instruction Timing................................................................................................................... 99
Moving and Transferring Data................................................................................................ 99
Arithmetic Operations............................................................................................................. 99
Logical and Rotate Operation.............................................................................................. 100
Branches and Control Transfer............................................................................................ 100
Bit Operations...................................................................................................................... 100
Table Read Operations........................................................................................................ 100
Other Operations.................................................................................................................. 100
Instruction Set Summary...................................................................................................... 101
Instruction Definition.................................................................................... 103
Package Information.....................................................................................112
28-pin SKDIP (300mil) Outline Dimensions..........................................................................113
28-pin SOP (300mil) Outline Dimensions.............................................................................114
28-pin SSOP (150mil) Outline Dimensions...........................................................................115
44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions.............................................116
64-pin LQFP (7mm×7mm) Outline Dimensions....................................................................117
Rev. 1.30
5
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Features
CPU Features
• Operating voltage:
fSYS= 4MHz: 2.2V~5.5V
fSYS=8MHz: 3.0V~5.5V
fSYS=12MHz: 4.5V~5.5V
• Up to 0.33μs instruction cycle with 12MHz system clock at VDD= 5V
• Idle/Sleep mode and wake-up functions to reduce power consumption
• Oscillator types:
External high frequency Crystal – HXT
External RC – ERC
Internal RC – HIRC
External low frequency crystal – LXT
• Four operational modes: Normal, Slow, Idle, Sleep
• Fully integrated internal 4MHz, 8MHz and 12MHz oscillator requires no external components
• Watchdog Timer function
• LIRC oscillator function for watchdog timer
• All instructions executed in one or two instruction cycles
• Table read instructions
• 63 powerful instructions
• Up to 8-level subroutine nesting
• Bit manipulation instruction
• Low voltage reset function
• Low voltage detect function
• Wide range of available package types
Peripheral Features
• Up to 62 bidirectional I/O lines
• Up to 4 channel 8-bit PWM
• Single channel 12-bit DAC
• Serial Interfaces Module with Dual SPI and I2C interfaces
• Single Serial SPI Interface
• Software controlled 4-SCOM lines LCD COM driver with 1/2 bias
• External interrupt input shared with an I/O line
• Two 8-bit programmable Timer/Event Counter with overflow interrupt and prescaler
• Single 16-bit programmable Timer/Event Counter with overflow interrupt
• Time-Base function
• Programmable Frequency Divider – PFD
Rev. 1.30
6
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
General Description
The Enhanced I/O MCUs are a series of 8-bit high performance, RISC architecture microcontrollers
specifically designed for a wide range of applications. The usual Holtek microcontroller features of
low power consumption, I/O flexibility, timer functions, oscillator options, power down and wakeup functions, watchdog timer and low voltage reset, combine to provide devices with a huge range
of functional options while still maintaining a high level of cost effectiveness. The fully integrated
system oscillator HIRC, which requires no external components and which has three frequency
selections, opens up a huge range of new application possibilities for these devices, some of which
may include industrial control, consumer products, household appliances subsystem controllers, etc.
Selection Table
Program
Memory
Part No.
Data
Memory
I/O
8-bit
Timer
16-bit
Timer
Time
Base
HIRC
(MHz)
HT48R068B
16Kx16
512x8
50
2
1
1
4/8/12
HT48R069B
32Kx16
1024x8
62
2
1
1
4/8/12
Part No.
RTC
LCD
(LXT) SCOM
PWM
D/A
Interface
PFD Stack
Package
HT48R068B
√(*)
4
8-bitx4 12-bitx1 SPI/I2C, SPI
√
8
28SKDIP/SOP/SSOP
44LQFP
HT48R069B
√(*)
4
8-bitx4 12-bitx1 SPI/I2C, SPI
√
8
44/64LQFP
Note: "*" the oscillator is connected to the XT1/XT2 pins with TinyPowerTM design.
Block Diagram
The following block diagram illustrates the main functional blocks.
   Rev. 1.30
 7
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Pin Assignment
PA4/PWM0/TC1/AUD
PA3/INT
PA�/TC0
PA1/P�D
PA0
PC6
PC7
PC0
PC1
PD0/TC�
PD1/PWM3
PB0/SCOM0
PB1/SCOM1
PB�/SCOM�
1
�8
�
�7
3
�6
4
��
�
�4
6
�3
7
��
8
�1
9
�0
10
19
11
18
1�
17
13
16
14
1�
VSS
VDD
PA�/OSC�
PA6/OSC1
PC�/XT1
PC4/XT�
PA7/RES
PC3/PWM1
PC�/PWM�
PD3/PCK
PD�
PB�
PB4
PB3/SCOM3
HT48R068B
28 SKDIP-A/SOP-A/SSOP-A
PC�/XT1
PA6/OSC1
PA�/OSC�
VDD
VSS
PA4/PWM0/TC1/AUD
PA3/INT
PA�/TC0
PA1/P�D
PA0
PC6
PC7
PC0
PC1
PE0
PE1
PE�
PE3
PE4
PE�
PE6
PE7
44 43 4� 41 40 39 38 37 36 3� 34
1
33
�
3�
3
31
4
30
�
�9
HT48R068B
6
�8
44
LQFP-A
7
�7
8
�6
9
��
10
�4
11
�3
1� 13 14 1� 16 17 18 19 �0 �1 ��
PC4/XT�
PA7/RES
PC3/PWM1
PC�/PWM�
PD7/SDO
PD6/SDI/SDA
PD�/SCK/SCL
PD4/SCS
PD3/PCLK
PD�
P�1/SDIA
P�0/SDOA
PB7/SCKA
PB6/SCSA
PB�
PB4
PB3/SCOM3
PB�/SCOM�
PB1/SCOM1
PB0/SCOM0
PD1/PWM3
PD0/TC�
Rev. 1.30
8
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
PC�/XT1
PA6/OSC1
PA�/OSC�
VDD
VSS
PA4/PWM0/TC1/AUD
PA3/INT
PA�/TC0
PA1/P�D
PA0
PC6
PC7
PC0
PC1
PE0
PE1
PE�
PE3
PE4
PE�
PE6
PE7
44 43 4� 41 40 39 38 37 36 3� 34
1
33
�
3�
3
31
4
30
�
�9
HT48R069B
6
�8
44
LQFP-A
7
�7
8
�6
9
��
10
�4
11
�3
1� 13 14 1� 16 17 18 19 �0 �1 ��
PC4/XT�
PA7/RES
PC3/PWM1
PC�/PWM�
PD7/SDO
PD6/SDI/SDA
PD�/SCK/SCL
PD4/SCS
PD3/PCLK
PD�
P�1/SDIA
P�0/SDOA
PB7/SCKA
PB6/SCSA
PB�
PB4
PB3/SCOM3
PB�/SCOM�
PB1/SCOM1
PB0/SCOM0
PD1/PWM3
PD0/TC�
PC3/PWM1
PA7/RES
PC4/XT�
PC�/XT1
PA6/OSC1
PA�/OSC�
VDD
VSS
PA4/PWM0/TC1/AUD
PA3/INT
PA�/TC0
PA1/P�D
PA0
PC6
PC7
PC0
PC1
PE0
PE1
PE�
PE3
PE4
PE�
PE6
PE7
PG0
PG1
PG�
PG3
PG4
PG�
PG6
64 63 6� 6160 �9 �8�7�6 �� �4 �3�� �4 �3 ��
48
1
�
47
3
46
4
4�
�
44
6
43
7
4�
HT48R069B
8
41
9
40
64 LQFP-A
10
39
11
38
37
1�
13
36
3�
14
1�
34
33
16
1718 19 �0�1 ���3 �4�� �6 �7�8 �930313�
PC�/PWM�
PD7/SDO
PD6/SDI/SDA
PD�/SCK/SCL
PD4/SCS
PD3/PCLK
PD�
PH�
PH4
PH3
PH�
PH1
PH0
P�7
P�6
P��
P�4
P�3
P��
P�1/SDIA
P�0/SDOA
PB7/SCKA
PB6/SCSA
PB�
PB4
PB3/SCOM3
PB�/SCOM�
PB1/SCOM1
PB0/SCOM0
PD1/PWM3
PD0/TC�
PG7
Rev. 1.30
9
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Pin Description
Pin Name
Function
PA0
PA0
PA1/PFD
PA2/TC0
PA3/INT
PA1
PFD
PA2
TC0
PA3
INT
PA4
PA4/PWM0/TC1/AUD
PA5/OSC2
PA6/OSC1
PA7/RES
PB0/SCOM0
PB1/SCOM1
PB2/SCOM2
PB3/SCOM3
PB4,PB5
PB6/SCSA
PB7/SCKA
PC0
PC1
PC2/PWM2
PC3/PWM1
PC4/XT2
PC5/XT1
PC6
PC7
PD0/TC2
PD1/PWM3
PD2
Rev. 1.30
PWM0
TC1
AUD
PA5
OSC2
PA6
OSC1
PA7
RES
PB0
SCOM0
PB1
SCOM1
PB2
SCOM2
PB3
SCOM3
PB4,PB5
PB6
SCSA
PB7
SCKA
PC0
PC1
PC2
PWM2
PC3
PWM1
PC4
XT2
PC5
XT1
PC6
PC7
PD0
TC2
PD1
PWM3
PD2
OPT
PAPU
PAWK
PAPU
PAWK
CTRL0
PAPU
PAWK
—
PAPU
PAWK
—
PAPU
PAWK
CTRL0
—
—
PAPU
PAWK
CO
PAPU
PAWK
CO
PAWK
CO
PBPU
SCOMC
PBPU
SCOMC
PBPU
SCOMC
PBPU
SCOMC
PBPU
PBPU
—
PBPU
—
PCPU
PCPU
PCPU
CTRL2
PCPU
CTRL0
PCPU
CO
PCPU
CO
PCPU
PCPU
PDPU
—
PDPU
CTRL2
PDPU
I/T
O/T
ST
CMOS
ST
CMOS
—
CMOS
ST
CMOS
ST
—
ST
CMOS
ST
—
ST
CMOS
—
ST
—
CMOS
—
AN
ST
CMOS
—
OSC
ST
CMOS
OSC
ST
ST
ST
—
ST
—
ST
—
ST
—
ST
ST
ST
ST
ST
ST
ST
ST
—
ST
—
ST
—
ST
—
ST
ST
ST
ST
ST
—
ST
—
NMOS
—
CMOS
SCOM
CMOS
SCOM
CMOS
SCOM
CMOS
SCOM
CMOS
CMOS
—
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
LXT
CMOS
LXT
CMOS
CMOS
CMOS
—
CMOS
CMOS
CMOS
10
Descriptions
General purpose I/O. Register enabled pull-up and
wake-up.
General purpose I/O. Register enabled pull-up and
wake-up.
PFD output
General purpose I/O. Register enabled pull-up and
wake-up.
External Timer 0 clock input
General purpose I/O. Register enabled pull-up and
wake-up.
External Interrupt input
General purpose I/O. Register enabled pull-up and
wake-up.
PWM output
External Timer 1 clock input
DAC output
General purpose I/O. Register enabled pull-up and
wake-up.
Oscillator pin
General purpose I/O. Register enabled pull-up and
wake-up.
Oscillator pin
General purpose I/O. Register enabled wake-up.
Reset input
General purpose I/O. Register enabled pull-up
Software controlled 1/2 bias LCD COM
General purpose I/O. Register enabled pull-up
Software controlled 1/2 bias LCD COM
General purpose I/O. Register enabled pull-up
Software controlled 1/2 bias LCD COM
General purpose I/O. Register enabled pull-up
Software controlled 1/2 bias LCD COM
General purpose I/O. Register enabled pull-up
General purpose I/O. Register enabled pull-up
SPI Slave Select
General purpose I/O. Register enabled pull-up
SPI Serial Clock
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
PWM output
General purpose I/O. Register enabled pull-up.
PWM output
General purpose I/O. Register enabled pull-up.
Low frequency crystal pin
General purpose I/O. Register enabled pull-up.
Low frequency crystal pin
General purpose I/O. Register enabled pull-up .
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up .
External Timer 2 clock input
General purpose I/O. Register enabled pull-up .
PWM output
General purpose I/O. Register enabled pull-up .
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Pin Name
PD3/PCLK
PD4/SCS
PD5/SCK/SCL
PD6/SDI/SDA
PD7/SDO
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PF0/SDOA
PF1/SDIA
PF2~PF7
PG0~PG7
PH0~PH5
VDD
VSS
Function
PD3
PCLK
PD4
SCS
PD5
SCK
SCL
PD6
SDI
SDA
PD7
SDO
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PF0
SDOA
PF1
SDIA
PFn
PGn
PHn
VDD
VSS
OPT
PDPU
—
PDPU
—
PDPU
—
—
PDPU
—
—
PDPU
—
PEPU
PEPU
PEPU
PEPU
PEPU
PEPU
PEPU
PEPU
PFPU
—
PFPU
—
PFPU
PGPU
PHPU
—
—
I/T
ST
—
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
ST
ST
ST
ST
ST
PWR
PWR
O/T
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
NMOS
CMOS
—
NMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
—
CMOS
CMOS
CMOS
—
—
Descriptions
General purpose I/O. Register enabled pull-up .
Peripheral Clock output
General purpose I/O. Register enabled pull-up .
SPI Slave Select
General purpose I/O. Register enabled pull-up .
SPI Serial Clock
I2C Clock
General purpose I/O. Register enabled pull-up .
SPI Data input
I2C Data
General purpose I/O. Register enabled pull-up .
SPI Data output
General purpose I/O. Register enabled pull-up .
General purpose I/O. Register enabled pull-up .
General purpose I/O. Register enabled pull-up .
General purpose I/O. Register enabled pull-up .
General purpose I/O. Register enabled pull-up .
General purpose I/O. Register enabled pull-up .
General purpose I/O. Register enabled pull-up .
General purpose I/O. Register enabled pull-up .
General purpose I/O. Register enabled pull-up .
SPI Data output
General purpose I/O. Register enabled pull-up .
SPI Data input
General purpose I/O. Register enabled pull-up .
General purpose I/O. Register enabled pull-up .
General purpose I/O. Register enabled pull-up .
Power supply
Ground
Note: I/T: Input type; O/T: Output type
OPT: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option
ST: Schmitt Trigger input; CMOS: CMOS output;
AN: Analog output
SCOM: Software controlled LCD COM
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
Absolute Maximum Ratings
Supply Voltage .................................................................................................VSS-0.3V to VSS+6.0V
Input Voltage ...................................................................................................VSS-0.3V to VDD+0.3V
IOL Total .................................................................................................. 100mA
Total Power Dissipation ......................................................................................................... 500mW
Storage Temperature .................................................................................................. -50°C to 125°C
Operating Temperature . ............................................................................................... -40°C to 85°C
IOH Total................................................................................................. -100mA
Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute
Maximum Ratings” may cause substantial damage to the device. Functional operation of
this device at other conditions beyond those listed in the specification is not implied and
prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.30
11
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Operating Voltage
—
IDD1
Operating Current
(HXT, HIRC, ERC)
IDD2
Operating Current
(HXT, HIRC, ERC)
3V
5V
3V
5V
IDD3
Operating Current
(HXT, HIRC, ERC)
IDD4
Operating Current
(HIRC + LXT, Slow Mode)
No load, fSYS=8MHz
Max.
Unit
2.2
3.0
4.5
—
—
—
—
—
—
—
0.8
1.5
1.4
2.8
5.5
5.5
5.5
1.2
2.25
2.1
4.2
V
V
V
mA
mA
mA
mA
—
4
6
mA
3V
No load, fSYS=32768Hz
(LXT on OSC1/OSC2,
LVR disabled, LXTLP=1)
—
5
10
μA
—
12
24
μA
No load, fSYS=32768Hz
(LXT on XT1/XT2,
LVR disabled, LXTLP=1)
—
5
10
μA
—
10
20
μA
—
—
5
μA
—
—
10
μA
—
—
1
μA
—
—
2
μA
No load, system HALT
(LXT on OSC1/OSC2)
—
—
5
μA
—
—
10
μA
No load, system HALT
(LXT on XT1/XT2)
—
—
3
μA
—
—
5
μA
—
0.3VDD
V
VDD
V
0.4VDD
V
5V
3V
ISTB1
Standby Current
(LIRC On, LXT Off)
ISTB2
Standby Current
(LIRC Off, LXT Off)
3V
ISTB3
Standby Current
(LIRC Off, LXT On, LXTLP=1)
5V
5V
3V
5V
3V
5V
VIH1
No load, fSYS=4MHz
Typ.
No load, fSYS=12MHz
3V
Input Low Voltage for I/O,
TCn and INT
Input High Voltage for I/O,
TCn and INT
fSYS=4MHz
fSYS=8MHz
fSYS=12MHz
Min.
5V
5V
VIL1
Conditions
VDD
No load, system HALT
No load, system HALT
—
—
0
—
—
0.7VDD
—
0
—
0.9VDD
—
VDD
V
3.98
2.98
1.98
4.12
3.12
2.08
4.2
3.15
2.1
4.4
3.3
2.2
4.42
3.32
2.22
4.70
3.50
2.32
V
V
V
V
V
V
VIL2
Input Low Voltage (RES)
—
VIH2
Input High Voltage (RES)
—
VLVR1
VLVR2
VLVR3
VLVD1
VLVD2
VLVD2
Low Voltage Reset 1
Low Voltage Reset 2
Low Voltage Reset 3
Low Voltage Detector Voltage 1
Low Voltage Detector Voltage 2
Low Voltage Detector Voltage 3
—
—
—
—
—
—
IOL1
I/O Port Sink Current
(PA, PB, PC, PD, PE, PF, PG, PH)
3V
IOH
I/O Port Source Current
IOL2
PA7 Sink Current
RPH
Pull-high Resistance
ISCOM
SCOM Operating Current
5V
VSCOM
VDD/2 Voltage for LCD COM
5V
5V
3V
5V
5V
3V
5V
VLVR=4.2V
VLVR=3.15V
VLVR=2.1V
VLVD= 4.4 V
VLVD= 3.3 V
VLVD= 2.2 V
VOL=0.1VDD
VOH=0.9VDD
VOL=0.1VDD
—
—
SCOMC, ISEL[1:0]=00
SCOMC, ISEL[1:0]=01
SCOMC, ISEL[1:0]=10
SCOMC, ISEL[1:0]=11
No load
—
—
4
8
—
mA
10
20
—
mA
-2
-5
2
20
10
17.5
35
70
140
0.475
-4
-10
3
60
30
25.0
50
100
200
0.500
—
—
—
100
50
32.5
65
130
260
0.525
mA
mA
mA
kΩ
kΩ
μA
μA
μA
μA
VDD
Note: The standby current (ISTB1~ISTB3) and IDD4 are measured with all I/O pins in input mode and tied to VDD.
Rev. 1.30
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HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
A.C. Characteristics
Ta=25°C
Symbol
fSYS
fHIRC
Parameter
System Clock
System Clock (HIRC)
Test Conditions
—
Typ.
Max.
Unit
2.2V~5.5V
32
—
4000
kHz
3.0V~5.5V
32
—
8000
kHz
4.5V~5.5V
32
—
12000
kHz
Conditions
3V/5V
Ta=25°C
-2%
4
+2%
MHz
3V/5V
Ta=25°C
-2%
8
+2%
MHz
5V
Ta=25°C
-2%
12
+2%
MHz
3V/5V
Ta=0~70°C
-5%
4
+5%
MHz
3V/5V
Ta=0~70°C
-5%
8
+5%
MHz
5V
Ta=0~70°C
-5%
12
+5%
MHz
2.2V~3.6V Ta=0~70°C
-8%
4
+8%
MHz
3.0V~5.5V Ta=0~70°C
-8%
4
+8%
MHz
3.0V~5.5V Ta=0~70°C
-8%
8
+8%
MHz
4.5V~5.5V Ta=0~70°C
-8%
12
+8%
MHz
2.2V~3.6V Ta=-40°C~85°C
-12%
4
+12%
MHz
3.0V~5.5V Ta=-40°C~85°C
-12%
4
+12%
MHz
3.0V~5.5V Ta=-40°C~85°C
-12%
8
+12%
MHz
4.5V~5.5V Ta=-40°C~85°C
-12%
12
+12%
MHz
5V
Ta=25°C, R=120KΩ*
-2%
4
+2%
MHz
5V
Ta=0~70°C, R=120KΩ*
-5%
4
+5%
MHz
5V
Ta=-40°C~85°C, R=120KΩ*
-7%
4
+7%
MHz
2.2V~5.5V Ta=-40°C~85°C, R=120KΩ*
-11%
4
+11%
MHz
—
32768
—
Hz
2.2V~5.5V
3.0V~5.5V
0
0
—
—
4000
8000
kHz
4.5V~5.5V
0
—
12000
kHz
kHz
fERC
System Clock (ERC)
fLXT
System Clock (LXT)
—
Timer Input Frequency
(TCn)
—
tTIMER
Min.
VDD
—
3V
—
5
10
15
kHz
5V
—
6.5
13
19.5
kHz
tRES
External Reset Low Pulse
Width
—
—
1
—
—
μs
tSST
System Start-up time Period
—
tINT
Interrupt Fulse Width
—
—
—
—
—
1
1204
2
1024
—
—
—
—
—
tSYS
tSYS
tSYS
μs
tLVR
Low Voltage Width to Reset
—
—
0.25
1
2
ms
—
—
—
100
—
ms
fLIRC
LIRC Oscillator
For HXT/LXT
RESTD Reset Delay Time
For ERC/IRC
(By configuration option)
Note: 1. tSYS=1/fSYS
2.*For fERC, as the resistor tolerance will influence the frequency a percision resistor is recommended.
3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
Rev. 1.30
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HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
DAC Electrical Characteristics
Symbol
Parameter
Test Conditions
VDAC
DAC operating voltage
VDD
—
IQ
DAC quiescent current
5V
IDAC
DAC operating current
5V
RES
VO
Resolution
Output Voltage Level
—
—
Conditions
—
Code= 0000H
VOL=00H
1 kHz sin wave, full-scale
( 8K sample rate )
—
—
Min.
Typ.
Max.
Unit
2.4
—
—
V
—
2
3
mA
—
3
4.5
mA
—
0.01
—
—
12
0.99
bit
VDD
Power-on Reset Characteristics
Ta=25°C
Symbol
VPOR
RRVDD
tPOR
Parameter
VDD Start Voltage to Ensure
Power-on Reset
VDD Raising Rate to Ensure
Power-on Reset
Minimum Time for VDD to remain
at VPOR to ensure Power-on
Reset
VDD
Test Conditions
Conditions
Typ.
Max.
Unit
—
—
—
—
100
mV
—
—
0.035
—
—
V/ms
—
—
1
—
—
ms
Rev. 1.30
Min.
14
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to the internal system architecture. The range of devices take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and enhanced performance.
The pipelining scheme is implemented in such a way that instruction fetching and instruction
execution are overlapped, hence instructions are effectively executed in one cycle, with the
exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations
of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment,
decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and
can be directly or indirectly addressed. The simple addressing methods of these registers along
with additional architectural features ensure that a minimum of external components is required to
provide a functional I/O control system with maximum reliability and flexibility.
Clocking and Pipelining
The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into
four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at
the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecutive
instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the
contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the
instruction will take one more instruction cycle to execute.
For instructions involving branches, such as jump or call instructions, two instruction cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.​
   
 
  
System Clocking and Pipelining
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HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
  
    
 Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the next
instruction to be executed. It is automatically incremented by one each time an instruction is
executed except for instructions, such as "JMP" or "CALL" that demand a jump to a non-consecutive
Program Memory address. Note that the Program Counter width varies with the Program Memory
capacity depending upon which device is selected. However, it must be noted that only the lower 8
bits, known as the Program Counter Low Register, are directly addressable by user.
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control
by loading the required address into the Program Counter. For conditional skip instructions, once
the condition has been met, the next instruction, which has already been fetched during the present
instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is
obtained.
Program Counter
DEVICE
Program Counter
High Byte
HT48R068B
PC13~PC8
HT48R069B
PC14~PC8
14
13
12
8 7
PCL Register
PCL7~PCL0
0
Program Counter
BP 6 BP 5
Bank Pointer(BP)
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly, however, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory, that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle will
be inserted.
The lower byte of the Program Counter is fully accessible under program control. Manipulating the
PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information
on the PCL register can be found in the Special Function Register section.
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Enhanced I/O 8-Bit OTP MCU
Stack
This is a special part of the memory which is used to save the contents of the Program Counter
only. The stack is neither part of the Data or Program Memory space, and is neither readable nor
writeable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor
writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter
are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return
instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After
a device reset, the Stack Pointer will point to the top of the stack.
P ro g ra m
T o p o f S ta c k
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
B o tto m
C o u n te r
P ro g ra m
M e m o ry
S ta c k L e v e l 3
o f S ta c k
S ta c k L e v e l 8
Device
Stack Levels
HT48R068B
HT48R069B
8
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,
the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use
the structure more easily. However, when the stack is full, a CALL subroutine instruction can still
be executed which will result in a stack overflow. Precautions should be taken to avoid such cases
which might cause unpredictable program branching.
Arithmetic and Logic Unit – ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
• Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
• Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
• Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
• Increment and Decrement INCA, INC, DECA, DEC
• Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
Rev. 1.30
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HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Program Memory
The Program Memory is the location where the user code or program is stored. The device is
supplied with One-Time Programmable, OTP, memory where users can program their application
code into the device. By using the appropriate programming tools, OTP devices offer users the
flexibility to freely develop their applications which may be useful during debug or for products
requiring frequent upgrades or program changes.
Structure
The Program Memory has a capacity of 16Kx16/32Kx16. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupt entries. Table data, which
can be setup in any location within the Program Memory, is addressed by separate table pointer
registers.
Device
Capacity
Banks
HT48R068B
16Kx16
0,1
HT48R069B
32Kx16
0~3
The devices have their Program Memory divided into a number of banks which are selected using
the Bank Pointer register. The HT48R068B has its Program Memory divided into two Banks, Bank
0 and Bank 1. The required Bank is selected using Bit 5 of the BP Register. The HT48R069B has
its Program Memory divided into four banks, from Bank0 to Bank3. The required Bank is selected
using Bit 5 and Bit 6 of the BP Register.


 
 
    Rev. 1.30
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February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and
interrupts.
Reset Vector
This vector is reserved for use by the device reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.
External interrupt vector
This vector is used by the external interrupt. If the external interrupt pin on the device receives an
edge transition, the program will jump to this location and begin execution if the external interrupt is
enabled and the stack is not full. The external interrupt active edge transition type, whether high to
low, low to high or both is specified in the CTRL1 register.
Timer/Event 0/1/2 counter interrupt vector
This internal vector is used by the Timer/Event Counters. If a Timer/Event Counter overflow occurs,
the program will jump to its respective location and begin execution if the associated Timer/Event
Counter interrupt is enabled and the stack is not full.
Multi-function interrupt vector
The Multi-function Interrupt vector is shared by several internal functions: a Time Base overflow,
an SPI/I2C or SPIA data transfer completion. The program will jump to this location and begin
execution if the relevant interrupt is enabled and the stack is not full.
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower
order address of the look up data to be retrieved in the table pointer register, TBLP. This register
defines the lower 8-bit address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the current Program Memory
page or last Program Memory page using the "TABRDC[m]" or "TABRDL[m]" instructions,
respectively. When these instructions are executed, the lower order table byte from the Program
Memory will be transferred to the user defined Data Memory register [m] as specified in the
instruction. The higher order table data byte from the Program Memory will be transferred to the
TBLH special register. Any unused bits in this transferred higher order byte will be read as "0".
The following diagram illustrates the addressing/data flow of the look-up table:
Rev. 1.30
   19
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Table Program Example
The accompanying example shows how the table pointer and table data is defined and retrieved from
the device. This example uses raw table data located in the last page which is stored there using the
ORG and rombank statement. The value at this ORG statement is "7F00H" which refers to the start
address of the last page within the 32K Program Memory of the microcontrollers. The table pointer
is setup here to have an initial value of "06H". This will ensure that the first data read from the data
table will be at the Program Memory address "7F06H" or 6 locations after the start of the last page.
Note that the value for the table pointer is referenced to the first address of the present page if the
"TABRDC [m]" instruction is being used. The high byte of the table data which in this case is equal
to zero will be transferred to the TBLH register automatically when the "TABRDL [m]" instruction
is executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use the table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
Instruction(s)
Table Location
b7
b6
b5
b4
b3
b2
b1
TABRDC [m] PC14 PC13 PC12 PC11 PC10 PC9 PC8 @7
@6
@5
@4
@3
@2
@1 @0
TABRDL [m]
b14 b13 b12 b11 b10
1
1
1
1
1
b9
1
b8
1
b0
@7 @6 @5 @4 @3 @2 @1 @0
Note: PC14~PC13: refer to BP.6~BP.5, which are used to specify program memory bank. PC12~PC8: Current Program Counter bits. @[email protected]: Table Pointer TBLP bits
For the HT48R068B, the Table address location is 14 bits, i.e. from b13~b0
For the HT48R069B, the Table address location is 15 bits, i.e. from b14~b0
Rev. 1.30
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HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Table Read Program Example
rombank 3 code3
tempreg1db ? ; temporary register #1
tempreg2db ? ; temporary register #2
:
:
mova,060h
mov bp,a ; select the last bank of prog. memory
mov a, 06h ; initialise table pointer - note that this address is referenced
mov tblp,a ; to the last page or present page
mov a, 7fh ; initialise high table pointer
; HT48R069B ROM=32K, TBHP=7FH
; HT48R068B ROM=16K, TBHP=3FH
mov tbhp, a ; it is not necessary to set tbhp if executing tabrdl
:
:
tabrdctempreg1
tabrdltempreg1; transfers value in table referenced by table pointer to tempregl
; data at prog. memory address "7F06H" transferred to tempreg1 and
TBLH
dec tblp ; reduce value of table pointer by one
tabrdctempreg2
tabrdltempreg2; transfers value in table referenced by table pointer to tempreg2
; data at prog.memory address "7F05H" transferred to tempreg2 and
TBLH
; in this example the data "1AH" is transferred to
; tempreg1 and data "0FH" to register tempreg2
; the value "00H" will be transferred to the high byte register TBLH
:
:
Code3 .section `code`
org 1F00h ; sets initial address of last page
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Rev. 1.30
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HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored.
Structure
Divided into two sections, the first of these is an area of RAM where special function registers are
located. These registers have fixed locations and are necessary for correct operation of the device.
Many of these registers can be read from and written to directly under program control, however,
some remain protected from user manipulation. The second area of Data Memory is reserved for
general purpose use. All locations within this area are read and write accessible under program
control.
Device
Capacity
Banks
HT48R068B
512x8
0~3
HT48R069B
1024x8
0~7
The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are
located at consecutive locations. All are implemented in RAM and are 8 bits wide but the length of
each memory section is dictated by the type of microcontroller chosen. The start address of the Data
Memory for all devices is the address "00H".
All microcontroller programs require an area of read/write memory where temporary data can be
stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose
Data Memory. This area of Data Memory is fully accessible by the user program for both read and
write operations. By using the "SET [m].i" and "CLR [m].i" instructions individual bits can be set
or reset under program control giving the user a large range of flexibility for bit manipulation in the
Data Memory.
For some devices, the Data Memory is subdivided into several banks, which are selected using
a Bank Pointer. Only data in Bank 0 can be directly addressed, data in Bank 1~Bank 7 must be
indirectly addressed.
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HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
S p e c ia l P u r p o s e
D a ta M e m o ry
0 0 H
7 F H
8 0 H
B a n k 0
G e n e ra l P u rp o s e
D a ta M e m o ry
F F H
B a n k 0
B a n k 1 ~ 3
G e n e ra l P u rp o s e
D a ta M e m o ry
B a n k 1
B a n k 2
B a n k 3
HT48R068B
S p e c ia l P u r p o s e
D a ta M e m o ry
0 0 H
7 F H
8 0 H
B a n k 0
G e n e ra l P u rp o s e
D a ta M e m o ry
F F H
B a n k 0
B a n k 1 ~ 7
G e n e ra l P u rp o s e
D a ta M e m o ry
B a n k 1
B a n k 2
B a n k 3
B a n k 7
HT48R069B
Data Memory Structure
Note: Most of the Data Memory bits can be directly manipulated using the "SET [m].i" and "CLR
[m].i" with the exception of a few dedicated bits. The Data meomory can also be accessed
through the memory pointer registers.
Special Purpose Data Memory
This area of Data Memory is where registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are both readable and writeable but some are
protected and are readable only, the details of which are located under the relevant Special Function
Register section. Note that for locations that are unused, any read instruction to these addresses will
return the value "00H".
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HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in
the Data Memory area. These registers ensure correct operation of internal functions such as timers,
interrupts, etc., as well as external functions such as I/O data control. The location of these registers
within the Data Memory begins at the address "00H" and are mapped from Bank 0 to Bank 7. Any
unused Data Memory locations between these special function registers and the point where the
General Purpose Memory begins is reserved and attempting to read data from these locations will
return a value of "00H".
Indirect Addressing Registers – IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM
register space, do not actually physically exist as normal registers. The method of indirect addressing
for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in
contrast to direct memory addressing, where the actual memory address is specified. Actions on the
IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather
to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as
a pair, IAR0 with MP0 and IAR1 with MP1 can together access data from the Data Memory. As
the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing
Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in
no operation.
Memory Pointers – MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be manipulated in the same way as normal
registers providing a convenient way with which to indirectly address and track data. MP0 can only
be used to indirectly address data in Bank 0 while MP1 can be used to address data from Bank 0
and Bank 7. When any operation to the relevant Indirect Addressing Registers is carried out, the
actual address that the microcontroller is directed to, is the address specified by the related Memory
Pointer. Note that indirect addressing using MP1 and IAR1 must be used to access any data in Bank
1~Bank 7 . The following example shows how to clear a section of four Data Memory locations
already defined as locations adres1 to adres4.
Rev. 1.30
HT48R068B
HT48R069B
00H
IAR0
IAR0
01H
MP0
MP0
02H
IAR1
IAR1
03H
MP1
MP1
04H
BP
BP
05H
ACC
ACC
06H
PCL
PCL
07H
TBLP
TBLP
08H
TBLH
TBLH
09H
WDTS
WDTS
0AH
STATUS
STATUS
0BH
INTC0
INTC0
0CH
TMR0
TMR0
0DH
TMR0C
TMR0C
0EH
TMR1
TMR1
24
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
HT48R068B
HT48R069B
0FH
TMR1C
TMR1C
10H
PA
PA
11H
PAC
PAC
12H
PAPU
PAPU
13H
PAWK
PAWK
14H
PB
PB
15H
PBC
PBC
16H
PBPU
PBPU
17H
PC
PC
18H
PCC
PCC
19H
PCPU
PCPU
1AH
CTRL0
CTRL0
1BH
CTRL1
CTRL1
1CH
SCOMC
SCOMC
1DH
PWM1
PWM1
1EH
INTC1
INTC1
1FH
PWM0
PWM0
24H
MFIC
MFIC
25H
PD
PD
26H
PDC
PDC
27H
PDPU
PDPU
28H
PE
PE
29H
PEC
PEC
2AH
PEPU
PEPU
20H
21H
22H
23H
2BH
PF
PF
2CH
PFC
PFC
2DH
PFPU
PFPU
2EH
2FH
30H
PWM2
PWM2
31H
CTRL2
CTRL2
…
…
32H
…
3AH
3BH
Rev. 1.30
PG
3CH
PGC
3DH
PGPU
3EH
PH
3FH
PHC
40H
PHPU
41H
TMR2L
TMR2L
42H
TMR2H
TMR2H
25
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
HT48R068B
HT48R069B
43H
TMR2C
TMR2C
44H
PWM3
PWM3
45H
46H
SIMC0
SIMC0
47H
SIMC1
SIMC1
48H
SIMD
SIMD
49H
SIMA/SIMC2
SIMA/SIMC2
4AH
SBCR
SBCR
4BH
SBDR
SBDR
4CH
4DH
4EH
4FH
50H
DAL
DAL
51H
DAH
DAH
52H
VOL
VOL
LVDC
LVDC
514 bytes
4 banks
(80H~FFH)
1024 bytes
8 banks
(80H~FFH)
53H
54H
…..
7FH
Genernal
purpose
data
memory
Indirect Addressing Program Example
data .section 'data'
adres1
db ?
adres2
db ?
adres3
db ?
adres4
db ?
blockdb ?
code .section at 0 code
org
00h
start:
mov a,04h
; setup
mov block,a
mov a,offset adres1
mov mp0,a
loop:
clr IAR0
; clear
inc mp0
sdz block
; check
jmp loop
continue:
size of block
; Accumulator loaded with first RAM address
; setup memory pointer with first RAM address
the data at address defined by MP0
; increment memory pointer
if last memory location has been cleared
The important point to note here is that in the example shown above, no reference is made to specific
Data Memory addresses.
Rev. 1.30
26
February 05, 2015
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Enhanced I/O 8-Bit OTP MCU
Accumulator – ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
Program Counter Low Register – PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Bank Pointer – BP
In the HT48R068B and HT48R069B devices, the Data Memory is divided into several Banks, from
Bank 0 to Bank 7. A Bank Pointer is used to select the required Data Memory bank. Only data in
Bank 0 can be directly addressed as data in Bank 1~Bank 7 must be indirectly addressed using
Memory Pointer MP1 and Indirect Addressing Register IAR1. Using Memory Pointer MP0 and
Indirect Addressing Register IAR0 will always access data from Bank 0, irrespective of the value
of the Bank Pointer. Memory Pointer MP1 and Indirect Addressing Register IAR1 can indirectly
address data in either Bank 0 or Bank 1~Bank 7 depending upon the value of the Bank Pointer.
The Data Memory is initialised to Bank 0 after a reset, except for the WDT time-out reset in the Idle/
Sleep Mode, in which case, the Data Memory bank remains unaffected. It should be noted that Special
Function Data Memory is not affected by the bank selection, which means that the Special Function
Registers can be accessed from within either Bank 0 or Bank 1~Bank 7. Directly addressing the Data
Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer.
HT48R068B
Bit
Name
R/W
POR
Rev. 1.30
7
—
—
—
6
—
—
—
5
PMBP0
R/W
0
4
—
—
—
3
—
—
—
Bit 7~6
unimplemented, read as "0"
Bit 5
PMBP0: Program Memory Bank Pointer
0: Bank 0
1: Bank 1
Bit 4~2
unimplemented, read as "0"
Bit 1,0
DMBP1,DMBP0: Data Memory Bank Pointer
00:Bank 0
01:Bank 1
10:Bank 2
11:Bank 3
27
2
—
—
—
1
DMBP1
R/W
0
0
DMBP0
R/W
0
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
HT48R069B
Bit
BP
R/W
POR
7
—
—
—
6
PMBP1
R/W
0
5
PMBP0
R/W
0
4
—
—
—
3
—
—
—
2
DMBP2
R/W
0
Bit 7 unimplemented, read as "0"
Bit 6, 5
PMBP1, PMBP0: Program Memory Bank Pointer
00: Bank 0
01: Bank 1
10: Bank 2
11: Bank 3
Bit 4~3
unimplemented, read as "0"
Bit 2~0
DMBP2, DMBP1, DMBP0: Data Memory Bank Pointer
000: Bank 0
001: Bank 1
010: Bank 2
011: Bank 3
100: Bank 4
101: Bank 5
110: Bank 6
111: Bank 7
1
DMBP1
R/W
0
0
DMBP0
R/W
0
Status Register – STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation
and system management flags are used to record the status and operation of the microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing
the "HALT" or "CLR WDT" instruction or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and
if the interrupt routine can change the status register, precautions must be taken to correctly save it.
Note that bits 0~3 of the STATUS register are both readable and writeable bits.
Rev. 1.30
28
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the port PA, PB, etc data I/O registers and their
associated control register PAC, PBC, etc play a prominent role. These registers are mapped to
specific addresses within the Data Memory as shown in the Data Memory table. The data I/O
registers, are used to transfer the appropriate output or input data on the port. The control registers
specifies which pins of the port are set as inputs and which are set as outputs. To setup a pin as an
input, the corresponding bit of the control register must be set high, for an output it must be set low.
During program initialisation, it is important to first setup the control registers to specify which
pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One
flexible feature of these registers is the ability to directly program single bits using the "SET [m].i"
and "CLR [m].i" instructions. The ability to change I/O pins from output to input and vice versa by
manipulating specific bits of the I/O control registers during normal program operation is a useful
feature of these devices.
STATUS Register
Bit
Name
R/W
POR
7
—
—
—
6
—
—
—
5
TO
R
0
4
PDF
R
0
3
OV
R/W
X
2
Z
R/W
X
1
AC
R/W
X
0
C
R/W
X
"X" unknown
Rev. 1.30
Bit 7,6
Unimplemented, read as "0"
Bit 5
TO: Watchdog Time-Out flag
0: After power up or executing the "CLR WDT" or "HALT" instruction
1: A watchdog time-out occured.
Bit 4 PDF: Power down flag
0: After power up or executing the "CLR WDT" instruction
1: By executing the "HALT" instruction
Bit 3
OV: Overflow flag
0: no overflow
1: an operation results in a carry into the highest-order bit but not a carry out of
thehighest-order bit or vice versa.
Bit 2
Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is not zero
Bit 1
AC: Auxiliary flag
0: no auxiliary carry
1: an operation results in a carry out of the low nibbles in addition, or no borrow
from the high nibble into the low nibble in subtraction
Bit 0
C: Carry flag
0: no carry-out
1: an operation results in a carry during an addition operation or if a borrow does
not take place during a subtraction operation
C is also affected by a rotate through carry instruction.
29
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HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
System Control Registers – CTRL0, CTRL1, CTRL2
These registers are used to provide control over various internal functions. Some of these include
the PFD control, PWM control, certain system clock options, the LXT Oscillator low power control,
external Interrupt edge trigger type, Watchdog Timer enable function, Time Base function division
ratio, and the LXT oscillator enable control.
CTRL0 Register
Rev. 1.30
Bit
7
6
Name
PCFG
PFDCS
5
R/W
R/W
R/W
R/W
POR
0
0
0
4
3
2
1
0
PWMC0
PFDC
LXTLP
CLKMOD
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
PWMSEL PWMC1
Bit 7
PCFG: I/O configuration
0: (PWM0/TC1)/INT/PFD pin-shared with PA4/PA3/PA1
1: (PWM0/TC1)/INT/PFD pin-shared with PB5/PB4/PB3
Bit 6
PFDCS: PFD clock source
0: timer0
1: timer1
Bit 5
PWMSEL: PWM type selection
0: 6+2
1: 7+1
Bit 4
PWMC1: I/O or PWM1
0: I/O
1: PWM1
Bit 3
PWMC0: I/O or PWM0
0: I/O
1: PWM0
Bit 2
PFDC: I/O or PFD
0: I/O
1: PFD
Bit 1
LXTLP: LXT oscillator low power control function
0: LXT Oscillator quick start-up mode
1: LXT Oscillator Low Power Mode
Bit 0
CLKMOD: system clock mode selection.
0: High speed system clock
1: LXT system clock, high speed oscillator stopped
Note: If PWM0/1/2/3 output is selected by PWMC0/1/2/3 bit, fTP comes always from
fSYS. (fTP is the clock source for timer0, time base and PWM)
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February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
CTRL1 Register
Bit
7
6
5
4
Name
INTEG1
INTEG0
TBSEL1
TBSEL0
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
0
0
0
1
0
1
0
WDTEN3 WDTEN2 WDTEN1 WDTEN0
Bit 7, 6
INTEG1, INTEG0: External interrupt edge type
00: disable
01: rising edge trigger
10: falling edge trigger
11: dual edge trigger
Bit 5, 4
TBSEL1, TBSEL0: Time base period selection
00: 210 x (1/fTP)
01: 211 x (1/fTP)
10: 212 x (1/fTP)
11: 213 x (1/fTP)
Bit 3~0
WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable
1010: WDT disabled
Other values: WDT enabled - Recommended value is 0101
If the "watchdog timer enable" is configuration option is selected, then the watchdog
timer will always be enabled and the WDTEN3~WDTEN0 control bits will have no
effect.
Note: The WDT is only disabled when both the WDT configuration option is disabled
and when bits WDTEN3~WDTEN0=1010. The WDT is enabled when either the
WDT configuration option is enabled or when bits WDTEN3~WDTEN0≠1010.
CTRL2 Register
Rev. 1.30
Bit
7
6
5
4
3
2
1
0
Name
DACEN
—
PWMC3
PWMC2
—
—
—
LXTEN
R/W
R/W
—
R/W
R/W
—
—
—
R/W
POR
0
—
0
0
—
—
—
1
Bit 7
DACEN: DAC disable/enable control
0: disable
1: enable
Bit 6
unimplemented, read as "0"
Bit 5
PWMC3: IO or PWM3 control
0: I/O
1: PWM3 output
Bit4
PWMC2: IO or PWM2 control
0: I/O
1: PWM2 output
Bit 3~1
unimplemented, read as "0"
Bit 0
LXTEN: LXT Oscillator on/off control after execution of HALT instruction
0: LXT off in Idle Mode
1: LXT on in Idle mode
31
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Wake-up Function Register – PAWK
When the microcontroller enters the Idle/Sleep Mode, various methods exist to wake the device up
and continue with normal operation. One method is to allow a falling edge on the I/O pins to have a
wake-up function. This register is used to select which Port A I/O pins are used to have this wake-up
function.
Pull-high Registers – PAPU~PHPU
The I/O pins, if configured as inputs, can have internal pull-high resistors connected, which eliminates
the need for external pull-high resistors. This register selects which I/O pins are connected to internal
pull-high resistors.
Software COM Register – SCOMC
The pins PB0~PB3 on Port B can be used as SCOM lines to drive an external LCD panel. To
implement this function, the SCOMC register is used to setup the correct bias voltages on these pins.
Oscillator
Various oscillator options offer the user a wide range of functions according to their various
application requirements. The flexible features of the oscillator functions ensure that the best
optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation
are selected through a combination of configuration options and registers.
System Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources
for other functions such as the Watchdog Timer, Timer/Event Counter, Time Base etc. The system
oscillator can be provided from a choice of three high speed oscillators, the HXT, ERC or HIRC
oscillators, or a single low speed, LXT crystal oscillator. The LIRC oscillator is used only as a
Watchdog Timer clock source.
Type
External Crystal
Name
Freq.
Pins
Function
HXT
OSC1/
400kHz~12MHz OSC2
High Speed System Clock
400kHz~12MHz OSC1
High Speed System Clock
External RC
ERC
Internal Highb Speed RC
HIRC
4, 8 or 12MHz
—
High Speed System Clock
External Low Speed Crystal
LXT
32768Hz
XT1/
XT2
Low Speed System Clock
Clock source for: Watchdog, Time
Base, Timer/Event Counters 0/1
Clock/SPI/SPIA
Internal Low Speed RC
LIRC
13kHz
—
Watchdog Timer Clock
External Crystal/Resonator Oscillator – HXT
The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and
feedback for oscillation. However, for some crystals and most resonator types, to ensure oscillation
and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and
C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator
manufacturer's specification.
For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure
that the crystal and any associated resistors and capacitors along with inter connecting lines are all
located as close to the MCU as possible.
Rev. 1.30
32
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
     Crystal/Resonator Oscillator — HXT
Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
12MHz
8pF
8MHz
8pF
4MHz
8pF
1MHz
100pF
Note: C1 and C2 values are for guidance only.
C2
10pF
10pF
10pF
100pF
Crystal Recommended Capacitor Values
External RC Oscillator – ERC
Using the ERC oscillator only requires that a resistor, with a value between 24kΩ and 1.5MΩ,
is connected between OSC1 and VDD, and a capacitor is connected between OSC and ground,
providing a low cost oscillator configuration. It is only the external resistor that determines the
oscillation frequency; the external capacitor has no influence over the frequency and is connected
for stability purposes only. Device trimming during the manufacturing process and the inclusion
of internal frequency compensation circuits are used to ensure that the influence of the power
supply voltage, temperature and process variations on the oscillation frequency are minimised. As a
resistance/frequency reference point, it can be noted that with an external 120K resistor connected
and with a 5V voltage power supply and temperature of 25 degrees, the oscillator will have a
frequency of 4MHz within a tolerance of 2%. Here only the OSC1 pin is used, which is shared with
I/O pin PA6, leaving pin PA5 free for use as a normal I/O pin.
For oscillator stability and to minimise the effects of noise and crosstalk, it is important to locate the
capacitor and resistoras close to the MCU as possible.
External RC Oscillator — ERC
Rev. 1.30
33
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Internal RC Oscillator – HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has three fixed frequencies of either 4MHz, 8MHz or 12MHz. Device
trimming during the manufacturing process and the inclusion of internal frequency compensation
circuits are used to ensure that the influence of the power supply voltage, temperature and process
variations on the oscillation frequency are minimised. As a result, at a power supply of either 3V or
5V and at a temperature of 25 degrees, the fixed oscillation frequency of 4MHz, 8MHz or 12MHz
will have a tolerance within 2%. Note that if this internal system clock option is selected, as it
requires no external pins for its operation, I/O pins PA5 and PA6 are free for use as normal I/O pins.
P A 5 /O S C 2
P A 6 /O S C 1
In te rn a l R C
O s c illa to r
N o te : P A 5 /P A 6 u s e d a s n o rm a l I/O s
Internal RC Oscillator — HIRC
External 32768Hz Crystal Oscillator – LXT
The LXT oscillator is used both as the slow system clock and also as a selectable source clock for
some peripheral functions including the Watchdog Timer, Time Base, Timer/Event Counters and SPI
functions. It must be first enabled using a configuration option.
To select the LXT oscillator to be the low speed system oscillator, the CLKMOD bit in the CTRL0
register should be set high. When a HALT instruction is executed, the system clock is stopped, but
the LXTEN bit in the CTRL2 register determines if the LXT oscillator continues running when the
microcontroller powers down. Setting the LXTEN bit high will enable the LXT to keep running
after a HALT instruction is executed and enable the LXT oscillator to remain as a possible clock
source for the Watchdog Timer, the Time-Base and the Timer/Event Counter 0/1.
The LXT oscillator is implemented using a 32768Hz crystal connected to pins XT1/XT2. However,
for some crystals and to ensure oscillation and accurate frequency generation, it is normally
necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2
should be selected in consultation with the crystal or resonator manufacturer specification. The
external parallel feedback resistor, Rp, may also be required.
Rev. 1.30
34
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure
that the crystal and any associated resistors and capacitors along with inter connecting lines are all
located as close to the MCU as possible.
   ­
   External LXT Oscillator - HXT
LXT Oscillator C1 and C2 Values
Crystal Frequency
C1
32768Hz
8pF
Note: 1. C1 and C2 values are for guidance only.
2. RP=5M~10MΩ is recommended.
C2
10pF
32768Hz Crystal Recommended Capacitor Values
LXT Oscillator Low Power Function
The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power
Mode. The mode selection is executed using the LXTLP bit in the CTRL0 register.
LXTLP Bit
0
1
LXT Mode
Quick Start
Low-power
After power on the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator
is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up
and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed
into the Low-power mode by setting the LXTLP bit high. The oscillator will continue to run but
with reduced current consumption, as the higher current consumption is only required during the
LXT oscillator start-up. In power sensitive applications, such as battery applications, where power
consumption must be kept to a minimum, it is therefore recommended that the application program
sets the LXTLP bit high about 2 seconds after power-on.
It should be noted that, no matter what condition the LXTLP bit is set to, the LXT oscillator will
always function normally, the only difference is that it will take more time to start up if in the Lowpower mode.
Internal Low Speed Oscillator – LIRC
The LIRC is a fully self-contained free running on-chip RC oscillator with a typical frequency
of 13kHz at 5V requiring no external components. When the device enters the Idle/Sleep Mode,
the system clock will stop running but the WDT oscillator continues to free-run and to keep the
watchdog active. However, to preserve power in certain applications the LIRC can be disabled via a
configuration option.
Rev. 1.30
35
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Operating Modes
By using the LXT low frequency oscillator in combination with a high frequency oscillator, the
system can be selected to operate in a number of different modes. These Modes are Normal, Slow,
Idle and Sleep.
Mode Types and Selection
The higher frequency oscillators provide higher performance but carry with it the disadvantage of
higher power requirements, while the opposite is of course true for the lower frequency oscillators.
With the capability of dynamically switching between fast and slow oscillators, the device has the
flexibility to optimise the performance/power ratio, a feature especially important in power sensitive
portable applications.
For these devices the LXT oscillator can run together with any of the high speed oscillators, namely
the HXT, ERC or the HIRC. The CLKMOD bit in the CTRL0 register can be used to switch the
system clock from the selected high speed oscillator to the low speed LXT oscillator. When the
HALT instruction is executed the LXT oscillator can be chosen to run or not using the LXTEN bit in
the CTRL2 register.
       
 ­  €  € ‚ ƒ
  

System Clock Configurations
For all devices, when the system enters the Sleep or Idle Mode, the high frequency system clock will
always stop running. The accompanying tables shows the relationship between the CLKMOD bit,
the HALT instruction and the high/low frequency oscillators. The CLMOD bit can change normal or
Slow Mode.
Operating Mode Control
HALT
CLKMOD
Instruction
bit
0
Not
executed
1
x
Executed
x
Rev. 1.30
LXTEN
bit
x
x
1
0
High Speed System Clock
Low Speed
XTAL/IRC/ERC
System Clock LXT
Run
On
Stop
On
Stop
On
Stop
Off
36
Operating
Mode
Normal
Slow
Idle
Sleep
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Mode Switching
The devices are switched between one mode and another using a combination of the CLKMOD bit
in the CTRL0 register and the HALT instruction. The CLKMOD bit chooses whether the system
runs in either the Normal or Slow Mode by selecting the system clock to be sourced from either
a high or low frequency oscillator. The HALT instruction forces the system into either the Idle or
Sleep Mode, depending upon whether the LXT oscillator is running or not. The HALT instruction
operates independently of the CLKMOD bit condition.
When a HALT instruction is executed and the LXT oscillator is not running, the system enters the
Sleep mode the following conditions exist:
• The system oscillator will stop running and the application program will stop at the "HALT"
instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT clock source is selected to come from
the LIRC oscillator. The WDT will stop if its clock source originates from the system clock.
• The I/O ports will maintain their present condition.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Standby Current Considerations
As the main reason for entering the Idle/Sleep Mode is to keep the current consumption of the
MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are
other considerations which must also be taken into account by the circuit designer if the power
consumption is to be minimised.
Special attention must be made to the I/O pins on the device. All high-impedance input pins must
be connected to either a fixed high or low level as any floating input pins could create internal
oscillations and result in increased current consumption. Care must also be taken with the loads,
which are connected to I/O pins, which are setup as outputs. These should be placed in a condition
in which minimum current is drawn or connected only to external circuits that do not draw current,
such as other CMOS inputs.
If the configuration options have enabled the Watchdog Timer internal oscillator LIRC then this
will continue to run when in the Idle/Sleep Mode and will thus consume some power. For power
sensitive applications it may be therefore preferable to use the system clock source for the Watchdog
Timer. The LXT, if configured for use, will also consume a limited amount of power, as it continues
to run when the device enters the Idle Mode. To keep the LXT power consumption to a minimum
level the LXTLP bit in the CTRL0 register, which controls the low power function, should be set
high.
Rev. 1.30
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February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Wake-up
After the system enters the Idle/Sleep Mode, it can be woken up from one of various sources listed
as follows:
• An external reset
• An external falling edge on PA0 to PA7
• A system interrupt
• A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset,
however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated.
Although both of these wake-up methods will initiate a reset operation, the actual source of the
wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog Timer instructions and is set when executing the
"HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and Stack Pointer, the other flags remain in their original status.
Pins PA0 to PA7 can be setup via the PAWUK register to permit a negative transition on the pin to
wake-up the system. When a PA0 to PA7 pin wake-up occurs, the program will resume execution at the
instruction following the "HALT" instruction.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where
the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the
program will resume execution at the instruction following the "HALT" instruction. In this situation,
the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced
later when the related interrupt is finally enabled or when a stack level becomes free. The other
situation is where the related interrupt is enabled and the stack is not full, in which case the regular
interrupt response takes place. If an interrupt request flag is set to "1" before entering the Idle/Sleep
Mode, then any future interrupt requests will not generate a wake-up function of the related interrupt
will be ignored.
No matter what the source of the wake-up event is, once a wake-up event occurs, there will be a
time delay before normal program execution resumes. Consult the table for the related time.
Oscillator Type
Wake-up
Source
ERC, IRC
Crystal
External RES
tRSDT + tSST1
tRSDT + tSST2
tSST1
tSST2
PA Port
Interrupt
WDT Overflow
Note: 1. tRSTD (reset delay time), tSYS (system clock)
2. tRSTD is power-on delay, typical time=100ms
3. tSST1= 2 or 1024 tSYS
4. tSST2= 1024 tSYS
Wake-up Delay Time
Rev. 1.30
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February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Watchdog Timer
The Watchdog Timer, also known as the WDT, is provided to inhibit program malfunctions caused
by the program jumping to unknown locations due to certain uncontrollable external events such as
electrical noise.
Watchdog Timer Operation
It operates by providing a device reset when the Watchdog Timer counter overflows. Note that if the
Watchdog Timer function is not enabled, then any instructions related to the Watchdog Timer will
result in no operation.
Setting up the various Watchdog Timer options are controlled via the configuration options and two
internal registers WDTS and CTRL1. Enabling the Watchdog Timer can be controlled by both a
configuration option and the WDTEN bits in the CTRL1 internal register in the Data Memory.
Configuration Option
Disable
Disable
Enable
CTRL1 Register
Disable
Enable
x
WDT Function
OFF
ON
ON
Watchdog Timer On/Off Control
The Watchdog Timer will be disabled if bits WDTEN3~WDTEN0 in the CTRL1 register are written
with the binary value 1010B and WDT configuration option is disable. This will be the condition
when the device is powered up. Although any other data written to WDTEN3~WDTEN0 will ensure
that the Watchdog Timer is enabled, for maximum protection it is recommended that the value
0101B is written to these bits.
The Watchdog Timer clock can emanate from three different sources, selected by configuration
option. These are LXT, fSYS/4, or LIRC. It is important to note that when the system enters the Idle/
Sleep Mode the instruction clock is stopped, therefore if the configuration options have selected
fSYS/4 as the Watchdog Timer clock source, the Watchdog Timer will cease to function. For systems
that operate in noisy environments, using the LIRC or the LXT as the clock source is therefore
the recommended choice. The division ratio of the prescaler is determined by bits 0, 1 and 2 of
the WDTS register, known as WS0, WS1 and WS2. If the Watchdog Timer internal clock source
is selected and with the WS0, WS1 and WS2 bits of the WDTS register all set high, the prescaler
division ratio will be 1:128, which will give a maximum time-out period.
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the Idle/Sleep Mode, when a Watchdog Timer timeout occurs, the device will be woken up, the TO bit in the status register will be set and only the
Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents
of the Watchdog Timer. The first is an external hardware reset, which means a low level on the
external reset pin, the second is using the Clear Watchdog Timer software instructions and the third
is when a HALT instruction is executed. There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen by configuration option. The first option
is to use the single "CLR WDT" instruction while the second is to use the two commands "CLR
WDT1" and "CLR WDT2". For the first option, a simple execution of "CLR WDT" will clear the
Watchdog Timer while for the second option, both "CLR WDT1" and "CLR WDT2" must both
be executed to successfully clear the Watchdog Timer. Note that for this second option, if "CLR
WDT1" is used to clear the Watchdog Timer, successive executions of this instruction will have no
effect, only the execution of a "CLR WDT2" instruction will clear the Watchdog Timer. Similarly
after the "CLR WDT2" instruction has been executed, only a successive "CLR WDT1" instruction
can clear the Watchdog Timer.
Rev. 1.30
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February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
         ­      €
Watchdog Timer
WDTS Register
Bit
Name
R/W
POR
7
—
—
—
6
—
—
—
5
—
—
—
4
—
—
—
3
—
—
—
Bit 7~3 unimplemented, read as "0"
Bit 2~0
WS2, WS1, WS0: WDT time-out period selection
000: 28 tWDTCK
001: 29 tWDTCK
010: 210 tWDTCK
011: 211 tWDTCK
100: 212 tWDTCK
101: 213 tWDTCK
110: 214 tWDTCK
111: 215 tWDTCK
2
WS2
R/W
1
1
WS1
R/W
1
0
WS0
R/W
1
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from the
lowest Program Memory address.
In addition to the power-on reset, situations may arise where it is necessary to forcefully apply
a reset condition when the microcontroller is running. One example of this is where after power
has been applied and the microcontroller is already running, the RES line is forcefully pulled low.
In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with normal operation after the reset line is
allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the
microcontroller. All types of reset operations result in different register conditions being setup.
Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES
reset is implemented in situations where the power supply voltage falls below a certain threshold.
Rev. 1.30
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February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Reset Functions
There are five ways in which a microcontroller reset can occur, through events occurring both
internally and externally:
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring that
all pins will be first set to inputs.
Although the microcontroller has an internal RC reset function, if the VDD power supply rise time
is not fast enough or does not stabilise quickly at power-on, the internal reset function may be
incapable of providing proper reset operation. For this reason it is recommended that an external
RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin
remains low for an extended period to allow the power supply to stabilise. During this time delay,
normal operation of the microcontroller will be inhibited. After the RES line reaches a certain
voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the
microcontroller will begin normal operation. The abbreviation SST in the figures stands for System
Start-up Timer.
Power-On Reset Timing Chart
Note: tRSTD is power-on delay, typical time=100ms
For most applications a resistor connected between VDD and the RES pin and a capacitor connected
between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the
RES pin should be kept as short as possible to minimise any stray noise interference.
For applications that operate within an environment where more noise is present the Enhanced Reset
Circuit shown is recommended.
External RES Circuit
Note: "*" It is recommended that this component is added ESD protection.
"**" It is recommended that this component is added in environments where power line noise
is significant.
More information regarding external reset circuits is located in Application Note HA0075E on the
Holtek website.
Rev. 1.30
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February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
RES Pin Reset
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully
pulled low by external hardware such as an external switch. In this case as in the case of other reset,
the Program Counter will reset to zero and program execution initiated from this point.
RES Reset Timing Chart
Note: tRSTD is power-on delay, typical time=100ms
Low Voltage Reset — LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the
device. The LVR function is selected via a configuration option. If the supply voltage of the device
drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will
automatically reset the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage
in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C.
characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the
low supply voltage and will not perform a reset function. The actual VLVR value can be selected via
configuration options.
Low Voltage Reset Timing Chart
Note: tRSTD is power-on delay, typical time=100ms
Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset
except that the Watchdog time-out flag TO will be set to "1".
WDT Reset during Normal Operation Timing Chart
Note: tRSTD is power-on delay, typical time=100ms
Watchdog Time-out Reset during Idle/Sleep mode
The Watchdog time-out Reset during Idle/Sleep mode is a little different from other kinds of reset. Most
of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be
cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for tSST details.
WDT Time-out Reset during Idle/Sleep Timing Chart
Note: The tSST can be chosen to be either 1024 or 2 clock cycles via configuration option if the
system clock source is provided by ERC or HIRC. The SST is 1024 for HXT or LXT.
Rev. 1.30
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February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the Idle/Sleep function or Watchdog Timer. The reset flags are shown in the
table:
TO
0
u
1
1
PDF
0
u
u
1
RESET Conditions
Power-on reset
RES or LVR reset during Normal or Slow Mode operation
WDT time-out reset during Normal or Slow Mode operation
WDT time-out reset during Idle or Sleep Mode operation
Note: "u" stands for unchanged
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Program Counter
Interrupts
WDT
Timer/Event Counter
Prescaler
Input/Output Ports
Stack Pointer
Condition After RESET
Reset to zero
All interrupts will be disabled
Clear after reset, WDT begins counting
Timer Counter will be turned off
The Timer Counter Prescaler will be cleared
I/O ports will be setup as inputs
Stack Pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects each of the microcontroller internal registers.
HT48R068B
HT48R069B
Power-on
Reset
PCL
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
MP0
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
u u u u u u u u
MP1
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
u u u u u u u u
BP
●
– – 0 – – – 0 0
– – 0 – – – 0 0
– – 0 – – – 0 0
– – 0 – – – 0 0
– – u – – – u u
●
– 0 0 – – 0 0 0
– 0 0 – – 0 0 0
– 0 0 – – 0 0 0
– 0 0 – – 0 0 0
– u u – – u u u
Register
BP
RES or LVR
Reset
(Idle/Sleep)
WDT Time-out
WDT Time-out
(Normal
(Idle/Sleep)
Operation)
ACC
●
●
x x x x x x x x
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
TBLP
●
●
x x x x x x x x
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
TBLH
●
●
x x x x x x x x
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
WDTS
●
●
– – – – – 1 1 1
– – – – – 1 1 1
– – – – – 1 1 1
– – – – – 1 1 1
– – – – – u u u
STATUS
●
●
– – 0 0 x x x x
– – u u u u u u
– – 0 1 u u u u
– – 1 u u u u u
– – 1 1 u u u u
INTC0
●
●
– 0 0 0 0 0 0 0
– 0 0 0 0 0 0 0
– 0 0 0 0 0 0 0
– 0 0 0 0 0 0 0
– u u u u u u u
– 0 – 0 – 0 – 0
– 0 – 0 – 0 – 0
– 0 – 0 – 0 – 0
– 0 – 0 – 0 – 0
– u – u – u – u
INTC1
Rev. 1.30
RES or LVR
Reset
(Normal
Operation)
●
●
– 0 0 0 – 0 0 0
– 0 0 0 – 0 0 0
– 0 0 0 – 0 0 0
– 0 0 0 – 0 0 0
– u u u – u u u
MFIC
●
●
– 0 0 0 – 0 0 0
– 0 0 0 – 0 0 0
– 0 0 0 – 0 0 0
– 0 0 0 – 0 0 0
– u u u – u u u
TMR0
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
u u u u u u u u
TMR0C
●
●
0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0
u u u u u u u u
TMR1
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
u u u u u u u u
TMR1C
●
●
0 0 0 0 1 – – –
0 0 0 0 1 – – –
0 0 0 0 1 – – –
0 0 0 0 1 – – –
u u u u u – – –
TMR2L
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
u u u u u u u u
43
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
HT48R068B
HT48R069B
Rev. 1.30
Power-on
Reset
RES or LVR
Reset
(Normal
Operation)
RES or LVR
Reset
(Idle/Sleep)
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
u u u u u u u u
●
●
0 0 0 0 1 – – –
0 0 0 0 1 – – –
0 0 0 0 1 – – –
0 0 0 0 1 – – –
u u u u u – – –
●
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PAC
●
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PAWK
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
PAPU
●
●
– 0 0 0 0 0 0 0
– 0 0 0 0 0 0 0
– 0 0 0 0 0 0 0
– 0 0 0 0 0 0 0
– u u u u u u u
PB
●
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PBC
●
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PBPU
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
Register
TMR2H
TMR2C
PA
WDT Time-out
WDT Time-out
(Normal
(Idle/Sleep)
Operation)
PC
●
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PCC
●
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PCPU
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
PD
●
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PDC
●
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PDPU
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
PE
●
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PEC
●
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PEPU
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
PF
●
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PFC
●
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PFPU
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
PG
●
– – – – – – 1 1
– – – – – – 1 1
– – – – – – 1 1
– – – – – – 1 1
– – – – – – u u
PGC
●
– – – – – – 1 1
– – – – – – 1 1
– – – – – – 1 1
– – – – – – 1 1
– – – – – – u u
PGPU
●
– – – – – – 0 0
– – – – – – 0 0
– – – – – – 0 0
– – – – – – 0 0
– – – – – – u u
PG


●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PGC
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PGPU
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
PH
●
– – 1 1 1 1 1 1
– – 1 1 1 1 1 1
– – 1 1 1 1 1 1
– – 1 1 1 1 1 1
– – u u u u u u
PHC
●
– – 1 1 1 1 1 1
– – 1 1 1 1 1 1
– – 1 1 1 1 1 1
– – 1 1 1 1 1 1
– – u u u u u u
PHPU
●
– – 0 0 0 0 0 0
– – 0 0 0 0 0 0
– – 0 0 0 0 0 0
– – 0 0 0 0 0 0
– – u u u u u u
CTRL0
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
CTRL1
●
●
1 0 0 0 1 0 1 0
1 0 0 0 1 0 1 0
1 0 0 0 1 0 1 0
1 0 0 0 1 0 1 0
u u u u u u u u
CTRL2
●
●
0 – 0 0 – – – 1
0 – 0 0 – – – 1
0 – 0 0 – – – 1
0 – 0 0 – – – 1
u – u u – – – u
SCOMC
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
PWM0
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
u u u u u u u u
PWM1
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
u u u u u u u u
PWM2
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
u u u u u u u u
PWM3
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
u u u u u u u u
SIMC0
●
●
1 1 1 0 0 0 0 –
1 1 1 0 0 0 0 –
1 1 1 0 0 0 0 –
1 1 1 0 0 0 0 –
u u u u u u u –
SIMC1
●
●
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1
u u u u u u u u
SIMD
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
u u u u u u u u
SIMA/
SIMC2
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
SBCR
●
●
0 1 1 0 0 0 0 0
0 1 1 0 0 0 0 0
0 1 1 0 0 0 0 0
0 1 1 0 0 0 0 0
u u u u u u u u
SBDR
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
u u u u u u u u
44
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
HT48R069B
DAL
HT48R068B
Register
Power-on
Reset
RES or LVR
Reset
(Normal
Operation)
RES or LVR
Reset
(Idle/Sleep)
●
●
0 0 0 0 – – – –
0 0 0 0 – – – –
0 0 0 0 – – – –
0 0 0 0 – – – –
u u u u – – – –
WDT Time-out
WDT Time-out
(Normal
(Idle/Sleep)
Operation)
DAH
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
VOL
●
●
0 0 0 0 – – – –
0 0 0 0 – – – –
0 0 0 0 – – – –
0 0 0 0 – – – –
u u u u – – – –
LVDC
●
●
– – 0 0 – – – –
– – 0 0 – – – –
– – 0 0 – – – –
– – 0 0 – – – –
– – u u – – – –
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. Most pins can have either an
input or output designation under user program control. Additionally, as there are pull-high resistors
and wake-up software configurations, the user is provided with an I/O structure to meet the needs of
a wide range of application possibilities.
For input operation, these ports are non-latching, which means the inputs must be ready at the T2
rising edge of instruction "MOV A,[m]", where m denotes the port address. For output operation, all
the data is latched and remains unchanged until the output latch is rewritten.
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the use
of an external resistor. To eliminate the need for these external resistors, when configured as an input
have the capability of being connected to an internal pull-high resistor. These pull-high resistors are
selectable via a register known as PAPU~PHPU located in the Data Memory. The pull-high resistors
are implemented using weak PMOS transistors. Note that pin PA7 does not have a pull-high resistor
selection.
Port A Wake-up
If the HALT instruction is executed, the device will enter the Idle/Sleep Mode, where the system
clock will stop resulting in power being conserved, a feature that is important for battery and other
low-power applications.
Various methods exist to wake-up the microcontroller, one of which is to change the logic condition
on one of the PA0~PA7 pins from high to low. After a HALT instruction forces the microcontroller
into entering the Idle/Sleep Mode, the processor will remain idle or in a low-power state until the
logic condition of the selected wake-up pin on Port A changes from high to low. This function is
especially suitable for applications that can be woken up via external switches. Note that pins PA0
to PA7 can be selected individually to have this wake-up feature using an internal register known as
PAWK, located in the Data Memory.
Rev. 1.30
45
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
PAWK, PAC~PHC, PAPU~PHPU Register
• HT48R068B
Bit
Register
Name
POR
7
6
5
4
3
2
1
0
PAWK
00H
PAWK7
PAWK6
PAWK5
PAWK4
PAWK3
PAWK2
PAWK1
PAWK0
PAC
FFH
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
00H
—
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PBC
FFH
PBC7
PBC6
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
PBPU
00H
PBPU7
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0
PCC
FFH
PCC7
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PCPU
00H
PCPU7
PCPU6
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
PDC
FFH
PDC7
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDPU
00H
PDPU7
PDPU6
PDPU5
PDPU4
PDPU3
PDPU2
PDPU1
PDPU0
PEC
FFH
PEC7
PEC6
PEC5
PEC4
PEC3
PEC2
PEC1
PEC0
PEPU
00H
PEPU7
PEPU6
PEPU5
PEPU4
PEPU3
PEPU2
PEPU1
PEPU0
PFC
03H
—
—
—
—
—
—
PFC1
PFC0
PFPU
00H
—
—
—
—
—
—
PFPU1
PFPU0
"—" Unimplemented, read as "0"
PAWKn: PA wake-up function enable
0: disable
1: enable
PACn/PBCn/PCCn/PDCn/PECn/PFCn: I/O type selection
0: output
1: input
PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn: Pull-high function enable
0: disable
1: enable
Rev. 1.30
46
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
• HT48R069B
Register
Name
POR
PAWK
Bit
7
6
5
4
3
2
1
0
00H
PAWK7
PAWK6
PAWK5
PAWK4
PAWK3
PAWK2
PAWK1
PAWK0
PAC
FFH
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
00H
—
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PBC
FFH
PBC7
PBC6
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
PBPU
00H
PBPU7
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0
PCC
FFH
PCC7
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PCPU
00H
PCPU7
PCPU6
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
PDC
FFH
PDC7
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDPU
00H
PDPU7
PDPU6
PDPU5
PDPU4
PDPU3
PDPU2
PDPU1
PDPU0
PEC
FFH
PEC7
PEC6
PEC5
PEC4
PEC3
PEC2
PEC1
PEC0
PEPU
00H
PEPU7
PEPU6
PEPU5
PEPU4
PEPU3
PEPU2
PEPU1
PEPU0
PFC
FFH
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
PFPU
00H
PFPU7
PFPU6
PFPU5
PFPU4
PFPU3
PFPU2
PFPU1
PFPU0
PGC
FFH
PGC7
PGC6
PGC5
PGC4
PGC3
PGC2
PGC1
PGC0
PGPU
00H
PGPU7
PGPU6
PGPU5
PGPU4
PGPU3
PGPU2
PGPU1
PGPU0
PHC
3FH
—
—
PHC5
PHC4
PHC3
PHC2
PHC1
PHC0
PHPU
00H
—
—
PHPU5
PHPU4
PHPU3
PHPU2
PHPU1
PHPU0
"—" Unimplemented, read as "0"
PAWKn: PA wake-up function enable
0: disable
1: enable
PACn/PBCn/PCCn/PDCn/PECn/PFCn/PGCn/PHCn: I/O type selection
0: output
1: input
PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn/PGPUn/PHPUn: Pull-high function enable
0: disable
1: enable
I/O Port Control Registers
Each Port has its own control register, known as PAC, PBC, PCC, PDC, PEC, PFC, PGC, PHC
which controls the input/output configuration. With this control register, each I/O pin with or without
pull-high resistors can be reconfigured dynamically under software control. For the I/O pin to
function as an input, the corresponding bit of the control register must be written as a "1". This will
then allow the logic state of the input pin to be directly read by instructions. When the corresponding
bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin
is currently setup as an output, instructions can still be used to read the output register. However, it
should be noted that the program will in fact only read the status of the output data latch and not the
actual logic status of the output pin.
Rev. 1.30
47
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more
than one function. Limited numbers of pins can force serious design constraints on designers but by
supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the
chosen function of the multi-function I/O pins is set by configuration options while for others the
function is set by application program control.
External Interrupt Input
The external interrupt pin, INT, is pin-shared with an I/O pin. To use the pin as an external interrupt
input the correct bits in the INTC0 register must be programmed. The pin must also be setup as an
input by setting the PAC3 bit in the Port Control Register. A pull-high resistor can also be selected
via the appropriate port pull-high resistor register. Note that even if the pin is setup as an external
interrupt input the I/O function still remains.
External Timer/Event Counter Input
The Timer/Event Counter pins, TC0, TC1 and TC2 are pin-shared with I/O pins. For these shared
pins to be used as Timer/Event Counter inputs, the Timer/Event Counter must be configured to be
in the Event Counter or Pulse Width Capture Mode. This is achieved by setting the appropriate bits
in the Timer/Event Counter Control Register. The pins must also be setup as inputs by setting the
appropriate bit in the Port Control Register. Pull-high resistor options can also be selected using the
port pull-high resistor registers. Note that even if the pin is setup as an external timer input the I/O
function still remains.
PFD Output
The PFD function output is pin-shared with an I/O pin. The output function of this pin is chosen
using the CTRL0 register. Note that the corresponding bit of the port control register, must
setup the pin as an output to enable the PFD output. If the port control register has setup the pin as
an input, then the pin will function as a normal logic input with the usual pull-high selection, even if
the PFD function has been selected.
PWM Outputs
The PWM function whose outputs are pin-shared with I/O pins. The PWM output functions are
chosen using the CTRL0 and CTRL2 registers. Note that the corresponding bit of the port control
registers, for the output pin, must setup the pin as an output to enable the PWM output. If the
pins are setup as inputs, then the pin will function as a normal logic input with the usual pull-high
selections, even if the PWM registers have enabled the PWM function.
SCOM Driver Pins
Pins PB0~PB3 on Port B can be used as LCD COM driver pins. This function is controlled using
the SCOMC register which will generate the necessary 1/2 bias signals on these four pins.
Rev. 1.30
48
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Pin Remapping Configuration
The pin remapping function enables the function pins PWM0/TC1, INT and PFD to be located on
different port pins. It is important not to confuse the Pin Remapping function with the Pin-shared
function, these two functions have no interdependence.
The PCFG bit in the CTRL0 register allows the three function pins PWM0/TC1, INT and PFD to
be remapped to different port pins. After power up, this bit will be reset to zero, which will define
the default port pins to which these three functions will be mapped. Changing this bit will move the
functions to other port pins.
Examination of the pin names on the package diagrams will reveal that some pin function names
are repeated, this indicates a function pin that can be remapped to other port pins. If the pin name is
bracketed then this indicates its alternative location. Pin names without brackets indicates its default
location which is the condition after Power-on.
PCFG Bit Status
PCFG Bit
0
(PWM0/TC1)/PA4
INT/PA3
PFD/PA1
Pin Mapping
1
[(PWM0/TC1)]/PB5
[INT]/PB4
[PFD]/PB3
Pin Remapping
I/O Pin Structures
The diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O
pin may differ from these drawings, they are supplied as a guide only to assist with the functional
understanding of the I/O pins.
   
   Generic Input/Output Ports
Rev. 1.30
49
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
     

PA7 NMOS Input/Output Port
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PB Input/Output Port
Rev. 1.30
50
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, the I/
O data register and I/O port control register will be set high. This means that all I/O pins will default
to an input state, the level of which depends on the other connected circuitry and whether pull-high
options have been selected. If the port control registers, are then programmed to setup some pins
as outputs, these output pins will have an initial high output value unless the associated port data
register is first programmed. Selecting which pins are inputs and which are outputs can be achieved
byte-wide by loading the correct value into the port control register or by programming individual
bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when
using these bit control instructions, a read-modify-write operation takes place. The microcontroller
must first read in the data on the entire port, modify it to the required new bit values and then rewrite
this data back to the output ports.
Read Modify Write Timing
Pins PA0 to PA7 each have a wake-up functions, selected via the PAWK register. When the device is
in the Idle/Sleep Mode, various methods are available to wake the device up. One of these is a high
to low transition of any of the these pins. Single or multiple pins on Port A can be setup to have this
function.
Timer/Event Counters
The provision of timers form an important part of any microcontroller, giving the designer a means
of carrying out time related functions. The devices contain two 8-bit and one 16-bit timer. As the
timers have three different operating modes, they can be configured to operate as a general timer, an
external event counter or as a pulse width capture device. The provision of an internal prescaler to
the clock circuitry on gives added range to the timers.
There are two types of registers related to the Timer/Event Counters. The first is the register that
contains the actual value of the timer and into which an initial value can be preloaded. Reading from
this register retrieves the contents of the Timer/Event Counter. The second type of associated register
is the Timer Control Register which defines the timer options and determines how the timer is to
be used. The device can have the timer clock configured to come from the internal clock source. In
addition, the timer clock source can also be configured to come from an external timer pin.
Configuring the Timer/Event Counter Input Clock Source
The Timer/Event Counter clock source can originate from various sources, an internal clock or an
external pin. The internal clock source is used when the timer is in the timer mode or in the pulse
width capture mode. For some Timer/Event Counters, this internal clock source is first divided by a
prescaler, the division ratio of which is conditioned by the Timer Control Register bits. An external
clock source is used when the timer is in the event counting mode, the clock source being provided
on an external timer pin TCn. Depending upon the condition of the TnEG bit, each high to low, or
low to high transition on the external timer pin will increment the counter by one.
Rev. 1.30
51
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Timer Registers – TMR0, TMR1, TMR2L, TMR2H
The timer registers are special function registers located in the Special Purpose Data Memory and
is the place where the actual timer value is stored. These registers are known as TMR0, TMR1,
TMR2L and TMR2H. The value in the timer registers increases by one each time an internal clock
pulse is received or an external transition occurs on the external timer pin. The timer will count from
the initial value loaded by the preload register to the full count of FFH for the 8-bit Timer/Event
Counter or FFFFH for the 16-bit Timer/Event Counters, at which point the timer overflows and
an internal interrupt signal is generated. The timer value will then be reset with the initial preload
register value and continue counting. Note that to achieve a maximum full range count of FFH or
FFFFH, the preload register must first be cleared to all zeros. It should be noted that after power-on,
the preload registers will be in an unknown condition. Note that if the Timer/Event Counter is in an
OFF condition and data is written to its preload register, this data will be immediately written into
the actual counter. However, if the counter is enabled and counting, any new data written into the
preload data register during this period will remain in the preload register and will only be written
into the actual counter the next time an overflow occurs.
Timer Control Registers – TMR0C, TMR1C, TMR2C
The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in
three different modes, the options of which are determined by the contents of their respective control
register.
The Timer Control Register is known as TMRnC. It is the Timer Control Register together with
its corresponding timer register that control the full operation of the Timer/Event Counter. Before
the timer can be used, it is essential that the Timer Control Register is fully programmed with the
right data to ensure its correct operation, a process that is normally carried out during program
initialisation.
To choose which of the three modes the timer is to operate in, either in the timer mode, the event
counting mode or the pulse width capture mode, bits 7 and 6 of the Timer Control Register, which
are known as the bit pair TnM1/TnM0, must be set to the required logic levels.
The timer-on bit, which is bit 4 of the Timer Control Register and known as TnON, provides the
basic on/off control of the respective timer. Setting the bit high allows the counter to run, clearing
the bit stops the counter. Bits 0~2 of the Timer Control Register determine the division ratio of the
input clock prescaler. The prescaler bit settings have no effect if an external clock source is used. If
the timer is in the event count or pulse width capture mode, the active transition edge level type is
selected by the logic level of bit 3 of the Timer Control Register which is known as TnEG. The TnS
bit selects the internal clock source.
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Clock Structure for Timer/PWM/Time Base
Rev. 1.30
52
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
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16-bit Timer/Event Counter 2 Structure
PFDCS
PFD0
0
MUX
PFD1
PFD output
1
Note: If PWM0/PWM1/PWM2/PWM3 is enabled, then fTP
comes from fSYS (ignore T0S)
Rev. 1.30
53
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
TMR0C Register
Bit
Name
R/W
POR
Rev. 1.30
7
T0M1
R/W
0
6
T0M0
R/W
0
5
T0S
R/W
0
4
T0ON
R/W
0
3
T0EG
R/W
1
2
T0PSC2
R/W
0
1
T0PSC1
R/W
0
0
T0PSC0
R/W
0
Bit 7,6
T0M1, T0M0: Timer0 operation mode selection
00: no mode available
01: event counter mode
10: timer mode
11: pulse width capture mode
Bit 5
T0S: timer clock source
0: fSYS
1: LXT oscillator
T0S selects the clock source for fTP which is provided for Timer 0~2, the Time-Base
and the PWM. If the PWM is enabled, then fSYS will be selected, overriding the T0S
selection.
Bit 4
T0ON: Timer/event counter counting enable
0: disable
1: enable
Bit 3
T0EG:
Event counter active edge selection
0: count on raising edge
1: count on falling edge
Pulse Width Capture active edge selection
0: start counting on falling edge, stop on raising edge
1: start counting on raising edge, stop on falling edge
Bit 2~0
T0PSC2, T0PSC1, T0PSC0: Timer prescaler rate selection
Timer internal clock=
000: fTP
001: fTP/2
010:fTP/4
011:fTP/8
100:fTP/16
101:fTP/32
110:fTP/64
111:fTP/128
54
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
TMR1C Register
Bit
Name
R/W
POR
7
T1M1
R/W
0
6
T1M0
R/W
0
5
T1S
R/W
0
4
T1ON
R/W
0
3
T1EG
R/W
1
2
—
—
—
Bit 7,6
T1M1, T1M0: Timer 1 operation mode selection
00: no mode available
01: event counter mode
10: timer mode
11: pulse width capture mode
Bit 5
T1S: timer clock source
0: fSYS/4
1: LXT oscillator
Bit 4
T1ON: Timer/event counter counting enable
0: disable
1: enable
Bit 3
T1EG: Event counter active edge selection
0: count on raising edge
1: count on falling edge
Pulse Width Capture active edge selection
0: start counting on falling edge, stop on raising edge
1: start counting on raising edge, stop on falling edge
Bit 2~0
unimplemented, read as "0"
1
—
—
—
0
—
—
—
1
—
—
—
0
—
—
—
TMR2C Register
Bit
Name
R/W
POR
Rev. 1.30
7
T2M1
R/W
0
6
T2M0
R/W
0
5
T2S
R/W
0
4
T2ON
R/W
0
3
T2EG
R/W
1
Bit 7,6
T2M1, T2M0: Timer 2 operation mode selection
00: no mode available
01: event counter mode
10: timer mode
11: pulse width capture mode
Bit 5
T2S: timer clock source
0: fSYS/4
1: LXT oscillator
Bit 4
T2ON: Timer/event counter counting enable
0: disable
1: enable
Bit 3
T2EG: Event counter active edge selection
0: count on raising edge
1: count on falling edge
Pulse Width Capture active edge selection
0: start counting on falling edge, stop on raising edge
1: start counting on raising edge, stop on falling edge
Bit 2~0
unimplemented, read as "0"
55
2
—
—
—
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
To choose which of the three modes the timer is to operate in, either in the timer mode, the event
counting mode or the pulse width capture mode, bits 7 and 6 of the Timer Control Register, which
are known as the bit pair TnM1/TnM0, must be set to the required logic levels.
The timer-on bit, which is bit 4 of the Timer Control Register and known as TnON, provides the
basic on/off control of the respective timer. Setting the bit high allows the counter to run, clearing
the bit stops the counter. Bits 0~2 of the Timer Control Register determine the division ratio of the
input clock prescaler. The prescaler bit settings have no effect if an external clock source is used. If
the timer is in the event count or pulse width capture mode, the active transition edge level type is
selected by the logic level of bit 3 of the Timer Control Register which is known as TnEG. The TnS
bit selects the internal clock source if used.
Timer Mode
In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing
an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode,
the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the
correct value as shown.
Control Register Operating Mode
Select Bits for the Timer Mode
Bit7
1
Bit6
0
In this mode the internal clock is used as the timer clock. The timer input clock source is either fSYS
, fSYS/4 or the LXT oscillator. However, this timer clock source is further divided by a prescaler, the
value of which is determined by the bits TnPSC2~TnPSC0 in the Timer Control Register. The timeron bit, TnON must be set high to enable the timer to run. Each time an internal clock high to low
transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt
signal is generated and the timer will reload the value already loaded into the preload register and
continue counting. A timer overflow condition and corresponding internal interrupt is one of the
wake-up sources, however, the internal interrupts can be disabled by ensuring that the ETnI bits of
the INTCn register are reset to zero.
Event Counter Mode
In this mode, a number of externally changing logic events, occurring on the external timer TCn pin,
can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode Select bit
pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Event Counter Mode
Bit7
0
Bit6
1
In this mode, the external timer TCn pin, is used as the Timer/Event Counter clock source, however
it is not divided by the internal prescaler. After the other bits in the Timer Control Register have
been setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can be set high to
enable the Timer/Event Counter to run. If the Active Edge Select bit, TnEG, which is bit 3 of the
Timer Control Register, is low, the Timer/Event Counter will increment each time the external timer
pin receives a low to high transition. If the TnEG is high, the counter will increment each time the
external timer pin receives a high to low transition. When it is full and overflows, an interrupt signal
is generated and the Timer/Event Counter will reload the value already loaded into the preload
register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event
Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as
an event counter input pin, two things have to happen. The first is to ensure that the Operating Mode
Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting
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Mode, the second is to ensure that the port control register configures the pin as an input. It should
be noted that in the event counting mode, even if the is in the Idle/Sleep Mode, the Timer/Event
Counter will continue to record externally changing logic events on the timer input TCn pin. As a
result when the timer overflows it will generate a timer interrupt and corresponding wake-up source.
Timer Mode Timing Chart
Event Counter Mode Timing Chart (TnEG=1)
Pulse Width Capture Mode
In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses
applied to the external timer pin. To operate in this mode, the Operating Mode Select bit pair, TnM1/
TnM0, in the Timer Control Register must be set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Pulse Width Capture Mode
Bit7
1
Bit6
1
In this mode the internal clock, fSYS , fSYS/4 or the LXT, is used as the internal clock for the 8-bit
Timer/Event Counter. However, the clock source, fSYS, for the 8-bit timer is further divided by a
prescaler, the value of which is determined by the Prescaler Rate Select bits TnPSC2~TnPSC0,
which are bits 2~0 in the Timer Control Register. After the other bits in the Timer Control Register
have been setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can be set high
to enable the Timer/Event Counter, however it will not actually start counting until an active edge is
received on the external timer pin.
If the Active Edge Select bit TnEG, which is bit 3 of the Timer Control Register, is low, once a high
to low transition has been received on the external timer pin, the Timer/Event Counter will start
counting until the external timer pin returns to its original high level. At this point the enable bit will
be automatically reset to zero and the Timer/Event Counter will stop counting. If the Active Edge
Select bit is high, the Timer/Event Counter will begin counting once a low to high transition has
been received on the external timer pin and stop counting when the external timer pin returns to its
original low level. As before, the enable bit will be automatically reset to zero and the Timer/Event
Counter will stop counting. It is important to note that in the pulse width capture Mode, the enable
bit is automatically reset to zero when the external control signal on the external timer pin returns
to its original level, whereas in the other two modes the enable bit can only be reset to zero under
program control.
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The residual value in the Timer/Event Counter, which can now be read by the program, therefore
represents the length of the pulse received on the TCn pin. As the enable bit has now been reset, any
further transitions on the external timer pin will be ignored. The timer cannot begin further pulse
width capture until the enable bit is set high again by the program. In this way, single shot pulse
measurements can be easily made.
It should be noted that in this mode the Timer/Event Counter is controlled by logical transitions on the
external timer pin and not by the logic level. When the Timer/Event Counter is full and overflows, an
interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the
preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event
Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero.
As the TCn pin is shared with an I/O pin, to ensure that the pin is configured to operate as a pulse
width capture pin, two things have to happen. The first is to ensure that the Operating Mode Select
bits in the Timer Control Register place the Timer/Event Counter in the pulse width capture Mode,
the second is to ensure that the port control register configures the pin as an input.
Prescaler
Bits T0PSC0~T0PSC2 of the TMR0C register can be used to define a division ratio for the internal
clock source of the Timer/Event Counter enabling longer time out periods to be setup.
PFD Function
The Programmable Frequency Divider provides a means of producing a variable frequency output
suitable for applications, such as piezo-buzzer driving or other interfaces requiring a precise
frequency generator.
The Timer/Event Counter overflow signal is the clock source for the PFD function, which is controlled
by PFDCS bit in CTRL0. For applicable devices the clock source can come from either Timer/Event
Counter 0 or Timer/Event Counter 1. The output frequency is controlled by loading the required values
into the timer prescaler and timer registers to give the required division ratio. The counter will begin
to count-up from this preload register value until full, at which point an overflow signal is generated,
causing both the PFD outputs to change state. The counter will then be automatically reloaded with the
preload register value and continue counting-up.
If the CTRL0 register has selected the PFD function, then for PFD output to operate, it is essential
for the Port A control register PAC, to setup the PFD pins as outputs. PA1 must be set high to
activate the PFD. The output data bits can be used as the on/off control bit for the PFD outputs. Note
that the PFD outputs will all be low if the output data bit is cleared to zero.
Using this method of frequency generation, and if a crystal oscillator is used for the system clock,
very precise values of frequency can be generated.
           ­
Pulse Width Capture Mode Timing Chart (TnEG=0)
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PFD Function
I/O Interfacing
The Timer/Event Counter, when configured to run in the event counter or pulse width capture
mode, requires the use of an external timer pin for its operation. As this pin is a shared pin it must
be configured correctly to ensure that it is setup for use as a Timer/Event Counter input pin. This is
achieved by ensuring that the mode select bits in the Timer/Event Counter control register, select either
the event counter or pulse width capture mode. Additionally the corresponding Port Control Register
bit must be set high to ensure that the pin is setup as an input. Any pull-high resistor connected to this
pin will remain valid even if the pin is used as a Timer/Event Counter input.
Programming Considerations
When configured to run in the timer mode, the internal system clock is used as the timer clock
source and is therefore synchronised with the overall operation of the microcontroller. In this mode
when the appropriate timer register is full, the microcontroller will generate an internal interrupt
signal directing the program flow to the respective internal interrupt vector. For the pulse width
capture mode, the internal system clock is also used as the timer clock source but the timer will only
run when the correct logic condition appears on the external timer input pin. As this is an external
event and not synchronised with the internal timer clock, the microcontroller will only see this
external event when the next timer clock pulse arrives. As a result, there may be small differences
in measured values requiring programmers to take this into account during programming. The same
applies if the timer is configured to be in the event counting mode, which again is an external event
and not synchronised with the internal system or timer clock.
When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited
to avoid errors, however as this may result in a counting error, this should be taken into account by the
programmer. Care must be taken to ensure that the timers are properly initialised before using them
for the first time. The associated timer enable bits in the interrupt control register must be properly set
otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer
mode and clock source control bits in timer control register must also be correctly set to ensure the
timer is properly configured for the required application. It is also important to ensure that an initial
value is first loaded into the timer registers before the timer is switched on; this is because after poweron the initial values of the timer registers are unknown. After the timer has been initialised the timer can
be turned on and off by controlling the enable bit in the timer control register.
When the Timer/Event Counter overflows, its corresponding interrupt request flag in the interrupt
control register will be set. If the Timer/Event Counter interrupt is enabled this will in turn generate
an interrupt signal. However irrespective of whether the interrupts are enabled or not, a Timer/Event
Counter overflow will also generate a wake-up signal if the device is in a Power-down condition.
This situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the
external signal continues to change state. In such a case, the Timer/Event Counter will continue to
count these external events and if an overflow occurs the device will be woken up from its Powerdown condition. To prevent such a wake-up from occurring, the timer interrupt request flag should
first be set high before issuing the "HALT" instruction to enter the Idle/Sleep Mode.
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Timer Program Example
The program shows how the Timer/Event Counter registers are setup along with how the interrupts
are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the
Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the
same bit. This example program sets the Timer/Event Counters to be in the timer mode, which uses
the internal system clock as their clock source.
PFD Programming Example
org04h
; external interrupt vector
org08h
; Timer Counter 0 interrupt vector
jmp tmr0int ; jump here when Timer 0 overflows
::
org20h
; main program
::
;internal Timer 0 interrupt routine
tmr0int:
:
; Timer 0 main program placed here
:
:
begin:
;setup Timer 0 registers
mov a,09bh ; setup Timer 0 preload value
movtmr0,a
mov a,081h ; setup Timer 0 control register
mov tmr0c,a ; timer mode and prescaler set to /2
;setup interrupt register
mov a,00dh ; enable master interrupt and both timer interrupts
movintc0,a
::
set tmr0c.4 ; start Timer 0
::
Time Base
The device includes a Time Base function which is used to generate a regular time interval signal.
The Time Base time interval magnitude is determined using an internal 13 stage counter sets the
division ratio of the clock source. This division ratio is controlled by both the TBSEL0 and TBSEL1
bits in the CTRL1 register. The clock source is selected using the T0S bit in the TMR0C register.
When the Time Base time out, a Time Base interrupt signal will be generated. It should be noted that
as the Time Base clock source is the same as the Timer/Event Counter clock source, care should be
taken when programming.
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Pulse Width Modulator
Every device includes a multiple output 8-bit PWM function. Useful for such applications such as
motor speed control, the PWM function provides outputs with a fixed frequency but with a duty
cycle that can be varied by setting particular values into the corresponding PWM register.
 

 PWM Block Diagram
Device
HT48R068B
HT48R069B
Rev. 1.30
Channels
4
61
Mode
Pins
Registers
6+2
7+1
PA4
PC3
PC2
PD1
PWM0
PWM1
PWM2
PWM3
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PWM Operation
A single register, known as PWMn and located in the Data Memory is assigned to each Pulse Width
Modulator channel. It is here that the 8-bit value, which represents the overall duty cycle of one
modulation cycle of the output waveform, should be placed. To increase the PWM modulation
frequency, each modulation cycle is subdivided into two or four individual modulation subsections,
known as the 7+1 mode or 6+2 mode respectively. The required mode and the on/off control for each
PWM channel is selected using the CTRL0 and CTRL2 registers. Note that when using the PWM,
it is only necessary to write the required value into the PWMn register and select the required mode
setup and on/off control using the CTRL0 and CTRL2 registers, the subdivision of the waveform
into its sub-modulation cycles is implemented automatically within the microcontroller hardware.
The PWM clock source is the system clock fSYS. This method of dividing the original modulation
cycle into a further 2 or 4 sub-cycles enable the generation of higher PWM frequencies which allow
a wider range of applications to be served. The difference between what is known as the PWM
cycle frequency and the PWM modulation frequency should be understood. As the PWM clock
is the system clock, fSYS, and as the PWM value is 8-bits wide, the overall PWM cycle frequency
is fSYS/256. However, when in the 7+1 mode of operation the PWM modulation frequency will be
fSYS/128, while the PWM modulation frequency for the 6+2 mode of operation will be fSYS/64.
PWM Modulation
PWM Cycle Frequency
PWM Cycle Duty
fSYS/64 for (6+2) bits mode
fSYS/128 for (7+1) bits mode
fSYS/256
[PWM]/256
6+2 PWM Mode
Each full PWM cycle, as it is controlled by an 8-bit PWM register, has 256 clock periods. However,
in the 6+2 PWM mode, each PWM cycle is subdivided into four individual sub-cycles known as
modulation cycle 0 ~ modulation cycle 3, denoted as i in the table. Each one of these four sub-cycles
contains 64 clock cycles. In this mode, a modulation frequency increase of four is achieved. The 8-bit
PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into
two groups. The first group which consists of bit2~bit7 is denoted here as the DC value. The second
group which consists of bit0~bit1 is known as the AC value. In the 6+2 PWM mode, the duty cycle
value of each of the four modulation sub-cycles is shown in the following table.
Parameter
Modulation cycle i
(i=0~3)
AC (0~3)
DC
(Duty Cycle)
i < AC
DC+1
64
i≧AC
DC
64
6+2 Mode Modulation Cycle Values
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The following diagram illustrates the waveforms associated with the 6+2 mode of PWM operation.
It is important to note how the single PWM cycle is subdivided into 4 individual modulation cycles,
numbered from 0~3 and how the AC value is related to the PWM value.
  6+2 PWM Mode
PWM Register for 6+2 Mode
7+1 PWM Mode
Each full PWM cycle, as it is controlled by an 8-bit PWM register, has 256 clock periods. However,
in the 7+1 PWM mode, each PWM cycle is subdivided into two individual sub-cycles known as
modulation cycle 0 ~ modulation cycle 1, denoted as i in the table. Each one of these two sub-cycles
contains 128 clock cycles. In this mode, a modulation frequency increase of two is achieved. The 8-bit
PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into
two groups. The first group which consists of bit1~bit7 is denoted here as the DC value. The second
group which consists of bit0 is known as the AC value. In the 7+1 PWM mode, the duty cycle value
of each of the two modulation sub-cycles is shown in the following table.
Parameter
AC (0~1)
i < AC
Modulation cycle i
(i=0~1)
i≧AC
DC
(Duty Cycle)
DC+1
128
DC
128
7+1 Mode Modulation Cycle Values
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The following diagram illustrates the waveforms associated with the 7+1 mode PWM operation. It
is important to note how the single PWM cycle is subdivided into 2 individual modulation cycles,
numbered 0 and 1 and how the AC value is related to the PWM value.
     7+1 PWM Mode
PWM Register for 7+1 Mode
PWM Output Control
The PWM outputs are pin-shared with the I/O pins PA4/PB5,PC2,PC3 and PD1. To operate as a
PWM output and not as an I/O pin, the correct bits must be set in the CTRL0 and CTRL2 register.
A zero value must also be written to the corresponding bit in the I/O port control register PAC.4,
PCC.2 and PCC.3 to ensure that the corresponding PWM output pin is setup as an output. After
these two initial steps have been carried out, and of course after the required PWM value has been
written into the PWMn register, writing a high value to the corresponding bit in the output data
register PA.4, PC.2 and PC.3 will enable the PWM data to appear on the pin. Writing a zero value
will disable the PWM output function and force the output low. In this way, the Port data output
registers can be used as an on/off control for the PWM function. Note that if the CTRL0 and CTRL2
registers have selected the PWM function, but a high value has been written to its corresponding bit
in the PAC/PBC,PCC or PDC control register to configure the pin as an input, then the pin can still
function as a normal input line, with pull-high resistor options.
PWM Programming Example
The following sample program shows how the PWM0 output is setup and controlled.
mov a,64h
; setup PWM value of decimal 100
mov pwm0,a
set ctrl0.5 ; select the 7+1 PWM mode
set ctrl0.3 ; select pin PA4 to have a PWM function
clr pac.4 ; setup pin PA4 as an output
set pa.4
; enable the PWM output
::
clr pa.4 ; disable the PWM output_ pin
; PA4 forced low
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Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an
internal function such as a Timer/Event Counter or Time Base requires microcontroller attention,
their corresponding interrupt will enforce a temporary suspension of the main program allowing the
microcontroller to direct attention to their respective needs.
The device contains a single external interrupt and multiple internal interrupts. The external interrupt
is controlled by the action of the external interrupt pin, while the internal interrupts are generated by
the various functions such as Timer/Event Counters, and Time Base.
Interrupt Register
Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by
using two registers, INTC0, INTC1 and MFIC. By controlling the appropriate enable bits in this
registers each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the
corresponding request flag will be set by the microcontroller. The global enable flag if cleared to
zero will disable all interrupts.
INTC0 Register
Bit
Name
R/W
POR
Rev. 1.30
7
-
-
-
6
T1F
R/W
0
5
T0F
R/W
0
4
EIF
R/W
0
3
ET1I
R/W
0
Bit 7 unimplemented, read as “0”
Bit 6
T1F: Timer/Event Counter 1 interrupt request flag
0: inactive
1: active
Bit 5
T0F: Timer/Event Counter 0 interrupt request flag
0: inactive
1: active
Bit 4
EIF: External interrupt request flag
0: inactive
1: active
Bit 3
ET1I: Timer/Event Counter 1 interrupt enable
0: disable
1: enable
Bit 2
ET0I: Timer/Event Counter 0 interrupt enable
0: disable
1: enable
Bit 1
EEI: External interrupt enable
0: disable
1: enable
Bit 0
EMI: Master interrupt global enable
0: disable
1: enable
65
2
ET0I
R/W
0
1
EEI
R/W
0
0
EMI
R/W
0
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INTC1 Register
Bit
Name
R/W
POR
Bit 7 Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
Bit 1 Bit 0
7
-
-
-
6
MFF
R/W
0
5
-
-
-
4
T2F
R/W
0
3
-
-
-
2
EMFI
R/W
0
1
-
-
-
0
ET2I
R/W
0
2
ESII
R/W
0
1
ESIM
R/W
0
0
ETBI
R/W
0
unimplemented, read as “0”
MFF: Multi-function interrupt request flag
0: inactive
1: active
unimplemented, read as “0”
T2F: Timer/Event Counter 2 interrupt request flag
0: inactive
1: active
unimplemented, read as “0”
EMFI: Multi-function interrupt enable
0: disable
1: enable
unimplemented, read as “0”
ET2I: Timer/Event Counter 2 interrupt enable
0: disable
1: enable
MFIC Register
Bit
Name
R/W
POR
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Rev. 1.30
7
-
-
-
6
SIF
R/W
0
5
SIMF
R/W
0
4
TBF
R/W
0
3
-
-
-
unimplemented, read as “0”
SIF: SPIA interrupt request flag
0: inactive
1: active
SIMF: SIM interrupt request flag
0: inactive
1: active
TBF: Time Base interrupt request flag
0: inactive
1: active
unimplemented, read as “0”
ESII: SPIA interrupt enable
0: disable
1: enable
ESIM: SIM interrupt enable 0: disable
1: enable
ETBI: Time Base interrupt enable
0: disable
1: enable
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Interrupt Operation
A Timer/Event Counter overflow, an active edge on the external interrupt pin, a serial data byte
transmitted or received completion, or a Time Base event will all generate an interrupt request by
setting their corresponding request flag, if their appropriate interrupt enable bit is set. When this
happens, the Program Counter, which stores the address of the next instruction to be executed, will
be transferred onto the stack. The Program Counter will then be loaded with a new address which
will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next
instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement
which will jump to another section of program which is known as the interrupt service routine.
Here is located the code to control the appropriate interrupt. The interrupt service routine must be
terminated with a RETI instruction, which retrieves the original Program Counter address from
the stack and allows the microcontroller to continue with normal execution at the point where the
interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
following diagram with their order of priority.
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‚ €        †     Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will
be cleared automatically. This will prevent any further interrupt nesting from occurring. However,
if other interrupt requests occur during this interval, although the interrupt will not be immediately
serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the
program is already in another interrupt service routine, the EMI bit should be set after entering the
routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged,
even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service
is desired, the stack must be prevented from becoming full.
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When an interrupt request is generated it takes 2 or 3 instruction cycle before the program jumps
to the interrupt vector. If the device is in the Sleep or Idle Mode and is woken up by an interrupt
request then it will take 3 cycles before the program jumps to the interrupt vector.
Main
P�og�am
N
Ena�le Bit Set ?
Y
A�tomaticall� Disa�le Inte���pt
Clea� EMI & Req�est �lag
Main
P�og�am
Wait fo� � ~ 3 Inst��ction C�cles
ISR Ent��
…
…
RETI
(it will set EMI A�tomaticall�)
Interrupt Flow
Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of
simultaneous requests, the following table shows the priority that is applied. These can be masked
by resetting the EMI bit.
Interrupt Source
External Interrupt
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
Timer/Event Counter 2 Overflow
Multi-function Interrupt
(Time Base, SIM, SPIA)
Priority
1
2
3
4
Vector
04H
08H
0CH
10H
5
18H
In cases where both external and internal interrupts are enabled and where an external and internal
interrupt occurs simultaneously, the external interrupt will always have priority and will therefore be
serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent
simultaneous occurrences.
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External Interrupt
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable
bit, INTE, must first be set. An actual external interrupt will take place when the external interrupt
request flag, INTF, is set, a situation that will occur when an edge transition appears on the external
INT line. The type of transition that will trigger an external interrupt, whether high to low, low to
high or both is determined by the INTEG0 and INTEG1 bits, which are bits 6 and 7 respectively, in
the CTRL1 control register. These two bits can also disable the external interrupt function.
INTEG1
0
0
1
1
INTEG0
0
1
0
1
Edge Trigger Type
External interrupt disable
Rising edge Trigger
Falling edge Trigger
Both edge Trigger
The external interrupt pin is pin-shared with the I/O pin PA3 and can only be configured as an
external interrupt pin if the corresponding external interrupt enable bit in the INTC0 register has
been set and the edge trigger type has been selected using the CTRL1 register. The pin must also
be setup as an input by setting the corresponding PAC.3 bit in the port control register. When the
interrupt is enabled, the stack is not full and an active transition appears on the external interrupt pin,
a subroutine call to the external interrupt vector at location 04H, will take place. When the interrupt
is serviced, the external interrupt request flag, EIF, will be automatically reset and the EMI bit will
be automatically cleared to disable other interrupts. Note that any pull-high resistor connections on
this pin will remain valid even if the pin is used as an external interrupt input.
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the
corresponding timer interrupt enable bit, TnE, must first be set. An actual Timer/Event Counter
interrupt will take place when the Timer/Event Counter request flag, TnF, is set, a situation that will
occur when the relevant Timer/Event Counter overflows. When the interrupt is enabled, the stack is
not full and a Timer/Event Counter n overflow occurs, a subroutine call to the relevant timer interrupt
vector, will take place. When the interrupt is serviced, the timer interrupt request flag, TnF, will be
automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
Multi-function Interrupt
Unlike the other independent interrupts, the Multi-function Interrupt has no independent source, but
rather is formed from other existing interrupt sources, namely the Time-base Interrupt, SIM Interrupt
and SPIA Interrupt. A Multi-function Interrupt request will take place when the Multi-function
Interrupt request flag, MFF is set. The Multi-function Interrupt flag will be set when any of their
included functions generate an interrupt request flag. To allow the program to branch to its respective
interrupt vector address, when the Multi-function Interrupt is enabled and the stack is not full, and
either one of the interrupts contained within each of Multi-function Interrupt occurs, a subroutine
call to the Multi-function Interrupt vector will take place. When the interrupt is serviced, the MultiFunction Interrupt request flag will be automatically reset and the EMI bit will be automatically
cleared to disable other interrupts. However, it must be noted that, although the Multi-function
Interrupt flag will be automatically reset when the interrupt is serviced, the request flags from the
original source of the Multi-function Interrupt, namely the Time-base Interrupt, SIM Interrupt
and SPIA Interrupt will not be automatically reset and must be manually reset by the application
program. After a Multi-function has been generated, the application program can determine which
interrupt source has occurred by interrogating the interrupt request flags, SIF, SIMF or TBF within
the MFIC register.
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Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being
serviced, however, once an interrupt request flag is set, it will re- main in this condition in the
interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by
the application program.
Where a certain interrupt is contained within the Multi-function interrupt, then when the
interrupt service routine is executed, as only the Multi-function interrupt request flag, MFF, will
be automatically cleared, the individual request flag for the function needs to be cleared by the
application program.
It is recommended that programs do not use the CALL instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.
If only one stack is left and the interrupt is not well controlled, the original control sequence will be
damaged once a CALL subroutine is executed in the interrupt subroutine.
Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE
Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is
required to prevent a certain interrupt from waking up the microcontroller then its respective request
flag should be first set high before entering the SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the
contents of the accumulator, status register or other registers are altered by the interrupt service
program, their contents should be saved to the memory at the beginning of the interrupt service
routine.
To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI
instruction in addition to executing a return to the main program also automatically sets the EMI
bit high to allow further interrupts. The RET instruction however only executes a return to the main
program leaving the EMI bit in its present zero state and therefore disabling the execution of further
interrupts.
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LCD SCOM Function
The devices have the capability of driving external LCD panels. The common pins for LCD driving,
SCOM0~SCOM3, are pin shared with the PB0~ PB3 pins. The LCD signals, COM and SEG, are
generated using the application program.
LCD Operation
An external LCD panel can be driven using this device by configuring the PB0~PB3 pins as common
pins and using other output ports lines as segment pins. The LCD driver function is controlled
using the SCOMC register which in addition to controlling the overall on/off function also controls
the bias voltage setup function. This enables the LCD COM driver to generate the necessaryVDD/2
voltage levels for LCD 1/2 bias operation. The SCOMEN bit in the SCOMC register is the overall
master control for the LCD Driver, however this bit is used in conjunction with the COMnEN bits to
select which Port B pins are used for LCD driving. Note that the Port Control register does not need
to first setup the pins as outputs to enable the LCD driver operation.
SCOM Circuit
SCOMEN
0
1
1
COMnEN
X
0
1
Pin Function
I/O
I/O
SCOMn
O/P Level
0 or 1
0 or 1
VDD/2
Output Control
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LCD Bias Control
The LCD COM driver enables a range of selections to be provided to suit the requirement of the
LCD panel which is being used. The bias resistor choice is implemented using the ISEL1 and ISEL0
bits in the SCOMC register.
SCOMC Register
Bit
Name
R/W
POR
Rev. 1.30
7
—
R/W
0
6
ISEL1
R/W
0
5
ISEL0
R/W
0
4
3
2
1
0
SCOMEN COM3EN COM2EN COM1EN COM0EN
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit 7
Reserved Bit
1: Unpredictable operation - bit must NOT be set high
0: Correct level - bit must be reset to zero for correct operation
Bit 6,5
ISEL1, ISEL0: SCOM operating current selection (VDD=5V)
00: 25μA
01: 50μA
10: 100μA
11: 200μA
Bit 4 SCOMEN: SCOM module on/off control
0: disable
1: enable
SCOMn can be enable by COMnEN if SCOMEN=1
Bit 3 COM3EN: PB3 or SCOM3 selection
0: I/O
1: SCOM3
Bit 2 COM2EN: PB2 or SCOM2 selection
0: I/O
1: SCOM2
Bit 1 COM1EN: PB1 or SCOM1 selection
0: I/O
1: SCOM1
Bit 0 COM0EN: PB0 or SCOM0 selection
0: I/O
1: SCOM0
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Serial Interface Module – SIM
These devices contain a Serial Interface Module, which includes both the four line SPI interface or
the two line I2C interface types, to allow an easy method of communication with external peripheral
hardware. Having relatively simple communication protocols, these serial interface types allow
the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or
EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins therefore the SIM
interface function must first be selected using a configuration option. As both interface types share
the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM
operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of
the SIM pin-shared I/O are selected using pull-high control registers, and also if the SIM function is
enabled.
SPI Interface
This SPI interface function which is part of the Serial Interface Module, should not be confused with
the other independent SPI function, known as SPIA, which is described in another section of this
datasheet.
The SPI interface is often used to communicate with external peripheral devices such as sensors,
Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI
interface is a synchronous serial data interface that has a relatively simple communication protocol
simplifying the programming requirements when communicating with external hardware devices.
The communication is full duplex and operates as a slave/master type, where the device can be
either master or slave. Although the SPI interface specification can control multiple slave devices
from a single master, but this device provided only one SCS pin. If the master needs to control
multiple slave devices from a single master, the master can use I/O pin to select the slave devices.
SPI Interface Operation
The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin
names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output
lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pinshared with normal I/O pins and with the I2C function pins, the SPI interface must first be enabled by
selecting the SIM enable configuration option and setting the correct bits in the SIMC0 and SIMC2
registers. After the SPI configuration option has been configured it can also be additionally disabled
or enabled using the SIMEN bit in the SIMC0 register. Communication between devices connected
to the SPI interface is carried out in a slave/master mode with all data transfer initiations being
implemented by the master. The Master also controls the clock signal. As the device only contains
a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set
CSEN bit to "1" to enable SCS pin function, set CSEN bit to "0" the SCS pin will be floating state.
SPI Master/Slave Connection
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The SPI function in this device offers the following features:
• Full duplex synchronous data transferBoth Master and Slave modes
• LSB first or MSB first data transmission modes
• Transmission complete flag
• Rising or falling active clock edge
• WCOL and CSEN bit enabled or disable select
The status of the SPI interface pins is determined by a number of factors such as whether the device
is in the master or slave mode and upon the condition of certain control bits such as CSEN and
SIMEN.
There are several configuration options associated with the SPI interface. One of these is to
enable the SIM function which selects the SIM pins rather than normal I/O pins. Note that if the
configuration option does not select the SIM function then the SIMEN bit in the SIMC0 register will
have no effect. Another two SPI configuration options determine if the CSEN and WCOL bits are to
be used.
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SPI Registers
There are three internal registers which control the overall operation of the SPI interface. These are
the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only
used by the I2C interface.
Register
Name
SIMC0
SIMD
SIMC2
Bit
7
SIM2
D7
D7
6
SIM1
D6
D6
5
SIM0
D5
CKPOLB
4
PCKEN
D4
CKEG
3
PCKP1
D3
MLS
2
PCKP0
D2
CSEN
1
SIMEN
D1
WCOL
0
—
D0
TRF
SIM Registers List
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to
be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the
device can read it from the SIMD register. Any transmission or reception of data from the SPI bus
must be made via the SIMD register.
SIMD Regisater
Bit
Name
R/W
POR
7
D7
R/W
x
6
D6
R/W
x
5
D5
R/W
x
4
D4
R/W
x
3
D3
R/W
x
2
D2
R/W
x
1
D1
R/W
x
0
D0
R/W
x
"x" unknown
There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2
register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used
by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable
function and to set the data transmission clock frequency. Although not connected with the SPI
function, the SIMC0 register is also used to control the Peripheral Clock Prescaler. Register SIMC2
is used for other control functions such as LSB/MSB selection, write collision flag etc.
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SIMC0 Register
Bit
Name
R/W
POR
Bit 7~5
6
SIM1
R/W
1
5
SIM0
R/W
1
4
PCKEN
R/W
0
3
PCKP1
R/W
0
2
PCKP0
R/W
0
1
SIMEN
R/W
0
0
—
—
—
SIM2, SIM1, SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS/4
001: SPI master mode; SPI clock is fSYS/16
010: SPI master mode; SPI clock is fSYS/64
011: SPI master mode; SPI clock is fLXT
100: SPI master mode; SPI clock is Timer/Event Counter 0 output/2 (PFD0)
101: SPI slave mode
110: I2C slave mode
111: Unused mode
These bits setup the overall operating mode of the SIM function. As well as selecting
if the I2C or SPI function, they are used to control the SPI Master/Slave selection
and the SPI Master clock frequency. The SPI clock is a function of the system clock
but can also be chosen to be sourced from the Timer/Event Counter 0. If the SPI
Slave Mode is selected then the clock will be supplied by an external Master device.
Bit 4 PCKEN: Peripheral Clock Pin Control
Described elsewhere.
Bit 3~2
PCKP1, PCKP0: Select PCK output pin frequency
Described elsewhere.
Bit 1
SIMEN: SIM Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is
cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA
and SCL lines will be in a floating condition and the SIM operating current will be
reduced to a minimum value. When the bit is high the SIM interface is enabled.
The SIM configuration option must have first enabled the SIM interface for this
bit to be effective. If the SIM is configured to operate as an SPI interface via the
SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous
settings when the SIMEN bit changes from low to high and should therefore be first
initialised by the application program. If the SIM is configured to operate as an I2C
interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the
contents of the I2C control bits such as HTX and TXAK will remain at the previous
settings and should therefore be first initialised by the application program while the
relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their
default states.
Bit 0 Rev. 1.30
7
SIM2
R/W
1
unimplemented, read as "0"
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SIMC2 Register
Bit
Name
R/W
POR
6
D6
R/W
0
5
CKPOLB
R/W
0
4
CKEG
R/W
0
3
MLS
R/W
0
2
CSEN
R/W
0
1
WCOL
R/W
0
0
TRF
R/W
0
Bit 7~6
Undefined bit
This bit can be read or written by user software program.
Bit 5
CKPOLB: Determines the base condition of the clock line
0: the SCK line will be high when the clock is inactive
1: the SCK line will be low when the clock is inactive
The CKPOLB bit determines the base condition of the clock line, if the bit is high,
then the SCK line will be low when the clock is inactive. When the CKPOLB bit is
low, then the SCK line will be high when the clock is inactive.
Bit 4
CKEG: Determines SPI SCK active clock edge type
CKPOLB=0
0: SCK is high base level and data capture at SCK rising edge
1: SCK is high base level and data capture at SCK falling edge
CKPOLB=1
0: SCK is low base level and data capture at SCK falling edge
1: SCK is low base level and data capture at SCK rising edge
The CKEG and CKPOLB bits are used to setup the way that the clock signal
outputs and inputs data on the SPI bus. These two bits must be configured before
data transfer is executed otherwise an erroneous clock edge may be generated.
The CKPOLB bit determines the base condition of the clock line, if the bit
is high, then the SCK line will be low when the clock is inactive. When the
CKPOLB bit is low, then the SCK line will be high when the clock is inactive.
The CKEG bit determines active clock edge type which depends upon the condition
of CKPOLB bit.
Bit 3
Bit 2
Bit 1
Rev. 1.30
7
D7
R/W
0
MLS: SPI Data shift order
0: LSB
1: MSB
This is the data shift select bit and is used to select how the data is transferred, either
MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.
CSEN: SPI SCS pin Control
0: Disable
1: Enable
The CSEN bit is used as an enable/disable for the SCS pin. If this bit is
low, then the SCS pin will be disabled and placed into a floating condition.
If the bit is high the SCS pin will be enabled and used as a select pin.
Note that using the CSEN bit can be disabled or enabled via configuration option.
WCOL: SPI Write Collision flag
0: No collision
1: Collision
The WCOL flag is used to detect if a data collision has occurred. If this bit is high it
means that data has been attempted to be written to the SIMD register during a data
transfer operation. This writing operation will be ignored if data is being transferred.
The bit can be cleared by the application program. Note that using the WCOL bit can
be disabled or enabled via configuration option.
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TRF: SPI Transmit/Receive Complete flag
0: Data is being transferred
1: SPI data transmission is completed
The TRF bit is the Transmit/Receive Complete flag and is set "1" automatically
when an SPI data transmission is completed, but must set to "0" by the application
program. It can be used to generate an interrupt.
Bit 0
SPI Communication
After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when
data is written to the SIMD register, transmission/reception will begin simultaneously. When the
data transfer is complete, the TRF flag will be set automatically, but must be cleared using the
application program. In the Slave Mode, when the clock signal from the master has been received,
any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into
the SIMD register. The master should output an SCS signal to enable the slave device before a
clock signal is provided. The slave data to be transferred should be well prepared at the appropriate
moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG
bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal
for various configurations of the CKPOLB and CKEG bits.
The SPI will continue to function even in the IDLE Mode.
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Rev. 1.30
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Enhanced I/O 8-Bit OTP MCU
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I2C Interface
The I 2C interface is used to communicate with external peripheral devices such as sensors,
EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface
for synchronous serial data transfer. The advantage of only two lines for communication, relatively
simple communication protocol and the ability to accommodate multiple devices on the same bus
has made it an extremely popular interface type for many applications.
I2C Mater Slave Bus Connection
I2C Interface Operation
The I 2 C serial interface is a two line interface, a serial data line, SDA, and serial clock
line, SCL. As many devices may be connected together on the same bus, their outputs are
both open drain types. For this reason it is necessary that external pull-high resistors are
connected to these outputs. Note that no chip select line exists, as each device on the I 2C
bus is identified by a unique address which will be transmitted and received on the I2C bus.
When two devices communicate with each other on the bidirectional I 2 C bus, one is
known as the master device and one as the slave device. Both master and slave can
transmit and receive data, however, it is the master device that has overall control of
the bus. For these devices, which only operates in slave mode, there are two methods
of transferring data on the I 2C bus, the slave transmit mode and the slave receive mode.
There are several configuration options associated with the I2C interface. One of these is to enable
the function which selects the SIM pins rather than normal I/O pins. Note that if the configuration
option does not select the SIM function then the SIMEN bit in the SIMC0 register will have no
effect. A configuration option exists to allow a clock other than the system clock to drive the I2C
interface. Another configuration option determines the debounce time of the I2C interface. This uses
the internal clock to in effect add a debounce time to the external clock to reduce the possibility of
glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen
to be either 1 or 2 system clocks.
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Enhanced I/O 8-Bit OTP MCU
START signal
from Master
Send slave address
and R/W bit from Master
Acknowledge
from slave
Send data byte
from Master
Acknowledge
from slave
STOP signal
from Master
I2C Registers
There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMA and one
data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store
the data being transmitted and received on the I2C bus. Before the microcontroller writes data to
the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is
received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission
or reception of data from the I2C bus must be made via the SIMD register.
Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN
and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface.
Register
Name
SIMC0
SIMC1
SIMD
SIMA
Bit
7
SIM2
HCF
D7
IICA6
6
SIM1
HAAS
D6
IICA5
5
SIM0
HBB
D5
IICA4
4
PCKEN
HTX
D4
IICA3
3
PCKP1
TXAK
D3
IICA2
2
PCKP0
SRW
D2
IICA1
1
SIMEN
IAMWU
D1
IICA0
0
—
RXAK
D0
D0
I2C Registers List
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SIMC0 Register
Bit
Name
R/W
POR
Bit 7~5
6
SIM1
R/W
1
5
SIM0
R/W
1
4
PCKEN
R/W
0
3
PCKP1
R/W
0
2
PCKP0
R/W
0
1
SIMEN
R/W
0
0
—
—
—
SIM2, SIM1, SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS/4
001: SPI master mode; SPI clock is fSYS/16
010: SPI master mode; SPI clock is fSYS/64
011: SPI master mode; SPI clock is fLXT
100: SPI master mode; SPI clock is Timer/Event Counter 0 output/2 (PFD0)
101: SPI slave mode
110: I2C slave mode
111: Unused mode
These bits setup the overall operating mode of the SIM function. As well as selecting
if the I2C or SPI function, they are used to control the SPI Master/Slave selection
and the SPI Master clock frequency. The SPI clock is a function of the system clock
but can also be chosen to be sourced from Timer/Event Counter 0. If the SPI Slave
Mode is selected then the clock will be supplied by an external Master device.
Bit 4 PCKEN: Peripheral Clock Pin control
Described elsewhere.
Bit 3~2
PCKP1, PCKP0: Select PCK output pin frequency
Described elsewhere.
Bit 1
SIMEN: SIM Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is
cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA
and SCL lines will be in a floating condition and the SIM operating current will be
reduced to a minimum value. When the bit is high the SIM interface is enabled. The
SIM configuration option must have first enabled the SIM interface for this bit to
be effective. If the SIM is configured to operate as an SPI interface via SIM2~SIM0
bits, the contents of the SPI control registers will remain at the previous settings
when the SIMEN bit changes from low to high and should therefore be first
initialised by the application program. If the SIM is configured to operate as an I2C
interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the
contents of the I2C control bits such as HTX and TXAK will remain at the previous
settings and should therefore be first initialised by the application program while the
relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their
default states.
Bit 0 Rev. 1.30
7
SIM2
R/W
1
unimplemented, read as "0"
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SIMC1 Register
Bit
Name
R/W
POR
Bit 7
Bit 6
Bit 5
6
HAAS
R
0
5
HBB
R
0
4
HTX
R/W
0
3
TXAK
R/W
0
2
SRW
R
0
1
IAMWU
R/W
0
0
RXAK
R
1
HCF: I2C Bus data transfer completion flag
0: Data is being transferred
1: Completion of an 8-bit data transfer
The HCF flag is the data transfer flag. This flag will be zero when data is being
transferred. Upon completion of an 8-bit data transfer the flag will go high and an
interrupt will be generated.
HAAS: I2C Bus address match flag
0: Not address match
1: Address match
The HASS flag is the address match flag. This flag is used to determine if the slave
device address is the same as the master transmit address. If the addresses match
then this bit will be high, if there is no match then the flag will be low.
HBB: I2C Bus busy flag
0: I2C Bus is not busy
1: I2C Bus is busy
The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy
which will occur when a START signal is detected. The flag will be set to "0" when
the bus is free which will occur when a STOP signal is detected.
Bit 4 HTX: Select I2C slave device is transmitter or receiver
0: Slave device is the receiver
1: Slave device is the transmitter
Bit 3
TXAK: I2C Bus transmit acknowledge flag
0: Slave send acknowledge flag
1: Slave do not send acknowledge flag
The TXAK bit is the transmit acknowledge flag. After the slave device receipt of
8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave
device. The slave device must always set TXAK bit to "0" before further data is
received.
Bit 2
Rev. 1.30
7
HCF
R
1
SRW: I2C Slave Read/Write flag
0: Slave device should be in receive mode
1: Slave device should be in transmit mode
The SRW flag is the I2C Slave Read/Write flag. This flag determines whether
the master device wishes to transmit or receive data from the I2C bus. When the
transmitted address and slave address is match, that is when the HAAS flag is set
high, the slave device will check the SRW flag to determine whether it should be in
transmit mode or receive mode. If the SRW flag is high, the master is requesting to
read data from the bus, so the slave device should be in transmit mode. When the
SRW flag is zero, the master will write data to the bus, therefore the slave device
should be in receive mode to read this data.
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Enhanced I/O 8-Bit OTP MCU
Bit 1
Bit 0
IAMWU: I2C Address Match Wake-up Control
0: Disable
1: Enable
This bit should be set to "1" to enable I2C address match wake up from SLEEP or
IDLE Mode.
RXAK: I2C Bus Receive acknowledge flag
0: Slave receive acknowledge flag
1: Slave do not receive acknowledge flag
The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it
means that a acknowledge signal has been received at the 9th clock, after 8 bits of
data have been transmitted. When the slave device in the transmit mode, the slave
device checks the RXAK flag to determine if the master receiver wishes to receive
the next byte. The slave transmitter will therefore continue sending out data until the
RXAK flag is "1". When this occurs, the slave transmitter will release the SDA line
to allow the master to send a STOP signal to release the I2C Bus.
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to
be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the
device can read it from the SIMD register. Any transmission or reception of data from the SPI bus
must be made via the SIMD register.
SIMD Register
Bit
Name
R/W
POR
7
D7
R/W
x
6
D6
R/W
x
5
D5
R/W
x
4
D4
R/W
x
3
D3
R/W
x
2
D2
R/W
x
1
D1
R/W
x
0
D0
R/W
x
"x" unknown
SIMA Register
Bit
Name
R/W
POR
7
IICA6
R/W
x
6
IICA5
R/W
x
5
IICA4
R/W
x
4
IICA3
R/W
x
3
IICA2
R/W
x
2
IICA1
R/W
x
1
IICA0
R/W
x
0
—
—
—
"x"unknown
Bit 7~1
Bit 0
Rev. 1.30
IICA6~ IICA0: I C slave address
IICA6~ IICA0 is the I2C slave address bit 6~ bit 0.
The SIMA register is also used by the SPI interface but has the name SIMC2. The
SIMA register is the location where the 7-bit slave address of the slave device is
stored. Bits 7~ 1 of the SIMA register define the device slave address. Bit 0 is not
defined.
When a master device, which is connected to the I2C bus, sends out an address,
which matches the slave address in the SIMA register, the slave device will be
selected. Note that the SIMA register is the same register address as SIMC2 which is
used by the SPI interface.
2
Undefined bit
This bit can be read or written by user software program.
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Enhanced I/O 8-Bit OTP MCU
  † †     „  … ‚ €  € ƒ „    ­ €   
‡ I2C Block Diagram
I2C Bus Communication
Communication on the I2C bus requires four separate steps, a START signal, a slave device address
transmission, a data transmission and finally a STOP signal. When a START signal is placed on
the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of
data on the bus. The first seven bits of the data will be the slave address with the first bit being the
MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the
SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service
routine, the slave device must first check the condition of the HAAS bit to determine whether the
interrupt source originates from an address match or from the completion of an 8-bit data transfer.
During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit,
which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be
checked by the slave device to determine whether to go into transmit or receive mode. Before any
transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are
steps to achieve this:
Step 1
Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to "1" to enable the I2C bus.
Step 2
Write the slave address of the device to the I2C bus address register SIMA.
Step 3
Set the ESIM and SIM Muti-Function interrupt enable bit of the interrupt control register to enable
the SIM interrupt and Multi-function interrupt.
Rev. 1.30
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Enhanced I/O 8-Bit OTP MCU

 € ‚   ƒ „ … ‚     ­
  ­
I2C Bus Initialisation Flow Chart
I2C Bus Start Signal
The START signal can only be generated by the master device connected to the I2C bus and not by
the slave device. This START signal will be detected by all devices connected to the I2C bus. When
detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START
condition occurs when a high to low transition on the SDA line takes place when the SCL line
remains high.
Slave Address
The transmission of a START signal by the master will be detected by all devices on the I2C bus.
To determine which slave device the master wishes to communicate with, the address of the slave
device will be sent out immediately following the START signal. All slave devices, after receiving
this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by
the master matches the internal address of the microcontroller slave device, then an internal I2C bus
interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines
the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will
then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set
the status flag HAAS when the addresses match.
As an I 2C bus interrupt can come from two sources, when the program enters the interrupt
subroutine, the HAAS bit should be examined to see whether the interrupt source has come from
a matching slave address or from the completion of a data byte transfer. When a slave address is
matched, the device must be placed in either the transmit mode and then write data to the SIMD
register, or in the receive mode where it must implement a dummy read from the SIMD register to
release the SCL line.
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Enhanced I/O 8-Bit OTP MCU
I2C Bus Read/Write Signal
The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the
I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to
be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes
to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as
a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C
bus, therefore the slave device must be setup to read data from the I2C bus as a receiver.
I2C Bus Slave Address Acknowledge Signal
After the master has transmitted a calling address, any slave device on the I 2C bus, whose
own internal address matches the calling address, must generate an acknowledge signal. The
acknowledge signal will inform the master that a slave device has accepted its calling address. If no
acknowledge signal is received by the master then a STOP signal must be transmitted by the master
to end the communication. When the HAAS flag is high, the addresses have matched and the slave
device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag
is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register
should be set to "1". If the SRW flag is low, then the microcontroller slave device should be setup as
a receiver and the HTX bit in the SIMC1 register should be set to "0".
I2C Bus Data and Acknowledge Signal
The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged
receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last.
After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before
it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal
from the master receiver, then the slave transmitter will release the SDA line to allow the master
to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD
register. If setup as a transmitter, the slave device must first write the data to be transmitted into the
SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD
register.
When the slave receiver receives the data byte, it must generate an acknowledge bit, known as
TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit
in the SIMC1 register to determine if it is to send another data byte, if not then it will release the
SDA line and await the receipt of a STOP signal from the master.
Rev. 1.30
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Enhanced I/O 8-Bit OTP MCU
€
€


­
         ­ I2C Communication Timing Diagram
Note: *When a slave address is matched, the device must be placed in either the transmit mode and
then write data to the SIMD register, or in the receive mode where it must implemented a
dummy read from the SIMD register to release the SCL line.
          I2C Bus ISR Flow Chart
Rev. 1.30
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Peripheral Clock Output
The Peripheral Clock Output allows the device to supply external hardware with a clock signal
synchronised to the microcontroller clock.
Peripheral Clock Operation
As the peripheral clock output pin, PCK, is shared with I/O line, the required pin function is chosen
via PCKEN in the SIMC0 register. The Peripheral Clock function is controlled using the SIMC0
register. The clock source for the Peripheral Clock Output can originate from either the Timer/
Event Counter 0 output/2 or a divided ratio of the internal fSYS clock. The PCKEN bit in the SIMC0
register is the overall on/off control, setting PCKEN bit to "1" enables the Peripheral Clock, setting
PCKEN bit to "0" disables it. The required division ratio of the system clock is selected using the
PCKP1 and PCKP0 bits in the same register.
SIMC0 Register
Bit
Name
R/W
POR
Rev. 1.30
7
SIM2
R/W
1
6
SIM1
R/W
1
5
SIM0
R/W
1
4
PCKEN
R/W
0
3
PCKP1
R/W
0
Bit 7~5
SIM2, SIM1, SIM0: SIM operating mode control
Described elsewhere
Bit 4 PCKEN: Peripheral Clock Pin control
0: Disable
1: Enable
Bit 3~2
PCKP1, PCKP0: select PCK output pin frequency
00: fSYS
01: fSYS/4
10: fSYS/8
11: Timer/Event Counter 0 output /2 (PFD0)
Bit 1 SIMEN: SIM control
Described elsewhere
Bit 0 unimplemented, read as "0"
89
2
PCKP0
R/W
0
1
SIMEN
R/W
0
0
—
—
—
February 05, 2015
HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
SPIA Serial Interface – SPIA
The devices contain an independent SPIA function, known as the SPIA. It is important not to
confuse this independent SPIA function with the additional one contained within the combined SIM
function, which is described in another section of this datasheet.
The device includes a single SPIA Serial Interface. The SPIA interface is a full duplex serial data
link, originally designed by Motorola, which allows multiple devices connected to the same SPIA
bus to communicate with each other. The devices communicate using a master/slave technique
where only the single master device can initiate a data transfer. A simple four line signal bus is used
for all communication and these pins are shared with normal I/O pins. The SPIA function is selected
via a configuration option.
SPIA Interface Communication
Four lines are used for SPIA communication known as SDIA - Serial Data Input, SDOA - Serial
Data Output, SCKA - Serial Clock and SCSA - Slave Select. Note that the condition of the Slave
Select line is conditioned by the CSEN bit in the SBCR control register. If the CSEN bit is high then
the SCSA line is active while if the bit is low then the SCSA line will be in a floating condition. The
following timing diagram depicts the basic timing protocol of the SPIA bus.
SPIA Registers
There are two registers associated with the SPIA Interface. These are the SBCR register which is
the control register and the SBDR which is the data register. The SBCR register is used to setup the
required setup parameters for the SPIA bus and also used to store associated operating flags, while
the SBDR register is used for data storage.
After Power on, the contents of the SBDR register will be in an unknown condition while the SBCR
register will default to the condition below:
CKS
0
M1
1
M0
1
SBEN
0
MLSA
0
CSENA
0
WCOLA
0
TRFA
0
Note that data written to the SBDR register will only be written to the TXRX buffer, whereas data
read from the SBDR register will actual be read from the register.
SPIA Bus Enable/Disable
To enable the SPIA bus, CSEN = 1, SCSA=0, then wait for data to be written to the SBDR (TXRX
bufffer) register. For the Master Mode, after data has been written to the SBDR (TXRX buffer)
register, then transmission or reception will start automatically. When all the data has been
transferred the TRF bit should be set. For the Slave Mode, when clock pulses are received on SCKA,
data in the TXRX buffer will be shifted out or data on SDIA will be shifted in.
To Disable the SPIA bus SCKA, SDIA, SDOA, SCSA should be in a floating condition.
Rev. 1.30
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Enhanced I/O 8-Bit OTP MCU
ˆ ‡ ‰ ‡    
 
     ­
 „ € ‚
ƒ … † ‡ SPIA Block Diagram
SBCR Register
Bit
Name
R/W
POR
Bit 7 Bit 6,5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 7
CKS
R/W
0
6
M1
R/W
1
5
M0
R/W
1
4
SBEN
R/W
0
3
MLSA
R/W
0
2
CSENA
R/W
0
1
WCOLA
R/W
0
0
TRFA
R/W
0
CKS: SPIA Clock Source Select Bit
0: fSPIA =fSYS/4
1: fSPIA =fLXT
M1,M0: Master/Slave/Baud Rate Bits
00: Master, Baud rate : fSPIA
01: Master, Baud rate : fSPIA /4 10: Master, Baud rate : fSPIA /16 11: Slave mode
SBEN: Serial Bus Enable/Disable bit 0: Disable
1: Enable
Dependent upon CSEN bit
MLSA: MSB/LSB First Bit
0: LSB shift first
1: MSB shift first
CSENA: Selection Signal Enable/Disable Bit
0: SCSA floating
1: Enable
WCOLA: Write Collision Bit 0: Collision free
1: Collision detected
TRFA: Transmit /Receive Flag
0: Not complete
1: Transmission/reception complete
Note: The TRFA flag will also generate an SPIA interrupt signal, for more informaton refer to the
Interrupt section.
Rev. 1.30
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Enhanced I/O 8-Bit OTP MCU
    ­ € ‚ ƒ   
  
SPIA Bus Timing
SPIA Operation
All communication is carried out using the 4-line interface for both Master or Slave Mode. The
timing diagram shows the basic operation of the bus.
The CSENA bit in the SBCR register controls the overall function of the SPIA interface. Setting this
bit high, will enable the SPIA interface by allowing the SCSA line to be active, which can then be
used to control the SPIA inteface. If the CSENA bit is low, the SPIA interface will be disabled and
the SCSA line will be in a floating condition and can therefore not be used for control of the SPIA
interface. The SBEN bit in the SBCR register must also be high which will place the SDIA line in a
floating condition and the SDOA line high. If in Master Mode the SCKA line will be either high or
low depending upon the clock polarity configuration option. If in Slave Mode the SCKA line will be
in a floating condition. If SBEN is low then the bus will be disabled and SCSA, SDIA, SDOA and
SCKA will all be in a floating condition.
In the Master Mode the Master will always generate the clock signal. The clock and data
transmission will be initiated after data has been written to the SBDR register. In the Slave Mode,
the clock signal will be received from an external master device for both data transmission or
reception. The following sequences show the order to be followed for data transfer in both Master
and Slave Mode:
Master Mode
• Step 1
Select the clock source using the CKS bit in the SBCR control register.
• Step 2
Setup the M0 and M1 bits in the SBCR control register to select the Master Mode and the
required Baud rate. Values of 00, 01 or 10 can be selected.
• Step 3
Setup the CSENA bit and setup the MLS bit to choose if the data is MSB or LSB first, this must
be same as the Slave device.
• Step 4
Setup the SBEN bit in the SBCR control register to enable the SPIA interface.
• Step 5
For write operations: write the data to the SBDR register, which will actually place
the data into the TXRX buffer. Then use the SCKA and SCSA lines to output the data.
Goto to step6. For read operations: the data transferred in on the SDIA line will be stored in the
TXRX buffer until all the data has been received at which point it will be latched into the SBDR
register.
Rev. 1.30
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Enhanced I/O 8-Bit OTP MCU
• Step 6
Check the WCOLA bit, if set high then a collision error has occurred so return to step5.
If equal to zero then go to the following step.
• Step 7
Check the TRFA bit or wait for an SPIA serial bus interrupt.
• Step 8
Read data from the SBDR register.
• Step 9
Clear TRFA.
• Step10
Goto step 5.
• Slave Mode
• Step 1
The CKS bit has a don't care value in the slave mode.
• Step 2
Setup the M0 and M1 bits to 00 to select the Slave Mode. The CKS bit is don't care.
• Step 3
Setup the CSENA bit and setup the MLS bit to choose if the data is MSB or LSB first, this must
be same as the Master device.
• Step 4
Setup the SBEN bit in the SBCR control register to enable the SPIA interface.
• Step 5
For write operations: write data to the SBCR register, which will actually place the data into
the TXRX register, then wait for the master clock and SCSA signal. After this goto step 6.
For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer
until all the data has been received at which point it will be latched into the SBDR register.
• Step 6
Check the WCOL bit, if set high then a collision error has occurred so return to step5.
If equal to zero then go to the following step.
• Step 7
Check the TRF bit or wait for an SBI serial bus interrupt.
• Step 8
Read data from the SBDR register.
• Step 9
Clear TRF
• Step10
Goto step 5
SPIA Configuration Options
Several configuration options exist for the SPIA Interface function which must be setup during
device programming. One option is to enable the operation of the WCOL, write collision bit, in the
SBCR register. Another option exists to select the clock polarity of the SCKA line. A configuration
option also exists to disable or enable the operation of the CSENA bit in the SBCR register. If the
configuration option disables the CSENA bit then this bit cannot be used to affect overall control of
the SPIA Interface.
Rev. 1.30
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Enhanced I/O 8-Bit OTP MCU
Error Detection
The WCOL bit in the SBCR register is provided to indicate errors during data transfer. The bit is
set by the Serial Interface but must be cleared by the application program. This bit indicates a data
collision has occurred which happens if a write to the SBDR register takes place during a data
transfer operation and will prevent the write operation from continuing. The bit will be set high by
the Serial Interface but has to be cleared by the user application program. The overall function of the
WCOL bit can be disabled or enabled by a configuration option.
Programming Considerations
When the device is placed into the Idle Mode note that data reception and transmission will
continue. The TRF bit is used to generate an interrupt when data has been transferred or received.
Digital to Analog Converter – DAC
The devices include a 12-bit Digital to Analog Converter function. This function allows digital data
contained in the device to generate audio signals.
Operation
The data to be converted is stored in two registers DAL and DAH. The DAH register stores the
highest 8-bits, DA4~DA11, while DAL stores the lowest 4-bits, DA0~DA3. An bit in the control
register, CTRL2, provides overall DAC on/off control and a volume control register, VOL, provides
a 3-bit 8-level volume control. The DAC output is channeled to pin AUD which is pin-shared with I/
O pin PA4. When the DAC is enabled by setting the DACEN pin high, then the original I/O function
will be disabled, along with any pull-high resistor options. The DAC output reference voltage is the
power supply voltage VDD.
DAH Register
Bit
Name
R/W
POR
Bits 7~0
7
DA11
R/W
0
6
DA10
R/W
0
5
DA9
R/W
0
4
DA8
R/W
0
3
DA7
R/W
0
2
DA6
R/W
0
1
DA5
R/W
0
0
DA4
R/W
0
2
—
—
0
1
—
—
0
0
—
—
0
DA11~DA0 Audio Output DAC high byte bits
DAL Register
Bit
Name
R/W
POR
Bits 7~4
Bits 3~0
Rev. 1.30
7
DA3
R/W
0
6
DA2
R/W
0
5
DA1
R/W
0
4
DA0
R/W
0
3
—
—
0
DA3~DA0 Audio Output DAC low bits Unimplemented – read as “0”
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Enhanced I/O 8-Bit OTP MCU
CTRL2 Register
Bit
Name
R/W
POR
7
DACEN
R/W
0
6
—
—
—
5
PWMC3
R/W
0
4
PWMC2
R/W
0
3
—
—
—
2
—
—
—
1
—
—
—
0
LXTEN
R/W
1
Bit 7 DACEN: DAC disable/enable control
0: disable
1: enable
Bit 6 unimplemented, read as "0"
Bit 5 PWMC3: IO or PWM3 control
Described elsewhere
Bit 4 PWMC2: IO or PWM2 control
Described elsewhere
Bit 3~1
unimplemented, read as "0"
Bit 0 LXTEN: LXT Oscillator on/off control after execution of HALT instruction
Described elsewhere
VOL Register
Bit
Name
R/W
POR
Bits 7~5
Bits 4~0
Rev. 1.30
7
VOL2
R/W
0
6
VOL1
R/W
0
5
VOL0
R/W
0
4
—
R/W
0
3
—
—
0
2
—
—
0
1
—
—
0
0
—
—
0
VOL2~VOL0 Audio Volume Control
Unimplemented – read as “0”
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Low Voltage Detector – LVD
Each device has a Low Voltage Detector function, also known as LVD. This enables the device to
monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain
level. This function may be especially useful in battery applications where the supply voltage will
gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated.
LVD Register
The Low Voltage Detector is controlled using a single register, LVDC, and configuration options.
The voltage threshold level to be detected is determined using a configuration option, therefore
cannot be modified by the application program.
A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates
that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the
overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage
detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low
voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit
when not in use, an important consideration in power sensitive battery powered applications.
LVDC Register
Bit
Name
R/W
POR
Bit 7~6 Bit 5 Bit 4 Bit 3~0:
7
—
—
—
6
—
—
—
5
LVDC
R
0
4
LVDEN
R/W
0
3
—
—
—
2
—
—
—
1
—
—
—
0
—
—
—
unimplemented, read as "0"
LVDO: LVD Output Flag
0: No Low Voltage Detect
1: Low Voltage Detect
LVDEN: Low Voltage Detector Control
0: Disable
1: Enable
unimplemented, read as "0"
LVD Operation
The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a
pre-specified voltage level voltage level setup using a configuration option. When the power supply
voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low
power supply voltage condition. The Low Voltage Detector function is supplied by a reference
voltage which will be automatically enabled. When the device is powered down the low voltage
detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a
time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note
also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there
may be multiple bit LVDO transitions.
LVD Operation
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Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the OTP
Program Memory device during the programming process. During the development process,
these options are selected using the HT-IDE software development tools. As these options are
programmed into the device using the hardware programming tools, once they are selected they
can not be changed later by the application software. All options must be defined for proper system
function, the details of which are shown in the table.
No.
Options
Oscillator Options
High Speed System Oscillator Selection - fH:
1. HXT
1
2. ERC
3. HIRC
Low Speed System Oscillator Selection - fL:
2
1. LXT
2. LIRC
WDT Clock Selection - fS:
1. LXT
3
2. LIRC
3. fSYS/4
HIRC Frequency Selection:
1. 4MHz
4
2. 8MHz
3. 12MHz
SST for HIRC/ERC-Tsst:
5
1. 1024 clocks
2. 2 clocks
Reset Pin Options
PA7/RES Pin Options:
6
1. RES pin
2. I/O pin
Watchdog Options
Watchdog Timer Function:
7
1. Enable
2. Disable
CLRWDT Instructions Selection:
8
1. 1 instructions
2. 2 instructions
LVR Options
LVR Function:
9
1. Enable
2. Disable
LVR/LVD Voltage Selection:
1. 2.1V/2.2V
10
2. 3.15V/3.3V
3. 4.2V/4.4V
SIM Options
SIM Function:
11
1. Enable
2. Disable
SPI - WCOL bit:
12 1. Enable
2. Disable
SPI - CSEN bit:
13 1. Enable
2. Disable
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No.
Options
I2C Debounce Time Selection:
1. No debounce
14
2. 1 system clock debounce
3. 2 system clock debounce
I2C-RNIC bit:
15 1. Enable
2. Disable
SPI Function:
16 1. Enable
2. Disable
SPI-CPOL bit:
17 1. Falling edge
2. Rising edge
DAC Options
DAC Function:
18 1. DAC
2. I/O
Application Circuit
   Note: "*" It is recommended that this component is added for ESD protection.
"**" It is recommended that this component is added in environments where power line noise
is significant.
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Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5μs and branch or call instructions would be implemented within
1μs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.
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Logical and Rotate Operation
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
which rotate data operations are used is to implement multiplication and division calculations.
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction
or to a subroutine using the CALL instruction. They differ in the sense that in the case of a
subroutine call, the program must return to the instruction immediately when the subroutine has
been carried out. This is done by placing a return instruction “RET” in the subroutine which will
cause the program to jump back to the address right after the CALL instruction. In the case of a JMP
instruction, the program simply jumps to the desired location. There is no requirement to jump back
to the original jumping off point as in the case of the CALL instruction. One special and extremely
useful set of branch instructions are the conditional branches. Here a decision is first made regarding
the condition of a certain data memory or individual bits. Depending upon the conditions, the
program will continue with the next instruction or skip over it and jump to the following instruction.
These instructions are the key to decision making and branching within the program perhaps
determined by the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i”
instructions respectively. The feature removes the need for programmers to first read the 8-bit output
port, manipulate the input data to ensure that other bits are not changed and then output the port with
the correct new data. This read-modify-write process is taken care of automatically when these bit
operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be setup as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the “HALT” instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
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Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function and
can be consulted as a basic instruction reference using the following listed conventions.
Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
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Mnemonic
Description
Cycles
Flag Affected
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no
skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the “CLR WDT1” and “CLR WDT2” instructions the TO and PDF flags may be affected by the
execution status. The TO and PDF flags are cleared after both “CLR WDT1” and “CLR WDT2”
instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m]
Description
Operation
Affected flag(s)
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C
ADCM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C
Add Data Memory to ACC
ADD A,[m]
Description
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C
ADD A,x
Description
Operation
Affected flag(s)
Add immediate data to ACC
The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator.
ACC ← ACC + x
OV, Z, AC, C
ADDM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C
AND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
AND A,x
Description
Operation
Affected flag(s)
Logical AND immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ x
Z
ANDM A,[m]
Description
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
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CALL addr
Description
Operation
Affected flag(s)
Subroutine call
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Stack ← Program Counter + 1
Program Counter ← addr
None
CLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
CLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
CLR WDT
Description
Operation
Affected flag(s)
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT1
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in
conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have
effect. Repetitively executing this instruction without alternately executing CLR WDT2 will
have no effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT2
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction
with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect.
Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CPL [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
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CPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
DAA [m]
Description
Operation
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or [m] ← ACC + 60H or
[m] ← ACC + 66H
C
DEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
DECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
HALT
Description
Operation
Affected flag(s)
Enter power down mode
This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
TO ← 0
PDF ← 1
TO, PDF
INC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
INCA [m]
Description
Operation
Affected flag(s)
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
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JMP addr
Description
Operation
Affected flag(s)
Jump unconditionally
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Program Counter ← addr
None
MOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
MOV A,x
Description
Operation
Affected flag(s)
Move immediate data to ACC
The immediate data specified is loaded into the Accumulator.
ACC ← x
None
MOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
NOP
Description
Operation
Affected flag(s)
No operation
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Description
Operation
Affected flag(s)
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
OR A,x
Description
Operation
Affected flag(s)
Logical OR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ x
Z
ORM A,[m]
Description
Operation
Affected flag(s)
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
RET
Description
Operation
Affected flag(s)
Return from subroutine
The Program Counter is restored from the stack. Program execution continues at the restored
address.
Program Counter ← Stack
None
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RET A,x
Description
Operation
Affected flag(s)
Return from subroutine and load immediate data to ACC
The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address.
Program Counter ← Stack
ACC ← x
None
RETI
Description
Operation
Affected flag(s)
Return from interrupt
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Program Counter ← Stack
EMI ← 1
None
RL [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
RLA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
RLC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
RLCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
RR [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
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RRA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
RRC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
RRCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
SBC A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C
SBCM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C
SDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
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SDZA [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
SET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
SET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
SIZ [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
SIZA [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
SNZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is not 0
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
SUB A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C
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SUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C
SUB A,x
Description
Operation
Affected flag(s)
Subtract immediate data from ACC
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − x
OV, Z, AC, C
SWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
SWAPA [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
SZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
SZA [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
SZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
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TABRDC [m]
Description
Operation
Affected flag(s)
Read table (current page) to TBLH and Data Memory
The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDL [m]
Description
Operation
Affected flag(s)
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
XOR A,[m]
Description
Operation
Affected flag(s)
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
XORM A,[m]
Description
Operation
Affected flag(s)
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
XOR A,x
Description
Operation
Affected flag(s)
Logical XOR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ x
Z
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Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the package information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant
section to be transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.30
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28-pin SKDIP (300mil) Outline Dimensions
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
1.380
—
1.420
B
0.280
—
0.310
C
0.060
—
0.130
D
0.125
—
0.200
E
0.015
—
0.022
0.065
F
0.045
—
G
—
0.1 BSC
—
H
0.300
—
0.325
I
—
—
0.400
Symbol
Rev. 1.30
Dimensions in mm
Min.
Nom.
Max.
36.07
A
35.05
—
B
7.11
—
7.87
C
1.52
—
3.30
D
3.18
—
5.08
E
0.38
—
0.56
F
1.14
—
1.65
G
—
2.54 BSC
—
H
7.62
—
8.26
I
—
—
10.16
113
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28-pin SOP (300mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
A
—
0.406 BSC
—
B
—
0.295 BSC
—
Max.
0.020
C
0.012
—
C’
—
0.705 BSC
—
D
—
—
0.104
E
—
0.050 BSC
—
F
0.004
—
0.012
G
0.016
—
0.050
H
0.008
—
0.013
α
0°
―
8°
Symbol
Rev. 1.30
Dimensions in mm
Min.
Nom.
Max.
A
—
10.30 BSC
—
B
—
7.5 BSC
—
C
0.31
—
0.51
C’
—
17.9 BSC
—
D
—
—
2.65
E
—
1.27 BSC
—
F
0.10
—
0.30
G
0.40
—
1.27
H
0.20
—
0.33
α
0°
―
8°
114
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Enhanced I/O 8-Bit OTP MCU
28-pin SSOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
—
A
—
0.236 BSC
B
—
0.154 BSC
—
C
0.008
—
0.012
C’
—
0.390 BSC
—
D
—
—
0.069
E
—
0.025 BSC
—
F
0.004
—
0.010
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
—
8°
Symbol
Rev. 1.30
Dimensions in mm
Min.
Nom.
Max.
—
A
—
6.0 BSC
B
—
3.9 BSC
—
C
0.20
—
0.30
C’
—
9.9 BSC
—
D
—
—
1.75
E
—
0.635 BSC
—
F
0.10
—
0.25
G
0.41
—
1.27
H
0.10
—
0.25
α
0°
—
8°
115
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44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions
Symbol
Nom.
Max.
A
—
0.472 BSC
—
B
—
0.394 BSC
—
C
—
0.472 BSC
—
D
—
0.394 BSC
—
E
—
0.032 BSC
—
F
0.012
0.015
0.018
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Rev. 1.30
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
—
12.00 BSC
—
B
—
10.00 BSC
—
C
—
12.00 BSC
—
D
—
10.00 BSC
—
E
—
0.80 BSC
—
F
0.30
0.37
0.45
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
—
7°
116
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Enhanced I/O 8-Bit OTP MCU
64-pin LQFP (7mm×7mm) Outline Dimensions
Symbol
Min.
Nom.
Max.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.016 BSC
—
F
0.005
0.007
0.009
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Rev. 1.30
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
—
9.0 BSC
—
B
—
7.0 BSC
—
C
—
9.0 BSC
—
D
—
7.0 BSC
—
E
—
0.4 BSC
—
F
0.13
0.18
0.23
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
—
7°
117
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HT48R068B/HT48R069B
Enhanced I/O 8-Bit OTP MCU
Copyright © 2015 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.30
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