S I GN S W DE RT E N R A O ENT P DED F MM EN REPL ACEM O C E NO T R MMENDED 2 1 0 2 ZL R ECO 6A Digital Synchronous Step-Down DC/DC Converter with Auto Compensation ZL2101 Features The ZL2101 is a 6A digital converter with auto compensation and integrated power management that combines an integrated synchronous step-down DC/DC converter with key power management functions in a small package, resulting in a flexible and integrated solution. • Integrated MOSFET Switches The ZL2101 can provide an output voltage from 0.54V to 5.5V (with margin) from an input voltage between 4.5V and 14V. Internal low rDS(ON) synchronous power MOSFETs enable the ZL2101 to deliver continuous loads up to 6A with high efficiency. An internal Schottky bootstrap diode reduces discrete component count. The ZL2101 also supports phase spreading to reduce system input capacitance. • Snapshot™ Parametric Capture Power management features such as digital soft-start delay and ramp, sequencing, tracking, and margining can be configured by simple pin-strapping or through an on-chip serial port. The ZL2101 uses the PMBus™ protocol for communication with a host controller and the Digital-DC bus for interoperability between other Zilker Labs devices. • Test and Measurement Equipment • 6A Continuous Output Current • ±1% Output Voltage Accuracy • Auto Compensation • I2C/SMBus Interface, PMBus Compatible • Internal Non-Volatile Memory (NVM) Applications • Telecom, Networking, Storage equipment • Industrial Control Equipment • 5V and 12V Distributed Power Systems Related Literature • AN2010 “Thermal and Layout Guidelines for Digital-DC™ Products” • AN2033 “Zilker Labs PMBus Command Set - DDC Products” • AN2035 “Compensation Using CompZL™” 100 VOUT = 3.3V EFFICIENCY (%) 90 80 70 60 50 40 0.0 VIN = 12V fSW = 200kHz L = 6µH 1.0 2.0 3.0 4.0 5.0 6.0 IOUT (A) FIGURE 1. ZL2101 EFFICIENCY January 23, 2012 FN7730.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ZL2101 Typical Application Circuit The following application circuit represents a typical implementation of the ZL2101. For PMBus operation, it is recommended to tie the enable pin (EN) to SGND. C RA 4.7 µF F.B. VDDP 29 1 PG VDDP 28 VR 31 VDDS 30 VRA 32 DDC 34 V2P5 33 EN 36 PGOOD MGN 35 DDC Bus ENABLE 3 SYNC SW 25 SW 24 ZL2106 ZL2101 LOUT 2.2µH SW 23 6 SCL SW 22 7 SDA SW 21 SW 20 18 PGND 17 PG ND VOUT 3.3V C OUT 150 µF PGND 19 16 PGND 15 PGND 13 VSEN 12 VTRK 11 SS 10 CFG 9 FC 14 SGND 8 SALRT e PAD (SG ND) CB 47nF VDDP 27 BST 26 4 VSET I2C/ SMBus †† C IN 100 µF 2 DGND 5 SA VIN 12V C DD 2.2 µF CR 4.7µF C 25 10 µF † ‡ Notes: ‡ Ferrite bead is optional for input noise suppression. † The DDC bus pull-up resistance will vary based on the capacitive loading of the bus, including the number of devices connected. The 10 kΩ default value, assuming a maximum of 100 pF per device, provides the necessary 1 µs pull-up rise time. Please refer to the Digital-DC Bus section for more details. †† 2 The I C/SMBus pull -up resistance will vary based on the capacitive loading of the bus, including the number of devices connected. Please refer to the I2 C/SMBus specifications for more details. FIGURE 2. 12V TO 3.3V/6A APPLICATION CIRCUIT (5ms SS DELAY, 5ms SS RAMP) Block Diagram 2.5V LDO 5V LDO 7V LDO VDDP VDDS VR EN VRA V2P5 VIN BST PG VTRK SALRT SMBus SCL DDC Bus SA SDA DDC PWM Control & Drivers SW VOUT VSEN NVM PGND Power Mgmt SYNC MGN VSET CFG SS FIGURE 3. BLOCK DIAGRAM 2 FN7730.0 January 23, 2012 ZL2101 Pin Configuration 28 29 30 31 32 33 34 1 27 2 26 3 25 4 24 ZL2101 ZL2106 5 23 6 22 7 Exposed Paddle 8 Connect to SGND 21 20 18 17 16 15 14 13 VDDP BST SW SW SW SW SW SW PGND CFG SS VTRK VSEN SGND PGND PGND PGND PGND 12 19 11 9 10 PG DGND SYNC VSET SA SCL SDA SALRT FC 35 36 EN MGN DDC V2P5 VRA VR VDDS VDDP VDDP ZL2101 (36 LD QFN) TOP VIEW FIGURE 4. Pin Descriptions PIN LABEL TYPE (Note 1) 1 PG O 2 DGND PWR 3 SYNC I/O, M (Note 2) 4 VSET I, M Output voltage select pin. Used to set VOUT set-point and VOUT max. 5 SA I, M Serial address select pin. Used to assign unique SMBus address to each IC. 6 SCL I/O Serial clock. Connect to external host interface. 7 SDA I/O Serial data. Connect to external host interface. 8 SALRT O 9 FC I, M Auto compensation configuration pin. Used to set up auto compensation. 10 CFG I, M Configuration pin. Used to control the SYNC pin, sequencing and enable tracking. 11 SS I, M Soft-start pin. Used to set the ramp delay and ramp time, sets UVLO and configure tracking. 12 VTRK I Track sense pin. Used to track an external voltage source. 13 VSEN I Output voltage positive feedback sensing pin. 14 SGND PWR Common return for analog signals. Connect to low impedance ground plane. 15, 16, 17, 18, 19 PGND PWR Power ground. Common return for internal switching MOSFETs. Connect to low impedance ground plane. 20, 21, 22, 23, 24, 25 SW I/O 26 BST PWR Bootstrap voltage for level-shift driver (referenced to SW). 27, 28, 29 VDDP PWR Bias supply voltage for internal switching MOSFETs (return is PGND). 30 VDDS PWR IC supply voltage (return is SGND). 3 DESCRIPTION Power-good. This pin transitions high 100ms after output voltage stabilizes within regulation band. Selectable open drain or push-pull output. Factory default is open drain. Digital ground. Common return for digital signals. Connect to low impedance ground plane. Clock synchronization pin. Used to set switching frequency of internal clock or for synchronization to external frequency reference. Serial alert. Connect to external host interface if desired. Switching node (level-shift common). FN7730.0 January 23, 2012 ZL2101 Pin Descriptions (Continued) PIN LABEL TYPE (Note 1) 31 VR PWR Regulated bias from internal 7V low-dropout regulator (return is PGND). Decouple with a 4.7µF capacitor to PGND. 32 VRA PWR Regulated bias from internal 5V low-dropout regulator for internal analog circuitry (return is SGND). Decouple with a 4.7µF capacitor to SGND. 33 V2P5 PWR Regulated bias from internal 2.5V low-dropout regulator for internal digital circuitry (return is DGND). Decouple with a 10µF capacitor. 34 DDC I/O 35 MGN I Margin pin. Used to enable margining of the output voltage. 36 EN I Enable pin. Used to enable the device (active high). ePad SGND PWR DESCRIPTION Digital-DC Bus (open drain). Interoperability between Zilker Labs devices. Exposed thermal pad. Common return for analog signals. Connect to low impedance ground plane. NOTES: 1. I = Input, O = Output, PWR = Power or Ground, M = Multi-mode pins. Please refer to Section “Multi-mode Pins” on page 11. 2. The SYNC pin can be used as a logic pin, a clock input or a clock output. Ordering Information PART NUMBER (Notes 4, 5) PART MARKING TEMP RANGE (°C) PACKAGE PKG. DWG. # ZL2101ALAF 2101 -40 to +85 36 Ld 6mmx6mm QFN L36.6x6C ZL2101ALAFT (Note 3) 2101 -40 to +85 36 Ld 6mmx6mm QFN L36.6x6C ZL2101ALAFTK (Note 3) 2101 -40 to +85 36 Ld 6mmx6mm QFN L36.6x6C ZL2101EVAL1Z Evaluation Board NOTES: 3. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. For Moisture Sensitivity Level (MSL), please see device information page for ZL2101. For more information on MSL please see techbrief TB363. 4 FN7730.0 January 23, 2012 ZL2101 Table of Contents Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ZL2101 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Digital-DC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Conversion Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Multi-mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin-strap Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Resistor Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C/SMBus Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Conversion Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Internal Bias Regulators and Input Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 High-side Driver Boost Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Start-up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Soft-start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-good (PG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Configuration A: SYNC OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Configuration B: SYNC INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Configuration C: SYNC AUTO DETECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Design Goal Trade-offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bootstrap Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CV2P5 Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CVR Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CVRA Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Current Sensing and Current Limit Threshold Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Driver Dead-time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output Pre-Bias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Tracking Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Tracking Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Tracking Configured by Pin-Strap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I2C/SMBus Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C/SMBus Device Address Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Monitoring via I2C/SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Snapshot™ Parametric Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Non-Volatile Memory and Device Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 FN7730.0 January 23, 2012 ZL2101 Absolute Maximum Ratings Thermal Information DC Supply Voltage for VDDP, VDDS Pins . . . . . . . . . . . . . . . . . . -0.3V to 17V High-Side Supply Voltage for BST Pin. . . . . . . . . . . . . . . . . . . . . -0.3V to 25V High-Side Boost Voltage for BST - SW Pins . . . . . . . . . . . . . . . . . -0.3V to 8V Internal MOSFET Reference for VR Pin . . . . . . . . . . . . . . . . . . -0.3V to 8.5V Internal Analog Reference for VRA Pin . . . . . . . . . . . . . . . . . . -0.3V to 6.5V Internal 2.5V Reference for V2P5 Pin . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V Logic I/O Voltage for EN, CFG, DDC, FC, MGN, PG, SDA, SCL, SA, SALRT, SS, SYNC, VTRK, VSET, VSEN Pins . . . . . . . . . . -0.3V to 6.5V Ground Differential for DGND - SGND, PGND - SGND Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V MOSFET Drive Reference Current for VR Pin Internal Bias Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Switch Node Current for SW Pin Peak (Sink Or Source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10A ESD Rating Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V Latch-Up (Tested per JESD78C) Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 36 Ld QFN (Notes 6, 7) . . . . . . . . . . . . . . . . 28 1.7 Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C Dissipation Limits (Note 8) TA = +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5W TA = +55°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5W TA = +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4W Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Input Supply Voltage Range, VDDP, VDDS (See Figure 14) VDDS tied to VR, VRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V VDDS tied to VR, VRA Floating . . . . . . . . . . . . . . . . . . . . . . . . 5.5V to 7.5V VR, VRA Floating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.5V to 14V Output Voltage Range, VOUT (Note 9) . . . . . . . . . . . . . . . . . . . . 0.54V to 5.5V Operating Junction Temperature Range, TJ . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 8. Thermal impedance depends on layout. 9. Includes margin limits. Electrical Specifications VDDP = VDDS = 12V, TA = -40°C to +85°C unless otherwise noted. (Note 10) Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. MIN (Note 20) TYP MAX (Note 20) UNIT fSW = 200kHz, no load - 11 20 mA fSW = 1MHz, no load - 15 30 mA - 0.6 1 mA PARAMETER CONDITIONS INPUT AND SUPPLY CHARACTERISTICS IDD Supply Current I2C/SMBus IDDS Shutdown Current EN = 0V, No VR Reference Output Voltage VDD > 8V, IVR < 10mA 6.5 7.0 7.5 V VRA Reference Output Voltage VDD > 5.5V, IVRA < 20mA 4.5 5.1 5.5 V V2P5 Reference Output Voltage IV2P5 < 20mA 2.25 2.5 2.75 V - - 6 A 0.6 - 5.0 V - 10 - mV - ±0.025 - % FS (Note 12) activity OUTPUT CHARACTERISTICS Output Current IRMS, Continuous Output Voltage Adjustment Range (Note 11) VIN > VOUT Output Voltage Setpoint Resolution Set using resistors Set using I2C/SMBus VSEN Output Voltage Accuracy Includes line, load, temp -1 - 1 % VSEN Input Bias Current VSEN = 5.5V - 110 200 µA Soft-start Delay Duration Range (Note 13) Set using SS pin or resistor 2 - 20 ms 0.002 - 500 s Set using I2C/SMBus 6 FN7730.0 January 23, 2012 ZL2101 Electrical Specifications VDDP = VDDS = 12V, TA = -40°C to +85°C unless otherwise noted. (Note 10) Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) MIN (Note 20) TYP MAX (Note 20) UNIT Turn-on delay (precise mode) (Notes 13, 14) - ±0.25 - ms Turn-on delay (normal mode) (Note 15) - -0.25/+4 - ms Turn-off delay (Note 15) - -0.25/+4 - ms Set using SS pin or resistor 2 - 20 ms 0 - 200 ms - 100 – µs -250 - 250 nA - - 0.8 V - 1.4 - V 2.0 - - V PARAMETER CONDITIONS Soft-start Delay Duration Accuracy Soft-start Ramp Duration Range Set using I2C/SMBus Soft-start Ramp Duration Accuracy LOGIC INPUT/OUTPUT CHARACTERISTICS Logic Input Leakage Current Digital pins Logic input low, VIL Logic input OPEN (N/C) Multi-mode logic pins Logic Input High, VIH Logic Output Low, VOL IOL ≤ 4mA - - 0.4 V Logic Output High, VOH IOH ≥ -2mA 2.25 - - V - - 9 A 200 - 1000 kHz OSCILLATOR AND SWITCHING CHARACTERISTICS Switch Node Current, ISW Peak (source or sink) (Note 16) Switching Frequency Range Switching Frequency Set-point Accuracy Predefined settings (Table 9) -5 - 5 % PWM Duty Cycle (max) Factory default (Note 17) - - 95 (Note 18) % 150 - - ns SYNC Pulse Width (min) Input Clock Frequency Drift Tolerance External clock source -13 - 13 % rDS(ON) of High Side N-channel FETs ISW = 6A, VGS = 6.5V - 60 85 mΩ rDS(ON) of Low Side N-channel FETs ISW = 6A, VGS = 12V - 43 65 mΩ VTRK Input Bias Current VTRK = 5.5V - 110 200 µA VTRK Tracking Ramp Accuracy 100% Tracking, VOUT - VTRK -100 - 100 mV VTRK Regulation Accuracy 100% Tracking, VOUT - VTRK -1 - 1 % Configurable via I2C/SMBus 2.85 - 16 V -150 - 150 mV - 3 - % 0 - 100 % - - 2.5 µs TRACKING FAULT PROTECTION CHARACTERISTICS UVLO Threshold Range UVLO Set-point Accuracy UVLO Hysteresis Factory default Configurable via I2C/SMBus UVLO Delay Power-good VOUT Threshold Factory default - 90 - % VOUT Power-good VOUT Hysteresis Factory default - 5 - % Power-good Delay Using pin-strap or resistor 2 - 20 ms 0 - 500 s Configurable via 7 I2C/SMBus FN7730.0 January 23, 2012 ZL2101 Electrical Specifications VDDP = VDDS = 12V, TA = -40°C to +85°C unless otherwise noted. (Note 10) Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER CONDITIONS VSEN Undervoltage Threshold VSEN Overvoltage Threshold MIN (Note 20) TYP MAX (Note 20) UNIT Factory default - 85 - % VOUT Configurable via I2C/SMBus 0 - 110 % VOUT Factory default - 115 - % VOUT Configurable via I2C/SMBus 0 - 115 % VOUT VSEN Undervoltage Hysteresis - 5 - % VOUT VSEN Undervoltage/Overvoltage Fault Response Time Factory default - 16 - µs Configurable via I2C/SMBus 5 - 60 µs Peak Current Limit Threshold Factory default - - 9.0 A 0.2 - 9.0 A - ±10 - % FS (Note 12) Factory default - 5 - tSW (Note 19) Configurable via I2C/SMBus 1 - 32 tSW (Note 19) - 125 - °C -40 - 125 °C - 15 - °C Configurable via I2C/SMBus Current Limit Set-point Accuracy Current Limit Protection Delay Thermal Protection Threshold (Junction Temperature) Factory default Configurable via I2C/SMBus Thermal Protection Hysteresis NOTES: 10. Refer to Safe Operating Area in Figure 8 and thermal design guidelines in AN2010. 11. Does not include margin limits. 12. Percentage of Full Scale (FS) with temperature compensation applied. 13. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this delay period to approximately 2ms, where in normal mode it may vary up to 4ms. 14. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable. Precise ramp timing mode is automatically disabled for a self-enabled device (EN pin tied high). 15. The devices may require up to a 4ms delay following the assertion of the enable signal (normal mode) or following the de-assertion of the enable signal. Precise mode requires Re-Enable delay = TOFF+TFALL+10µs. 16. Switch node current should not exceed IRMS of 6A. 17. Factory default is the initial value in firmware. The value can be changed via PMBus commands. 18. Maximum duty cycle is limited by the equation MAX_DUTY(%) = [1 - (150×10-9 × fSW)] × 100 and not to exceed 95%. 19. tSW = 1/fSW, where fSW is the switching frequency. 20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8 FN7730.0 January 23, 2012 ZL2101 Typical Performance Curves 1.4 1.4 1.3 1.3 NORMALIZED rDS(ON) NORMALIZED rDS(ON) For some applications, ZL2101 operating conditions (input voltage, output voltage, switching frequency, temperature) may require de-rating to remain within the Safe Operating Area (SOA). VIN = VDDP = VDDS, TJ = +125°C 1.2 1.1 1.0 0.9 0.8 0 25 50 75 1.2 1.1 1.0 0.9 0.8 100 0 25 50 TJ (°C) TJ (°C) 6 65 5 60 TJ = +110°C VOUT (V) TJ = +80°C 50 TJ = +25°C 6 7 VIN = 6V 3 VIN = 8.6V TO 14V 2 TJ = +50°C 40 VIN = 7.5V 4 55 45 100 FIGURE 6. HIGH-SIDE rDS(ON) vs TJ NORMALIZED FOR TJ = +25°C (VDDS = 12V, BST – SW = 6.5V, IDRAIN = 0.3A) 70 1 8 9 10 11 12 0 13 0.2 0.3 0.4 VDDS (V) 0.5 0.6 0.7 0.8 0.9 1 1.0 fSW (MHz) FIGURE 8. SAFE OPERATING AREA, TJ ≤ +125°C FIGURE 7. LOW-SIDE r DS(ON) vs V DDS WITH TJ 0.95 VOUT MAY NOT EXCEED 5.5V AT ANY TIME 0.90 0.85 VOUT/VIN (V) rDS(ON) (mΩ) FIGURE 5. LOW-SIDE rDS(ON) vs TJ NORMALIZED FOR TJ = +25°C (VDDS = 12V, IDRAIN = 0.3A) 75 0.80 0.75 0.70 0.65 0.60 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 fSW (MHz) FIGURE 9. MAXIMUM CONVERSION RATIO, TJ ≤ +125°C 9 FN7730.0 January 23, 2012 ZL2101 ZL2101 Overview Digital-DC Architecture The ZL2101 is an innovative mixed-signal power conversion and power management IC based on Zilker Labs patented Digital-DC technology that provides an integrated, high performance stepdown converter for point of load applications. The ZL2101 integrates all necessary PWM control circuitry as well as low rDS(ON) synchronous power MOSFETs to provide an extremely small solution for supplying load currents up to 6A. Its unique PWM loop utilizes an ideal mix of analog and digital blocks to enable precise control of the entire power conversion process with no software required, resulting in a very flexible device that is also very easy to use. An extensive set of power management functions are fully integrated and can be configured using simple pin connections. The user configuration can be saved in an internal non-volatile memory (NVM). Additionally, all functions can be configured and monitored via the SMBus hardware interface using standard PMBus commands, allowing ultimate flexibility. The ZL2101 can be configured by simply connecting its pins according to the tables provided in the following sections. Additionally, a comprehensive set of application notes are available to help simplify the design process. An evaluation board is also available to help the user become familiar with the device. This board can be evaluated as a standalone platform using pin configuration settings. A Windows™-based GUI is also provided to enable full configuration and monitoring capability via the I2C/SMBus interface using an available computer and the included USB cable. Power Conversion Overview The ZL2101 operates as a voltage-mode, synchronous buck converter with a selectable constant frequency pulse width modulator (PWM) control scheme. The ZL2101 integrates dual low rDS(ON) synchronous MOSFETs to minimize the circuit footprint. Figure 10 illustrates the basic synchronous buck converter topology showing the primary power train components. This converter is also called a step-down converter, as the output voltage must always be lower than the input voltage. Once enabled, the ZL2101 is immediately ready to regulate power and perform power management tasks with no programming required. Advanced configuration options and realtime configuration changes are available via the I2C/SMBus interface if desired and continuous monitoring of multiple operating parameters is possible with minimal interaction from a host controller. Integrated sub-regulation circuitry enables single supply operation from any external supply between 4.5V and 14V with no secondary bias supplies needed. The ZL2101 can also be configured to operate from a 3.3V or 5V standby supply when the main power rail is not present, allowing the user to configure and/or read diagnostic information from the device when the main power has been interrupted or is disabled. VIN CIN LDO DB QH CB VOUT QL FIGURE 10. SYNCHRONOUS BUCK CONVERTER VTRK VSET POWER MANAGEMENT DIGITAL DIGITAL COMPENSATOR COMPENSATOR FC LDO NVM BST ISENSE HS FET DRIVER D-PWM SYNC GEN SYNC VDDP SS VDDS EN MGN CFG > VRA VR PG COUT ZL INPUT VOLTAGE BUS > L1 PWM SW VOUT LS FET DRIVER PLL Σ ADC - + ISENSE ADC RESET REF DDC VDD SALRT SDA SCL SA ADC COMMUNICATION VSEN MUX TEMP SENSOR FIGURE 11. ZL2101 BLOCK DIAGRAM 10 FN7730.0 January 23, 2012 ZL2101 The ZL2101 integrates two N-channel power MOSFETs; QH is the top control MOSFET and QL is the bottom synchronous MOSFET. The amount of time that QH is on as a fraction of the total switching period is known as the duty cycle D, which is described by Equation 1: D≈ VOUT VIN (EQ. 1) During time D, QH is on and VIN – VOUT is applied across the inductor. The output current ramps up as shown in Figure 12. When QH turns off (time 1-D), the current flowing in the inductor must continue to flow from the ground up through QL, during which the current ramps down. Since the output capacitor COUT exhibits low impedance at the switching frequency, the AC component of the inductor current is filtered from the output voltage so the load sees nearly a DC voltage. The maximum conversion ratio is shown in Figure 9. Typically, buck converters specify a maximum duty cycle that effectively limits the maximum output voltage that can be realized for a given input voltage and switching frequency. This duty cycle limit ensures that the low-side MOSFET is allowed to turn on for a minimum amount of time during each switching cycle, which enables the bootstrap capacitor to be charged up and provide adequate gate drive voltage for the high-side MOSFET. VIN - VOUT IO 0 Current (A) Voltage (V) IL PK ILV -VOUT value with an analog to digital (A/D) converter. The digital signal is also applied to an adjustable digital compensation filter and the compensated signal is used to derive the appropriate PWM duty cycle for driving the internal MOSFETs in a way that produces the desired output. Power Management Overview The ZL2101 incorporates a wide range of configurable power management features that are simple to implement without additional components. Also, the ZL2101 includes circuit protection features that continuously safeguard the device and load from damage due to unexpected system faults. The ZL2101 can continuously monitor input voltage, output voltage/current and internal temperature. A Power-good output signal is also included to enable power-on reset functionality for an external processor. All power management functions can be configured using either pin configuration techniques (see Figure 13) or via the I2C/SMBus interface. Monitoring parameters can also be preconfigured to provide alerts for specific conditions. See Application Note AN2033 for more details on SMBus monitoring. Multi-mode Pins In order to simplify circuit design, the ZL2101 incorporates patented multi-mode pins that allow the user to easily configure many aspects of the device without programming. Most power management features can be configured using these pins. The multi-mode pins can respond to four different connections, as shown in Table 1. These pins are sampled when power is applied or by issuing a PMBus Restore command (See Application Note AN2033). PIN-STRAP SETTINGS This is the simplest method, as no additional components are required. Using this method, each pin can take on one of three possible states: LOW, OPEN, or HIGH. These pins can be connected to the V2P5 pin for logic HIGH settings as this pin provides a regulated voltage higher than 2V. Using a single pin one of three settings can be selected. TABLE 1. MULTI-MODE PIN CONFIGURATION D 1-D PIN TIED TO VALUE FIGURE 12. INDUCTOR WAVEFORM LOW (Logic LOW) < 0.8VDC In general, the size of components L1 and COUT as well as the overall efficiency of the circuit are inversely proportional to the switching frequency, fSW. Therefore, the highest efficiency circuit may be realized by switching the MOSFETs at the lowest possible frequency; however, this will result in the largest component size. Conversely, the smallest possible footprint may be realized by switching at the fastest possible frequency but this gives a somewhat lower efficiency. Each user should determine the optimal combination of size and efficiency when determining the switching frequency for each application. OPEN (N/C) No connection HIGH (Logic HIGH) > 2.0VDC Resistor to SGND Set by resistor value Time The block diagram for the ZL2101 is illustrated in Figure 11. In this circuit, the target output voltage is regulated by connecting the VSEN pin directly to the output regulation point. The VSEN signal is then compared to an internal reference voltage that had been set to the desired output voltage level by the user. The error signal derived from this comparison is converted to a digital 11 Logic high Open ZL ZL Multi- mode Pin Multi- mode Pin RSET Logic low Pinstrap Settings Resistor Settings FIGURE 13. PIN-STRAP AND RESISTOR SETTING EXAMPLES FN7730.0 January 23, 2012 ZL2101 RESISTOR SETTINGS VIN This method allows a greater range of adjustability when connecting a finite value resistor (in a specified range) between the multi-mode pin and SGND. Standard 1% resistor values are used, and only every fourth E96 resistor value is used so the device can reliably recognize the value of resistance connected to the pin while eliminating the error associated with the resistor accuracy. Up to 31 unique selections are available using a single resistor. I2C/SMBUS METHOD ZL2101 functions can be configured via the I2C/SMBus interface using standard PMBus commands. Additionally, any value that has been configured using the pin-strap or resistor setting methods can also be re-configured and/or verified via the I2C/SMBus. See Application Note AN2033 for more details. The SMBus device address and VOUT_MAX are the only parameters that must be set by external pins. All other device parameters can be set via the I2C/SMBus. The device address is set using the SA pin. VOUT_MAX is determined as 10% greater than the voltage set by the VSET pin. Resistor pin-straps are recommended to be used for all available device parameters to allow a safe initial power-up before configuration is stored via the I2C/SMBus. For example, this can be accomplished by pin-strapping the undervoltage lockout threshold (using SS pin) to a value greater than the expected input voltage, thus preventing the device from enabling prior to loading a configuration file. Power Conversion Functional Description Internal Bias Regulators and Input Supply Connections The ZL2101 employs three internal low dropout (LDO) regulators to supply bias voltages for internal circuitry, allowing it to operate from a single input supply. The internal bias regulators are as follows: • VR: The VR LDO provides a regulated 7V bias supply for the high-side MOSFET driver circuit. It is powered from the VDDS pin and supplies bias current internally. A 4.7µF filter capacitor is required at the VR pin. The VDDS pin directly supplies the low-side MOSFET driver circuit. • VRA: The VRA LDO provides a regulated 5V bias supply for the current sense circuit and other analog circuitry. It is powered from the VDDS pin and supplies bias current internally. A 4.7µF filter capacitor is required at the VRA pin. 12 VIN VIN VDDS VDDS VDDS VR VR VR VRA VRA VRA 4.5V ≤ VIN ≤ 5.5V 5.5V < V IN ≤ 7.5V 7.5V < V IN ≤ 14V FIGURE 14. INPUT SUPPLY CONNECTIONS • V2P5:The V2P5 LDO provides a regulated 2.5V bias supply for the main controller circuitry. It is powered from the VRA LDO and supplies bias current internally. A 10µF filter capacitor is required at the V2P5 pin. When the input supply (VDDS) is higher than 7.5V, the VR and VRA pins should not be connected to any other pins. These pins should only have a filter capacitor attached. Due to the dropout voltage associated with the VR and VRA bias regulators, the VDDS pin must be connected to these pins for designs operating from a supply below 7.5V. Figure 14 illustrates the required connections for all cases. Note: The internal bias regulators, VR and VRA, are not designed to be outputs for powering other circuitry. Do not attach external loads to any of these pins. Only the multi-mode pins may be connected to the V2P5 pin for logic HIGH settings. High-side Driver Boost Circuit The gate drive voltage for the high-side MOSFET driver is generated by a floating bootstrap capacitor, CB (see Figure 10). When the lower MOSFET (QL) is turned on, the SW node is pulled to ground and the capacitor is charged from the internal VR bias regulator through diode DB. When QL turns off and the upper MOSFET (QH) turns on, the SW node is pulled up to VDDP and the voltage on the bootstrap capacitor is boosted approximately 6.5V above VDDP to provide the necessary voltage to power the highside driver. An internal Schottky diode is used with CB to help maximize the high-side drive supply voltage. Output Voltage Selection The output voltage may be set to any voltage between 0.6V and 5.0V provided that the input voltage is higher than the desired output voltage by an amount sufficient to prevent the device from exceeding its maximum duty cycle specification. Using the pin-strap method, VOUT can be set to one of three standard voltages as shown in Table 2. TABLE 2. PIN-STRAP OUTPUT VOLTAGE SETTINGS VSET VOUT LOW 1.2V OPEN 1.5V HIGH 3.3V FN7730.0 January 23, 2012 ZL2101 TABLE 3. ZL2101 START-UP SEQUENCE STEP # STEP NAME 1 Power Applied 2 Internal Memory Check 3 Multi-mode Pin Check 4 Device Ready 5 Pre-ramp Delay DESCRIPTION Input voltage is applied to the ZL2101’s VDD pins (VDDP and VDDS). Depends on input supply ramp time The device will check for values stored in its internal memory. This step is also performed after a Restore command. The device loads values configured by the multi-mode pins. Approximately 5ms to 10ms (device will ignore an enable signal or PMBus traffic during this period) The device is ready to accept an enable signal. - The device requires approximately 2ms following an enable signal and prior to ramping its output. Additional pre-ramp delay may be configured using the SS pin. Approximately 2ms TABLE 4. RESISTORS FOR SETTING OUTPUT VOLTAGE RSET (kΩ) VOUT (V) 10 0.6 11 0.7 12.1 0.75 13.3 0.8 14.7 0.9 16.2 1.0 17.8 1.1 19.6 1.2 21.5 1.25 23.7 1.3 26.1 1.4 28.7 1.5 31.6 1.6 34.8 1.7 38.3 1.8 42.2 1.9 46.4 2.0 51.1 2.1 56.2 2.2 61.9 2.3 68.1 2.4 75 2.5 82.5 2.6 90.9 2.7 100 2.8 110 2.9 121 3.0 133 3.1 147 3.2 162 3.3 178 5.0 13 TIME DURATION The resistor setting method can be used to set the output voltage to levels not available in Table 2. To set VOUT using resistors, use Table 4 to select the resistor that corresponds to the desired voltage. The output voltage may also be set to any value between 0.6V and 5.0V using the I2C interface. See Application Note AN2033 for details. Start-up Procedure The ZL2101 follows a specific internal start-up procedure after power is applied to the VDD pins (VDDP and VDDS). Table 3 describes the start-up sequence. If the device is to be synchronized to an external clock source, the clock frequency must be stable prior to asserting the EN pin. The device requires approximately 5ms to 10ms to check for specific values stored in its internal memory. If the user has stored values in memory, those values will be loaded. The device will then check the status of all multi-mode pins and load the values associated with the pin settings. Once this process is completed, the device is ready to accept commands via the I2C/SMBus interface and the device is ready to be enabled. Once enabled, the device requires approximately 2ms before its output voltage may be allowed to start its ramp-up process. If a soft-start delay period less than 2ms has been configured (using PMBus commands), the device will default to a 2ms delay period. If a delay period greater than 2ms is configured, the device will wait for the configured delay period prior to starting to ramp its output. After the delay period has expired, the output will begin to ramp towards its target voltage according to the pre-configured soft-start ramp time that has been set using the SS pin. It should be noted that if the EN pin is tied to VDDP or VDDS, the device will still require approximately 5ms to 10ms before the output can begin its ramp-up as described in Table 3. Soft-start Delay and Ramp Times It may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. In addition, the designer may wish to set the time required for VOUT to ramp to its target value after the delay period has expired. These features may be used as part of an overall inrush current management strategy or to control how fast a load IC is turned on. The ZL2101 gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. FN7730.0 January 23, 2012 ZL2101 The soft-start delay period begins when the EN pin is asserted and ends when the delay time expires. The soft-start delay period is set using the SS pin. Precise ramp delay timing mode reduces the delay time variations and is available when the appropriate bit in the MISC_CONFIG register had been set. Please refer to Application Note AN2033 for details. The soft-start ramp timer enables a precisely controlled ramp to the nominal VOUT value that begins once the delay period has expired. The ramp-up is guaranteed monotonic and its slope may be precisely set using the SS pin. Using the pin-strap method, the soft-start delay and ramp times can be set to one of three standard values according to Table 5. TABLE 5. SOFT-START DELAY AND RAMP SETTINGS SS PIN SETTING DELAY AND RAMP TIME (ms) LOW 2 OPEN 5 HIGH 10 UVLO 7.5V If the desired soft-start delay and ramp times are not one of the values listed in Table 5, the times can be set to a custom value by connecting a resistor from the SS pin to SGND using the appropriate resistor value from Table 6. The value of this resistor is measured upon start-up or Restore and will not change if the resistor is varied after power has been applied to the ZL2101 (see Figure 15). SS ZL RSS FIGURE 15. SS PIN RESISTOR CONNECTIONS The soft-start delay and ramp times can also be set to custom values via the I2C/SMBus interface. When the SS delay time is set to 0ms, the device will begin its ramp-up after the internal circuitry has initialized (~2ms). When the soft-start ramp period is set to 0ms, the output will ramp up as quickly as the output load capacitance and loop settings will allow. It is generally recommended to set the soft-start ramp to a value greater than 500µs to prevent inadvertent fault conditions due to excessive inrush current. TABLE 6. DELAY AND RAMP CONFIGURATION RSS (kΩ) DELAY TIME (ms) 10 5 11 10 12.1 20 13.3 5 14.7 10 16.2 20 17.8 5 19.6 10 21.5 20 23.7 5 26.1 10 28.7 20 31.6 5 34.8 10 38.3 20 42.2 5 46.4 10 51.1 20 56.2 5 61.9 10 68.1 20 75 5 82.5 10 90.9 20 100 5 110 10 121 20 133 5 147 10 162 20 RAMP TIME (ms) UVLO (V) 5 4.5 10 2 5 5.5 10 20 2 5 7.5 10 20 Note that when Auto Compensation is enabled, the minimum tON_DELAY is 5ms. Power-good (PG) The ZL2101 provides a Power-good (PG) signal that indicates the output voltage is within a specified tolerance of its target level and no fault condition exists. By default, the PG pin will assert if the output is within +15%/-10% of the target voltage. These limits may be changed via the I2C/SMBus interface. See Application Note AN2033 for details. A PG delay period is the time from when all conditions for asserting PG are met and when the PG pin is actually asserted. This feature is commonly used instead of an external reset controller to signal the power supply is at its target voltage prior to enabling any powered circuitry. By default, the ZL2101 PG delay is set to 1ms and may be changed using the I2C/SMBus interface as described in AN2033. 14 FN7730.0 January 23, 2012 ZL2101 Switching Frequency and PLL The ZL2101 incorporates an internal phase-locked loop (PLL) to clock the internal circuitry. The PLL can be driven by an external clock source connected to the SYNC pin. When using the internal oscillator, the SYNC pin can be configured as a clock source for other Zilker Labs devices. The SYNC pin is a unique pin that can perform multiple functions depending on how it is configured. The CFG pin is used to select the operating mode of the SYNC pin as shown in Table 4. Figure 16 illustrates the typical connections for each mode. TABLE 7. SYNC PIN FUNCTION SELECTION CFG PIN SYNC PIN FUNCTION LOW SYNC is configured as an input OPEN Auto detect mode HIGH SYNC is configured as an output fSW = 400kHz CONFIGURATION A: SYNC OUTPUT When the SYNC pin is configured as an output (CFG pin is tied HIGH), the device will run from its internal oscillator and will drive the resulting internal oscillator signal (preset to 400kHz) onto the SYNC pin so other devices can be synchronized to it. The SYNC pin will not be checked for an incoming clock signal while in this mode. 200kHz to 1MHz with a minimum duty cycle and must be stable when the EN pin is asserted. The external clock signal must also exhibit the necessary performance requirements (see the “Electrical Specifications” table beginning on page 6). In the event of a loss of the external clock signal, the output voltage may show transient over/undershoot. If this happens, the ZL2101 will automatically switch to its internal oscillator and switch at a frequency close to the previous incoming frequency. CONFIGURATION C: SYNC AUTO DETECT When the SYNC pin is configured in auto detect mode (CFG pin is left OPEN), the device will automatically check for a clock signal on the SYNC pin after enable is asserted. If a valid clock signal is present, the ZL2101’s oscillator will then synchronize with the rising edge of the external clock (refer to SYNC INPUT description). If no incoming clock signal is present, the ZL2101 will configure the switching frequency according to the state of the SYNC pin as listed in Table 8. In this mode, the ZL2101 will only read the SYNC pin connection during the start-up sequence. Changes to the SYNC pin connection will not affect fSW until the power (VDDS) is cycled off and on again. TABLE 8. SWITCHING FREQUENCY SELECTION SYNC PIN FREQUENCY CONFIGURATION B: SYNC INPUT LOW 200kHz When the SYNC pin is configured as an input (CFG pin is tied LOW), the device will automatically check for an external clock signal on the SYNC pin each time the EN pin is asserted. The internal oscillator will then synchronize with the rising edge of the external clock. The incoming clock signal must be in the range of OPEN 400kHz HIGH 1MHz Resistor See Table 9 SYNC 200kHz – 1MHz ZL2101 ZL2106 ZL2106 ZL2101 N/C Open SYNC OR Logic low N/C CFG SYNC 200kHz – 1MHz B) SYNC = input Logic high CFG N/C ZL2101 ZL2106 ZL2106 ZL2101 SYNC OR RSYNC CFG A) SYNC = output CFG SYNC 200kHz – 1MHz CFG Logic high ZL2106 ZL2101 C) SYNC = Auto Detect FIGURE 16. SYNC PIN CONFIGURATIONS 15 FN7730.0 January 23, 2012 ZL2101 If the user wishes to run the ZL2101 at a frequency not listed in Table 8, the switching frequency can be set using an external resistor, RSYNC, connected between SYNC and SGND using Table 9. TABLE 9. RSYNC RESISTOR VALUES RSYNC (kΩ) FSW (kHz) 10 200 TABLE 10. POWER SUPPLY REQUIREMENTS PARAMETER RANGE EXAMPLE VALUE Input voltage (VIN) 4.5V to 14.0V 12V Output voltage (VOUT) 0.6V to 5.0V 3.3V Output current (IOUT) 0A to 6A 4A <3% of VOUT ±1% of VOUT <Io ±25% of Io Output load step rate - 2.5A/µs Output deviation due to load step - ±3% of VOUT +120°C +85°C Desired efficiency - 85% Other considerations - Optimize for small size 11 222 12.1 242 13.3 267 14.7 296 16.2 320 17.8 364 19.6 400 21.5 421 23.7 471 26.1 533 28.7 571 31.6 615 34.8 667 DESIGN GOAL TRADE-OFFS 38.3 727 42.2 889 46.4 1000 The design of the buck power stage requires several compromises among size, efficiency and cost. The inductor core loss increases with frequency, so there is a trade-off between a small output filter made possible by a higher switching frequency and getting better power supply efficiency. Size can be decreased by increasing the switching frequency at the expense of efficiency. Cost can be minimized by using through-hole inductors and capacitors; however these components are physically large. The switching frequency can also be set to any value between 200kHz and 1MHz using the I2C/SMBus interface. The available frequencies are defined by fSW = 8MHz/N, where whole number N is 8 ≤ N ≤ 40. See Application Note AN2033 for details. If a value other than fSW = 8MHz/N is entered using a PMBus command, the internal circuitry will select the valid switching frequency value that is closest to the entered value. For example, if 810kHz is entered, the device will select 800kHz (N = 10). Output voltage ripple (Vorip) Output load step (Iostep) Maximum PCB temp. To start the design, select a frequency based on Table 11. This frequency is a starting point and may be adjusted as the design progresses. TABLE 11. CIRCUIT DESIGN CONSIDERATIONS Note: The switching frequency read back using the appropriate PMBus command will differ slightly from the selected value in Table 9. The difference is due to hardware quantization. FREQUENCY RANGE EFFICIENCY CIRCUIT SIZE 200kHz to 400kHz Highest Larger When multiple Zilker Labs devices are used together, connecting the SYNC pins together will force all devices to synchronize with each other. The CFG pin of one device must set its SYNC pin as an output and the remaining devices must have their SYNC pins set as an input or as auto detect. 400kHz to 800kHz Moderate Smaller 800kHz to 1MHz Lower Smallest Note: Precise ramp timing mode must be disabled to use SYNC clock auto detect. Component Selection The ZL2101 is a synchronous buck converter with integrated MOSFETs that uses an external inductor and capacitors to perform the power conversion process. The proper selection of the external components is critical for optimized performance. To select the appropriate external components for the desired performance goals, the power supply requirements listed in Table 10 must be defined. 16 INDUCTOR SELECTION The output inductor selection process must include several tradeoffs. A high inductance value will result in a low ripple current (Iopp), which will reduce output capacitance and produce a low output ripple voltage, but may also compromise output transient load performance. Therefore, a balance must be struck between output ripple and optimal load transient performance. A good starting point is to select the output inductor ripple equal to the expected load transient step magnitude (Iostep): I opp = I ostep (EQ. 2) FN7730.0 January 23, 2012 ZL2101 Now the output inductance can be calculated using Equation 3, where VINM is the maximum input voltage: LOUT ⎛ V VOUT × ⎜⎜1 − OUT ⎝ V INM = fsw × I opp ⎞ ⎟⎟ ⎠ I opp 2 Select an inductor rated for the average DC current with a peak current rating above the peak current computed in Equation 4. In overcurrent or short-circuit conditions, the inductor may have currents greater than 2X the normal maximum rated output current. It is desirable to use an inductor that still provides some inductance to protect the load and the internal MOSFETs from damaging currents in this situation. Once an inductor is selected, the DCR and core losses in the inductor are calculated. Use the DCR specified in the inductor manufacturer’s data sheet. PLDCR = DCR × I Lrms 2 (EQ. 5) ILrms is given by Equation 6: 2 (EQ. 7) Vorip 2 Vorip (EQ. 8) 2 × I opp Use these values to make an initial capacitor selection, using a single capacitor or several capacitors in parallel. After a capacitor has been selected, the resulting output voltage ripple can be calculated using Equation 9: Vorip = I opp × ESR + I opp 8 × f sw × C OUT (EQ. 6) opp 12 where IOUT is the maximum output current. Next, calculate the core loss of the selected inductor. Since this calculation is specific to each inductor and manufacturer, refer to the chosen inductor data sheet. Add the core loss and the DCR loss and compare the total loss to the maximum power dissipation recommendation in the inductor data sheet. OUTPUT CAPACITOR SELECTION Several trade-offs must also be considered when selecting an output capacitor. Low ESR values are needed to have a small output deviation during transient load steps (Vosag) and low output voltage ripple (Vorip). However, capacitors with low ESR, such as semi-stable (X5R and X7R) dielectric ceramic capacitors, also have relatively low capacitance values. Many designs can use a combination of high capacitance devices and low ESR devices in parallel. For high ripple currents, a low capacitance value can cause a significant amount of output voltage ripple. Likewise, in high transient load steps, a relatively large amount of capacitance is needed to minimize the output voltage deviation while the inductor current ramps up or down to the new steady state output current value. As a starting point, apportion one-half of the output ripple voltage to the capacitor ESR and the other half to capacitance, as 17 (EQ. 9) Because each part of this equation was made to be less than or equal to half of the allowed output ripple voltage, the Vorip should be less than the desired maximum output ripple. INPUT CAPACITOR It is highly recommended that dedicated input capacitors be used in any point-of-load design, even when the supply is powered from a heavily filtered 5V or 12V “bulk” supply from an off-line power supply. This is because of the high RMS ripple current that is drawn by the buck converter topology. This ripple (ICINrms) can be determined from Equation 10: I CINrms = I OUT × D × (1 − D) (I ) 2 I Lrms = I OUT + 8 × f sw × ESR = (EQ. 4) I opp C OUT = (EQ. 3) The average inductor current is equal to the maximum output current. The peak inductor current (ILpk) is calculated using Equation 4 where IOUT is the maximum output current: I Lpk = I OUT + shown in Equations 7 and 8: (EQ. 10) Without capacitive filtering near the power supply circuit, this current would flow through the supply bus and return planes, coupling noise into other system circuitry. The input capacitors should be rated at 1.2X the ripple current calculated in Equation 10 to avoid overheating of the capacitors due to the high ripple current, which can cause premature failure. Ceramic capacitors with X7R or X5R dielectric with low ESR and 1.1X the maximum expected input voltage are recommended. BOOTSTRAP CAPACITOR SELECTION The high-side driver boost circuit utilizes an internal Schottky diode (DB) and an external bootstrap capacitor (CB) to supply sufficient gate drive for the high-side MOSFET driver. CB should be a 47nF ceramic type rated for at least 10V. CV2P5 SELECTION This capacitor is used to both stabilize and provide noise filtering for the 2.5V internal power supply. It should be between 4.7µF and 10µF, should use a semi-stable X5R or X7R dielectric ceramic with a low ESR (less than 10mΩ) and should have a rating of 4V or more. CVR SELECTION This capacitor is used to both stabilize and provide noise filtering for the 7V reference supply. It should be between 4.7µF and 10µF, should use a semi-stable X5R or X7R dielectric ceramic capacitor with a low ESR (less than 10mΩ) and should have a rating of 10V or more. Because the current for the bootstrap supply is drawn from this capacitor, CVR should be sized at least 10X the value of CB so that a discharged CB does not cause the voltage on it to droop excessively during a CB recharge pulse. FN7730.0 January 23, 2012 ZL2101 CVRA SELECTION Loop Compensation This capacitor is used to both stabilize and provide noise filtering for the analog 5V reference supply. It should be between 2.2µF and 10µF, should use a semi-stable X5R or X7R dielectric ceramic capacitor with a low ESR (less than 10mΩ) and should have a rating of 6.3V or more. The ZL2101 has an auto compensation feature that measures the characteristics of the power train and calculates the proper tap coefficients. Auto compensation is configured using the FC pin as shown in Table 12. TABLE 12. PIN #9 (FC) AUTO COMPENSATION MODE THERMAL CONSIDERATIONS In typical applications, the ZL2101’s high efficiency will limit the internal power dissipation inside the package. However, in applications that require a high ambient operating temperature the user must perform some thermal analysis to ensure that the ZL2101’s maximum junction temperature is not exceeded. The ZL2101 has a maximum junction temperature limit of +125°C, and the internal over-temperature limiting circuitry will force the device to shut down if its junction temperature exceeds this threshold. In order to calculate the maximum junction temperature, the user must first calculate the power dissipated inside the IC (PQ) as expressed in Equation 11: ( 2 PQ = I LOAD )[(R DS (ON )QH )(D) + (R DS (ON )QL )(1− D)] (EQ. 11) The maximum operating junction temperature can then be calculated using Equation 12: T j max = TPCB + (PQ × θ JC ) (EQ. 12) Where TPCB is the expected maximum printed circuit board temperature and θJC is the junction-to-case thermal resistance for the ZL2101 package. Current Sensing and Current Limit Threshold Selection The ZL2101 incorporates a patented “lossless” current sensing method across the internal low-side MOSFET that is independent of rDS(ON) variations, including temperature. The default value for the gain, which does not represent a rDS(ON) value, and the offset of the internal current sensing circuit can be modified by the IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands. The design should include a current limiting mechanism to protect the power supply from damage and prevent excessive current from being drawn from the input supply in the event that the output is shorted to ground or an overload condition is imposed on the output. Current limiting is accomplished by sensing the current through the circuit during a portion of the duty cycle. The current limit threshold is set to 9A by default. The current limit threshold can set to a custom value via the I2C/SMBus interface. Please refer to Application Note AN2033 for further details. Additionally, the ZL2101 gives the power supply designer several choices for the fault response during over or under current conditions. The user can select the number of violations allowed before declaring a fault, a blanking time and the action taken when a fault is detected. The blanking time represents the time when no current measurement is taken. This is to avoid taking a reading just after a current load step (less accurate due to potential ringing). Please refer to Application note AN2033 for further details. 18 RFC STORE VALUES LOW SINGLE / REPEAT PG ASSERT AUTO COMP GAIN Auto Comp Disabled OPEN Not Stored Single After Auto Comp HIGH Store in Flash Single After Auto Comp 10 kΩ Not Stored 11 kΩ Store in Flash 12.1 kΩ Not Stored 13.3 kΩ Store in Flash 14.7 kΩ Not Stored 16.2 kΩ Store in Flash 17.8 kΩ Not Stored 19.6 kΩ Store in Flash Repeat 1s 21.5 kΩ Store in Flash Single 23.7 kΩ Not Stored Repeat 1min 26.1 kΩ Store in Flash 28.7 kΩ Not Stored 31.6 kΩ Store in Flash 34.8 kΩ Not Stored 38.3 kΩ Store in Flash 42.2 kΩ Not Stored 46.4 kΩ Store in Flash 51.1 kΩ Not Stored 56.2 kΩ Store in Flash 61.9 kΩ Not Stored 68.1 kΩ Store in Flash 75 kΩ Not Stored 82.5 kΩ Store in Flash 90.9 kΩ Not Stored 100 kΩ Store in Flash 110 kΩ Not Stored 121 kΩ Store in Flash 133 kΩ Not Stored 147 kΩ Store in Flash 162 kΩ Not Stored 178 kΩ Store in Flash 100% Single Repeat 1s After Auto Comp Single After PG Delay 100% After Auto Comp Single Repeat 1min After PG Delay Single Repeat 1s After Auto Comp Single Repeat 1s After PG Delay 50% Single Repeat 1min After Auto Comp Single Repeat 1min After PG Delay FN7730.0 January 23, 2012 ZL2101 When auto compensation is enabled, the routine can be set to execute one time after ramp or periodically while regulating. Note that the Auto Compensation feature requires a minimum tON_DELAY as described in "Soft-Start Delay and Ramp Times" on page 14. If the device is configured to store auto comp values, the calculated compensation values will be saved in the Auto Comp Store and may be read back through the PID_TAPS command. If repeat mode is enabled, the first Auto Comp results after the first ramp will be stored; the values calculated periodically are not stored in the Auto Comp Store. When compensation values are saved in the Auto Comp Store, the device will use those compensation values on subsequent regulation voltage. In repeat mode, the latest Auto Comp results will always be used during operation. Stored Auto Comp results can only be cleared by disabling Auto Comp Store, which is not permitted while the output is enabled. However, sending the AUTOCOMP_CONTROL command while enabled in Store mode will cause the next results to be stored, overwriting previously stored values. If auto compensation is disabled, the device will use the compensation parameters that are stored in the DEFAULT_STORE or USER_STORE. If the PG Assert parameter is set to "Use PG Delay," PG will be asserted according to the POWER_GOOD_DELAY command, after which Auto Comp will begin. When Auto Comp is enabled, the user must not program a Power-Good Delay that will expire before the ramp is finished. If PG Assert is set to "After Auto Comp," PG will be asserted immediately after the first Auto Comp cycle completes (POWER_GOOD_DELAY will be ignored). The Auto Comp Gain control scales the Auto Comp results to allow a trade-off between transient response and steady-state duty cycle jitter. A setting of 100% will provide the fastest transient response while a setting of 10% will produce the lowest jitter. Note that if Auto Comp is enabled, for best results Vin must be stable before Auto Comp begins, as shown in Equation 13. ΔVin 100% -------------------- ( in% ) ≤ --------------------------------------Vin Nom 256 • Vout ---------------------------1+ Vin Nom (EQ. 13) The auto compensation function can also be configured via the AUTO_COMP_CONFIG command and controlled using the AUTO_COMP_CONTROL command over the I2C/SMBus interface. Please refer to Application Note AN2033 for further details. Driver Dead-time Control The ZL2101 utilizes a predetermined fixed dead-time applied between the gate drive signals for the top and bottom MOSFETs. In a synchronous buck converter, the MOSFET drive circuitry must be operated such that the top and bottom MOSFETs are never in the conducting state at the same time. This is because potentially damaging currents flow in the circuit if both MOSFETs are on simultaneously for periods of time exceeding a few nanoseconds. Conversely, long periods of time in which both MOSFETs are off reduces overall circuit efficiency by allowing current to flow in their parasitic body diodes. Therefore, it is advantageous to minimize the dead-time to provide peak optimal efficiency without compromising system reliability. The ZL2101 has optimized the dead-time for the integrated MOSFETs to maximizing efficiency. 19 Power Management Functional Description Input Undervoltage Lockout The input undervoltage lockout (UVLO) prevents the ZL2101 from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. The UVLO threshold (VUVLO) can be set to either 4.5V or 10.8V using the SS pin according to Table 6. The UVLO voltage can also be set to any value between 2.85V and 16V via the I2C/SMBus interface. Once an input undervoltage fault condition occurs, the device can respond in a number of ways as follows: 1. Continue operating without interruption. 2. Continue operating for a given delay period, followed by shutdown if the fault still exists. The device will remain in shutdown until instructed to restart. 3. Initiate an immediate shutdown until the fault has been cleared. The user can select a specific number of retry attempts. The default response from a UVLO fault is an immediate shutdown of the device. Please refer to Application Note AN2033 for details on how to configure the UVLO threshold or to select specific UVLO fault response options via the I2C/SMBus interface. Output Overvoltage Protection The ZL2101 offers an internal output overvoltage protection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. A hardware comparator is used to compare the actual output voltage (seen at the VSEN pin) to a threshold set to 15% higher than the target output voltage (the default setting). If the VSEN voltage exceeds this threshold, the PG pin will de-assert and the device can then respond in a number of ways as follows: 1. Initiate an immediate shutdown until the fault has been cleared. The user can select a specific number of retry attempts. 2. Turn off the high-side MOSFET and turn on the low-side MOSFET. The low-side MOSFET remains on until the device attempts a restart. The default response from an overvoltage fault is to immediately shut down. For continuous overvoltage protection when operating from an external clock, the only allowed response is an immediate shutdown. Please refer to Application Note AN2033 for details on how to select specific overvoltage fault response options via I2C/SMBus. Output Pre-Bias Protection An output pre-bias condition exists when an externally applied voltage is present on a power supply’s output before the power supply’s control IC is enabled. Certain applications require that the converter not be allowed to sink current during start up if a pre-bias condition exists at the output. The ZL2101 provides prebias protection by sampling the output voltage prior to initiating an output ramp. FN7730.0 January 23, 2012 ZL2101 If a pre-bias voltage lower than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled. The output voltage is then ramped to the final regulation value at the ramp rate set by the SS pin. The actual time the output will take to ramp from the pre-bias voltage to the target voltage will vary depending on the pre-bias voltage but the total time elapsed from when the delay period expires and when the output reaches its target value will match the pre-configured ramp time (see Figure 17). If a pre-bias voltage higher than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled with a PWM duty cycle that would ideally create the prebias voltage. Once the pre-configured soft-start ramp period has expired, the PG pin will be asserted (assuming the pre-bias voltage is not higher than the overvoltage limit). The PWM will then adjust its duty cycle to match the original target voltage and the output will ramp down to the pre-configured output voltage. Output Overcurrent Protection The ZL2101 can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. Once the current limit threshold has been selected (see “Current Sensing and Current Limit Threshold Selection” on page 18), the user may determine the desired course of action in response to the fault condition. The following overcurrent protection response options are available: 1. Initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. Initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. Continue operating for a given delay period, followed by shutdown if the fault still exists. 4. Continue operating through the fault (this could result in permanent damage to the power supply). 5. Initiate an immediate shutdown. 6. The default response from an overcurrent fault is an immediate shutdown of the device. Please refer to Application Note AN2033 for details on how to select specific overcurrent fault response options via I2C/SMBus. Thermal Overload Protection The ZL2101 includes an on-chip thermal sensor that continuously measures the internal temperature of the die and will shutdown the device when the temperature exceeds the preset limit. The factory default temperature limit is set to +125°C, but the user may set the limit to a different value if desired. See Application Note AN2033 for details. Note that setting a higher thermal limit via the I2C/SMBus interface may result in permanent damage to the device. Once the device has been disabled due to an internal temperature fault, the user may select one of several fault response options as follows: 1. Initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. Initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. Continue operating for a given delay period, followed by shutdown if the fault still exists. 4. Continue operating through the fault (this could result in permanent damage to the power supply). 5. Initiate an immediate shutdown. If the user has configured the device to restart, the device will wait the preset delay period (if configured to do so) and will then check the device temperature. If the temperature has dropped below a threshold that is approximately +15°C lower than the selected temperature fault limit, the device will attempt to re-start. If the temperature still exceeds the fault limit the device will wait the preset delay period and retry again. FIGURE 17. OUTPUT RESPONSES TO PRE-BIAS VOLTAGES If a pre-bias voltage higher than the overvoltage limit exists, the device will not initiate a turn-on sequence and will declare an overvoltage fault condition to exist. In this case, the device will respond based on the output overvoltage fault response method that has been selected. See “Output Overvoltage Protection” on page 19 for response options due to an overvoltage condition. 20 The default response from a temperature fault is an immediate shutdown of the device. Please refer to Application Note AN2033 for details on how to select specific temperature fault response options via I2C/SMBus. FN7730.0 January 23, 2012 ZL2101 Figure 22 is an example of a basic pin-strap tracking configuration. The VTRK pin is an analog input that, when tracking mode is enabled, the voltage applied to the VTRK pin performs as a reference for the device's output voltage. The ZL2101 offers two modes of tracking: coincident and ratiometric. Figures 19 and 20 illustrate the output voltage waveform for the two tracking modes. a. Track at 50% VOUT limited. Member rail tracks the reference rail and stops when the member reaches 50% of the target voltage, Figure 20 (A). b. Track at 50% VTRK limited. Member rail tracks the reference at the instantaneous voltage value applied to the VTRK pin until the member rail reaches 50% of the reference rail voltage, or if the member is configured to less than 50% of the reference the member will achieve its configured target, Figure 20 (B). ~ ~ VREF = 1.8V VMEM = 0.9V VREF tON_DLY ~ ~ TRACK @ 50% VOUT LIMITED VMEM tOFF_DLY VREF = 1.8V VMEM = 0.9V 0 EN A. TRACK @ 50% V TRK LIMITED VREF = 1.8V VMEM = 0.9V VREF tON_DLY ~ ~ High performance systems place stringent demands on the order in which the power supply voltages turn on. This is particularly true when powering FPGAs, ASICs, and other advanced processor devices that require multiple supply voltages to power a single die. In most cases, the I/O interface operates at a higher voltage than the core and therefore the core supply voltage must not exceed the I/O supply voltage according to the manufacturers' specifications. Voltage tracking protects these sensitive ICs by limiting the differential voltage among multiple power supplies during the power-up and power-down sequence. The ZL2101 integrates a lossless tracking scheme that allows its output to track a voltage that is applied to the VTRK pin with no additional components required. Figure 18 shows a basic I2C/SMBus tracking configuration. Please refer to Application Note AN2033 for more information on configuring tracking mode using PMBus commands. 2. Ratiometric. This mode configures the ZL2101 to ramp its output voltage as a percentage of the voltage applied to the VTRK pin. The default setting is 50%, but an external resistor may be used to configure a different tracking ratio. ~ ~ Voltage Tracking VMEM tOFF_DLY VREF = 1.8V VMEM = 0.9V 0 EN B. SDA SCL FIGURE 20. RATIOMETRIC TRACKING SDA SCL ZL2101 VOUT_R L4 SW REFERENCE SDA SCL ZL2101 VTRK SW VOUT_M L3 MEMBER FIGURE 18. BASIC I2C TRACKING CONFIGURATION 1. Coincident. This mode configures the ZL2101 to ramp its output voltage at the same rate as the voltage applied to the VTRK pin. Two options are available for this mode; a. Track at 100% VOUT limited. Member rail tracks the reference rail and stops when the member reaches its target voltage, Figure 19 (A). b. Track at 100% VTRK limited. Member rail tracks the reference at the instantaneous voltage value applied to the VTRK pin, Figure 19 (B). tON_DLY ~ ~ VREF ~ ~ TRACK @ 100% VOUT LIMITED VREF > VMEM VMEM tOFF_DLY 0 VREF = 1.8V VMEM = 0.9V EN A. TRACK @ 100% V TRK LIMITED tOFF_DLY VMEM 0 EN B. FIGURE 19. COINCIDENT TRACKING 21 When the ZL2101 is configured to the voltage tracking mode, the voltage applied to the VTRK pin acts as a reference for the member device(s) output regulation. The soft-start values (Rise/Fall times) are used to calculate the loop gain used during the turn-on/turn-off ramps, therefore the minimum rise/fall time has been constrained to 5ms to ensure accuracy. Tracking accuracy can be improved by increasing the rise and fall times beyond 5ms. Tracking Groups In a tracking group, the device configured to the highest voltage within the group is defined as the reference device. The device(s) that track the reference are called the member device(s). The reference device will control the ramp delay and ramp rate of all tracking devices and is not placed in the tracking mode. The reference device is configured to the highest output voltage for the group and all other device(s) output voltages are meant to track and never exceed the reference device output voltage. The reference device must be configured to have a minimum Time-On Delay and Time-On Rise as shown in Equation 14. tONDLY(REF) ≥ tONDLY(MEM) + tONRISE(REF) + 5ms ≥ tONDLY(MEM) + 10ms ~ ~ VREF = VMEM V REF tON_DLY Tracking Overview VREF = 1.8V VMEM = 1.8V (EQ. 14) This delay allows the member device(s) to prepare their control loops for tracking following the assertion of ENABLE. The member device Time-Off Delay has been redefined to describe the time that the VTRK pin will follow the reference voltage after enable is de-asserted. The delay setting sets the FN7730.0 January 23, 2012 ZL2101 timeout for the member's output voltage to turnoff in the event that the reference output voltage does not achieve zero volts. The member device(s) must have a minimum Time-Off Delay of as shown in Equation 15. tOFFDLY(MEM) ≥ tOFFDLY(REF) + tOFFFALL(REF) + 5ms (EQ. 15) It is assumed for a tracking group, that all of the ENABLE pins are connected together and driven by a single logic source or PMBus Broadcast Enable is used. The configuration settings for Figures 19 and 20 are shown below in Figure 21. In each case the reference and member rise times are set to the same value. Tracking Configured by Pin-Strap Tracking is enabled with the CFG pin as shown in Table 16 on page 24, and configured to a specific ramp rate using the SS pin, as shown in Table 13 on page 23. Figure 22 shows the basic schematic of pin-strap tracking. ENABLE EN EN VOUT_R ZL2101 L1 SW REFERENCE CFG SS R1 R3 VOUT_M ZL2101 SW VTRK L2 MEMBER CFG SS R2 R4 Tracking Configuration Figure 20 (A) Rail Reference Member Vout Set (Volts) 1.8 0.9 Time On Dly (ms) 15 5 Time On Rise (ms) 5 5 Time Off Dly (ms) 5 15 Time Off Fall ( ms) 5 5 Mode Track Disabled 100% Vout Limited Tracking Configuration Figure 20 (B) Time On Dly (ms) 15 5 Time On Rise (ms) 5 5 Time Off Dly (ms) 5 15 Time Off Fall ( ms) 5 5 Rail Vout Set (Volts) Reference Member 1.8 1.8 Rail Vout Set (Volts) Time On Dly (ms) Time On Rise (ms) Time Off Dly (ms) Time Off Fall ( ms) Mode Reference Member 1.8 0.9 15 5 5 5 5 15 5 5 Track Disabled Track 50% Vout Limited Rail Vout Set 0.8 (Volts) Reference Member 1.8 1.8 Mode Track Disabled 100% VTRK Limited Tracking Configuration Figure 21 (A) Tracking Configuration Figure 21 (B) Time On Dly (ms) 15 5 Time On Rise (ms) 5 5 Time Off Dly (ms) 5 15 Time Off Fall Mode ( ms) 5 Track Disabled 5 Track 50% VTRK Limited FIGURE 21. TRACKING CONFIGURATION FOR FIGURES 19 AND 20 FIGURE 22. BASIC PIN-STRAP TRACKING CONFIGURATION Voltage Margining The ZL2101 offers a simple means to vary its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. The MGN command is set by driving the MGN pin or through the I2C/SMBus interface. The MGN pin is a tri-level input that is continuously monitored and can be driven directly by a processor I/O pin or other logic-level output. The ZL2101’s output will be forced higher than its nominal set point when the MGN command is set HIGH, and the output will be forced lower than its nominal set point when the MGN command is set LOW. Default margin limits of VNOM ±5% are pre-loaded in the factory, but the margin limits can be modified through the I2C/SMBus interface to as high as VNOM + 10% or as low as 0V, where VNOM is the nominal output voltage set point determined by the VSET pin. A safety feature prevents the user from configuring the output voltage to exceed VNOM + 10% under any conditions. The margin limits and the MGN command can both be set individually through the I2C/SMBus interface. Additionally, the transition rate between the nominal output voltage and either margin limit can be configured through the I2C/SMBus interface. Please refer to Application Note AN2033 for detailed instructions on modifying the margining configurations. 22 FN7730.0 January 23, 2012 ZL2101 TABLE 13. TRACKING MODE CONFIGURATION RSS (kΩ) UVLO (V) TRACKING RATIO (%) 19.6 UPPER TRACK LIMIT Limited by target voltage 21.5 26.1 Limited by VTRK pin voltage Output not allowed to decrease before PG Output will always follow VTRK 5.5 28.7 Output not allowed to decrease before PG Output will always follow VTRK 100 23.7 RAMP-UP/DOWN BEHAVIOR Limited by target voltage 31.6 Output will always follow VTRK 50 34.8 Output not allowed to decrease before PG Limited by VTRK pin voltage 38.3 Output not allowed to decrease before PG Output will always follow VTRK 56.2 Limited by target voltage 61.9 Output will always follow VTRK 100 68.1 75 Limited by VTRK pin voltage Output not allowed to decrease before PG Output will always follow VTRK 7.5 82.5 Output not allowed to decrease before PG Limited by target voltage 90.9 Output will always follow VTRK 50 100 Output not allowed to decrease before PG Limited by VTRK pin voltage 110 Output not allowed to decrease before PG Output will always follow VTRK I2C/SMBus Communications Digital-DC Bus The ZL2101 provides an I2C/SMBus digital interface that enables The Digital-DC Communications (DDC) bus is used to communicate between Zilker Labs Digital-DC devices. This dedicated bus provides the communication channel between devices for features such as sequencing and fault spreading. The DDC pin on all Digital-DC devices in an application should be connected together. A pull-up resistor is required on the DDC bus in order to guarantee the rise time as expressed in Equation 16: the user to configure all aspects of the device operation as well as monitor the input and output parameters. The ZL2101 can be used with any standard 2-wire I2C host device. In addition, the device is compatible with SMBus version 2.0 and includes an SALRT line to help mitigate bandwidth limitations related to continuous fault monitoring. Pull-up resistors are required on the I2C/SMBus as specified in the SMBus 2.0 specification. The ZL2101 accepts most standard PMBus commands. When controlling the device with PMBus commands, it is recommended that the enable pin is tied to SGND. I2C/SMBus Device Address Selection When communicating with multiple devices using the I2C/SMBus interface, each device must have its own unique address so the host can distinguish between the devices. The device address can be set according to the pin-strap options listed in Table 14. Address values are right-justified. TABLE 14. SMBUS DEVICE ADDRESS SELECTION SA PIN SETTING SMBus ADDRESS LOW 0x20 OPEN 0x21 HIGH 0x22 Rise Time = RPU •CLOAD ≈ 1µs (EQ. 16) Where RPU is the DDC bus pull-up resistance and CLOAD is the bus loading. The pull-up resistor may be tied to VRA or to an external 3.3V or 5V supply as long as this voltage is present prior to or during device power-up. As rules of thumb, each device connected to the DDC bus presents approximately 10pF of capacitive loading, and each inch of FR4 PCB trace introduces approximately 2pF. The ideal design will use a central pull-up resistor that is well matched to the total load capacitance. In power module applications, the user should consider whether to place the pull-up resistor on the module or on the PCB of the end application. The minimum pull-up resistance should be limited to a value that enables any device to assert the bus to a voltage that will ensure a logic 0 (typically 0.8V at the device monitoring point) given the pull-up voltage (5V if tied to VRA) and the pull-down current capability of the ZL2101 (nominally 4mA). If additional device addresses are required, a resistor can be connected to the SA pin according to Table 15 to provide up to 30 unique device addresses. 23 FN7730.0 January 23, 2012 ZL2101 TABLE 15. SMBus ADDRESS VALUES RSA (kΩ) SMBus ADDRESS 10 0x20 11 0x21 12.1 0x22 13.3 0x23 14.7 0x24 16.2 0x25 17.8 0x26 19.6 0x27 21.5 0x28 23.7 0x29 26.1 0x2A 28.7 0x2B 31.6 0x2C 34.8 0x2D 38.3 0x2E 42.2 0x2F 46.4 0x30 51.1 0x31 56.2 0x32 61.9 0x33 68.1 0x34 75 0x35 82.5 0x36 described in “Switching Frequency and PLL” on page 15. Selecting the phase offset for the device is accomplished by selecting a device address according to the following equation: Phase offset = device address x 45° For example: • A device address of 0x00 or 0x20 would configure no phase offset • A device address of 0x01 or 0x21 would configure 45° of phase offset • A device address of 0x02 or 0x22 would configure 90° of phase offset The phase offset of each device may also be set to any value between 0° and 360° in 22.5° increments via the I2C/SMBus interface. Refer to Application Note AN2033 for further details. Output Sequencing A group of Zilker Labs devices may be configured to power up in a predetermined sequence. This feature is especially useful when powering advanced processors, FPGAs, and ASICs that require one supply to reach its operating voltage prior to another supply reaching its operating voltage in order to avoid latch-up from occurring. Multi-device sequencing can be achieved by configuring each device through the I2C/SMBus interface or by using Zilker Labs patented autonomous sequencing mode. Autonomous sequencing mode configures sequencing by using events transmitted between devices over the DDC bus. The sequencing order is determined using each device’s SMBus address. Using autonomous sequencing mode (configured using the CFG pin), the devices must be assigned sequential SMBus addresses with no missing addresses in the chain. This mode will also constrain each device to have a phase offset according to its SMBus address as described in section “Phase Spreading” on page 24. 90.9 0x37 100 0x38 110 0x39 121 0x3A 133 0x3B 147 0x3C RCFG SYNC PIN CONFIGURATION 162 0x3D Low Input Open Auto detect High Output 10kΩ Input 11kΩ Auto detect 12.1kΩ Output 14.7kΩ Input 16.2kΩ Auto detect 17.8kΩ Output 21.5kΩ Input 23.7kΩ Auto detect 26.1kΩ Output Phase Spreading When multiple point of load converters share a common DC input supply, it is desirable to adjust the clock phase offset of each device such that not all devices start to switch simultaneously. Setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. Since the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to the IRMS2 are reduced dramatically. In order to enable phase spreading, all converters must be synchronized to the same switching clock. The CFG pin is used to set the configuration of the SYNC pin for each device as 24 TABLE 16. CFG PIN CONFIGURATIONS FOR SEQUENCING AND TRACKING SEQUENCING CONFIGURATION Sequencing and Tracking are disabled. Sequencing and Tracking are disabled. Device is FIRST in nested sequence. Tracking disabled. Device is LAST in nested sequence. Tracking disabled. FN7730.0 January 23, 2012 ZL2101 TABLE 16. CFG PIN CONFIGURATIONS FOR SEQUENCING AND TRACKING (Continued) RCFG SYNC PIN CONFIGURATION 31.6kΩ Input 34.8kΩ Auto detect 38.3kΩ Output 46.4kΩ Input 51.1kΩ Auto detect 56.2kΩ Output SEQUENCING CONFIGURATION Device is MIDDLE in nested sequence. Tracking disabled. Sequence disabled. Tracking enabled as defined in Table 13. The sequencing group will turn on in order starting with the device with the lowest SMBus address and will continue through to turn on each device in the address chain until all devices connected have been turned on. When turning off, the device with the highest SMBus address will turn off first followed in reverse order by the other devices in the group. Sequencing is configured by connecting a resistor from the CFG pin to ground as described in Table 16. The CFG pin is also used to set the configuration of the SYNC pin as well as to determine the sequencing method and order. Please refer to section “Switching Frequency and PLL” on page 15 for more details on the operating parameters of the SYNC pin. Multiple device sequencing may also be achieved by issuing PMBus commands to assign the preceding device in the sequencing chain as well as the device that will follow in the sequencing chain. This method places fewer restrictions on the SMBus address (no need of sequential address) and also allows the user to assign any phase offset to any device irrespective of its SMBus device address. The Enable pins of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. Enable must be driven low to initiate a sequenced turnoff of the group. Please refer to Application Note AN2033 for details on sequencing via the I2C/SMBus interface. Fault Spreading Digital-DC devices can be configured to broadcast a fault event over the DDC bus to the other devices in the group. When a nondestructive fault occurs and the device is configured to shut down on a fault, the device will shut down and broadcast the fault event over the DDC bus. The other devices on the DDC bus will shut down together if configured to do so, and will attempt to restart in their prescribed order if configured to do so. Monitoring via I2C/SMBus A system controller can monitor a wide variety of different ZL2101 system parameters through the I2C/SMBus interface. The device can monitor for fault conditions by monitoring the SALRT pin, which will be pulled low when any number of preconfigured fault conditions occur. The device can also be monitored continuously for any number of power conversion parameters including input voltage, output voltage, output current, internal junction temperature, switching frequency and duty cycle. 25 The PMBus host should respond to SALRT as follows: 1. ZL device pulls SALRT low. 2. PMBus host detects that SALRT is now low, performs transmission with Alert Response Address to find which ZL device is pulling SALRT low. 3. PMBus host talks to the ZL device that has pulled SALRT low. The actions that the host performs are up to the system designer. If multiple devices are faulting, SALRT will still be low after doing the above steps and will require transmission with the Alert Response Address repeatedly until all faults are cleared. Please refer to Application Note AN2033 for details on how to monitor specific parameters via the I2C/SMBus interface. Snapshot™ Parametric Capture The ZL2101 offers a special feature that enables the user to capture parametric data during normal operation or following a fault. The Snapshot functionality is enabled by setting bit 1 of MISC_CONFIG to 1. See AN2033 for details on using Snapshot in addition to the parameters supported. The Snapshot feature enables the user to read the parameters via a block read transfer through the SMBus. This can be done during normal operation, although it should be noted that reading the 22 bytes will occupy the SMBus for some time. The SNAPSHOT_CONTROL command enables the user to store the snapshot parameters to Flash memory in response to a pending fault as well as to read the stored data from Flash memory after a fault has occurred. Table 17 describes the usage of this command. Automatic writes to Flash memory following a fault are triggered when any fault threshold level is exceeded, provided that the specific fault’s response is to shut down (writing to Flash memory is not allowed if the device is configured to re-try following the specific fault condition). It should also be noted that the device’s VDD voltage must be maintained during the time when the device is writing the data to Flash memory; a process that requires between 700µs to 1400µs depending on whether the data is set up for a block write. Undesirable results may be observed if the device’s VDD supply drops below 3.0V during this process. TABLE 17. SNAPSHOT_CONTROL COMMAND DATA VALUE DESCRIPTION 1 Copies current SNAPSHOT values from Flash memory to RAM for immediate access using SNAPSHOT command. 2 Writes current SNAPSHOT values to Flash memory. Only available when device is disabled. In the event that the device experiences a fault and power is lost, the user can extract the last SNAPSHOT parameters stored during the fault by writing a 1 to SNAPSHOT_CONTROL (transfers data from Flash memory to RAM) and then issuing a SNAPSHOT command (reads data from RAM via SMBus). FN7730.0 January 23, 2012 ZL2101 Non-Volatile Memory and Device Security Features The ZL2101 has internal non-volatile memory where user configurations are stored. Integrated security measures ensure that the user can only restore the device to a level that has been made available to them. Refer to “Start-up Procedure” on page 13 for details on how the device loads stored values from internal memory during start-up. During the initialization process, the ZL2101 checks for stored values contained in its internal memory. The ZL2101 offers two internal memory storage units that are accessible by the user as follows: user from being able to modify certain values that are related to the physical construction of the module. In this case, the module manufacturer would use the Default Store and would allow the user to restore the device to its default setting but would restrict the user from restoring the device to the factory settings. 2. User Store: The manufacturer of a piece of equipment may want to provide the ability to modify certain power supply settings while still protecting the equipment from modifying values that can lead to a system level fault. The equipment manufacturer would use the User Store to achieve this goal. Please refer to Application Note AN2033 for details on how to set specific security measures via the I2C/SMBus interface. 1. Default Store: A power supply module manufacturer may want to protect the module from damage by preventing the Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION January 23, 2012 FN7730.0 CHANGE Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ZL2101 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 26 FN7730.0 January 23, 2012 ZL2101 Package Outline Drawing L36.6x6C 36 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 4/10 4X 4.0 6.00 36X 0.50 A B 28 6 PIN 1 INDEX AREA 36 6 PIN #1 INDEX AREA 27 6.00 1 4 .10 ± 0.10 9 19 (4X) 0.15 18 10 TOP VIEW 36X 0.60 ± 0.10 36X 0.25 4 0.10 M C A B BOTTOM VIEW SEE DETAIL "X" 0.10 C MAX 1.00 C 0.08 C ( 5. 60 TYP ) ( 36 X 0 . 50 ) SIDE VIEW ( 4. 10 ) (36X 0.25 ) C ( 36X 0.80 ) 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be 7. JEDEC reference drawing: MO-220VJJD. either a mold or mark feature. 27 FN7730.0 January 23, 2012